developer | 9851a29 | 2022-12-15 17:33:43 +0800 | [diff] [blame] | 1 | From 10d82a8120c5998c64c6ce5a377d5b2cf925edc9 Mon Sep 17 00:00:00 2001 |
developer | 3e211f7 | 2022-12-08 19:55:32 +0800 | [diff] [blame] | 2 | From: Peter Chiu <chui-hao.chiu@mediatek.com> |
developer | 144824b | 2022-11-25 21:27:43 +0800 | [diff] [blame] | 3 | Date: Fri, 25 Nov 2022 14:37:58 +0800 |
developer | afd7587 | 2022-12-14 21:15:46 +0800 | [diff] [blame] | 4 | Subject: [PATCH 3009/3012] mt76: mt7915: wed: drop scatter and gather frame |
developer | 144824b | 2022-11-25 21:27:43 +0800 | [diff] [blame] | 5 | |
| 6 | The scatter and gather frame may be incorrect because WED and WO may |
| 7 | send frames to host driver interleaved. |
| 8 | |
developer | afd7587 | 2022-12-14 21:15:46 +0800 | [diff] [blame] | 9 | Signed-off-by: Peter Chiu <chui-hao.chiu@mediatek.com> |
developer | 144824b | 2022-11-25 21:27:43 +0800 | [diff] [blame] | 10 | --- |
developer | 3e211f7 | 2022-12-08 19:55:32 +0800 | [diff] [blame] | 11 | dma.c | 9 +++++++++ |
developer | 144824b | 2022-11-25 21:27:43 +0800 | [diff] [blame] | 12 | dma.h | 1 + |
| 13 | mt76.h | 1 + |
developer | 3e211f7 | 2022-12-08 19:55:32 +0800 | [diff] [blame] | 14 | 3 files changed, 11 insertions(+) |
developer | 144824b | 2022-11-25 21:27:43 +0800 | [diff] [blame] | 15 | |
| 16 | diff --git a/dma.c b/dma.c |
developer | eb6a018 | 2022-12-12 18:53:32 +0800 | [diff] [blame] | 17 | index 327ed3bc..0914266a 100644 |
developer | 144824b | 2022-11-25 21:27:43 +0800 | [diff] [blame] | 18 | --- a/dma.c |
| 19 | +++ b/dma.c |
developer | eb6a018 | 2022-12-12 18:53:32 +0800 | [diff] [blame] | 20 | @@ -420,6 +420,15 @@ mt76_dma_get_buf(struct mt76_dev *dev, struct mt76_queue *q, int idx, |
developer | 144824b | 2022-11-25 21:27:43 +0800 | [diff] [blame] | 21 | |
| 22 | *drop = !!(ctrl & (MT_DMA_CTL_TO_HOST_A | |
| 23 | MT_DMA_CTL_DROP)); |
| 24 | + |
developer | 3e211f7 | 2022-12-08 19:55:32 +0800 | [diff] [blame] | 25 | + if (*more || (q->flags & MT_QFLAG_WED_FRAG)) { |
| 26 | + *drop = true; |
| 27 | + |
| 28 | + if (!(*more) && FIELD_GET(MT_DMA_CTL_WO, desc->buf1)) |
| 29 | + q->flags &= ~MT_QFLAG_WED_FRAG; |
| 30 | + else |
| 31 | + q->flags |= MT_QFLAG_WED_FRAG; |
| 32 | + } |
developer | 144824b | 2022-11-25 21:27:43 +0800 | [diff] [blame] | 33 | } |
| 34 | } else { |
| 35 | buf = e->buf; |
| 36 | diff --git a/dma.h b/dma.h |
| 37 | index 4b9bc7f4..ce8ac426 100644 |
| 38 | --- a/dma.h |
| 39 | +++ b/dma.h |
| 40 | @@ -19,6 +19,7 @@ |
| 41 | #define MT_DMA_CTL_TO_HOST_A BIT(12) |
| 42 | #define MT_DMA_CTL_DROP BIT(14) |
| 43 | #define MT_DMA_CTL_TOKEN GENMASK(31, 16) |
| 44 | +#define MT_DMA_CTL_WO BIT(8) |
| 45 | |
| 46 | #define MT_DMA_PPE_CPU_REASON GENMASK(15, 11) |
| 47 | #define MT_DMA_PPE_ENTRY GENMASK(30, 16) |
| 48 | diff --git a/mt76.h b/mt76.h |
developer | 9851a29 | 2022-12-15 17:33:43 +0800 | [diff] [blame] | 49 | index 75975cb5..f1795778 100644 |
developer | 144824b | 2022-11-25 21:27:43 +0800 | [diff] [blame] | 50 | --- a/mt76.h |
| 51 | +++ b/mt76.h |
| 52 | @@ -30,6 +30,7 @@ |
| 53 | #define MT_QFLAG_WED_RING GENMASK(1, 0) |
| 54 | #define MT_QFLAG_WED_TYPE GENMASK(3, 2) |
| 55 | #define MT_QFLAG_WED BIT(4) |
| 56 | +#define MT_QFLAG_WED_FRAG BIT(5) |
| 57 | |
| 58 | #define __MT_WED_Q(_type, _n) (MT_QFLAG_WED | \ |
| 59 | FIELD_PREP(MT_QFLAG_WED_TYPE, _type) | \ |
| 60 | -- |
developer | 9851a29 | 2022-12-15 17:33:43 +0800 | [diff] [blame] | 61 | 2.18.0 |
developer | 144824b | 2022-11-25 21:27:43 +0800 | [diff] [blame] | 62 | |