blob: cb5281c53d7573cf88faadd6dcab8080f669dfeb [file] [log] [blame]
developere8045132023-08-04 14:40:12 +08001From 333678e670a88fe48c859af6dbb357405f084a52 Mon Sep 17 00:00:00 2001
developer4c6b6002022-05-30 16:36:44 +08002From: Shayne Chen <shayne.chen@mediatek.com>
3Date: Thu, 21 Apr 2022 15:43:19 +0800
developere8045132023-08-04 14:40:12 +08004Subject: [PATCH] wifi: mt76: testmode: additional supports
developer4c6b6002022-05-30 16:36:44 +08005
6Signed-off-by: Shayne Chen <shayne.chen@mediatek.com>
developer287ee9f2023-03-02 20:13:34 +08007Signed-off-by: StanleyYP Wang <StanleyYP.Wang@mediatek.com>
developer4c6b6002022-05-30 16:36:44 +08008---
developerf40484f2022-08-25 15:33:33 +08009 dma.c | 3 +-
10 mac80211.c | 12 +
developer62b3f572023-06-07 17:39:27 +080011 mt76.h | 108 +++-
developerf40484f2022-08-25 15:33:33 +080012 mt76_connac_mcu.c | 4 +
13 mt76_connac_mcu.h | 2 +
developerc670d342023-04-06 15:04:19 +080014 mt7915/eeprom.c | 2 +-
developerf40484f2022-08-25 15:33:33 +080015 mt7915/init.c | 2 +-
developer4feb1012023-01-30 17:29:07 +080016 mt7915/mac.c | 39 +-
developerf40484f2022-08-25 15:33:33 +080017 mt7915/main.c | 2 +-
developer62b3f572023-06-07 17:39:27 +080018 mt7915/mcu.c | 22 +-
developerdec31212023-05-02 16:45:27 +080019 mt7915/mcu.h | 29 +-
developerf40484f2022-08-25 15:33:33 +080020 mt7915/mmio.c | 2 +
developerc670d342023-04-06 15:04:19 +080021 mt7915/mt7915.h | 16 +-
developerf40484f2022-08-25 15:33:33 +080022 mt7915/regs.h | 3 +
developere8045132023-08-04 14:40:12 +080023 mt7915/testmode.c | 1222 ++++++++++++++++++++++++++++++++++++++++++---
developerf40484f2022-08-25 15:33:33 +080024 mt7915/testmode.h | 278 +++++++++++
developer62b3f572023-06-07 17:39:27 +080025 testmode.c | 282 +++++++++--
developerf40484f2022-08-25 15:33:33 +080026 testmode.h | 75 +++
developer62713c82023-03-20 10:46:08 +080027 tools/fields.c | 84 +++-
developerf40484f2022-08-25 15:33:33 +080028 tx.c | 3 +-
developere8045132023-08-04 14:40:12 +080029 20 files changed, 2024 insertions(+), 166 deletions(-)
developer4c6b6002022-05-30 16:36:44 +080030
31diff --git a/dma.c b/dma.c
developere8045132023-08-04 14:40:12 +080032index c9d2671..fc92e39 100644
developer4c6b6002022-05-30 16:36:44 +080033--- a/dma.c
34+++ b/dma.c
developer2324aa22023-04-12 11:30:15 +080035@@ -574,8 +574,7 @@ free:
developer4c6b6002022-05-30 16:36:44 +080036 if (mt76_is_testmode_skb(dev, skb, &hw)) {
37 struct mt76_phy *phy = hw->priv;
38
39- if (tx_info.skb == phy->test.tx_skb)
40- phy->test.tx_done--;
41+ phy->test.tx_done--;
42 }
43 #endif
44
45diff --git a/mac80211.c b/mac80211.c
developere8045132023-08-04 14:40:12 +080046index eac90b3..ed1d659 100644
developer4c6b6002022-05-30 16:36:44 +080047--- a/mac80211.c
48+++ b/mac80211.c
developer2324aa22023-04-12 11:30:15 +080049@@ -55,6 +55,13 @@ static const struct ieee80211_channel mt76_channels_5ghz[] = {
developer4c6b6002022-05-30 16:36:44 +080050 CHAN5G(60, 5300),
51 CHAN5G(64, 5320),
52
53+ CHAN5G(68, 5340),
54+ CHAN5G(80, 5400),
55+ CHAN5G(84, 5420),
56+ CHAN5G(88, 5440),
57+ CHAN5G(92, 5460),
58+ CHAN5G(96, 5480),
59+
60 CHAN5G(100, 5500),
61 CHAN5G(104, 5520),
62 CHAN5G(108, 5540),
developer2157bf82023-06-26 02:27:49 +080063@@ -76,6 +83,11 @@ static const struct ieee80211_channel mt76_channels_5ghz[] = {
developer4c6b6002022-05-30 16:36:44 +080064 CHAN5G(169, 5845),
65 CHAN5G(173, 5865),
developer2157bf82023-06-26 02:27:49 +080066 CHAN5G(177, 5885),
developer4c6b6002022-05-30 16:36:44 +080067+
68+ CHAN5G(184, 4920),
69+ CHAN5G(188, 4940),
70+ CHAN5G(192, 4960),
71+ CHAN5G(196, 4980),
72 };
73
74 static const struct ieee80211_channel mt76_channels_6ghz[] = {
75diff --git a/mt76.h b/mt76.h
developere8045132023-08-04 14:40:12 +080076index c2ad06a..a5908de 100644
developer4c6b6002022-05-30 16:36:44 +080077--- a/mt76.h
78+++ b/mt76.h
developer2157bf82023-06-26 02:27:49 +080079@@ -657,6 +657,21 @@ struct mt76_testmode_ops {
developer4c6b6002022-05-30 16:36:44 +080080 int (*set_params)(struct mt76_phy *phy, struct nlattr **tb,
81 enum mt76_testmode_state new_state);
82 int (*dump_stats)(struct mt76_phy *phy, struct sk_buff *msg);
83+ int (*set_eeprom)(struct mt76_phy *phy, u32 offset, u8 *val, u8 action);
84+};
85+
86+struct mt76_testmode_entry_data {
87+ struct sk_buff *tx_skb;
88+
89+ u16 tx_mpdu_len;
90+ u8 tx_rate_idx;
91+ u8 tx_rate_nss;
92+ u8 tx_rate_ldpc;
93+
94+ u8 addr[3][ETH_ALEN];
95+ u8 aid;
96+ u8 ru_alloc;
97+ u8 ru_idx;
98 };
99
100 #define MT_TM_FW_RX_COUNT BIT(0)
developer2157bf82023-06-26 02:27:49 +0800101@@ -665,16 +680,11 @@ struct mt76_testmode_data {
developer4c6b6002022-05-30 16:36:44 +0800102 enum mt76_testmode_state state;
103
104 u32 param_set[DIV_ROUND_UP(NUM_MT76_TM_ATTRS, 32)];
105- struct sk_buff *tx_skb;
106
107 u32 tx_count;
108- u16 tx_mpdu_len;
109
110 u8 tx_rate_mode;
111- u8 tx_rate_idx;
112- u8 tx_rate_nss;
113 u8 tx_rate_sgi;
114- u8 tx_rate_ldpc;
115 u8 tx_rate_stbc;
116 u8 tx_ltf;
117
developer2157bf82023-06-26 02:27:49 +0800118@@ -690,10 +700,37 @@ struct mt76_testmode_data {
developer4c6b6002022-05-30 16:36:44 +0800119 u8 tx_power[4];
120 u8 tx_power_control;
121
122- u8 addr[3][ETH_ALEN];
123+ struct list_head tm_entry_list;
124+ struct mt76_wcid *cur_entry;
125+ u8 entry_num;
126+ union {
127+ struct mt76_testmode_entry_data ed;
128+ struct {
129+ /* must be the same as mt76_testmode_entry_data */
130+ struct sk_buff *tx_skb;
131+
132+ u16 tx_mpdu_len;
133+ u8 tx_rate_idx;
134+ u8 tx_rate_nss;
135+ u8 tx_rate_ldpc;
136+
137+ u8 addr[3][ETH_ALEN];
138+ u8 aid;
139+ u8 ru_alloc;
140+ u8 ru_idx;
141+ };
142+ };
143
144 u8 flag;
145
146+ struct {
147+ u8 type;
148+ u8 enable;
149+ } cfg;
150+
151+ u8 txbf_act;
152+ u16 txbf_param[8];
153+
154 u32 tx_pending;
155 u32 tx_queued;
156 u16 tx_queued_limit;
developer2157bf82023-06-26 02:27:49 +0800157@@ -1258,6 +1295,59 @@ static inline bool mt76_testmode_enabled(struct mt76_phy *phy)
developer4c6b6002022-05-30 16:36:44 +0800158 #endif
159 }
160
161+#ifdef CONFIG_NL80211_TESTMODE
162+static inline struct mt76_wcid *
163+mt76_testmode_first_entry(struct mt76_phy *phy)
164+{
165+ if (list_empty(&phy->test.tm_entry_list) && !phy->test.aid)
166+ return &phy->dev->global_wcid;
167+
168+ return list_first_entry(&phy->test.tm_entry_list,
169+ typeof(struct mt76_wcid),
170+ list);
171+}
172+
173+static inline struct mt76_testmode_entry_data *
174+mt76_testmode_entry_data(struct mt76_phy *phy, struct mt76_wcid *wcid)
175+{
176+ if (!wcid)
177+ return NULL;
178+ if (wcid == &phy->dev->global_wcid)
179+ return &phy->test.ed;
180+
181+ return (struct mt76_testmode_entry_data *)((u8 *)wcid +
182+ phy->hw->sta_data_size);
183+}
184+
185+#define mt76_tm_for_each_entry(phy, wcid, ed) \
186+ for (wcid = mt76_testmode_first_entry(phy), \
187+ ed = mt76_testmode_entry_data(phy, wcid); \
188+ ((phy->test.aid && \
189+ !list_entry_is_head(wcid, &phy->test.tm_entry_list, list)) || \
190+ (!phy->test.aid && wcid == &phy->dev->global_wcid)) && ed; \
191+ wcid = list_next_entry(wcid, list), \
192+ ed = mt76_testmode_entry_data(phy, wcid))
193+#endif
194+
195+static inline bool __mt76_is_testmode_skb(struct mt76_phy *phy,
196+ struct sk_buff *skb)
197+{
198+#ifdef CONFIG_NL80211_TESTMODE
199+ struct mt76_testmode_entry_data *ed = &phy->test.ed;
200+ struct mt76_wcid *wcid;
201+
202+ if (skb == ed->tx_skb)
203+ return true;
204+
205+ mt76_tm_for_each_entry(phy, wcid, ed)
206+ if (skb == ed->tx_skb)
207+ return true;
208+ return false;
209+#else
210+ return false;
211+#endif
212+}
213+
214 static inline bool mt76_is_testmode_skb(struct mt76_dev *dev,
215 struct sk_buff *skb,
216 struct ieee80211_hw **hw)
developer2157bf82023-06-26 02:27:49 +0800217@@ -1268,7 +1358,8 @@ static inline bool mt76_is_testmode_skb(struct mt76_dev *dev,
developer1d9fede2022-08-29 15:24:07 +0800218 for (i = 0; i < ARRAY_SIZE(dev->phys); i++) {
219 struct mt76_phy *phy = dev->phys[i];
220
221- if (phy && skb == phy->test.tx_skb) {
222+ if (phy && mt76_testmode_enabled(phy) &&
223+ __mt76_is_testmode_skb(phy, skb)) {
224 *hw = dev->phys[i]->hw;
225 return true;
226 }
developer2157bf82023-06-26 02:27:49 +0800227@@ -1370,7 +1461,8 @@ int mt76_testmode_cmd(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
developer4c6b6002022-05-30 16:36:44 +0800228 int mt76_testmode_dump(struct ieee80211_hw *hw, struct sk_buff *skb,
229 struct netlink_callback *cb, void *data, int len);
230 int mt76_testmode_set_state(struct mt76_phy *phy, enum mt76_testmode_state state);
231-int mt76_testmode_alloc_skb(struct mt76_phy *phy, u32 len);
232+int mt76_testmode_init_skb(struct mt76_phy *phy, u32 len,
233+ struct sk_buff **tx_skb, u8 (*addr)[ETH_ALEN]);
234
235 static inline void mt76_testmode_reset(struct mt76_phy *phy, bool disable)
236 {
237diff --git a/mt76_connac_mcu.c b/mt76_connac_mcu.c
developere8045132023-08-04 14:40:12 +0800238index a558c68..74b63f0 100644
developer4c6b6002022-05-30 16:36:44 +0800239--- a/mt76_connac_mcu.c
240+++ b/mt76_connac_mcu.c
developerbbd45e12023-05-19 08:22:06 +0800241@@ -395,6 +395,7 @@ void mt76_connac_mcu_sta_basic_tlv(struct mt76_dev *dev, struct sk_buff *skb,
developer4c6b6002022-05-30 16:36:44 +0800242 switch (vif->type) {
243 case NL80211_IFTYPE_MESH_POINT:
244 case NL80211_IFTYPE_AP:
245+ case NL80211_IFTYPE_MONITOR:
developerbbd45e12023-05-19 08:22:06 +0800246 if (vif->p2p && !is_mt7921(dev))
developer4c6b6002022-05-30 16:36:44 +0800247 conn_type = CONNECTION_P2P_GC;
248 else
developer2324aa22023-04-12 11:30:15 +0800249@@ -576,6 +577,9 @@ void mt76_connac_mcu_wtbl_generic_tlv(struct mt76_dev *dev,
developer4c6b6002022-05-30 16:36:44 +0800250 rx->rca2 = 1;
251 rx->rv = 1;
252
253+ if (vif->type == NL80211_IFTYPE_MONITOR)
254+ rx->rca1 = 0;
255+
256 if (!is_connac_v1(dev))
257 return;
258
259diff --git a/mt76_connac_mcu.h b/mt76_connac_mcu.h
developere8045132023-08-04 14:40:12 +0800260index 92e0b91..e3980c3 100644
developer4c6b6002022-05-30 16:36:44 +0800261--- a/mt76_connac_mcu.h
262+++ b/mt76_connac_mcu.h
developer2157bf82023-06-26 02:27:49 +0800263@@ -998,6 +998,7 @@ enum {
developer4c6b6002022-05-30 16:36:44 +0800264 MCU_EXT_EVENT_FW_LOG_2_HOST = 0x13,
265 MCU_EXT_EVENT_THERMAL_PROTECT = 0x22,
266 MCU_EXT_EVENT_ASSERT_DUMP = 0x23,
267+ MCU_EXT_EVENT_BF_STATUS_READ = 0x35,
268 MCU_EXT_EVENT_RDD_REPORT = 0x3a,
269 MCU_EXT_EVENT_CSA_NOTIFY = 0x4f,
developer2157bf82023-06-26 02:27:49 +0800270 MCU_EXT_EVENT_WA_TX_STAT = 0x74,
271@@ -1200,6 +1201,7 @@ enum {
developer4c6b6002022-05-30 16:36:44 +0800272 MCU_EXT_CMD_PHY_STAT_INFO = 0xad,
273 /* for vendor csi and air monitor */
274 MCU_EXT_CMD_SMESH_CTRL = 0xae,
275+ MCU_EXT_CMD_RX_STAT_USER_CTRL = 0xb3,
276 MCU_EXT_CMD_CERT_CFG = 0xb7,
277 MCU_EXT_CMD_CSI_CTRL = 0xc2,
278 };
developerc670d342023-04-06 15:04:19 +0800279diff --git a/mt7915/eeprom.c b/mt7915/eeprom.c
developere8045132023-08-04 14:40:12 +0800280index 76be730..f5ab331 100644
developerc670d342023-04-06 15:04:19 +0800281--- a/mt7915/eeprom.c
282+++ b/mt7915/eeprom.c
developerbbd45e12023-05-19 08:22:06 +0800283@@ -131,7 +131,7 @@ static int mt7915_eeprom_load(struct mt7915_dev *dev)
developerc670d342023-04-06 15:04:19 +0800284 /* read eeprom data from efuse */
285 block_num = DIV_ROUND_UP(eeprom_size, eeprom_blk_size);
286 for (i = 0; i < block_num; i++) {
287- ret = mt7915_mcu_get_eeprom(dev, i * eeprom_blk_size);
288+ ret = mt7915_mcu_get_eeprom(dev, i * eeprom_blk_size, NULL);
289 if (ret < 0)
290 return ret;
291 }
developer4c6b6002022-05-30 16:36:44 +0800292diff --git a/mt7915/init.c b/mt7915/init.c
developere8045132023-08-04 14:40:12 +0800293index 361c384..6d1c0f7 100644
developer4c6b6002022-05-30 16:36:44 +0800294--- a/mt7915/init.c
295+++ b/mt7915/init.c
developer849549c2023-08-02 17:26:48 +0800296@@ -730,7 +730,7 @@ static void mt7915_init_work(struct work_struct *work)
developer4c6b6002022-05-30 16:36:44 +0800297 struct mt7915_dev *dev = container_of(work, struct mt7915_dev,
298 init_work);
299
300- mt7915_mcu_set_eeprom(dev);
301+ mt7915_mcu_set_eeprom(dev, dev->flash_mode);
302 mt7915_mac_init(dev);
developer849549c2023-08-02 17:26:48 +0800303 mt7915_txbf_init(dev);
304 }
developer4c6b6002022-05-30 16:36:44 +0800305diff --git a/mt7915/mac.c b/mt7915/mac.c
developere8045132023-08-04 14:40:12 +0800306index 7ae34b7..6c9401d 100644
developer4c6b6002022-05-30 16:36:44 +0800307--- a/mt7915/mac.c
308+++ b/mt7915/mac.c
developer2157bf82023-06-26 02:27:49 +0800309@@ -604,16 +604,38 @@ mt7915_mac_write_txwi_tm(struct mt7915_phy *phy, __le32 *txwi,
developer4c6b6002022-05-30 16:36:44 +0800310 {
311 #ifdef CONFIG_NL80211_TESTMODE
312 struct mt76_testmode_data *td = &phy->mt76->test;
313+ struct mt76_testmode_entry_data *ed;
314+ struct mt76_wcid *wcid;
315 const struct ieee80211_rate *r;
316- u8 bw, mode, nss = td->tx_rate_nss;
317- u8 rate_idx = td->tx_rate_idx;
318+ u8 bw, mode, nss, rate_idx, ldpc;
319 u16 rateval = 0;
320 u32 val;
321 bool cck = false;
322 int band;
323
324- if (skb != phy->mt76->test.tx_skb)
325+ txwi[3] &= ~cpu_to_le32(MT_TXD3_SN_VALID);
326+ txwi[7] |= cpu_to_le32(FIELD_PREP(MT_TXD7_SPE_IDX,
327+ phy->test.spe_idx));
328+
329+ if (td->tx_rate_mode == MT76_TM_TX_MODE_HE_MU) {
330+ txwi[1] |= cpu_to_le32(BIT(18));
331+ txwi[2] = 0;
332+ txwi[3] &= ~cpu_to_le32(MT_TXD3_NO_ACK);
333+ le32p_replace_bits(&txwi[3], 0x1f, MT_TXD3_REM_TX_COUNT);
334+
developerf40484f2022-08-25 15:33:33 +0800335 return;
developer4c6b6002022-05-30 16:36:44 +0800336+ }
337+
338+ mt76_tm_for_each_entry(phy->mt76, wcid, ed)
339+ if (ed->tx_skb == skb)
340+ break;
341+
342+ if (!ed)
developerf40484f2022-08-25 15:33:33 +0800343+ return;
344+
developer4c6b6002022-05-30 16:36:44 +0800345+ nss = ed->tx_rate_nss;
346+ rate_idx = ed->tx_rate_idx;
347+ ldpc = ed->tx_rate_ldpc;
developerf40484f2022-08-25 15:33:33 +0800348
developer4c6b6002022-05-30 16:36:44 +0800349 switch (td->tx_rate_mode) {
350 case MT76_TM_TX_MODE_HT:
developer2157bf82023-06-26 02:27:49 +0800351@@ -644,7 +666,7 @@ mt7915_mac_write_txwi_tm(struct mt7915_phy *phy, __le32 *txwi,
developer4feb1012023-01-30 17:29:07 +0800352 rate_idx += 4;
353
354 r = &phy->mt76->hw->wiphy->bands[band]->bitrates[rate_idx];
355- val = cck ? r->hw_value_short : r->hw_value;
356+ val = r->hw_value;
357
358 mode = val >> 8;
359 rate_idx = val & 0xff;
developer2157bf82023-06-26 02:27:49 +0800360@@ -703,13 +725,14 @@ mt7915_mac_write_txwi_tm(struct mt7915_phy *phy, __le32 *txwi,
developer4c6b6002022-05-30 16:36:44 +0800361 if (mode >= MT_PHY_TYPE_HE_SU)
362 val |= FIELD_PREP(MT_TXD6_HELTF, td->tx_ltf);
363
364- if (td->tx_rate_ldpc || (bw > 0 && mode >= MT_PHY_TYPE_HE_SU))
365+ if (ldpc || (bw > 0 && mode >= MT_PHY_TYPE_HE_SU))
366 val |= MT_TXD6_LDPC;
367
developerf40484f2022-08-25 15:33:33 +0800368 txwi[3] &= ~cpu_to_le32(MT_TXD3_SN_VALID);
developer4c6b6002022-05-30 16:36:44 +0800369+ if (phy->test.bf_en)
370+ val |= MT_TXD6_TX_IBF | MT_TXD6_TX_EBF;
371+
372 txwi[6] |= cpu_to_le32(val);
373- txwi[7] |= cpu_to_le32(FIELD_PREP(MT_TXD7_SPE_IDX,
374- phy->test.spe_idx));
375 #endif
376 }
377
developer2157bf82023-06-26 02:27:49 +0800378@@ -1415,7 +1438,7 @@ mt7915_mac_restart(struct mt7915_dev *dev)
developer356ecec2022-11-14 10:25:04 +0800379 goto out;
380
381 /* set the necessary init items */
382- ret = mt7915_mcu_set_eeprom(dev);
383+ ret = mt7915_mcu_set_eeprom(dev, dev->flash_mode);
384 if (ret)
385 goto out;
386
developer4c6b6002022-05-30 16:36:44 +0800387diff --git a/mt7915/main.c b/mt7915/main.c
developere8045132023-08-04 14:40:12 +0800388index 9b54ba1..d7bcd5f 100644
developer4c6b6002022-05-30 16:36:44 +0800389--- a/mt7915/main.c
390+++ b/mt7915/main.c
developer9851a292022-12-15 17:33:43 +0800391@@ -238,7 +238,7 @@ static int mt7915_add_interface(struct ieee80211_hw *hw,
developer4c6b6002022-05-30 16:36:44 +0800392 mvif->phy = phy;
developereb6a0182022-12-12 18:53:32 +0800393 mvif->mt76.band_idx = phy->mt76->band_idx;
developer4c6b6002022-05-30 16:36:44 +0800394
395- mvif->mt76.wmm_idx = vif->type != NL80211_IFTYPE_AP;
396+ mvif->mt76.wmm_idx = (vif->type != NL80211_IFTYPE_AP && vif->type != NL80211_IFTYPE_MONITOR);
397 if (ext_phy)
398 mvif->mt76.wmm_idx += 2;
399
400diff --git a/mt7915/mcu.c b/mt7915/mcu.c
developere8045132023-08-04 14:40:12 +0800401index 1f5f938..6a5f204 100644
developer4c6b6002022-05-30 16:36:44 +0800402--- a/mt7915/mcu.c
403+++ b/mt7915/mcu.c
developer2157bf82023-06-26 02:27:49 +0800404@@ -389,6 +389,11 @@ mt7915_mcu_rx_ext_event(struct mt7915_dev *dev, struct sk_buff *skb)
developer4c6b6002022-05-30 16:36:44 +0800405 case MCU_EXT_EVENT_BCC_NOTIFY:
406 mt7915_mcu_rx_bcc_notify(dev, skb);
407 break;
408+#ifdef CONFIG_NL80211_TESTMODE
409+ case MCU_EXT_EVENT_BF_STATUS_READ:
410+ mt7915_tm_txbf_status_read(dev, skb);
411+ break;
412+#endif
413 default:
414 break;
415 }
developer2157bf82023-06-26 02:27:49 +0800416@@ -420,6 +425,7 @@ void mt7915_mcu_rx_event(struct mt7915_dev *dev, struct sk_buff *skb)
417 rxd->ext_eid == MCU_EXT_EVENT_ASSERT_DUMP ||
418 rxd->ext_eid == MCU_EXT_EVENT_PS_SYNC ||
419 rxd->ext_eid == MCU_EXT_EVENT_BCC_NOTIFY ||
420+ rxd->ext_eid == MCU_EXT_EVENT_BF_STATUS_READ ||
421 !rxd->seq) &&
422 !(rxd->eid == MCU_CMD_EXT_CID &&
423 rxd->ext_eid == MCU_EXT_EVENT_WA_TX_STAT))
developer8f0d89b2023-07-28 07:16:44 +0800424@@ -2755,7 +2761,8 @@ int mt7915_mcu_set_chan_info(struct mt7915_phy *phy, int cmd)
developer62b3f572023-06-07 17:39:27 +0800425 }
426 #endif
427
428- if (mt76_connac_spe_idx(phy->mt76->antenna_mask))
429+ if (mt76_connac_spe_idx(phy->mt76->antenna_mask) &&
430+ !mt76_testmode_enabled(phy->mt76))
431 req.tx_path_num = fls(phy->mt76->antenna_mask);
432
433 if (dev->mt76.hw->conf.flags & IEEE80211_CONF_MONITOR)
developer8f0d89b2023-07-28 07:16:44 +0800434@@ -2823,21 +2830,21 @@ static int mt7915_mcu_set_eeprom_flash(struct mt7915_dev *dev)
developer4c6b6002022-05-30 16:36:44 +0800435 return 0;
436 }
437
438-int mt7915_mcu_set_eeprom(struct mt7915_dev *dev)
439+int mt7915_mcu_set_eeprom(struct mt7915_dev *dev, bool flash_mode)
440 {
441 struct mt7915_mcu_eeprom req = {
442 .buffer_mode = EE_MODE_EFUSE,
443 .format = EE_FORMAT_WHOLE,
444 };
445
446- if (dev->flash_mode)
447+ if (flash_mode)
448 return mt7915_mcu_set_eeprom_flash(dev);
449
450 return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(EFUSE_BUFFER_MODE),
developerc670d342023-04-06 15:04:19 +0800451 &req, sizeof(req), true);
452 }
453
454-int mt7915_mcu_get_eeprom(struct mt7915_dev *dev, u32 offset)
455+int mt7915_mcu_get_eeprom(struct mt7915_dev *dev, u32 offset, u8 *read_buf)
456 {
457 struct mt7915_mcu_eeprom_info req = {
458 .addr = cpu_to_le32(round_down(offset,
developer8f0d89b2023-07-28 07:16:44 +0800459@@ -2846,7 +2853,7 @@ int mt7915_mcu_get_eeprom(struct mt7915_dev *dev, u32 offset)
developerc670d342023-04-06 15:04:19 +0800460 struct mt7915_mcu_eeprom_info *res;
461 struct sk_buff *skb;
462 int ret;
463- u8 *buf;
464+ u8 *buf = read_buf;
465
466 ret = mt76_mcu_send_and_get_msg(&dev->mt76,
467 MCU_EXT_QUERY(EFUSE_ACCESS),
developer8f0d89b2023-07-28 07:16:44 +0800468@@ -2855,8 +2862,11 @@ int mt7915_mcu_get_eeprom(struct mt7915_dev *dev, u32 offset)
developerc670d342023-04-06 15:04:19 +0800469 return ret;
470
471 res = (struct mt7915_mcu_eeprom_info *)skb->data;
472- buf = dev->mt76.eeprom.data + le32_to_cpu(res->addr);
473+
474+ if (!buf)
475+ buf = dev->mt76.eeprom.data + le32_to_cpu(res->addr);
476 memcpy(buf, res->data, MT7915_EEPROM_BLOCK_SIZE);
477+
478 dev_kfree_skb(skb);
479
480 return 0;
developer4c6b6002022-05-30 16:36:44 +0800481diff --git a/mt7915/mcu.h b/mt7915/mcu.h
developere8045132023-08-04 14:40:12 +0800482index c15b4b7..9982735 100644
developer4c6b6002022-05-30 16:36:44 +0800483--- a/mt7915/mcu.h
484+++ b/mt7915/mcu.h
developerf64861f2022-06-22 11:44:53 +0800485@@ -8,10 +8,15 @@
developer4c6b6002022-05-30 16:36:44 +0800486
487 enum {
488 MCU_ATE_SET_TRX = 0x1,
489+ MCU_ATE_SET_TSSI = 0x5,
490+ MCU_ATE_SET_DPD = 0x6,
491+ MCU_ATE_SET_RATE_POWER_OFFSET = 0x7,
492+ MCU_ATE_SET_THERMAL_COMP = 0x8,
493 MCU_ATE_SET_FREQ_OFFSET = 0xa,
494 MCU_ATE_SET_PHY_COUNT = 0x11,
495 MCU_ATE_SET_SLOT_TIME = 0x13,
496 MCU_ATE_CLEAN_TXQUEUE = 0x1c,
497+ MCU_ATE_SET_MU_RX_AID = 0x1e,
498 };
499
developerf64861f2022-06-22 11:44:53 +0800500 struct mt7915_mcu_thermal_ctrl {
developerdec31212023-05-02 16:45:27 +0800501@@ -527,6 +532,12 @@ enum {
developer4c6b6002022-05-30 16:36:44 +0800502
503 enum {
504 MT_BF_SOUNDING_ON = 1,
505+ MT_BF_DATA_PACKET_APPLY = 2,
506+ MT_BF_PFMU_TAG_READ = 5,
507+ MT_BF_PFMU_TAG_WRITE = 6,
508+ MT_BF_PHASE_CAL = 14,
509+ MT_BF_IBF_PHASE_COMP = 15,
510+ MT_BF_PROFILE_WRITE_ALL = 17,
511 MT_BF_TYPE_UPDATE = 20,
512 MT_BF_MODULE_UPDATE = 25
513 };
developerdec31212023-05-02 16:45:27 +0800514@@ -775,10 +786,20 @@ struct mt7915_muru {
developer4c6b6002022-05-30 16:36:44 +0800515 #define MURU_OFDMA_SCH_TYPE_UL BIT(1)
516
developerf64861f2022-06-22 11:44:53 +0800517 /* Common Config */
developer4c6b6002022-05-30 16:36:44 +0800518-#define MURU_COMM_PPDU_FMT BIT(0)
519-#define MURU_COMM_SCH_TYPE BIT(1)
520-#define MURU_COMM_SET (MURU_COMM_PPDU_FMT | MURU_COMM_SCH_TYPE)
developer4c6b6002022-05-30 16:36:44 +0800521-/* DL&UL User config*/
developer4c6b6002022-05-30 16:36:44 +0800522+/* #define MURU_COMM_PPDU_FMT BIT(0) */
523+/* #define MURU_COMM_SCH_TYPE BIT(1) */
524+/* #define MURU_COMM_SET (MURU_COMM_PPDU_FMT | MURU_COMM_SCH_TYPE) */
developer4721e252022-06-21 16:41:28 +0800525+#define MURU_COMM_PPDU_FMT BIT(0)
526+#define MURU_COMM_SCH_TYPE BIT(1)
527+#define MURU_COMM_BAND BIT(2)
528+#define MURU_COMM_WMM BIT(3)
529+#define MURU_COMM_SPE_IDX BIT(4)
530+#define MURU_COMM_PROC_TYPE BIT(5)
developerdec31212023-05-02 16:45:27 +0800531+#define MURU_COMM_SET (MURU_COMM_PPDU_FMT | MURU_COMM_SCH_TYPE)
532+#define MURU_COMM_SET_TM (MURU_COMM_PPDU_FMT | MURU_COMM_BAND | \
533+ MURU_COMM_WMM | MURU_COMM_SPE_IDX)
developer4c6b6002022-05-30 16:36:44 +0800534+
535+/* DL&UL User config */
536 #define MURU_USER_CNT BIT(4)
537
538 enum {
539diff --git a/mt7915/mmio.c b/mt7915/mmio.c
developere8045132023-08-04 14:40:12 +0800540index b23679a..6505d76 100644
developer4c6b6002022-05-30 16:36:44 +0800541--- a/mt7915/mmio.c
542+++ b/mt7915/mmio.c
developerc04f5402023-02-03 09:22:26 +0800543@@ -134,6 +134,7 @@ static const u32 mt7915_offs[] = {
developer4c6b6002022-05-30 16:36:44 +0800544 [ARB_DRNGR0] = 0x194,
545 [ARB_SCR] = 0x080,
546 [RMAC_MIB_AIRTIME14] = 0x3b8,
547+ [AGG_AALCR0] = 0x048,
548 [AGG_AWSCR0] = 0x05c,
549 [AGG_PCR0] = 0x06c,
550 [AGG_ACR0] = 0x084,
developerc04f5402023-02-03 09:22:26 +0800551@@ -209,6 +210,7 @@ static const u32 mt7916_offs[] = {
developer4c6b6002022-05-30 16:36:44 +0800552 [ARB_DRNGR0] = 0x1e0,
553 [ARB_SCR] = 0x000,
554 [RMAC_MIB_AIRTIME14] = 0x0398,
555+ [AGG_AALCR0] = 0x028,
556 [AGG_AWSCR0] = 0x030,
557 [AGG_PCR0] = 0x040,
558 [AGG_ACR0] = 0x054,
559diff --git a/mt7915/mt7915.h b/mt7915/mt7915.h
developere8045132023-08-04 14:40:12 +0800560index bf0f7de..c91415f 100644
developer4c6b6002022-05-30 16:36:44 +0800561--- a/mt7915/mt7915.h
562+++ b/mt7915/mt7915.h
developer8f0d89b2023-07-28 07:16:44 +0800563@@ -272,6 +272,9 @@ struct mt7915_phy {
developer4c6b6002022-05-30 16:36:44 +0800564 u8 last_snr;
565
566 u8 spe_idx;
567+
568+ bool bf_en;
569+ bool bf_ever_en;
570 } test;
571 #endif
572
developer8f0d89b2023-07-28 07:16:44 +0800573@@ -368,6 +371,14 @@ struct mt7915_dev {
developer4c6b6002022-05-30 16:36:44 +0800574 void __iomem *dcm;
575 void __iomem *sku;
576
577+#ifdef CONFIG_NL80211_TESTMODE
578+ struct {
579+ void *txbf_phase_cal;
580+ void *txbf_pfmu_data;
581+ void *txbf_pfmu_tag;
582+ } test;
583+#endif
584+
585 #ifdef MTK_DEBUG
586 u16 wlan_idx;
587 struct {
developer849549c2023-08-02 17:26:48 +0800588@@ -539,8 +550,8 @@ int mt7915_mcu_set_fixed_rate_ctrl(struct mt7915_dev *dev,
developer4c6b6002022-05-30 16:36:44 +0800589 struct ieee80211_vif *vif,
590 struct ieee80211_sta *sta,
591 void *data, u32 field);
592-int mt7915_mcu_set_eeprom(struct mt7915_dev *dev);
developerc670d342023-04-06 15:04:19 +0800593-int mt7915_mcu_get_eeprom(struct mt7915_dev *dev, u32 offset);
developer4c6b6002022-05-30 16:36:44 +0800594+int mt7915_mcu_set_eeprom(struct mt7915_dev *dev, bool flash_mode);
developerc670d342023-04-06 15:04:19 +0800595+int mt7915_mcu_get_eeprom(struct mt7915_dev *dev, u32 offset, u8 *read_buf);
developer4c6b6002022-05-30 16:36:44 +0800596 int mt7915_mcu_get_eeprom_free_block(struct mt7915_dev *dev, u8 *block_num);
597 int mt7915_mcu_set_mac(struct mt7915_dev *dev, int band, bool enable,
developerc670d342023-04-06 15:04:19 +0800598 bool hdr_trans);
developer849549c2023-08-02 17:26:48 +0800599@@ -579,6 +590,7 @@ int mt7915_mcu_fw_log_2_host(struct mt7915_dev *dev, u8 type, u8 ctrl);
developer4c6b6002022-05-30 16:36:44 +0800600 int mt7915_mcu_fw_dbg_ctrl(struct mt7915_dev *dev, u32 module, u8 level);
601 void mt7915_mcu_rx_event(struct mt7915_dev *dev, struct sk_buff *skb);
602 void mt7915_mcu_exit(struct mt7915_dev *dev);
603+int mt7915_tm_txbf_status_read(struct mt7915_dev *dev, struct sk_buff *skb);
604
605 static inline u16 mt7915_wtbl_size(struct mt7915_dev *dev)
606 {
607diff --git a/mt7915/regs.h b/mt7915/regs.h
developere8045132023-08-04 14:40:12 +0800608index 038596c..428f482 100644
developer4c6b6002022-05-30 16:36:44 +0800609--- a/mt7915/regs.h
610+++ b/mt7915/regs.h
developer144824b2022-11-25 21:27:43 +0800611@@ -62,6 +62,7 @@ enum offs_rev {
developer4c6b6002022-05-30 16:36:44 +0800612 ARB_DRNGR0,
613 ARB_SCR,
614 RMAC_MIB_AIRTIME14,
615+ AGG_AALCR0,
616 AGG_AWSCR0,
617 AGG_PCR0,
618 AGG_ACR0,
developer2157bf82023-06-26 02:27:49 +0800619@@ -485,6 +486,8 @@ enum offs_rev {
developer4c6b6002022-05-30 16:36:44 +0800620 #define MT_WF_AGG_BASE(_band) ((_band) ? 0x820f2000 : 0x820e2000)
621 #define MT_WF_AGG(_band, ofs) (MT_WF_AGG_BASE(_band) + (ofs))
622
623+#define MT_AGG_AALCR0(_band, _n) MT_WF_AGG(_band, (__OFFS(AGG_AALCR0) + \
developer62b3f572023-06-07 17:39:27 +0800624+ (_n) * 4))
developer4c6b6002022-05-30 16:36:44 +0800625 #define MT_AGG_AWSCR0(_band, _n) MT_WF_AGG(_band, (__OFFS(AGG_AWSCR0) + \
626 (_n) * 4))
627 #define MT_AGG_PCR0(_band, _n) MT_WF_AGG(_band, (__OFFS(AGG_PCR0) + \
628diff --git a/mt7915/testmode.c b/mt7915/testmode.c
developere8045132023-08-04 14:40:12 +0800629index 4693919..e5d0ef9 100644
developer4c6b6002022-05-30 16:36:44 +0800630--- a/mt7915/testmode.c
631+++ b/mt7915/testmode.c
632@@ -9,6 +9,9 @@
633 enum {
634 TM_CHANGED_TXPOWER,
635 TM_CHANGED_FREQ_OFFSET,
636+ TM_CHANGED_AID,
637+ TM_CHANGED_CFG,
638+ TM_CHANGED_TXBF_ACT,
639
640 /* must be last */
641 NUM_TM_CHANGED
642@@ -17,6 +20,9 @@ enum {
643 static const u8 tm_change_map[] = {
644 [TM_CHANGED_TXPOWER] = MT76_TM_ATTR_TX_POWER,
645 [TM_CHANGED_FREQ_OFFSET] = MT76_TM_ATTR_FREQ_OFFSET,
646+ [TM_CHANGED_AID] = MT76_TM_ATTR_AID,
647+ [TM_CHANGED_CFG] = MT76_TM_ATTR_CFG,
648+ [TM_CHANGED_TXBF_ACT] = MT76_TM_ATTR_TXBF_ACT,
649 };
650
651 struct reg_band {
developer62b3f572023-06-07 17:39:27 +0800652@@ -33,6 +39,57 @@ struct reg_band {
developer4c6b6002022-05-30 16:36:44 +0800653 #define TM_REG_MAX_ID 20
654 static struct reg_band reg_backup_list[TM_REG_MAX_ID];
655
developerc6f56bb2022-06-14 18:36:30 +0800656+static void mt7915_tm_update_entry(struct mt7915_phy *phy);
657+
developer4c6b6002022-05-30 16:36:44 +0800658+static u8 mt7915_tm_chan_bw(enum nl80211_chan_width width)
659+{
660+ static const u8 width_to_bw[] = {
661+ [NL80211_CHAN_WIDTH_40] = TM_CBW_40MHZ,
662+ [NL80211_CHAN_WIDTH_80] = TM_CBW_80MHZ,
663+ [NL80211_CHAN_WIDTH_80P80] = TM_CBW_8080MHZ,
664+ [NL80211_CHAN_WIDTH_160] = TM_CBW_160MHZ,
665+ [NL80211_CHAN_WIDTH_5] = TM_CBW_5MHZ,
666+ [NL80211_CHAN_WIDTH_10] = TM_CBW_10MHZ,
667+ [NL80211_CHAN_WIDTH_20] = TM_CBW_20MHZ,
668+ [NL80211_CHAN_WIDTH_20_NOHT] = TM_CBW_20MHZ,
669+ };
670+
671+ if (width >= ARRAY_SIZE(width_to_bw))
672+ return 0;
673+
674+ return width_to_bw[width];
675+}
676+
developer62b3f572023-06-07 17:39:27 +0800677+static int
678+mt7915_tm_check_antenna(struct mt7915_phy *phy)
679+{
680+ struct mt76_testmode_data *td = &phy->mt76->test;
681+ struct mt7915_dev *dev = phy->dev;
682+ u8 band_idx = phy->mt76->band_idx;
683+ u32 chainmask = phy->mt76->chainmask;
684+
685+ chainmask = chainmask >> (dev->chainshift * band_idx);
686+ if (td->tx_antenna_mask & ~chainmask) {
687+ dev_err(dev->mt76.dev,
688+ "tx antenna mask %d exceeds hardware limitation (chainmask %d)\n",
689+ td->tx_antenna_mask, chainmask);
690+ return -EINVAL;
691+ }
692+
693+ return 0;
694+}
695+
developer4c6b6002022-05-30 16:36:44 +0800696+static void
697+mt7915_tm_update_channel(struct mt7915_phy *phy)
698+{
699+ mutex_unlock(&phy->dev->mt76.mutex);
700+ mt7915_set_channel(phy);
701+ mutex_lock(&phy->dev->mt76.mutex);
702+
703+ mt7915_mcu_set_chan_info(phy, MCU_EXT_CMD(SET_RX_PATH));
developerc6f56bb2022-06-14 18:36:30 +0800704+
705+ mt7915_tm_update_entry(phy);
developer4c6b6002022-05-30 16:36:44 +0800706+}
707
708 static int
709 mt7915_tm_set_tx_power(struct mt7915_phy *phy)
developer62b3f572023-06-07 17:39:27 +0800710@@ -119,18 +176,28 @@ mt7915_tm_set_trx(struct mt7915_phy *phy, int type, bool en)
developer4c6b6002022-05-30 16:36:44 +0800711 }
712
713 static int
714-mt7915_tm_clean_hwq(struct mt7915_phy *phy, u8 wcid)
715+mt7915_tm_clean_hwq(struct mt7915_phy *phy)
716 {
717+ struct mt76_testmode_entry_data *ed;
718+ struct mt76_wcid *wcid;
719 struct mt7915_dev *dev = phy->dev;
720 struct mt7915_tm_cmd req = {
721 .testmode_en = 1,
722 .param_idx = MCU_ATE_CLEAN_TXQUEUE,
723- .param.clean.wcid = wcid,
developereb6a0182022-12-12 18:53:32 +0800724 .param.clean.band = phy->mt76->band_idx,
developer4c6b6002022-05-30 16:36:44 +0800725 };
726
727- return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(ATE_CTRL), &req,
728- sizeof(req), false);
729+ mt76_tm_for_each_entry(phy->mt76, wcid, ed) {
730+ int ret;
731+
732+ req.param.clean.wcid = wcid->idx;
733+ ret = mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(ATE_CTRL),
734+ &req, sizeof(req), false);
735+ if (ret)
736+ return ret;
737+ }
738+
739+ return 0;
740 }
741
742 static int
developer62b3f572023-06-07 17:39:27 +0800743@@ -141,7 +208,7 @@ mt7915_tm_set_phy_count(struct mt7915_phy *phy, u8 control)
developereb6a0182022-12-12 18:53:32 +0800744 .testmode_en = 1,
745 .param_idx = MCU_ATE_SET_PHY_COUNT,
746 .param.cfg.enable = control,
747- .param.cfg.band = phy != &dev->phy,
748+ .param.cfg.band = phy->mt76->band_idx,
749 };
750
751 return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(ATE_CTRL), &req,
developere8045132023-08-04 14:40:12 +0800752@@ -182,12 +249,739 @@ mt7915_tm_set_tam_arb(struct mt7915_phy *phy, bool enable, bool mu)
developer4c6b6002022-05-30 16:36:44 +0800753 return mt7915_mcu_set_muru_ctrl(dev, MURU_SET_ARB_OP_MODE, op_mode);
754 }
755
756+static int
757+mt7915_tm_set_cfg(struct mt7915_phy *phy)
758+{
759+ static const u8 cfg_cmd[] = {
760+ [MT76_TM_CFG_TSSI] = MCU_ATE_SET_TSSI,
761+ [MT76_TM_CFG_DPD] = MCU_ATE_SET_DPD,
762+ [MT76_TM_CFG_RATE_POWER_OFFSET] = MCU_ATE_SET_RATE_POWER_OFFSET,
763+ [MT76_TM_CFG_THERMAL_COMP] = MCU_ATE_SET_THERMAL_COMP,
764+ };
765+ struct mt76_testmode_data *td = &phy->mt76->test;
766+ struct mt7915_dev *dev = phy->dev;
767+ struct mt7915_tm_cmd req = {
768+ .testmode_en = !(phy->mt76->test.state == MT76_TM_STATE_OFF),
769+ .param_idx = cfg_cmd[td->cfg.type],
770+ .param.cfg.enable = td->cfg.enable,
developereb6a0182022-12-12 18:53:32 +0800771+ .param.cfg.band = phy->mt76->band_idx,
developer4c6b6002022-05-30 16:36:44 +0800772+ };
773+
774+ return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(ATE_CTRL), &req,
775+ sizeof(req), false);
776+}
777+
778+static int
779+mt7915_tm_add_txbf(struct mt7915_phy *phy, struct ieee80211_vif *vif,
780+ struct ieee80211_sta *sta, u8 pfmu_idx, u8 nr,
781+ u8 nc, bool ebf)
782+{
783+ struct mt7915_vif *mvif = (struct mt7915_vif *)vif->drv_priv;
784+ struct mt7915_sta *msta = (struct mt7915_sta *)sta->drv_priv;
785+ struct mt7915_dev *dev = phy->dev;
786+ struct sk_buff *skb;
787+ struct sta_rec_bf *bf;
788+ struct tlv *tlv;
789+ u8 ndp_rate;
790+
791+ if (nr == 1)
792+ ndp_rate = 8;
793+ else if (nr == 2)
794+ ndp_rate = 16;
795+ else
796+ ndp_rate = 24;
797+
798+ skb = mt76_connac_mcu_alloc_sta_req(&dev->mt76, &mvif->mt76,
799+ &msta->wcid);
800+ if (IS_ERR(skb))
801+ return PTR_ERR(skb);
802+
803+ tlv = mt76_connac_mcu_add_tlv(skb, STA_REC_BF, sizeof(*bf));
804+ bf = (struct sta_rec_bf *)tlv;
805+
806+ bf->pfmu = cpu_to_le16(pfmu_idx);
807+ bf->sounding_phy = 1;
808+ bf->bf_cap = ebf;
809+ bf->ncol = nc;
810+ bf->nrow = nr;
811+ bf->ndp_rate = ndp_rate;
812+ bf->ibf_timeout = 0xff;
813+ bf->tx_mode = MT_PHY_TYPE_HT;
814+
815+ if (ebf) {
816+ bf->mem[0].row = 0;
817+ bf->mem[1].row = 1;
818+ bf->mem[2].row = 2;
819+ bf->mem[3].row = 3;
820+ } else {
821+ bf->mem[0].row = 4;
822+ bf->mem[1].row = 5;
823+ bf->mem[2].row = 6;
824+ bf->mem[3].row = 7;
825+ }
826+
827+ return mt76_mcu_skb_send_msg(&dev->mt76, skb,
828+ MCU_EXT_CMD(STA_REC_UPDATE), true);
829+}
830+
831+static int
832+mt7915_tm_entry_add(struct mt7915_phy *phy, u8 aid)
833+{
834+ struct mt76_testmode_data *td = &phy->mt76->test;
835+ struct mt76_testmode_entry_data *ed;
836+ struct ieee80211_sband_iftype_data *sdata;
837+ struct ieee80211_supported_band *sband;
838+ struct ieee80211_sta *sta;
839+ struct mt7915_sta *msta;
840+ int tid, ret;
841+
842+ if (td->entry_num >= MT76_TM_MAX_ENTRY_NUM)
843+ return -EINVAL;
844+
845+ sta = kzalloc(sizeof(*sta) + phy->mt76->hw->sta_data_size +
846+ sizeof(*ed), GFP_KERNEL);
847+ if (!sta)
848+ return -ENOMEM;
849+
850+ msta = (struct mt7915_sta *)sta->drv_priv;
851+ ed = mt76_testmode_entry_data(phy->mt76, &msta->wcid);
852+ memcpy(ed, &td->ed, sizeof(*ed));
853+
854+ if (phy->mt76->chandef.chan->band == NL80211_BAND_5GHZ) {
855+ sband = &phy->mt76->sband_5g.sband;
856+ sdata = phy->iftype[NL80211_BAND_5GHZ];
857+ } else if (phy->mt76->chandef.chan->band == NL80211_BAND_6GHZ) {
858+ sband = &phy->mt76->sband_6g.sband;
859+ sdata = phy->iftype[NL80211_BAND_6GHZ];
860+ } else {
861+ sband = &phy->mt76->sband_2g.sband;
862+ sdata = phy->iftype[NL80211_BAND_2GHZ];
863+ }
864+
865+ memcpy(sta->addr, ed->addr[0], ETH_ALEN);
866+ if (phy->test.bf_en) {
867+ u8 addr[ETH_ALEN] = {0x00, 0x11, 0x11, 0x11, 0x11, 0x11};
868+
869+ memcpy(sta->addr, addr, ETH_ALEN);
870+ }
871+
872+ if (td->tx_rate_mode >= MT76_TM_TX_MODE_HT)
developer6100db22023-04-05 13:22:26 +0800873+ memcpy(&sta->deflink.ht_cap, &sband->ht_cap, sizeof(sta->deflink.ht_cap));
developer4c6b6002022-05-30 16:36:44 +0800874+ if (td->tx_rate_mode >= MT76_TM_TX_MODE_VHT)
developer6100db22023-04-05 13:22:26 +0800875+ memcpy(&sta->deflink.vht_cap, &sband->vht_cap, sizeof(sta->deflink.vht_cap));
developer4c6b6002022-05-30 16:36:44 +0800876+ if (td->tx_rate_mode >= MT76_TM_TX_MODE_HE_SU)
developer6100db22023-04-05 13:22:26 +0800877+ memcpy(&sta->deflink.he_cap, &sdata[NL80211_IFTYPE_STATION].he_cap,
878+ sizeof(sta->deflink.he_cap));
developer4c6b6002022-05-30 16:36:44 +0800879+ sta->aid = aid;
880+ sta->wme = 1;
881+
882+ ret = mt7915_mac_sta_add(&phy->dev->mt76, phy->monitor_vif, sta);
883+ if (ret) {
884+ kfree(sta);
885+ return ret;
886+ }
887+
888+ /* prevent from starting tx ba session */
889+ for (tid = 0; tid < 8; tid++)
developer2157bf82023-06-26 02:27:49 +0800890+ set_bit(tid, &msta->wcid.ampdu_state);
developer4c6b6002022-05-30 16:36:44 +0800891+
892+ list_add_tail(&msta->wcid.list, &td->tm_entry_list);
893+ td->entry_num++;
894+
895+ return 0;
896+}
897+
898+static void
899+mt7915_tm_entry_remove(struct mt7915_phy *phy, u8 aid)
900+{
901+ struct mt76_testmode_data *td = &phy->mt76->test;
902+ struct mt76_wcid *wcid, *tmp;
903+
904+ if (list_empty(&td->tm_entry_list))
905+ return;
906+
907+ list_for_each_entry_safe(wcid, tmp, &td->tm_entry_list, list) {
developerc6f56bb2022-06-14 18:36:30 +0800908+ struct mt76_testmode_entry_data *ed;
developer4c6b6002022-05-30 16:36:44 +0800909+ struct mt7915_dev *dev = phy->dev;
developerc6f56bb2022-06-14 18:36:30 +0800910+ struct ieee80211_sta *sta;
developer4c6b6002022-05-30 16:36:44 +0800911+
developerc6f56bb2022-06-14 18:36:30 +0800912+ ed = mt76_testmode_entry_data(phy->mt76, wcid);
913+ if (aid && ed->aid != aid)
914+ continue;
915+
916+ sta = wcid_to_sta(wcid);
developer4c6b6002022-05-30 16:36:44 +0800917+ mt7915_mac_sta_remove(&dev->mt76, phy->monitor_vif, sta);
918+ mt76_wcid_mask_clear(dev->mt76.wcid_mask, wcid->idx);
919+
920+ list_del_init(&wcid->list);
921+ kfree(sta);
922+ phy->mt76->test.entry_num--;
923+ }
924+}
925+
926+static int
927+mt7915_tm_set_entry(struct mt7915_phy *phy)
928+{
929+ struct mt76_testmode_data *td = &phy->mt76->test;
930+ struct mt76_testmode_entry_data *ed;
931+ struct mt76_wcid *wcid;
932+
933+ if (!td->aid) {
934+ if (td->state > MT76_TM_STATE_IDLE)
935+ mt76_testmode_set_state(phy->mt76, MT76_TM_STATE_IDLE);
936+ mt7915_tm_entry_remove(phy, td->aid);
937+ return 0;
938+ }
939+
940+ mt76_tm_for_each_entry(phy->mt76, wcid, ed) {
941+ if (ed->aid == td->aid) {
942+ struct sk_buff *skb;
943+
944+ local_bh_disable();
945+ skb = ed->tx_skb;
946+ memcpy(ed, &td->ed, sizeof(*ed));
947+ ed->tx_skb = skb;
948+ local_bh_enable();
949+
950+ return 0;
951+ }
952+ }
953+
954+ return mt7915_tm_entry_add(phy, td->aid);
955+}
956+
developerc6f56bb2022-06-14 18:36:30 +0800957+static void
958+mt7915_tm_update_entry(struct mt7915_phy *phy)
959+{
960+ struct mt76_testmode_data *td = &phy->mt76->test;
961+ struct mt76_testmode_entry_data *ed, tmp;
962+ struct mt76_wcid *wcid, *last;
963+
964+ if (!td->aid || phy->test.bf_en)
965+ return;
966+
967+ memcpy(&tmp, &td->ed, sizeof(tmp));
968+ last = list_last_entry(&td->tm_entry_list,
969+ struct mt76_wcid, list);
970+
971+ mt76_tm_for_each_entry(phy->mt76, wcid, ed) {
972+ memcpy(&td->ed, ed, sizeof(td->ed));
973+ mt7915_tm_entry_remove(phy, td->aid);
974+ mt7915_tm_entry_add(phy, td->aid);
975+ if (wcid == last)
976+ break;
977+ }
978+
979+ memcpy(&td->ed, &tmp, sizeof(td->ed));
980+}
981+
developer4c6b6002022-05-30 16:36:44 +0800982+static int
983+mt7915_tm_txbf_init(struct mt7915_phy *phy, u16 *val)
984+{
985+ struct mt76_testmode_data *td = &phy->mt76->test;
986+ struct mt7915_dev *dev = phy->dev;
987+ bool enable = val[0];
988+ void *phase_cal, *pfmu_data, *pfmu_tag;
989+ u8 addr[ETH_ALEN] = {0x00, 0x22, 0x22, 0x22, 0x22, 0x22};
990+
991+ if (!enable) {
992+ phy->test.bf_en = 0;
993+ return 0;
994+ }
995+
996+ if (!dev->test.txbf_phase_cal) {
997+ phase_cal = devm_kzalloc(dev->mt76.dev,
998+ sizeof(struct mt7915_tm_txbf_phase) *
999+ MAX_PHASE_GROUP_NUM,
1000+ GFP_KERNEL);
1001+ if (!phase_cal)
1002+ return -ENOMEM;
1003+
1004+ dev->test.txbf_phase_cal = phase_cal;
1005+ }
1006+
1007+ if (!dev->test.txbf_pfmu_data) {
1008+ pfmu_data = devm_kzalloc(dev->mt76.dev, 512, GFP_KERNEL);
1009+ if (!pfmu_data)
1010+ return -ENOMEM;
1011+
1012+ dev->test.txbf_pfmu_data = pfmu_data;
1013+ }
1014+
1015+ if (!dev->test.txbf_pfmu_tag) {
1016+ pfmu_tag = devm_kzalloc(dev->mt76.dev,
1017+ sizeof(struct mt7915_tm_pfmu_tag), GFP_KERNEL);
1018+ if (!pfmu_tag)
1019+ return -ENOMEM;
1020+
1021+ dev->test.txbf_pfmu_tag = pfmu_tag;
1022+ }
1023+
1024+ memcpy(phy->monitor_vif->addr, addr, ETH_ALEN);
1025+ mt7915_mcu_add_dev_info(phy, phy->monitor_vif, true);
1026+
1027+ td->tx_rate_mode = MT76_TM_TX_MODE_HT;
1028+ td->tx_mpdu_len = 1024;
1029+ td->tx_rate_sgi = 0;
1030+ td->tx_ipg = 100;
1031+ phy->test.bf_en = 1;
1032+
1033+ return mt7915_tm_set_trx(phy, TM_MAC_TX, true);
1034+}
1035+
1036+static int
1037+mt7915_tm_txbf_phase_comp(struct mt7915_phy *phy, u16 *val)
1038+{
1039+ struct mt7915_dev *dev = phy->dev;
1040+ struct {
1041+ u8 category;
1042+ u8 wlan_idx_lo;
1043+ u8 bw;
1044+ u8 jp_band;
1045+ u8 dbdc_idx;
1046+ bool read_from_e2p;
1047+ bool disable;
1048+ u8 wlan_idx_hi;
1049+ u8 buf[40];
1050+ } __packed req = {
1051+ .category = MT_BF_IBF_PHASE_COMP,
1052+ .bw = val[0],
1053+ .jp_band = (val[2] == 1) ? 1 : 0,
developereb6a0182022-12-12 18:53:32 +08001054+ .dbdc_idx = phy->mt76->band_idx,
developer4c6b6002022-05-30 16:36:44 +08001055+ .read_from_e2p = val[3],
1056+ .disable = val[4],
1057+ };
1058+ struct mt7915_tm_txbf_phase *phase =
1059+ (struct mt7915_tm_txbf_phase *)dev->test.txbf_phase_cal;
1060+
1061+ wait_event_timeout(dev->mt76.tx_wait, phase[val[2]].status != 0, HZ);
1062+ memcpy(req.buf, &phase[val[2]].phase, sizeof(req.buf));
1063+
1064+ pr_info("ibf cal process: phase comp info\n");
1065+ print_hex_dump(KERN_INFO, "", DUMP_PREFIX_NONE, 16, 1,
1066+ &req, sizeof(req), 0);
1067+
1068+ return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(TXBF_ACTION), &req,
1069+ sizeof(req), true);
1070+}
1071+
1072+static int
1073+mt7915_tm_txbf_profile_tag_read(struct mt7915_phy *phy, u8 pfmu_idx)
1074+{
1075+ struct mt7915_dev *dev = phy->dev;
1076+ struct {
1077+ u8 format_id;
1078+ u8 pfmu_idx;
1079+ bool bfer;
1080+ u8 dbdc_idx;
1081+ } __packed req = {
1082+ .format_id = MT_BF_PFMU_TAG_READ,
1083+ .pfmu_idx = pfmu_idx,
1084+ .bfer = 1,
1085+ .dbdc_idx = phy != &dev->phy,
1086+ };
1087+ struct mt7915_tm_pfmu_tag *tag = phy->dev->test.txbf_pfmu_tag;
1088+
1089+ tag->t1.pfmu_idx = 0;
1090+
1091+ return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(TXBF_ACTION), &req,
1092+ sizeof(req), true);
1093+}
1094+
1095+static int
1096+mt7915_tm_txbf_profile_tag_write(struct mt7915_phy *phy, u8 pfmu_idx,
1097+ struct mt7915_tm_pfmu_tag *tag)
1098+{
1099+ struct mt7915_dev *dev = phy->dev;
1100+ struct {
1101+ u8 format_id;
1102+ u8 pfmu_idx;
1103+ bool bfer;
1104+ u8 dbdc_idx;
1105+ u8 buf[64];
1106+ } __packed req = {
1107+ .format_id = MT_BF_PFMU_TAG_WRITE,
1108+ .pfmu_idx = pfmu_idx,
1109+ .bfer = 1,
1110+ .dbdc_idx = phy != &dev->phy,
1111+ };
1112+
1113+ memcpy(req.buf, tag, sizeof(*tag));
1114+ wait_event_timeout(dev->mt76.tx_wait, tag->t1.pfmu_idx != 0, HZ);
1115+
1116+ return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(TXBF_ACTION), &req,
1117+ sizeof(req), false);
1118+}
1119+
1120+static int
1121+mt7915_tm_txbf_apply_tx(struct mt7915_phy *phy, u16 wlan_idx, bool ebf,
1122+ bool ibf, bool phase_cal)
1123+{
1124+#define to_wcid_lo(id) FIELD_GET(GENMASK(7, 0), (u16)id)
1125+#define to_wcid_hi(id) FIELD_GET(GENMASK(9, 8), (u16)id)
1126+ struct mt7915_dev *dev = phy->dev;
1127+ struct {
1128+ u8 category;
1129+ u8 wlan_idx_lo;
1130+ bool ebf;
1131+ bool ibf;
1132+ bool mu_txbf;
1133+ bool phase_cal;
1134+ u8 wlan_idx_hi;
1135+ u8 _rsv;
1136+ } __packed req = {
1137+ .category = MT_BF_DATA_PACKET_APPLY,
1138+ .wlan_idx_lo = to_wcid_lo(wlan_idx),
1139+ .ebf = ebf,
1140+ .ibf = ibf,
1141+ .phase_cal = phase_cal,
1142+ .wlan_idx_hi = to_wcid_hi(wlan_idx),
1143+ };
1144+
1145+ return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(TXBF_ACTION), &req,
1146+ sizeof(req), false);
1147+}
1148+
1149+static int mt7915_tm_txbf_set_rate(struct mt7915_phy *phy,
1150+ struct mt76_wcid *wcid)
1151+{
1152+ struct mt7915_dev *dev = phy->dev;
1153+ struct mt76_testmode_entry_data *ed = mt76_testmode_entry_data(phy->mt76, wcid);
1154+ struct ieee80211_sta *sta = wcid_to_sta(wcid);
1155+ struct sta_phy rate = {};
1156+
1157+ if (!sta)
1158+ return 0;
1159+
1160+ rate.type = MT_PHY_TYPE_HT;
1161+ rate.bw = mt7915_tm_chan_bw(phy->mt76->chandef.width);
1162+ rate.nss = ed->tx_rate_nss;
1163+ rate.mcs = ed->tx_rate_idx;
1164+ rate.ldpc = (rate.bw || ed->tx_rate_ldpc) * GENMASK(2, 0);
1165+
1166+ return mt7915_mcu_set_fixed_rate_ctrl(dev, phy->monitor_vif, sta,
1167+ &rate, RATE_PARAM_FIXED);
1168+}
1169+
1170+static int
1171+mt7915_tm_txbf_set_tx(struct mt7915_phy *phy, u16 *val)
1172+{
1173+ bool bf_on = val[0], update = val[3];
1174+ /* u16 wlan_idx = val[2]; */
1175+ struct mt7915_tm_pfmu_tag *tag = phy->dev->test.txbf_pfmu_tag;
1176+ struct mt76_testmode_data *td = &phy->mt76->test;
1177+ struct mt76_wcid *wcid;
1178+
1179+ if (bf_on) {
1180+ mt7915_tm_set_trx(phy, TM_MAC_RX_RXV, false);
1181+ mt7915_tm_txbf_profile_tag_read(phy, 2);
1182+ tag->t1.invalid_prof = false;
1183+ mt7915_tm_txbf_profile_tag_write(phy, 2, tag);
1184+
1185+ phy->test.bf_ever_en = true;
1186+
1187+ if (update)
1188+ mt7915_tm_txbf_apply_tx(phy, 1, 0, 1, 1);
1189+ } else {
1190+ if (!phy->test.bf_ever_en) {
1191+ if (update)
1192+ mt7915_tm_txbf_apply_tx(phy, 1, 0, 0, 0);
1193+ } else {
1194+ phy->test.bf_ever_en = false;
1195+
1196+ mt7915_tm_txbf_profile_tag_read(phy, 2);
1197+ tag->t1.invalid_prof = true;
1198+ mt7915_tm_txbf_profile_tag_write(phy, 2, tag);
1199+ }
1200+ }
1201+
1202+ wcid = list_first_entry(&td->tm_entry_list, struct mt76_wcid, list);
1203+ mt7915_tm_txbf_set_rate(phy, wcid);
1204+
1205+ return 0;
1206+}
1207+
1208+static int
1209+mt7915_tm_txbf_profile_update(struct mt7915_phy *phy, u16 *val, bool ebf)
1210+{
1211+ static const u8 mode_to_lm[] = {
1212+ [MT76_TM_TX_MODE_CCK] = 0,
1213+ [MT76_TM_TX_MODE_OFDM] = 0,
1214+ [MT76_TM_TX_MODE_HT] = 1,
1215+ [MT76_TM_TX_MODE_VHT] = 2,
1216+ [MT76_TM_TX_MODE_HE_SU] = 3,
1217+ [MT76_TM_TX_MODE_HE_EXT_SU] = 3,
1218+ [MT76_TM_TX_MODE_HE_TB] = 3,
1219+ [MT76_TM_TX_MODE_HE_MU] = 3,
1220+ };
1221+ struct mt76_testmode_data *td = &phy->mt76->test;
1222+ struct mt76_wcid *wcid;
1223+ struct ieee80211_vif *vif = phy->monitor_vif;
1224+ struct mt7915_tm_pfmu_tag *tag = phy->dev->test.txbf_pfmu_tag;
1225+ u8 pfmu_idx = val[0], nc = val[2], nr;
1226+ int ret;
1227+
1228+ if (td->tx_antenna_mask == 3)
1229+ nr = 1;
1230+ else if (td->tx_antenna_mask == 7)
1231+ nr = 2;
1232+ else
1233+ nr = 3;
1234+
1235+ memset(tag, 0, sizeof(*tag));
1236+ tag->t1.pfmu_idx = pfmu_idx;
1237+ tag->t1.ebf = ebf;
1238+ tag->t1.nr = nr;
1239+ tag->t1.nc = nc;
1240+ tag->t1.invalid_prof = true;
1241+
1242+ tag->t1.snr_sts4 = 0xc0;
1243+ tag->t1.snr_sts5 = 0xff;
1244+ tag->t1.snr_sts6 = 0xff;
1245+ tag->t1.snr_sts7 = 0xff;
1246+
1247+ if (ebf) {
1248+ tag->t1.row_id1 = 0;
1249+ tag->t1.row_id2 = 1;
1250+ tag->t1.row_id3 = 2;
1251+ tag->t1.row_id4 = 3;
1252+ tag->t1.lm = mode_to_lm[MT76_TM_TX_MODE_HT];
1253+ } else {
1254+ tag->t1.row_id1 = 4;
1255+ tag->t1.row_id2 = 5;
1256+ tag->t1.row_id3 = 6;
1257+ tag->t1.row_id4 = 7;
1258+ tag->t1.lm = mode_to_lm[MT76_TM_TX_MODE_OFDM];
1259+
1260+ tag->t2.ibf_timeout = 0xff;
1261+ tag->t2.ibf_nr = nr;
1262+ }
1263+
1264+ ret = mt7915_tm_txbf_profile_tag_write(phy, pfmu_idx, tag);
1265+ if (ret)
1266+ return ret;
1267+
1268+ wcid = list_first_entry(&td->tm_entry_list, struct mt76_wcid, list);
1269+ ret = mt7915_tm_add_txbf(phy, vif, wcid_to_sta(wcid), pfmu_idx, nr, nc, ebf);
1270+ if (ret)
1271+ return ret;
1272+
1273+ if (!ebf)
1274+ return mt7915_tm_txbf_apply_tx(phy, 1, false, true, true);
1275+
1276+ return 0;
1277+}
1278+
1279+static int
1280+mt7915_tm_txbf_phase_cal(struct mt7915_phy *phy, u16 *val)
1281+{
1282+#define GROUP_L 0
1283+#define GROUP_M 1
1284+#define GROUP_H 2
1285+ struct mt7915_dev *dev = phy->dev;
1286+ struct {
1287+ u8 category;
1288+ u8 group_l_m_n;
1289+ u8 group;
1290+ bool sx2;
1291+ u8 cal_type;
1292+ u8 lna_gain_level;
1293+ u8 _rsv[2];
1294+ } __packed req = {
1295+ .category = MT_BF_PHASE_CAL,
1296+ .group = val[0],
1297+ .group_l_m_n = val[1],
1298+ .sx2 = val[2],
1299+ .cal_type = val[3],
1300+ .lna_gain_level = 0, /* for test purpose */
1301+ };
1302+ struct mt7915_tm_txbf_phase *phase =
1303+ (struct mt7915_tm_txbf_phase *)dev->test.txbf_phase_cal;
1304+
1305+ phase[req.group].status = 0;
1306+
1307+ return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(TXBF_ACTION), &req,
1308+ sizeof(req), true);
1309+}
1310+
1311+int mt7915_tm_txbf_status_read(struct mt7915_dev *dev, struct sk_buff *skb)
1312+{
1313+#define BF_PFMU_TAG 16
1314+#define BF_CAL_PHASE 21
1315+ u8 format_id;
1316+
developerf64861f2022-06-22 11:44:53 +08001317+ skb_pull(skb, sizeof(struct mt76_connac2_mcu_rxd));
developer4c6b6002022-05-30 16:36:44 +08001318+ format_id = *(u8 *)skb->data;
1319+
1320+ if (format_id == BF_PFMU_TAG) {
1321+ struct mt7915_tm_pfmu_tag *tag = dev->test.txbf_pfmu_tag;
1322+
1323+ skb_pull(skb, 8);
1324+ memcpy(tag, skb->data, sizeof(struct mt7915_tm_pfmu_tag));
1325+ } else if (format_id == BF_CAL_PHASE) {
1326+ struct mt7915_tm_ibf_cal_info *cal;
1327+ struct mt7915_tm_txbf_phase *phase =
1328+ (struct mt7915_tm_txbf_phase *)dev->test.txbf_phase_cal;
1329+
1330+ cal = (struct mt7915_tm_ibf_cal_info *)skb->data;
1331+ switch (cal->cal_type) {
1332+ case IBF_PHASE_CAL_NORMAL:
1333+ case IBF_PHASE_CAL_NORMAL_INSTRUMENT:
1334+ if (cal->group_l_m_n != GROUP_M)
1335+ break;
1336+ phase = &phase[cal->group];
1337+ memcpy(&phase->phase, cal->buf + 16, sizeof(phase->phase));
1338+ phase->status = cal->status;
1339+ break;
1340+ case IBF_PHASE_CAL_VERIFY:
1341+ case IBF_PHASE_CAL_VERIFY_INSTRUMENT:
1342+ break;
1343+ default:
1344+ break;
1345+ }
1346+ }
1347+
1348+ wake_up(&dev->mt76.tx_wait);
1349+
1350+ return 0;
1351+}
1352+
1353+static int
1354+mt7915_tm_txbf_profile_update_all(struct mt7915_phy *phy, u16 *val)
1355+{
1356+ struct mt76_testmode_data *td = &phy->mt76->test;
developere8045132023-08-04 14:40:12 +08001357+ u8 nss = hweight8(td->tx_antenna_mask);
developer4c6b6002022-05-30 16:36:44 +08001358+ u16 pfmu_idx = val[0];
1359+ u16 subc_id = val[1];
1360+ u16 angle11 = val[2];
1361+ u16 angle21 = val[3];
1362+ u16 angle31 = val[4];
1363+ u16 angle41 = val[5];
1364+ s16 phi11 = 0, phi21 = 0, phi31 = 0;
1365+ struct mt7915_tm_pfmu_data *pfmu_data;
1366+
1367+ if (subc_id > 63)
1368+ return -EINVAL;
1369+
developere8045132023-08-04 14:40:12 +08001370+ if (nss == 2) {
developer4c6b6002022-05-30 16:36:44 +08001371+ phi11 = (s16)(angle21 - angle11);
developere8045132023-08-04 14:40:12 +08001372+ } else if (nss == 3) {
developer4c6b6002022-05-30 16:36:44 +08001373+ phi11 = (s16)(angle31 - angle11);
1374+ phi21 = (s16)(angle31 - angle21);
1375+ } else {
1376+ phi11 = (s16)(angle41 - angle11);
1377+ phi21 = (s16)(angle41 - angle21);
1378+ phi31 = (s16)(angle41 - angle31);
1379+ }
1380+
1381+ pfmu_data = (struct mt7915_tm_pfmu_data *)phy->dev->test.txbf_pfmu_data;
1382+ pfmu_data = &pfmu_data[subc_id];
1383+
1384+ if (subc_id < 32)
1385+ pfmu_data->subc_idx = cpu_to_le16(subc_id + 224);
1386+ else
1387+ pfmu_data->subc_idx = cpu_to_le16(subc_id - 32);
1388+ pfmu_data->phi11 = cpu_to_le16(phi11);
1389+ pfmu_data->phi21 = cpu_to_le16(phi21);
1390+ pfmu_data->phi31 = cpu_to_le16(phi31);
1391+
1392+ if (subc_id == 63) {
1393+ struct mt7915_dev *dev = phy->dev;
1394+ struct {
1395+ u8 format_id;
1396+ u8 pfmu_idx;
1397+ u8 dbdc_idx;
1398+ u8 _rsv;
1399+ u8 buf[512];
1400+ } __packed req = {
1401+ .format_id = MT_BF_PROFILE_WRITE_ALL,
1402+ .pfmu_idx = pfmu_idx,
1403+ .dbdc_idx = phy != &dev->phy,
1404+ };
1405+
1406+ memcpy(req.buf, dev->test.txbf_pfmu_data, 512);
1407+
1408+ return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(TXBF_ACTION),
1409+ &req, sizeof(req), true);
1410+ }
1411+
1412+ return 0;
1413+}
1414+
1415+static int
1416+mt7915_tm_txbf_e2p_update(struct mt7915_phy *phy)
1417+{
1418+ struct mt7915_tm_txbf_phase *phase, *p;
1419+ struct mt7915_dev *dev = phy->dev;
1420+ u8 *eeprom = dev->mt76.eeprom.data;
1421+ u16 offset;
1422+ bool is_7976;
1423+ int i;
1424+
1425+ is_7976 = mt7915_check_adie(dev, false) || is_mt7916(&dev->mt76);
1426+ offset = is_7976 ? 0x60a : 0x651;
1427+
1428+ phase = (struct mt7915_tm_txbf_phase *)dev->test.txbf_phase_cal;
1429+ for (i = 0; i < MAX_PHASE_GROUP_NUM; i++) {
1430+ p = &phase[i];
1431+
1432+ if (!p->status)
1433+ continue;
1434+
1435+ /* copy phase cal data to eeprom */
1436+ memcpy(eeprom + offset + i * sizeof(p->phase), &p->phase,
1437+ sizeof(p->phase));
1438+ }
1439+
1440+ return 0;
1441+}
1442+
1443+static int
1444+mt7915_tm_set_txbf(struct mt7915_phy *phy)
1445+{
1446+ struct mt76_testmode_data *td = &phy->mt76->test;
1447+ u16 *val = td->txbf_param;
1448+
1449+ pr_info("ibf cal process: act = %u, val = %u, %u, %u, %u, %u\n",
1450+ td->txbf_act, val[0], val[1], val[2], val[3], val[4]);
1451+
1452+ switch (td->txbf_act) {
1453+ case MT76_TM_TXBF_ACT_INIT:
1454+ return mt7915_tm_txbf_init(phy, val);
1455+ case MT76_TM_TXBF_ACT_UPDATE_CH:
1456+ mt7915_tm_update_channel(phy);
1457+ break;
1458+ case MT76_TM_TXBF_ACT_PHASE_COMP:
1459+ return mt7915_tm_txbf_phase_comp(phy, val);
1460+ case MT76_TM_TXBF_ACT_TX_PREP:
1461+ return mt7915_tm_txbf_set_tx(phy, val);
1462+ case MT76_TM_TXBF_ACT_IBF_PROF_UPDATE:
1463+ return mt7915_tm_txbf_profile_update(phy, val, false);
1464+ case MT76_TM_TXBF_ACT_EBF_PROF_UPDATE:
1465+ return mt7915_tm_txbf_profile_update(phy, val, true);
1466+ case MT76_TM_TXBF_ACT_PHASE_CAL:
1467+ return mt7915_tm_txbf_phase_cal(phy, val);
1468+ case MT76_TM_TXBF_ACT_PROF_UPDATE_ALL:
1469+ return mt7915_tm_txbf_profile_update_all(phy, val);
1470+ case MT76_TM_TXBF_ACT_E2P_UPDATE:
1471+ return mt7915_tm_txbf_e2p_update(phy);
1472+ default:
1473+ break;
1474+ };
1475+
1476+ return 0;
1477+}
1478+
1479 static int
developerf64861f2022-06-22 11:44:53 +08001480 mt7915_tm_set_wmm_qid(struct mt7915_phy *phy, u8 qid, u8 aifs, u8 cw_min,
developer4c6b6002022-05-30 16:36:44 +08001481- u16 cw_max, u16 txop)
1482+ u16 cw_max, u16 txop, u8 tx_cmd)
1483 {
developerf64861f2022-06-22 11:44:53 +08001484 struct mt7915_vif *mvif = (struct mt7915_vif *)phy->monitor_vif->drv_priv;
developer4c6b6002022-05-30 16:36:44 +08001485- struct mt7915_mcu_tx req = { .total = 1 };
1486+ struct mt7915_mcu_tx req = {
1487+ .valid = true,
1488+ .mode = tx_cmd,
1489+ .total = 1,
1490+ };
1491 struct edca *e = &req.edca[0];
1492
developerf64861f2022-06-22 11:44:53 +08001493 e->queue = qid + mvif->mt76.wmm_idx * MT76_CONNAC_MAX_WMM_SETS;
developere8045132023-08-04 14:40:12 +08001494@@ -263,7 +1057,8 @@ done:
developer4c6b6002022-05-30 16:36:44 +08001495
developerf64861f2022-06-22 11:44:53 +08001496 return mt7915_tm_set_wmm_qid(phy,
developer4c6b6002022-05-30 16:36:44 +08001497 mt76_connac_lmac_mapping(IEEE80211_AC_BE),
1498- aifsn, cw, cw, 0);
1499+ aifsn, cw, cw, 0,
1500+ mode == MT76_TM_TX_MODE_HE_MU);
1501 }
1502
1503 static int
developere8045132023-08-04 14:40:12 +08001504@@ -339,7 +1134,7 @@ mt7915_tm_set_tx_len(struct mt7915_phy *phy, u32 tx_time)
developer4c6b6002022-05-30 16:36:44 +08001505 bitrate = cfg80211_calculate_bitrate(&rate);
1506 tx_len = bitrate * tx_time / 10 / 8;
1507
1508- ret = mt76_testmode_alloc_skb(phy->mt76, tx_len);
1509+ ret = mt76_testmode_init_skb(phy->mt76, tx_len, &td->tx_skb, td->addr);
1510 if (ret)
1511 return ret;
1512
developere8045132023-08-04 14:40:12 +08001513@@ -458,64 +1253,227 @@ mt7915_tm_init(struct mt7915_phy *phy, bool en)
developer4c6b6002022-05-30 16:36:44 +08001514
1515 phy->mt76->test.flag |= MT_TM_FW_RX_COUNT;
1516
1517- if (!en)
1518+ if (!en) {
1519 mt7915_tm_set_tam_arb(phy, en, 0);
1520+
1521+ phy->mt76->test.aid = 0;
1522+ phy->mt76->test.tx_mpdu_len = 0;
1523+ phy->test.bf_en = 0;
1524+ mt7915_tm_set_entry(phy);
1525+ }
1526+}
1527+
1528+static bool
1529+mt7915_tm_check_skb(struct mt7915_phy *phy)
1530+{
1531+ struct mt76_testmode_entry_data *ed;
1532+ struct mt76_wcid *wcid;
1533+
1534+ mt76_tm_for_each_entry(phy->mt76, wcid, ed) {
1535+ struct ieee80211_tx_info *info;
1536+
1537+ if (!ed->tx_skb)
1538+ return false;
1539+
1540+ info = IEEE80211_SKB_CB(ed->tx_skb);
1541+ info->control.vif = phy->monitor_vif;
1542+ }
1543+
1544+ return true;
1545+}
1546+
1547+static int
1548+mt7915_tm_set_ba(struct mt7915_phy *phy)
1549+{
1550+ struct mt7915_dev *dev = phy->dev;
1551+ struct mt76_testmode_data *td = &phy->mt76->test;
1552+ struct mt76_wcid *wcid;
1553+ struct ieee80211_vif *vif = phy->monitor_vif;
1554+ struct mt7915_vif *mvif = (struct mt7915_vif *)vif->drv_priv;
1555+ struct ieee80211_ampdu_params params = { .buf_size = 256 };
1556+
1557+ list_for_each_entry(wcid, &td->tm_entry_list, list) {
1558+ int tid, ret;
1559+
1560+ params.sta = wcid_to_sta(wcid);
1561+ for (tid = 0; tid < 8; tid++) {
1562+ params.tid = tid;
1563+ ret = mt7915_mcu_add_tx_ba(phy->dev, &params, true);
1564+ if (ret)
1565+ return ret;
1566+ }
1567+ }
1568+
1569+ mt76_wr(dev, MT_AGG_AALCR0(mvif->mt76.band_idx, mvif->mt76.wmm_idx),
1570+ 0x01010101);
1571+
1572+ return 0;
1573+}
1574+
1575+static int
1576+mt7915_tm_set_muru_cfg(struct mt7915_phy *phy, struct mt7915_tm_muru *muru)
1577+{
1578+/* #define MURU_SET_MANUAL_CFG 100 */
1579+ struct mt7915_dev *dev = phy->dev;
1580+ struct {
1581+ __le32 cmd;
1582+ struct mt7915_tm_muru muru;
1583+ } __packed req = {
1584+ .cmd = cpu_to_le32(MURU_SET_MANUAL_CFG),
1585+ };
1586+
1587+ memcpy(&req.muru, muru, sizeof(struct mt7915_tm_muru));
1588+
1589+ return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(MURU_CTRL), &req,
1590+ sizeof(req), false);
1591+}
1592+
1593+static int
1594+mt7915_tm_set_muru_dl(struct mt7915_phy *phy)
1595+{
1596+ struct mt76_testmode_data *td = &phy->mt76->test;
1597+ struct mt76_testmode_entry_data *ed;
1598+ struct mt76_wcid *wcid;
1599+ struct cfg80211_chan_def *chandef = &phy->mt76->chandef;
1600+ struct ieee80211_vif *vif = phy->monitor_vif;
1601+ struct mt7915_vif *mvif = (struct mt7915_vif *)vif->drv_priv;
1602+ struct mt7915_tm_muru muru = {};
1603+ struct mt7915_tm_muru_comm *comm = &muru.comm;
1604+ struct mt7915_tm_muru_dl *dl = &muru.dl;
1605+ int i;
1606+
1607+ comm->ppdu_format = MURU_PPDU_HE_MU;
1608+ comm->band = mvif->mt76.band_idx;
1609+ comm->wmm_idx = mvif->mt76.wmm_idx;
1610+ comm->spe_idx = phy->test.spe_idx;
1611+
1612+ dl->bw = mt7915_tm_chan_bw(chandef->width);
developer62b3f572023-06-07 17:39:27 +08001613+ dl->gi = td->tx_rate_sgi;
developer4c6b6002022-05-30 16:36:44 +08001614+ dl->ltf = td->tx_ltf;
1615+ dl->tx_mode = MT_PHY_TYPE_HE_MU;
1616+
1617+ for (i = 0; i < sizeof(dl->ru); i++)
1618+ dl->ru[i] = 0x71;
1619+
1620+ mt76_tm_for_each_entry(phy->mt76, wcid, ed) {
1621+ struct mt7915_tm_muru_dl_usr *dl_usr = &dl->usr[dl->user_num];
1622+
1623+ dl_usr->wlan_idx = cpu_to_le16(wcid->idx);
1624+ dl_usr->ru_alloc_seg = ed->aid < 8 ? 0 : 1;
1625+ dl_usr->ru_idx = ed->ru_idx;
1626+ dl_usr->mcs = ed->tx_rate_idx;
1627+ dl_usr->nss = ed->tx_rate_nss - 1;
1628+ dl_usr->ldpc = ed->tx_rate_ldpc;
1629+ dl->ru[dl->user_num] = ed->ru_alloc;
1630+
1631+ dl->user_num++;
1632+ }
1633+
developerdec31212023-05-02 16:45:27 +08001634+ muru.cfg_comm = cpu_to_le32(MURU_COMM_SET_TM);
developer4c6b6002022-05-30 16:36:44 +08001635+ muru.cfg_dl = cpu_to_le32(MURU_DL_SET);
1636+
1637+ return mt7915_tm_set_muru_cfg(phy, &muru);
1638+}
1639+
1640+static int
1641+mt7915_tm_set_muru_pkt_cnt(struct mt7915_phy *phy, bool enable, u32 tx_count)
1642+{
1643+#define MURU_SET_TX_PKT_CNT 105
1644+#define MURU_SET_TX_EN 106
1645+ struct mt7915_dev *dev = phy->dev;
1646+ struct {
1647+ __le32 cmd;
1648+ u8 band;
1649+ u8 enable;
1650+ u8 _rsv[2];
1651+ __le32 tx_count;
1652+ } __packed req = {
developereb6a0182022-12-12 18:53:32 +08001653+ .band = phy->mt76->band_idx,
developer4c6b6002022-05-30 16:36:44 +08001654+ .enable = enable,
1655+ .tx_count = enable ? cpu_to_le32(tx_count) : 0,
1656+ };
1657+ int ret;
1658+
1659+ req.cmd = enable ? cpu_to_le32(MURU_SET_TX_PKT_CNT) :
1660+ cpu_to_le32(MURU_SET_TX_EN);
1661+
1662+ ret = mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(MURU_CTRL), &req,
1663+ sizeof(req), false);
1664+ if (ret)
1665+ return ret;
1666+
1667+ req.cmd = enable ? cpu_to_le32(MURU_SET_TX_EN) :
1668+ cpu_to_le32(MURU_SET_TX_PKT_CNT);
1669+
1670+ return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(MURU_CTRL), &req,
1671+ sizeof(req), false);
1672 }
1673
1674 static void
1675-mt7915_tm_update_channel(struct mt7915_phy *phy)
1676+mt7915_tm_tx_frames_mu(struct mt7915_phy *phy, bool enable)
1677 {
1678- mutex_unlock(&phy->dev->mt76.mutex);
1679- mt7915_set_channel(phy);
1680- mutex_lock(&phy->dev->mt76.mutex);
1681+ struct mt76_testmode_data *td = &phy->mt76->test;
1682
1683- mt7915_mcu_set_chan_info(phy, MCU_EXT_CMD(SET_RX_PATH));
1684+ if (enable) {
1685+ struct mt7915_dev *dev = phy->dev;
1686+
1687+ mt7915_tm_set_ba(phy);
1688+ mt7915_tm_set_muru_dl(phy);
1689+ mt76_rr(dev, MT_MIB_DR8(phy != &dev->phy));
1690+ } else {
1691+ /* set to zero for counting real tx free num */
1692+ td->tx_done = 0;
1693+ }
1694+
1695+ mt7915_tm_set_muru_pkt_cnt(phy, enable, td->tx_count);
1696+ usleep_range(100000, 200000);
1697 }
1698
1699 static void
developerd59e4772022-07-14 13:48:49 +08001700 mt7915_tm_set_tx_frames(struct mt7915_phy *phy, bool en)
1701 {
developer4c6b6002022-05-30 16:36:44 +08001702 struct mt76_testmode_data *td = &phy->mt76->test;
1703- struct mt7915_dev *dev = phy->dev;
1704- struct ieee80211_tx_info *info;
1705- u8 duty_cycle = td->tx_duty_cycle;
1706- u32 tx_time = td->tx_time;
1707- u32 ipg = td->tx_ipg;
1708
1709 mt7915_tm_set_trx(phy, TM_MAC_RX_RXV, false);
1710- mt7915_tm_clean_hwq(phy, dev->mt76.global_wcid.idx);
1711+ mt7915_tm_set_trx(phy, TM_MAC_TX, false);
1712
1713 if (en) {
1714- mt7915_tm_update_channel(phy);
1715+ u32 tx_time = td->tx_time, ipg = td->tx_ipg;
1716+ u8 duty_cycle = td->tx_duty_cycle;
1717+
1718+ if (!phy->test.bf_en)
1719+ mt7915_tm_update_channel(phy);
1720
developerd59e4772022-07-14 13:48:49 +08001721 if (td->tx_spe_idx)
developer4c6b6002022-05-30 16:36:44 +08001722 phy->test.spe_idx = td->tx_spe_idx;
developerd59e4772022-07-14 13:48:49 +08001723 else
1724 phy->test.spe_idx = mt76_connac_spe_idx(td->tx_antenna_mask);
developer4c6b6002022-05-30 16:36:44 +08001725- }
1726
1727- mt7915_tm_set_tam_arb(phy, en,
1728- td->tx_rate_mode == MT76_TM_TX_MODE_HE_MU);
1729+ /* if all three params are set, duty_cycle will be ignored */
1730+ if (duty_cycle && tx_time && !ipg) {
1731+ ipg = tx_time * 100 / duty_cycle - tx_time;
1732+ } else if (duty_cycle && !tx_time && ipg) {
1733+ if (duty_cycle < 100)
1734+ tx_time = duty_cycle * ipg / (100 - duty_cycle);
1735+ }
1736
1737- /* if all three params are set, duty_cycle will be ignored */
1738- if (duty_cycle && tx_time && !ipg) {
1739- ipg = tx_time * 100 / duty_cycle - tx_time;
1740- } else if (duty_cycle && !tx_time && ipg) {
1741- if (duty_cycle < 100)
1742- tx_time = duty_cycle * ipg / (100 - duty_cycle);
1743- }
1744+ mt7915_tm_set_ipg_params(phy, ipg, td->tx_rate_mode);
1745+ mt7915_tm_set_tx_len(phy, tx_time);
1746
1747- mt7915_tm_set_ipg_params(phy, ipg, td->tx_rate_mode);
1748- mt7915_tm_set_tx_len(phy, tx_time);
1749+ if (ipg)
1750+ td->tx_queued_limit = MT76_TM_TIMEOUT * 1000000 / ipg / 2;
1751
1752- if (ipg)
1753- td->tx_queued_limit = MT76_TM_TIMEOUT * 1000000 / ipg / 2;
1754+ if (!mt7915_tm_check_skb(phy))
1755+ return;
1756+ } else {
1757+ mt7915_tm_clean_hwq(phy);
1758+ }
1759
1760- if (!en || !td->tx_skb)
1761- return;
1762+ mt7915_tm_set_tam_arb(phy, en,
1763+ td->tx_rate_mode == MT76_TM_TX_MODE_HE_MU);
1764
1765- info = IEEE80211_SKB_CB(td->tx_skb);
1766- info->control.vif = phy->monitor_vif;
1767+ if (td->tx_rate_mode == MT76_TM_TX_MODE_HE_MU)
1768+ mt7915_tm_tx_frames_mu(phy, en);
1769
1770 mt7915_tm_set_trx(phy, TM_MAC_TX, en);
1771 }
developere8045132023-08-04 14:40:12 +08001772@@ -544,10 +1502,6 @@ mt7915_tm_get_rx_stats(struct mt7915_phy *phy, bool clear)
developer4c6b6002022-05-30 16:36:44 +08001773 return ret;
1774
1775 rs_band = (struct mt7915_tm_rx_stat_band *)skb->data;
1776- /* pr_info("mdrdy_cnt = %d\n", le32_to_cpu(rs_band->mdrdy_cnt)); */
1777- /* pr_info("fcs_err = %d\n", le16_to_cpu(rs_band->fcs_err)); */
1778- /* pr_info("len_mismatch = %d\n", le16_to_cpu(rs_band->len_mismatch)); */
1779- /* pr_info("fcs_ok = %d\n", le16_to_cpu(rs_band->fcs_succ)); */
1780
1781 if (!clear) {
developer1d9fede2022-08-29 15:24:07 +08001782 enum mt76_rxq_id q = req.band ? MT_RXQ_BAND1 : MT_RXQ_MAIN;
developere8045132023-08-04 14:40:12 +08001783@@ -562,13 +1516,61 @@ mt7915_tm_get_rx_stats(struct mt7915_phy *phy, bool clear)
developer4c6b6002022-05-30 16:36:44 +08001784 return 0;
1785 }
1786
1787+static int
1788+mt7915_tm_set_rx_user_idx(struct mt7915_phy *phy, u8 aid)
1789+{
1790+ struct mt7915_dev *dev = phy->dev;
1791+ struct mt76_wcid *wcid = NULL;
1792+ struct mt76_testmode_entry_data *ed;
1793+ struct {
1794+ u8 band;
1795+ u8 _rsv;
1796+ __le16 wlan_idx;
1797+ } __packed req = {
developereb6a0182022-12-12 18:53:32 +08001798+ .band = phy->mt76->band_idx,
developer4c6b6002022-05-30 16:36:44 +08001799+ };
1800+
1801+ mt76_tm_for_each_entry(phy->mt76, wcid, ed)
1802+ if (ed->aid == aid)
1803+ break;
1804+
1805+ if (!wcid)
1806+ return -EINVAL;
1807+
1808+ req.wlan_idx = cpu_to_le16(wcid->idx);
1809+
1810+ return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(RX_STAT_USER_CTRL),
1811+ &req, sizeof(req), false);
1812+}
1813+
1814+static int
1815+mt7915_tm_set_muru_aid(struct mt7915_phy *phy, u16 aid)
1816+{
1817+ struct mt7915_dev *dev = phy->dev;
1818+ struct mt7915_tm_cmd req = {
1819+ .testmode_en = 1,
1820+ .param_idx = MCU_ATE_SET_MU_RX_AID,
developereb6a0182022-12-12 18:53:32 +08001821+ .param.rx_aid.band = cpu_to_le32(phy->mt76->band_idx),
developer4c6b6002022-05-30 16:36:44 +08001822+ .param.rx_aid.aid = cpu_to_le16(aid),
1823+ };
1824+
1825+ return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(ATE_CTRL), &req,
1826+ sizeof(req), false);
1827+}
1828+
1829 static void
1830 mt7915_tm_set_rx_frames(struct mt7915_phy *phy, bool en)
1831 {
1832+ struct mt76_testmode_data *td = &phy->mt76->test;
1833+
1834+ mt7915_tm_set_trx(phy, TM_MAC_TX, false);
1835 mt7915_tm_set_trx(phy, TM_MAC_RX_RXV, false);
1836
1837 if (en) {
1838- mt7915_tm_update_channel(phy);
1839+ if (!phy->test.bf_en)
1840+ mt7915_tm_update_channel(phy);
1841+ if (td->aid)
1842+ mt7915_tm_set_rx_user_idx(phy, td->aid);
1843
1844 /* read-clear */
1845 mt7915_tm_get_rx_stats(phy, true);
developere8045132023-08-04 14:40:12 +08001846@@ -576,9 +1578,12 @@ mt7915_tm_set_rx_frames(struct mt7915_phy *phy, bool en)
developer4c6b6002022-05-30 16:36:44 +08001847 /* clear fw count */
1848 mt7915_tm_set_phy_count(phy, 0);
1849 mt7915_tm_set_phy_count(phy, 1);
1850-
1851- mt7915_tm_set_trx(phy, TM_MAC_RX_RXV, en);
1852 }
1853+
1854+ if (td->tx_rate_mode == MT76_TM_TX_MODE_HE_MU)
1855+ mt7915_tm_set_muru_aid(phy, en ? td->aid : 0xf800);
1856+
1857+ mt7915_tm_set_trx(phy, TM_MAC_RX_RXV, en);
1858 }
1859
1860 static int
developere8045132023-08-04 14:40:12 +08001861@@ -617,34 +1622,7 @@ mt7915_tm_set_tx_cont(struct mt7915_phy *phy, bool en)
developer4c6b6002022-05-30 16:36:44 +08001862 tx_cont->tx_ant = td->tx_antenna_mask;
developereb6a0182022-12-12 18:53:32 +08001863 tx_cont->band = band;
developer144824b2022-11-25 21:27:43 +08001864
developer4c6b6002022-05-30 16:36:44 +08001865- switch (chandef->width) {
1866- case NL80211_CHAN_WIDTH_40:
1867- tx_cont->bw = CMD_CBW_40MHZ;
1868- break;
1869- case NL80211_CHAN_WIDTH_80:
1870- tx_cont->bw = CMD_CBW_80MHZ;
1871- break;
1872- case NL80211_CHAN_WIDTH_80P80:
1873- tx_cont->bw = CMD_CBW_8080MHZ;
1874- break;
1875- case NL80211_CHAN_WIDTH_160:
1876- tx_cont->bw = CMD_CBW_160MHZ;
1877- break;
1878- case NL80211_CHAN_WIDTH_5:
1879- tx_cont->bw = CMD_CBW_5MHZ;
1880- break;
1881- case NL80211_CHAN_WIDTH_10:
1882- tx_cont->bw = CMD_CBW_10MHZ;
1883- break;
1884- case NL80211_CHAN_WIDTH_20:
1885- tx_cont->bw = CMD_CBW_20MHZ;
1886- break;
1887- case NL80211_CHAN_WIDTH_20_NOHT:
1888- tx_cont->bw = CMD_CBW_20MHZ;
1889- break;
1890- default:
1891- return -EINVAL;
1892- }
1893+ tx_cont->bw = mt7915_tm_chan_bw(chandef->width);
1894
1895 if (!en) {
developereb6a0182022-12-12 18:53:32 +08001896 req.op.rf.param.func_data = cpu_to_le32(band);
developere8045132023-08-04 14:40:12 +08001897@@ -728,6 +1706,12 @@ mt7915_tm_update_params(struct mt7915_phy *phy, u32 changed)
developer4c6b6002022-05-30 16:36:44 +08001898 mt7915_tm_set_freq_offset(phy, en, en ? td->freq_offset : 0);
1899 if (changed & BIT(TM_CHANGED_TXPOWER))
1900 mt7915_tm_set_tx_power(phy);
1901+ if (changed & BIT(TM_CHANGED_AID))
1902+ mt7915_tm_set_entry(phy);
1903+ if (changed & BIT(TM_CHANGED_CFG))
1904+ mt7915_tm_set_cfg(phy);
1905+ if (changed & BIT(TM_CHANGED_TXBF_ACT))
1906+ mt7915_tm_set_txbf(phy);
1907 }
1908
1909 static int
developere8045132023-08-04 14:40:12 +08001910@@ -737,6 +1721,11 @@ mt7915_tm_set_state(struct mt76_phy *mphy, enum mt76_testmode_state state)
developer287ee9f2023-03-02 20:13:34 +08001911 struct mt7915_phy *phy = mphy->priv;
1912 enum mt76_testmode_state prev_state = td->state;
1913
1914+ if (!phy->monitor_vif) {
1915+ dev_err(phy->dev->mt76.dev, "Please make sure monitor interface is up\n");
1916+ return -ENOTCONN;
1917+ }
1918+
1919 mphy->test.state = state;
1920
1921 if (prev_state == MT76_TM_STATE_TX_FRAMES ||
developere8045132023-08-04 14:40:12 +08001922@@ -757,7 +1746,7 @@ mt7915_tm_set_state(struct mt76_phy *mphy, enum mt76_testmode_state state)
developer62b3f572023-06-07 17:39:27 +08001923 (state == MT76_TM_STATE_OFF &&
1924 prev_state == MT76_TM_STATE_IDLE)) {
1925 u32 changed = 0;
1926- int i;
1927+ int i, ret;
1928
1929 for (i = 0; i < ARRAY_SIZE(tm_change_map); i++) {
1930 u16 cur = tm_change_map[i];
developere8045132023-08-04 14:40:12 +08001931@@ -766,6 +1755,10 @@ mt7915_tm_set_state(struct mt76_phy *mphy, enum mt76_testmode_state state)
developer62b3f572023-06-07 17:39:27 +08001932 changed |= BIT(i);
1933 }
1934
1935+ ret = mt7915_tm_check_antenna(phy);
1936+ if (ret)
1937+ return ret;
1938+
1939 mt7915_tm_update_params(phy, changed);
1940 }
1941
developere8045132023-08-04 14:40:12 +08001942@@ -778,10 +1771,8 @@ mt7915_tm_set_params(struct mt76_phy *mphy, struct nlattr **tb,
developer62b3f572023-06-07 17:39:27 +08001943 {
1944 struct mt76_testmode_data *td = &mphy->test;
1945 struct mt7915_phy *phy = mphy->priv;
1946- struct mt7915_dev *dev = phy->dev;
1947- u32 chainmask = mphy->chainmask, changed = 0;
1948- bool ext_phy = phy != &dev->phy;
1949- int i;
1950+ u32 changed = 0;
1951+ int i, ret;
1952
1953 BUILD_BUG_ON(NUM_TM_CHANGED >= 32);
1954
developere8045132023-08-04 14:40:12 +08001955@@ -789,9 +1780,9 @@ mt7915_tm_set_params(struct mt76_phy *mphy, struct nlattr **tb,
developer62b3f572023-06-07 17:39:27 +08001956 td->state == MT76_TM_STATE_OFF)
1957 return 0;
1958
1959- chainmask = ext_phy ? chainmask >> dev->chainshift : chainmask;
1960- if (td->tx_antenna_mask > chainmask)
1961- return -EINVAL;
1962+ ret = mt7915_tm_check_antenna(phy);
1963+ if (ret)
1964+ return ret;
1965
1966 for (i = 0; i < ARRAY_SIZE(tm_change_map); i++) {
1967 if (tb[tm_change_map[i]])
developere8045132023-08-04 14:40:12 +08001968@@ -807,6 +1798,7 @@ static int
developer4c6b6002022-05-30 16:36:44 +08001969 mt7915_tm_dump_stats(struct mt76_phy *mphy, struct sk_buff *msg)
1970 {
1971 struct mt7915_phy *phy = mphy->priv;
1972+ struct mt7915_dev *dev = phy->dev;
1973 void *rx, *rssi;
1974 int i;
1975
developere8045132023-08-04 14:40:12 +08001976@@ -852,11 +1844,75 @@ mt7915_tm_dump_stats(struct mt76_phy *mphy, struct sk_buff *msg)
developer4c6b6002022-05-30 16:36:44 +08001977
1978 nla_nest_end(msg, rx);
1979
1980+ if (mphy->test.tx_rate_mode == MT76_TM_TX_MODE_HE_MU)
1981+ mphy->test.tx_done += mt76_rr(dev, MT_MIB_DR8(phy != &dev->phy));
1982+
1983 return mt7915_tm_get_rx_stats(phy, false);
1984 }
1985
1986+static int
1987+mt7915_tm_write_back_to_efuse(struct mt7915_dev *dev)
1988+{
1989+ struct mt7915_mcu_eeprom_info req = {};
developer