developer | 691e73f | 2021-06-28 19:41:35 +0800 | [diff] [blame] | 1 | /dts-v1/; |
developer | 565bacb | 2021-09-28 21:26:32 +0800 | [diff] [blame] | 2 | #include "mt7986a.dtsi" |
| 3 | #include "mt7986a-pinctrl.dtsi" |
| 4 | #include "mt7986-spim-nor-partition.dtsi" |
developer | 691e73f | 2021-06-28 19:41:35 +0800 | [diff] [blame] | 5 | / { |
| 6 | model = "MediaTek MT7986a RFB"; |
| 7 | compatible = "mediatek,mt7986a-2500wan-nor-rfb"; |
developer | 565bacb | 2021-09-28 21:26:32 +0800 | [diff] [blame] | 8 | chosen { |
| 9 | bootargs = "console=ttyS0,115200n1 loglevel=8 \ |
| 10 | earlycon=uart8250,mmio32,0x11002000"; |
| 11 | }; |
| 12 | |
| 13 | memory { |
| 14 | reg = <0 0x40000000 0 0x10000000>; |
| 15 | }; |
| 16 | |
| 17 | sound { |
| 18 | compatible = "mediatek,mt7986-wm8960-machine"; |
| 19 | mediatek,platform = <&afe>; |
| 20 | audio-routing = "Headphone", "HP_L", |
| 21 | "Headphone", "HP_R", |
| 22 | "LINPUT1", "AMIC", |
| 23 | "RINPUT1", "AMIC"; |
| 24 | mediatek,audio-codec = <&wm8960>; |
| 25 | status = "okay"; |
| 26 | }; |
developer | 691e73f | 2021-06-28 19:41:35 +0800 | [diff] [blame] | 27 | }; |
| 28 | |
developer | 565bacb | 2021-09-28 21:26:32 +0800 | [diff] [blame] | 29 | &pwm { |
| 30 | pinctrl-names = "default"; |
| 31 | pinctrl-0 = <&pwm0_pin &pwm1_pin_g1>; |
developer | 691e73f | 2021-06-28 19:41:35 +0800 | [diff] [blame] | 32 | status = "okay"; |
developer | 565bacb | 2021-09-28 21:26:32 +0800 | [diff] [blame] | 33 | }; |
developer | 5b91be7 | 2021-09-27 14:03:07 +0800 | [diff] [blame] | 34 | |
developer | 565bacb | 2021-09-28 21:26:32 +0800 | [diff] [blame] | 35 | &uart0 { |
| 36 | status = "okay"; |
| 37 | }; |
| 38 | |
| 39 | &uart1 { |
| 40 | pinctrl-names = "default"; |
| 41 | pinctrl-0 = <&uart1_pins>; |
| 42 | status = "okay"; |
| 43 | }; |
| 44 | |
| 45 | &uart2 { |
| 46 | pinctrl-names = "default"; |
| 47 | pinctrl-0 = <&uart2_pins>; |
| 48 | status = "okay"; |
| 49 | }; |
| 50 | |
| 51 | &i2c0 { |
| 52 | pinctrl-names = "default"; |
| 53 | pinctrl-0 = <&i2c_pins>; |
| 54 | status = "okay"; |
| 55 | |
| 56 | wm8960: wm8960@1a { |
| 57 | compatible = "wlf,wm8960"; |
| 58 | reg = <0x1a>; |
developer | 5b91be7 | 2021-09-27 14:03:07 +0800 | [diff] [blame] | 59 | }; |
| 60 | }; |
| 61 | |
developer | 565bacb | 2021-09-28 21:26:32 +0800 | [diff] [blame] | 62 | &auxadc { |
| 63 | status = "okay"; |
developer | 5b91be7 | 2021-09-27 14:03:07 +0800 | [diff] [blame] | 64 | }; |
| 65 | |
developer | 565bacb | 2021-09-28 21:26:32 +0800 | [diff] [blame] | 66 | &watchdog { |
| 67 | status = "okay"; |
developer | 691e73f | 2021-06-28 19:41:35 +0800 | [diff] [blame] | 68 | }; |
| 69 | |
developer | 565bacb | 2021-09-28 21:26:32 +0800 | [diff] [blame] | 70 | ð { |
| 71 | status = "okay"; |
| 72 | |
| 73 | gmac0: mac@0 { |
| 74 | compatible = "mediatek,eth-mac"; |
| 75 | reg = <0>; |
| 76 | phy-mode = "2500base-x"; |
| 77 | |
| 78 | fixed-link { |
| 79 | speed = <2500>; |
| 80 | full-duplex; |
| 81 | pause; |
| 82 | }; |
| 83 | }; |
| 84 | |
| 85 | gmac1: mac@1 { |
| 86 | compatible = "mediatek,eth-mac"; |
| 87 | reg = <1>; |
| 88 | phy-mode = "2500base-x"; |
| 89 | |
| 90 | fixed-link { |
| 91 | speed = <2500>; |
| 92 | full-duplex; |
| 93 | pause; |
| 94 | }; |
| 95 | }; |
| 96 | |
| 97 | mdio: mdio-bus { |
| 98 | #address-cells = <1>; |
| 99 | #size-cells = <0>; |
developer | 691e73f | 2021-06-28 19:41:35 +0800 | [diff] [blame] | 100 | |
developer | 565bacb | 2021-09-28 21:26:32 +0800 | [diff] [blame] | 101 | phy5: phy@5 { |
| 102 | compatible = "ethernet-phy-id67c9.de0a"; |
| 103 | reg = <5>; |
| 104 | reset-gpios = <&pio 6 1>; |
| 105 | reset-deassert-us = <20000>; |
| 106 | phy-mode = "2500base-x"; |
| 107 | }; |
developer | 691e73f | 2021-06-28 19:41:35 +0800 | [diff] [blame] | 108 | |
developer | 565bacb | 2021-09-28 21:26:32 +0800 | [diff] [blame] | 109 | phy6: phy@6 { |
| 110 | compatible = "ethernet-phy-id67c9.de0a"; |
| 111 | reg = <6>; |
| 112 | phy-mode = "2500base-x"; |
| 113 | }; |
| 114 | |
| 115 | switch@0 { |
| 116 | compatible = "mediatek,mt7531"; |
| 117 | reg = <31>; |
| 118 | reset-gpios = <&pio 5 0>; |
| 119 | |
| 120 | ports { |
| 121 | #address-cells = <1>; |
| 122 | #size-cells = <0>; |
| 123 | |
| 124 | port@0 { |
| 125 | reg = <0>; |
| 126 | label = "lan0"; |
| 127 | }; |
| 128 | |
| 129 | port@1 { |
| 130 | reg = <1>; |
| 131 | label = "lan1"; |
| 132 | }; |
| 133 | |
| 134 | port@2 { |
| 135 | reg = <2>; |
| 136 | label = "lan2"; |
| 137 | }; |
| 138 | |
| 139 | port@3 { |
| 140 | reg = <3>; |
| 141 | label = "lan3"; |
| 142 | }; |
| 143 | |
| 144 | port@4 { |
| 145 | reg = <4>; |
| 146 | label = "lan4"; |
| 147 | }; |
| 148 | |
| 149 | port@5 { |
| 150 | reg = <5>; |
| 151 | label = "lan5"; |
| 152 | phy-mode = "2500base-x"; |
| 153 | |
| 154 | fixed-link { |
| 155 | speed = <2500>; |
| 156 | full-duplex; |
| 157 | pause; |
| 158 | }; |
| 159 | }; |
| 160 | |
| 161 | port@6 { |
| 162 | reg = <6>; |
| 163 | label = "cpu"; |
| 164 | ethernet = <&gmac0>; |
| 165 | phy-mode = "2500base-x"; |
| 166 | |
| 167 | fixed-link { |
| 168 | speed = <2500>; |
| 169 | full-duplex; |
| 170 | pause; |
| 171 | }; |
developer | 691e73f | 2021-06-28 19:41:35 +0800 | [diff] [blame] | 172 | }; |
| 173 | }; |
| 174 | }; |
| 175 | }; |
| 176 | }; |
developer | 565bacb | 2021-09-28 21:26:32 +0800 | [diff] [blame] | 177 | |
| 178 | &hnat { |
| 179 | mtketh-wan = "eth1"; |
| 180 | mtketh-lan = "lan"; |
| 181 | mtketh-max-gmac = <2>; |
| 182 | status = "okay"; |
| 183 | }; |
| 184 | |
| 185 | &spi0 { |
| 186 | pinctrl-names = "default"; |
| 187 | pinctrl-0 = <&spi_flash_pins>; |
| 188 | cs-gpios = <0>, <0>; |
| 189 | status = "okay"; |
| 190 | spi_nor@0 { |
| 191 | #address-cells = <1>; |
| 192 | #size-cells = <1>; |
| 193 | compatible = "jedec,spi-nor"; |
| 194 | reg = <0>; |
developer | b9b1ffc | 2021-12-16 14:19:08 +0800 | [diff] [blame] | 195 | spi-max-frequency = <52000000>; |
developer | 565bacb | 2021-09-28 21:26:32 +0800 | [diff] [blame] | 196 | spi-tx-buswidth = <4>; |
| 197 | spi-rx-buswidth = <4>; |
| 198 | }; |
| 199 | }; |
| 200 | |
| 201 | &spi1 { |
| 202 | pinctrl-names = "default"; |
| 203 | pinctrl-0 = <&spic_pins_g2>; |
| 204 | status = "okay"; |
| 205 | }; |
| 206 | |
| 207 | &pcie0 { |
| 208 | pinctrl-names = "default"; |
| 209 | pinctrl-0 = <&pcie0_pins>; |
| 210 | status = "okay"; |
| 211 | }; |
| 212 | |
| 213 | &wbsys { |
| 214 | mediatek,mtd-eeprom = <&factory 0x0000>; |
| 215 | status = "okay"; |
| 216 | }; |
| 217 | |
| 218 | &pio { |
| 219 | spi_flash_pins: spi-flash-pins-33-to-38 { |
| 220 | mux { |
| 221 | function = "flash"; |
| 222 | groups = "spi0", "spi0_wp_hold"; |
| 223 | }; |
| 224 | conf-pu { |
| 225 | pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP"; |
| 226 | drive-strength = <MTK_DRIVE_8mA>; |
| 227 | mediatek,pull-up-adv = <0>; /* bias-disable */ |
| 228 | }; |
| 229 | conf-pd { |
| 230 | pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO"; |
| 231 | drive-strength = <MTK_DRIVE_8mA>; |
| 232 | mediatek,pull-down-adv = <0>; /* bias-disable */ |
| 233 | }; |
| 234 | }; |
| 235 | }; |