developer | cd6a138 | 2022-01-11 15:45:19 +0800 | [diff] [blame] | 1 | /dts-v1/; |
| 2 | #include "mt7986a.dtsi" |
| 3 | #include "mt7986a-pinctrl.dtsi" |
| 4 | / { |
| 5 | model = "MediaTek MT7986a RFB"; |
| 6 | compatible = "mediatek,mt7986a-2500wan-sd-rfb"; |
| 7 | chosen { |
| 8 | bootargs = "console=ttyS0,115200n1 loglevel=8 \ |
| 9 | earlycon=uart8250,mmio32,0x11002000 \ |
| 10 | root=PARTLABEL=rootfs rootwait rootfstype=squashfs,f2fs"; |
| 11 | }; |
| 12 | |
| 13 | memory { |
| 14 | reg = <0 0x40000000 0 0x10000000>; |
| 15 | }; |
| 16 | |
| 17 | sound { |
| 18 | compatible = "mediatek,mt7986-wm8960-machine"; |
| 19 | mediatek,platform = <&afe>; |
| 20 | audio-routing = "Headphone", "HP_L", |
| 21 | "Headphone", "HP_R", |
| 22 | "LINPUT1", "AMIC", |
| 23 | "RINPUT1", "AMIC"; |
| 24 | mediatek,audio-codec = <&wm8960>; |
| 25 | status = "okay"; |
| 26 | }; |
| 27 | |
| 28 | reg_3p3v: regulator-3p3v { |
| 29 | compatible = "regulator-fixed"; |
| 30 | regulator-name = "fixed-3.3V"; |
| 31 | regulator-min-microvolt = <3300000>; |
| 32 | regulator-max-microvolt = <3300000>; |
| 33 | regulator-boot-on; |
| 34 | regulator-always-on; |
| 35 | }; |
| 36 | }; |
| 37 | |
| 38 | &pwm { |
| 39 | pinctrl-names = "default"; |
| 40 | pinctrl-0 = <&pwm0_pin &pwm1_pin_g1>; |
| 41 | status = "okay"; |
| 42 | }; |
| 43 | |
| 44 | &uart0 { |
| 45 | status = "okay"; |
| 46 | }; |
| 47 | |
| 48 | &uart1 { |
| 49 | pinctrl-names = "default"; |
| 50 | pinctrl-0 = <&uart1_pins>; |
| 51 | status = "okay"; |
| 52 | }; |
| 53 | |
| 54 | &uart2 { |
| 55 | pinctrl-names = "default"; |
| 56 | pinctrl-0 = <&uart2_pins>; |
| 57 | status = "okay"; |
| 58 | }; |
| 59 | |
| 60 | &i2c0 { |
| 61 | pinctrl-names = "default"; |
| 62 | pinctrl-0 = <&i2c_pins>; |
| 63 | status = "okay"; |
| 64 | |
| 65 | wm8960: wm8960@1a { |
| 66 | compatible = "wlf,wm8960"; |
| 67 | reg = <0x1a>; |
| 68 | }; |
| 69 | }; |
| 70 | |
| 71 | &auxadc { |
| 72 | status = "okay"; |
| 73 | }; |
| 74 | |
| 75 | &watchdog { |
| 76 | status = "okay"; |
| 77 | }; |
| 78 | |
| 79 | ð { |
| 80 | status = "okay"; |
| 81 | |
| 82 | gmac0: mac@0 { |
| 83 | compatible = "mediatek,eth-mac"; |
| 84 | reg = <0>; |
| 85 | phy-mode = "2500base-x"; |
| 86 | |
| 87 | fixed-link { |
| 88 | speed = <2500>; |
| 89 | full-duplex; |
| 90 | pause; |
| 91 | }; |
| 92 | }; |
| 93 | |
| 94 | gmac1: mac@1 { |
| 95 | compatible = "mediatek,eth-mac"; |
| 96 | reg = <1>; |
| 97 | phy-mode = "2500base-x"; |
| 98 | |
| 99 | fixed-link { |
| 100 | speed = <2500>; |
| 101 | full-duplex; |
| 102 | pause; |
| 103 | }; |
| 104 | }; |
| 105 | |
| 106 | mdio: mdio-bus { |
| 107 | #address-cells = <1>; |
| 108 | #size-cells = <0>; |
| 109 | |
| 110 | phy5: phy@5 { |
| 111 | compatible = "ethernet-phy-id67c9.de0a"; |
| 112 | reg = <5>; |
| 113 | reset-gpios = <&pio 6 1>; |
developer | 8c5a08b | 2022-05-06 09:10:38 +0800 | [diff] [blame] | 114 | reset-assert-us = <600>; |
developer | cd6a138 | 2022-01-11 15:45:19 +0800 | [diff] [blame] | 115 | reset-deassert-us = <20000>; |
| 116 | phy-mode = "2500base-x"; |
| 117 | }; |
| 118 | |
| 119 | phy6: phy@6 { |
| 120 | compatible = "ethernet-phy-id67c9.de0a"; |
| 121 | reg = <6>; |
| 122 | phy-mode = "2500base-x"; |
| 123 | }; |
| 124 | |
| 125 | switch@0 { |
| 126 | compatible = "mediatek,mt7531"; |
| 127 | reg = <31>; |
| 128 | reset-gpios = <&pio 5 0>; |
| 129 | |
| 130 | ports { |
| 131 | #address-cells = <1>; |
| 132 | #size-cells = <0>; |
| 133 | |
| 134 | port@0 { |
| 135 | reg = <0>; |
| 136 | label = "lan0"; |
| 137 | }; |
| 138 | |
| 139 | port@1 { |
| 140 | reg = <1>; |
| 141 | label = "lan1"; |
| 142 | }; |
| 143 | |
| 144 | port@2 { |
| 145 | reg = <2>; |
| 146 | label = "lan2"; |
| 147 | }; |
| 148 | |
| 149 | port@3 { |
| 150 | reg = <3>; |
| 151 | label = "lan3"; |
| 152 | }; |
| 153 | |
| 154 | port@4 { |
| 155 | reg = <4>; |
| 156 | label = "lan4"; |
| 157 | }; |
| 158 | |
| 159 | port@5 { |
| 160 | reg = <5>; |
| 161 | label = "lan5"; |
| 162 | phy-mode = "2500base-x"; |
| 163 | |
| 164 | fixed-link { |
| 165 | speed = <2500>; |
| 166 | full-duplex; |
| 167 | pause; |
| 168 | }; |
| 169 | }; |
| 170 | |
| 171 | port@6 { |
| 172 | reg = <6>; |
| 173 | label = "cpu"; |
| 174 | ethernet = <&gmac0>; |
| 175 | phy-mode = "2500base-x"; |
| 176 | |
| 177 | fixed-link { |
| 178 | speed = <2500>; |
| 179 | full-duplex; |
| 180 | pause; |
| 181 | }; |
| 182 | }; |
| 183 | }; |
| 184 | }; |
| 185 | }; |
| 186 | }; |
| 187 | |
| 188 | &hnat { |
| 189 | mtketh-wan = "eth1"; |
| 190 | mtketh-lan = "lan"; |
| 191 | mtketh-max-gmac = <2>; |
| 192 | status = "okay"; |
| 193 | }; |
| 194 | |
| 195 | &mmc0 { |
| 196 | pinctrl-names = "default", "state_uhs"; |
| 197 | pinctrl-0 = <&mmc0_pins_default>; |
| 198 | pinctrl-1 = <&mmc0_pins_uhs>; |
| 199 | bus-width = <4>; |
| 200 | max-frequency = <52000000>; |
| 201 | cap-sd-highspeed; |
| 202 | vmmc-supply = <®_3p3v>; |
| 203 | vqmmc-supply = <®_3p3v>; |
| 204 | status = "okay"; |
| 205 | }; |
| 206 | |
| 207 | &pcie0 { |
| 208 | pinctrl-names = "default"; |
| 209 | pinctrl-0 = <&pcie0_pins>; |
| 210 | status = "okay"; |
| 211 | }; |
| 212 | |
| 213 | &pio { |
| 214 | mmc0_pins_default: mmc0-pins-50-to-61-default { |
| 215 | mux { |
| 216 | function = "flash"; |
| 217 | groups = "emmc_51"; |
| 218 | }; |
| 219 | conf-cmd-dat { |
| 220 | pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2", |
| 221 | "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5", |
| 222 | "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD"; |
| 223 | input-enable; |
| 224 | drive-strength = <MTK_DRIVE_4mA>; |
| 225 | mediatek,pull-up-adv = <1>; /* pull-up 10K */ |
| 226 | }; |
| 227 | conf-clk { |
| 228 | pins = "EMMC_CK"; |
| 229 | drive-strength = <MTK_DRIVE_6mA>; |
| 230 | mediatek,pull-down-adv = <2>; /* pull-down 50K */ |
| 231 | }; |
| 232 | conf-ds { |
| 233 | pins = "EMMC_DSL"; |
| 234 | mediatek,pull-down-adv = <2>; /* pull-down 50K */ |
| 235 | }; |
| 236 | conf-rst { |
| 237 | pins = "EMMC_RSTB"; |
| 238 | drive-strength = <MTK_DRIVE_4mA>; |
| 239 | mediatek,pull-up-adv = <1>; /* pull-up 10K */ |
| 240 | }; |
| 241 | }; |
| 242 | |
| 243 | mmc0_pins_uhs: mmc0-pins-50-to-61-uhs { |
| 244 | mux { |
| 245 | function = "flash"; |
| 246 | groups = "emmc_51"; |
| 247 | }; |
| 248 | conf-cmd-dat { |
| 249 | pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2", |
| 250 | "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5", |
| 251 | "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD"; |
| 252 | input-enable; |
| 253 | drive-strength = <MTK_DRIVE_4mA>; |
| 254 | mediatek,pull-up-adv = <1>; /* pull-up 10K */ |
| 255 | }; |
| 256 | conf-clk { |
| 257 | pins = "EMMC_CK"; |
| 258 | drive-strength = <MTK_DRIVE_6mA>; |
| 259 | mediatek,pull-down-adv = <2>; /* pull-down 50K */ |
| 260 | }; |
| 261 | conf-ds { |
| 262 | pins = "EMMC_DSL"; |
| 263 | mediatek,pull-down-adv = <2>; /* pull-down 50K */ |
| 264 | }; |
| 265 | conf-rst { |
| 266 | pins = "EMMC_RSTB"; |
| 267 | drive-strength = <MTK_DRIVE_4mA>; |
| 268 | mediatek,pull-up-adv = <1>; /* pull-up 10K */ |
| 269 | }; |
| 270 | }; |
| 271 | |
| 272 | wf_2g_5g_pins: wf_2g_5g-pins { |
| 273 | mux { |
| 274 | function = "wifi"; |
| 275 | groups = "wf_2g", "wf_5g"; |
| 276 | }; |
| 277 | conf { |
| 278 | pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4", |
| 279 | "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6", |
| 280 | "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10", |
| 281 | "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1", |
| 282 | "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0", |
| 283 | "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8", |
| 284 | "WF1_TOP_CLK", "WF1_TOP_DATA"; |
| 285 | drive-strength = <MTK_DRIVE_4mA>; |
| 286 | }; |
| 287 | }; |
| 288 | |
| 289 | wf_dbdc_pins: wf_dbdc-pins { |
| 290 | mux { |
| 291 | function = "wifi"; |
| 292 | groups = "wf_dbdc"; |
| 293 | }; |
| 294 | conf { |
| 295 | pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4", |
| 296 | "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6", |
| 297 | "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10", |
| 298 | "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1", |
| 299 | "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0", |
| 300 | "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8", |
| 301 | "WF1_TOP_CLK", "WF1_TOP_DATA"; |
| 302 | drive-strength = <MTK_DRIVE_4mA>; |
| 303 | }; |
| 304 | }; |
| 305 | }; |