commit | 8c5a08bdd764771cedbdfb04d3a844af9cf43cac | [log] [tgz] |
---|---|---|
author | developer <developer@mediatek.com> | Fri May 06 09:10:38 2022 +0800 |
committer | developer <developer@mediatek.com> | Mon May 09 11:33:42 2022 +0800 |
tree | 791e2650cdbf4d131a21012f91812d392a23df03 | |
parent | beb7437f212fb2aec0581f5cb8288e5bbfb6a7a6 [diff] [blame] |
[][Help to reset Intel 2.5G Phy] [Description] Fix Panther/Cheetah GPIO reset Intel 2.5G EPHY's signal waveform did not meet spec, spec request at least 500us. [Release-Log] N/A Change-Id: Icb95e4c9e34ef796793390439e57617e6e3751ba Reviewed-on: https://gerrit.mediatek.inc/c/openwrt/feeds/mtk_openwrt_feeds/+/5933834
diff --git a/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986a-2500wan-sd-rfb.dts b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986a-2500wan-sd-rfb.dts index 2a1d0dc..d22b90c 100644 --- a/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986a-2500wan-sd-rfb.dts +++ b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986a-2500wan-sd-rfb.dts
@@ -111,6 +111,7 @@ compatible = "ethernet-phy-id67c9.de0a"; reg = <5>; reset-gpios = <&pio 6 1>; + reset-assert-us = <600>; reset-deassert-us = <20000>; phy-mode = "2500base-x"; };