blob: 7806761d27386d67618905a782b0dfc72d33a493 [file] [log] [blame]
developerb11a5392022-03-31 00:34:47 +08001// SPDX-License-Identifier: ISC
2/* Copyright (C) 2020 MediaTek Inc. */
3
4#include <linux/etherdevice.h>
5#include <linux/platform_device.h>
6#include <linux/pci.h>
7#include <linux/module.h>
developer7800b8d2022-06-23 22:15:56 +08008#include "besra.h"
developerb11a5392022-03-31 00:34:47 +08009#include "mcu.h"
10
developer7800b8d2022-06-23 22:15:56 +080011static bool besra_dev_running(struct besra_dev *dev)
developerb11a5392022-03-31 00:34:47 +080012{
developer7800b8d2022-06-23 22:15:56 +080013 struct besra_phy *phy;
developerb11a5392022-03-31 00:34:47 +080014
15 if (test_bit(MT76_STATE_RUNNING, &dev->mphy.state))
16 return true;
17
developer7800b8d2022-06-23 22:15:56 +080018 phy = besra_ext_phy(dev);
developerb11a5392022-03-31 00:34:47 +080019 if (phy && test_bit(MT76_STATE_RUNNING, &phy->mt76->state))
20 return true;
21
developer7800b8d2022-06-23 22:15:56 +080022 phy = besra_tri_phy(dev);
developerb11a5392022-03-31 00:34:47 +080023
24 return phy && test_bit(MT76_STATE_RUNNING, &phy->mt76->state);
25}
26
developer7800b8d2022-06-23 22:15:56 +080027static int besra_start(struct ieee80211_hw *hw)
developerb11a5392022-03-31 00:34:47 +080028{
developer7800b8d2022-06-23 22:15:56 +080029 struct besra_dev *dev = besra_hw_dev(hw);
30 struct besra_phy *phy = besra_hw_phy(hw);
31 u8 phy_idx = besra_get_phy_id(phy);
developerb11a5392022-03-31 00:34:47 +080032 bool running;
33 int ret;
34
35 flush_work(&dev->init_work);
36
37 mutex_lock(&dev->mt76.mutex);
38
developer7800b8d2022-06-23 22:15:56 +080039 running = besra_dev_running(dev);
developerb11a5392022-03-31 00:34:47 +080040
41 /* TODO: to be reworked */
42 if (!running) {
developer7800b8d2022-06-23 22:15:56 +080043 ret = besra_mcu_set_hdr_trans(dev, true);
developerb11a5392022-03-31 00:34:47 +080044 if (ret)
45 goto out;
46
developer7800b8d2022-06-23 22:15:56 +080047 /* besra_mac_enable_nf(dev, dev->phy.band_idx); */
developerb11a5392022-03-31 00:34:47 +080048 }
49
50 /* if (phy_idx != MT_MAIN_PHY) { */
51 /* ret = mt76_connac_mcu_set_pm(&dev->mt76, phy->band_idx, 0); */
52 /* if (ret) */
53 /* goto out; */
54
developer7800b8d2022-06-23 22:15:56 +080055 /* besra_mac_enable_nf(dev, phy->band_idx); */
developerb11a5392022-03-31 00:34:47 +080056 /* } */
57
developer7800b8d2022-06-23 22:15:56 +080058 ret = besra_mcu_set_rts_thresh(phy, 0x92b);
developerb11a5392022-03-31 00:34:47 +080059 if (ret)
60 goto out;
61
developer7800b8d2022-06-23 22:15:56 +080062 ret = besra_mcu_set_edcca_thresh(phy);
developerb11a5392022-03-31 00:34:47 +080063 if (ret)
64 goto out;
65
developer7800b8d2022-06-23 22:15:56 +080066 ret = besra_mcu_set_edcca_en(phy, true);
developerb11a5392022-03-31 00:34:47 +080067 if (ret)
68 goto out;
69
70 /* TODO: to be reworked */
developer7800b8d2022-06-23 22:15:56 +080071 /* ret = besra_mcu_set_sku_en(phy, true); */
developerb11a5392022-03-31 00:34:47 +080072 /* if (ret) */
73 /* goto out; */
74
developer7800b8d2022-06-23 22:15:56 +080075 ret = besra_mcu_set_chan_info(phy, UNI_CHANNEL_RX_PATH);
developerb11a5392022-03-31 00:34:47 +080076 if (ret)
77 goto out;
78
79 set_bit(MT76_STATE_RUNNING, &phy->mt76->state);
80
81 ieee80211_iterate_interfaces(dev->mt76.hw,
82 IEEE80211_IFACE_ITER_RESUME_ALL,
developer7800b8d2022-06-23 22:15:56 +080083 besra_mcu_set_pm, dev->mt76.hw);
developerb11a5392022-03-31 00:34:47 +080084
85 if (!mt76_testmode_enabled(phy->mt76))
86 ieee80211_queue_delayed_work(hw, &phy->mt76->mac_work,
developer7800b8d2022-06-23 22:15:56 +080087 BESRA_WATCHDOG_TIME);
developerb11a5392022-03-31 00:34:47 +080088
89 if (!running)
developer7800b8d2022-06-23 22:15:56 +080090 besra_mac_reset_counters(phy);
developerb11a5392022-03-31 00:34:47 +080091
92out:
93 mutex_unlock(&dev->mt76.mutex);
94
95 return ret;
96}
97
developer7800b8d2022-06-23 22:15:56 +080098static void besra_stop(struct ieee80211_hw *hw)
developerb11a5392022-03-31 00:34:47 +080099{
developer7800b8d2022-06-23 22:15:56 +0800100 struct besra_dev *dev = besra_hw_dev(hw);
101 struct besra_phy *phy = besra_hw_phy(hw);
102 u8 phy_idx = besra_get_phy_id(phy);
developerb11a5392022-03-31 00:34:47 +0800103
104 cancel_delayed_work_sync(&phy->mt76->mac_work);
105
106 mutex_lock(&dev->mt76.mutex);
107
108 mt76_testmode_reset(phy->mt76, true);
109
110 clear_bit(MT76_STATE_RUNNING, &phy->mt76->state);
111
developer7800b8d2022-06-23 22:15:56 +0800112 besra_mcu_set_edcca_en(phy, false);
developerb11a5392022-03-31 00:34:47 +0800113
114 ieee80211_iterate_interfaces(dev->mt76.hw,
115 IEEE80211_IFACE_ITER_RESUME_ALL,
developer7800b8d2022-06-23 22:15:56 +0800116 besra_mcu_set_pm, dev->mt76.hw);
developerb11a5392022-03-31 00:34:47 +0800117
118 mutex_unlock(&dev->mt76.mutex);
119}
120
121static inline int get_free_idx(u32 mask, u8 start, u8 end)
122{
123 return ffs(~mask & GENMASK(end, start));
124}
125
126static int get_omac_idx(enum nl80211_iftype type, u64 mask)
127{
128 int i;
129
130 switch (type) {
131 case NL80211_IFTYPE_MESH_POINT:
132 case NL80211_IFTYPE_ADHOC:
133 case NL80211_IFTYPE_STATION:
134 /* prefer hw bssid slot 1-3 */
135 i = get_free_idx(mask, HW_BSSID_1, HW_BSSID_3);
136 if (i)
137 return i - 1;
138
139 if (type != NL80211_IFTYPE_STATION)
140 break;
141
142 i = get_free_idx(mask, EXT_BSSID_1, EXT_BSSID_MAX);
143 if (i)
144 return i - 1;
145
146 if (~mask & BIT(HW_BSSID_0))
147 return HW_BSSID_0;
148
149 break;
150 case NL80211_IFTYPE_MONITOR:
151 case NL80211_IFTYPE_AP:
152 /* ap uses hw bssid 0 and ext bssid */
153 if (~mask & BIT(HW_BSSID_0))
154 return HW_BSSID_0;
155
156 i = get_free_idx(mask, EXT_BSSID_1, EXT_BSSID_MAX);
157 if (i)
158 return i - 1;
159
160 break;
161 default:
162 WARN_ON(1);
163 break;
164 }
165
166 return -1;
167}
168
developer7800b8d2022-06-23 22:15:56 +0800169static void besra_init_bitrate_mask(struct ieee80211_vif *vif)
developerb11a5392022-03-31 00:34:47 +0800170{
developer7800b8d2022-06-23 22:15:56 +0800171 struct besra_vif *mvif = (struct besra_vif *)vif->drv_priv;
developerb11a5392022-03-31 00:34:47 +0800172 int i;
173
174 for (i = 0; i < ARRAY_SIZE(mvif->bitrate_mask.control); i++) {
175 mvif->bitrate_mask.control[i].gi = NL80211_TXRATE_DEFAULT_GI;
developer66cd2092022-05-10 15:43:01 +0800176 mvif->bitrate_mask.control[i].he_gi = 0xff;
177 mvif->bitrate_mask.control[i].he_ltf = 0xff;
developerb11a5392022-03-31 00:34:47 +0800178 mvif->bitrate_mask.control[i].legacy = GENMASK(31, 0);
developer66cd2092022-05-10 15:43:01 +0800179 memset(mvif->bitrate_mask.control[i].ht_mcs, 0xff,
developerb11a5392022-03-31 00:34:47 +0800180 sizeof(mvif->bitrate_mask.control[i].ht_mcs));
developer66cd2092022-05-10 15:43:01 +0800181 memset(mvif->bitrate_mask.control[i].vht_mcs, 0xff,
developerb11a5392022-03-31 00:34:47 +0800182 sizeof(mvif->bitrate_mask.control[i].vht_mcs));
developer66cd2092022-05-10 15:43:01 +0800183 memset(mvif->bitrate_mask.control[i].he_mcs, 0xff,
developerb11a5392022-03-31 00:34:47 +0800184 sizeof(mvif->bitrate_mask.control[i].he_mcs));
185 }
186}
187
developer7800b8d2022-06-23 22:15:56 +0800188static int besra_add_interface(struct ieee80211_hw *hw,
developerb11a5392022-03-31 00:34:47 +0800189 struct ieee80211_vif *vif)
190{
developer7800b8d2022-06-23 22:15:56 +0800191 struct besra_vif *mvif = (struct besra_vif *)vif->drv_priv;
192 struct besra_dev *dev = besra_hw_dev(hw);
193 struct besra_phy *phy = besra_hw_phy(hw);
developerb11a5392022-03-31 00:34:47 +0800194 struct mt76_txq *mtxq;
developer7800b8d2022-06-23 22:15:56 +0800195 u8 phy_idx = besra_get_phy_id(phy);
developerb11a5392022-03-31 00:34:47 +0800196 int idx, ret = 0;
197
198 mutex_lock(&dev->mt76.mutex);
199
200 mt76_testmode_reset(phy->mt76, true);
201
202 if (vif->type == NL80211_IFTYPE_MONITOR &&
203 is_zero_ether_addr(vif->addr))
204 phy->monitor_vif = vif;
205
developer66cd2092022-05-10 15:43:01 +0800206 mvif->mt76.idx = __ffs64(~dev->mt76.vif_mask);
developer7800b8d2022-06-23 22:15:56 +0800207 if (mvif->mt76.idx >= (BESRA_MAX_INTERFACES << dev->dbdc_support)) {
developerb11a5392022-03-31 00:34:47 +0800208 ret = -ENOSPC;
209 goto out;
210 }
211
212 idx = get_omac_idx(vif->type, phy->omac_mask);
213 if (idx < 0) {
214 ret = -ENOSPC;
215 goto out;
216 }
217 mvif->mt76.omac_idx = idx;
218 mvif->phy = phy;
219 mvif->mt76.band_idx = phy->band_idx;
220
221 if (phy_idx == MT_MAIN_PHY)
222 mvif->mt76.wmm_idx = 0;
223 else if (phy_idx == MT_EXT_PHY)
224 mvif->mt76.wmm_idx = 1;
225 else
226 mvif->mt76.wmm_idx = 2;
227
developer7800b8d2022-06-23 22:15:56 +0800228 ret = besra_mcu_add_dev_info(phy, vif, true);
developerb11a5392022-03-31 00:34:47 +0800229 if (ret)
230 goto out;
231
developer7800b8d2022-06-23 22:15:56 +0800232 ret = besra_mcu_set_radio_en(phy, true);
developerb11a5392022-03-31 00:34:47 +0800233 if (ret)
234 goto out;
235
developer66cd2092022-05-10 15:43:01 +0800236 dev->mt76.vif_mask |= BIT_ULL(mvif->mt76.idx);
developerb11a5392022-03-31 00:34:47 +0800237 phy->omac_mask |= BIT_ULL(mvif->mt76.omac_idx);
238
239 /* TODO: force this to 201 during devlopment stage */
developer7800b8d2022-06-23 22:15:56 +0800240 idx = BESRA_WTBL_RESERVED + mvif->mt76.idx;
developerb11a5392022-03-31 00:34:47 +0800241
242 INIT_LIST_HEAD(&mvif->sta.rc_list);
243 INIT_LIST_HEAD(&mvif->sta.poll_list);
244 mvif->sta.wcid.idx = idx;
245 mvif->sta.wcid.phy_idx = phy_idx;
246 mvif->sta.wcid.hw_key_idx = -1;
247 mvif->sta.wcid.tx_info |= MT_WCID_TX_INFO_SET;
248 mt76_packet_id_init(&mvif->sta.wcid);
249
developer7800b8d2022-06-23 22:15:56 +0800250 besra_mac_wtbl_update(dev, idx,
developerb11a5392022-03-31 00:34:47 +0800251 MT_WTBL_UPDATE_ADM_COUNT_CLEAR);
252
253 rcu_assign_pointer(dev->mt76.wcid[idx], &mvif->sta.wcid);
254 if (vif->txq) {
255 mtxq = (struct mt76_txq *)vif->txq->drv_priv;
developer66cd2092022-05-10 15:43:01 +0800256 mtxq->wcid = idx;
developerb11a5392022-03-31 00:34:47 +0800257 }
258
259 if (vif->type != NL80211_IFTYPE_AP &&
260 (!mvif->mt76.omac_idx || mvif->mt76.omac_idx > 3))
261 vif->offload_flags = 0;
262 vif->offload_flags |= IEEE80211_OFFLOAD_ENCAP_4ADDR;
263
developer7800b8d2022-06-23 22:15:56 +0800264 besra_init_bitrate_mask(vif);
developerb11a5392022-03-31 00:34:47 +0800265 memset(&mvif->cap, -1, sizeof(mvif->cap));
266
developer7800b8d2022-06-23 22:15:56 +0800267 besra_mcu_add_bss_info(phy, vif, true);
268 besra_mcu_add_sta(dev, vif, NULL, true);
developerb11a5392022-03-31 00:34:47 +0800269
270out:
271 mutex_unlock(&dev->mt76.mutex);
272
273 return ret;
274}
275
developer7800b8d2022-06-23 22:15:56 +0800276static void besra_remove_interface(struct ieee80211_hw *hw,
developerb11a5392022-03-31 00:34:47 +0800277 struct ieee80211_vif *vif)
278{
developer7800b8d2022-06-23 22:15:56 +0800279 struct besra_vif *mvif = (struct besra_vif *)vif->drv_priv;
280 struct besra_sta *msta = &mvif->sta;
281 struct besra_dev *dev = besra_hw_dev(hw);
282 struct besra_phy *phy = besra_hw_phy(hw);
developerb11a5392022-03-31 00:34:47 +0800283 int idx = msta->wcid.idx;
284
developer7800b8d2022-06-23 22:15:56 +0800285 besra_mcu_add_bss_info(phy, vif, false);
286 besra_mcu_add_sta(dev, vif, NULL, false);
developerb11a5392022-03-31 00:34:47 +0800287
288 mutex_lock(&dev->mt76.mutex);
289 mt76_testmode_reset(phy->mt76, true);
290 mutex_unlock(&dev->mt76.mutex);
291
292 if (vif == phy->monitor_vif)
293 phy->monitor_vif = NULL;
294
developer7800b8d2022-06-23 22:15:56 +0800295 besra_mcu_add_dev_info(phy, vif, false);
296 besra_mcu_set_radio_en(phy, false);
developerb11a5392022-03-31 00:34:47 +0800297
298 rcu_assign_pointer(dev->mt76.wcid[idx], NULL);
299
300 mutex_lock(&dev->mt76.mutex);
developer66cd2092022-05-10 15:43:01 +0800301 dev->mt76.vif_mask &= ~BIT_ULL(mvif->mt76.idx);
developerb11a5392022-03-31 00:34:47 +0800302 phy->omac_mask &= ~BIT_ULL(mvif->mt76.omac_idx);
303 mutex_unlock(&dev->mt76.mutex);
304
305 spin_lock_bh(&dev->sta_poll_lock);
306 if (!list_empty(&msta->poll_list))
307 list_del_init(&msta->poll_list);
308 spin_unlock_bh(&dev->sta_poll_lock);
309
310 mt76_packet_id_flush(&dev->mt76, &msta->wcid);
311}
312
developer7800b8d2022-06-23 22:15:56 +0800313int besra_set_channel(struct besra_phy *phy)
developerb11a5392022-03-31 00:34:47 +0800314{
developer7800b8d2022-06-23 22:15:56 +0800315 struct besra_dev *dev = phy->dev;
developerb11a5392022-03-31 00:34:47 +0800316 int ret;
317
318 cancel_delayed_work_sync(&phy->mt76->mac_work);
319
320 mutex_lock(&dev->mt76.mutex);
321 set_bit(MT76_RESET, &phy->mt76->state);
322
323 mt76_set_channel(phy->mt76);
324
325 if (dev->flash_mode) {
developer7800b8d2022-06-23 22:15:56 +0800326 ret = besra_mcu_apply_tx_dpd(phy);
developerb11a5392022-03-31 00:34:47 +0800327 if (ret)
328 goto out;
329 }
330
developer7800b8d2022-06-23 22:15:56 +0800331 ret = besra_mcu_set_chan_info(phy, UNI_CHANNEL_SWITCH);
developerb11a5392022-03-31 00:34:47 +0800332 if (ret)
333 goto out;
334
developer7800b8d2022-06-23 22:15:56 +0800335 besra_mac_set_timing(phy);
336 ret = besra_dfs_init_radar_detector(phy);
337 besra_mac_cca_stats_reset(phy);
developerb11a5392022-03-31 00:34:47 +0800338
developer7800b8d2022-06-23 22:15:56 +0800339 besra_mac_reset_counters(phy);
developerb11a5392022-03-31 00:34:47 +0800340 phy->noise = 0;
341
342out:
343 clear_bit(MT76_RESET, &phy->mt76->state);
344 mutex_unlock(&dev->mt76.mutex);
345
346 mt76_txq_schedule_all(phy->mt76);
347
348 if (!mt76_testmode_enabled(phy->mt76))
349 ieee80211_queue_delayed_work(phy->mt76->hw,
350 &phy->mt76->mac_work,
developer7800b8d2022-06-23 22:15:56 +0800351 BESRA_WATCHDOG_TIME);
developerb11a5392022-03-31 00:34:47 +0800352
353 return ret;
354}
355
developer7800b8d2022-06-23 22:15:56 +0800356static int besra_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
developerb11a5392022-03-31 00:34:47 +0800357 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
358 struct ieee80211_key_conf *key)
359{
developer7800b8d2022-06-23 22:15:56 +0800360 struct besra_dev *dev = besra_hw_dev(hw);
361 struct besra_phy *phy = besra_hw_phy(hw);
362 struct besra_vif *mvif = (struct besra_vif *)vif->drv_priv;
363 struct besra_sta *msta = sta ? (struct besra_sta *)sta->drv_priv :
developerb11a5392022-03-31 00:34:47 +0800364 &mvif->sta;
365 struct mt76_wcid *wcid = &msta->wcid;
366 u8 *wcid_keyidx = &wcid->hw_key_idx;
367 int idx = key->keyidx;
368 int err = 0;
369
370 /* The hardware does not support per-STA RX GTK, fallback
371 * to software mode for these.
372 */
373 if ((vif->type == NL80211_IFTYPE_ADHOC ||
374 vif->type == NL80211_IFTYPE_MESH_POINT) &&
375 (key->cipher == WLAN_CIPHER_SUITE_TKIP ||
376 key->cipher == WLAN_CIPHER_SUITE_CCMP) &&
377 !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE))
378 return -EOPNOTSUPP;
379
380 /* fall back to sw encryption for unsupported ciphers */
381 switch (key->cipher) {
382 case WLAN_CIPHER_SUITE_AES_CMAC:
383 wcid_keyidx = &wcid->hw_key_idx2;
384 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIE;
385 break;
386 case WLAN_CIPHER_SUITE_TKIP:
387 case WLAN_CIPHER_SUITE_CCMP:
388 case WLAN_CIPHER_SUITE_CCMP_256:
389 case WLAN_CIPHER_SUITE_GCMP:
390 case WLAN_CIPHER_SUITE_GCMP_256:
391 case WLAN_CIPHER_SUITE_SMS4:
392 break;
393 case WLAN_CIPHER_SUITE_WEP40:
394 case WLAN_CIPHER_SUITE_WEP104:
395 default:
396 return -EOPNOTSUPP;
397 }
398
399 mutex_lock(&dev->mt76.mutex);
400
401 if (cmd == SET_KEY && !sta && !mvif->mt76.cipher) {
402 mvif->mt76.cipher = mt76_connac_mcu_get_cipher(key->cipher);
developer7800b8d2022-06-23 22:15:56 +0800403 besra_mcu_add_bss_info(phy, vif, true);
developerb11a5392022-03-31 00:34:47 +0800404 }
405
406 if (cmd == SET_KEY)
407 *wcid_keyidx = idx;
408 else if (idx == *wcid_keyidx)
409 *wcid_keyidx = -1;
410 else
411 goto out;
412
413 mt76_wcid_key_setup(&dev->mt76, wcid,
414 cmd == SET_KEY ? key : NULL);
415
developer7800b8d2022-06-23 22:15:56 +0800416 err = besra_mcu_add_key(&dev->mt76, vif, &msta->bip,
developerb11a5392022-03-31 00:34:47 +0800417 key, MCU_WMWA_UNI_CMD(STA_REC_UPDATE),
418 &msta->wcid, cmd);
419out:
420 mutex_unlock(&dev->mt76.mutex);
421
422 return err;
423}
424
developer7800b8d2022-06-23 22:15:56 +0800425static int besra_set_sar_specs(struct ieee80211_hw *hw,
developerb11a5392022-03-31 00:34:47 +0800426 const struct cfg80211_sar_specs *sar)
427{
developer7800b8d2022-06-23 22:15:56 +0800428 struct besra_phy *phy = besra_hw_phy(hw);
429 struct besra_dev *dev = besra_hw_dev(hw);
developerb11a5392022-03-31 00:34:47 +0800430 int err = -EINVAL;
431
432 mutex_lock(&dev->mt76.mutex);
433 if (!cfg80211_chandef_valid(&phy->mt76->chandef))
434 goto out;
435
436 err = mt76_init_sar_power(hw, sar);
437 if (err)
438 goto out;
439
440 /* TODO: need check */
developer7800b8d2022-06-23 22:15:56 +0800441 /* err = besra_mcu_set_txpower_sku(phy); */
developerb11a5392022-03-31 00:34:47 +0800442out:
443 mutex_unlock(&dev->mt76.mutex);
444
445 return err;
446}
447
developer7800b8d2022-06-23 22:15:56 +0800448static int besra_config(struct ieee80211_hw *hw, u32 changed)
developerb11a5392022-03-31 00:34:47 +0800449{
developer7800b8d2022-06-23 22:15:56 +0800450 struct besra_dev *dev = besra_hw_dev(hw);
451 struct besra_phy *phy = besra_hw_phy(hw);
developerb11a5392022-03-31 00:34:47 +0800452 int ret;
453
454 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
455#ifdef CONFIG_NL80211_TESTMODE
456 if (phy->mt76->test.state != MT76_TM_STATE_OFF) {
457 mutex_lock(&dev->mt76.mutex);
458 mt76_testmode_reset(phy->mt76, false);
459 mutex_unlock(&dev->mt76.mutex);
460 }
461#endif
462 ieee80211_stop_queues(hw);
developer7800b8d2022-06-23 22:15:56 +0800463 ret = besra_set_channel(phy);
developerb11a5392022-03-31 00:34:47 +0800464 if (ret)
465 return ret;
466 ieee80211_wake_queues(hw);
467 }
468
469 /* TODO: need check */
470 /* if (changed & IEEE80211_CONF_CHANGE_POWER) { */
developer7800b8d2022-06-23 22:15:56 +0800471 /* ret = besra_mcu_set_txpower_sku(phy); */
developerb11a5392022-03-31 00:34:47 +0800472 /* if (ret) */
473 /* return ret; */
474 /* } */
475
476 mutex_lock(&dev->mt76.mutex);
477
478 if (changed & IEEE80211_CONF_CHANGE_MONITOR) {
479 bool enabled = !!(hw->conf.flags & IEEE80211_CONF_MONITOR);
480
481 if (!enabled)
482 phy->rxfilter |= MT_WF_RFCR_DROP_OTHER_UC;
483 else
484 phy->rxfilter &= ~MT_WF_RFCR_DROP_OTHER_UC;
485
486 mt76_rmw_field(dev, MT_DMA_DCR0(phy->band_idx), MT_DMA_DCR0_RXD_G5_EN,
487 enabled);
488 mt76_testmode_reset(phy->mt76, true);
489 mt76_wr(dev, MT_WF_RFCR(phy->band_idx), phy->rxfilter);
490 }
491
492 mutex_unlock(&dev->mt76.mutex);
493
494 return 0;
495}
496
497static int
developer7800b8d2022-06-23 22:15:56 +0800498besra_conf_tx(struct ieee80211_hw *hw, struct ieee80211_vif *vif, u16 queue,
developerb11a5392022-03-31 00:34:47 +0800499 const struct ieee80211_tx_queue_params *params)
500{
developer7800b8d2022-06-23 22:15:56 +0800501 struct besra_vif *mvif = (struct besra_vif *)vif->drv_priv;
developerb11a5392022-03-31 00:34:47 +0800502
503 /* no need to update right away, we'll get BSS_CHANGED_QOS */
504 queue = mt76_connac_lmac_mapping(queue);
505 mvif->queue_params[queue] = *params;
506
507 return 0;
508}
509
developer7800b8d2022-06-23 22:15:56 +0800510static void besra_configure_filter(struct ieee80211_hw *hw,
developerb11a5392022-03-31 00:34:47 +0800511 unsigned int changed_flags,
512 unsigned int *total_flags,
513 u64 multicast)
514{
developer7800b8d2022-06-23 22:15:56 +0800515 struct besra_dev *dev = besra_hw_dev(hw);
516 struct besra_phy *phy = besra_hw_phy(hw);
developerb11a5392022-03-31 00:34:47 +0800517 u32 ctl_flags = MT_WF_RFCR1_DROP_ACK |
518 MT_WF_RFCR1_DROP_BF_POLL |
519 MT_WF_RFCR1_DROP_BA |
520 MT_WF_RFCR1_DROP_CFEND |
521 MT_WF_RFCR1_DROP_CFACK;
522 u32 flags = 0;
523
524#define MT76_FILTER(_flag, _hw) do { \
525 flags |= *total_flags & FIF_##_flag; \
526 phy->rxfilter &= ~(_hw); \
527 phy->rxfilter |= !(flags & FIF_##_flag) * (_hw); \
528 } while (0)
529
530 mutex_lock(&dev->mt76.mutex);
531
532 phy->rxfilter &= ~(MT_WF_RFCR_DROP_OTHER_BSS |
533 MT_WF_RFCR_DROP_OTHER_BEACON |
534 MT_WF_RFCR_DROP_FRAME_REPORT |
535 MT_WF_RFCR_DROP_PROBEREQ |
536 MT_WF_RFCR_DROP_MCAST_FILTERED |
537 MT_WF_RFCR_DROP_MCAST |
538 MT_WF_RFCR_DROP_BCAST |
539 MT_WF_RFCR_DROP_DUPLICATE |
540 MT_WF_RFCR_DROP_A2_BSSID |
541 MT_WF_RFCR_DROP_UNWANTED_CTL |
542 MT_WF_RFCR_DROP_STBC_MULTI);
543
544 MT76_FILTER(OTHER_BSS, MT_WF_RFCR_DROP_OTHER_TIM |
545 MT_WF_RFCR_DROP_A3_MAC |
546 MT_WF_RFCR_DROP_A3_BSSID);
547
548 MT76_FILTER(FCSFAIL, MT_WF_RFCR_DROP_FCSFAIL);
549
550 MT76_FILTER(CONTROL, MT_WF_RFCR_DROP_CTS |
551 MT_WF_RFCR_DROP_RTS |
552 MT_WF_RFCR_DROP_CTL_RSV |
553 MT_WF_RFCR_DROP_NDPA);
554
555 *total_flags = flags;
556 mt76_wr(dev, MT_WF_RFCR(phy->band_idx), phy->rxfilter);
557
558 if (*total_flags & FIF_CONTROL)
559 mt76_clear(dev, MT_WF_RFCR1(phy->band_idx), ctl_flags);
560 else
561 mt76_set(dev, MT_WF_RFCR1(phy->band_idx), ctl_flags);
562
563 mutex_unlock(&dev->mt76.mutex);
564}
565
566static void
developer7800b8d2022-06-23 22:15:56 +0800567besra_update_bss_color(struct ieee80211_hw *hw,
developerb11a5392022-03-31 00:34:47 +0800568 struct ieee80211_vif *vif,
569 struct cfg80211_he_bss_color *bss_color)
570{
developer7800b8d2022-06-23 22:15:56 +0800571 struct besra_dev *dev = besra_hw_dev(hw);
developerb11a5392022-03-31 00:34:47 +0800572
573 switch (vif->type) {
574 case NL80211_IFTYPE_AP: {
developer7800b8d2022-06-23 22:15:56 +0800575 struct besra_vif *mvif = (struct besra_vif *)vif->drv_priv;
developerb11a5392022-03-31 00:34:47 +0800576
577 if (mvif->mt76.omac_idx > HW_BSSID_MAX)
578 return;
579 fallthrough;
580 }
581 case NL80211_IFTYPE_STATION:
developer7800b8d2022-06-23 22:15:56 +0800582 besra_mcu_update_bss_color(dev, vif, bss_color);
developerb11a5392022-03-31 00:34:47 +0800583 break;
584 default:
585 break;
586 }
587}
588
developer7800b8d2022-06-23 22:15:56 +0800589static void besra_bss_info_changed(struct ieee80211_hw *hw,
developerb11a5392022-03-31 00:34:47 +0800590 struct ieee80211_vif *vif,
591 struct ieee80211_bss_conf *info,
592 u32 changed)
593{
developer7800b8d2022-06-23 22:15:56 +0800594 struct besra_phy *phy = besra_hw_phy(hw);
595 struct besra_dev *dev = besra_hw_dev(hw);
developerb11a5392022-03-31 00:34:47 +0800596
597 mutex_lock(&dev->mt76.mutex);
598
599 /*
600 * station mode uses BSSID to map the wlan entry to a peer,
601 * and then peer references bss_info_rfch to set bandwidth cap.
602 */
603 if (changed & BSS_CHANGED_BSSID &&
604 vif->type == NL80211_IFTYPE_STATION) {
605 bool join = !is_zero_ether_addr(info->bssid);
606
developer7800b8d2022-06-23 22:15:56 +0800607 besra_mcu_add_bss_info(phy, vif, join);
608 besra_mcu_add_sta(dev, vif, NULL, join);
developerb11a5392022-03-31 00:34:47 +0800609 }
610
611 if (changed & BSS_CHANGED_ASSOC) {
developer7800b8d2022-06-23 22:15:56 +0800612 besra_mcu_add_bss_info(phy, vif, info->assoc);
613 besra_mcu_add_obss_spr(dev, vif, info->he_obss_pd.enable);
developerb11a5392022-03-31 00:34:47 +0800614 }
615
616 if (changed & BSS_CHANGED_ERP_SLOT) {
617 int slottime = info->use_short_slot ? 9 : 20;
618
619 if (slottime != phy->slottime) {
620 phy->slottime = slottime;
developer7800b8d2022-06-23 22:15:56 +0800621 besra_mac_set_timing(phy);
developerb11a5392022-03-31 00:34:47 +0800622 }
623 }
624
625 if (changed & BSS_CHANGED_BEACON_ENABLED && info->enable_beacon) {
developer7800b8d2022-06-23 22:15:56 +0800626 besra_mcu_add_bss_info(phy, vif, true);
627 besra_mcu_add_sta(dev, vif, NULL, true);
developerb11a5392022-03-31 00:34:47 +0800628 }
629
630 /* ensure that enable txcmd_mode after bss_info */
631 if (changed & (BSS_CHANGED_QOS | BSS_CHANGED_BEACON_ENABLED))
developer7800b8d2022-06-23 22:15:56 +0800632 besra_mcu_set_tx(dev, vif);
developerb11a5392022-03-31 00:34:47 +0800633
634 if (changed & BSS_CHANGED_HE_OBSS_PD)
developer7800b8d2022-06-23 22:15:56 +0800635 besra_mcu_add_obss_spr(dev, vif, info->he_obss_pd.enable);
developerb11a5392022-03-31 00:34:47 +0800636
637 if (changed & BSS_CHANGED_HE_BSS_COLOR)
developer7800b8d2022-06-23 22:15:56 +0800638 besra_update_bss_color(hw, vif, &info->he_bss_color);
developerb11a5392022-03-31 00:34:47 +0800639
640 if (changed & (BSS_CHANGED_BEACON |
641 BSS_CHANGED_BEACON_ENABLED))
developer7800b8d2022-06-23 22:15:56 +0800642 besra_mcu_add_beacon(hw, vif, info->enable_beacon);
developerb11a5392022-03-31 00:34:47 +0800643
644 mutex_unlock(&dev->mt76.mutex);
645}
646
647static void
developer7800b8d2022-06-23 22:15:56 +0800648besra_channel_switch_beacon(struct ieee80211_hw *hw,
developerb11a5392022-03-31 00:34:47 +0800649 struct ieee80211_vif *vif,
650 struct cfg80211_chan_def *chandef)
651{
developer7800b8d2022-06-23 22:15:56 +0800652 struct besra_dev *dev = besra_hw_dev(hw);
developerb11a5392022-03-31 00:34:47 +0800653
654 mutex_lock(&dev->mt76.mutex);
developer7800b8d2022-06-23 22:15:56 +0800655 besra_mcu_add_beacon(hw, vif, true);
developerb11a5392022-03-31 00:34:47 +0800656 mutex_unlock(&dev->mt76.mutex);
657}
658
developer7800b8d2022-06-23 22:15:56 +0800659int besra_mac_sta_add(struct mt76_dev *mdev, struct ieee80211_vif *vif,
developerb11a5392022-03-31 00:34:47 +0800660 struct ieee80211_sta *sta)
661{
developer7800b8d2022-06-23 22:15:56 +0800662 struct besra_dev *dev = container_of(mdev, struct besra_dev, mt76);
663 struct besra_sta *msta = (struct besra_sta *)sta->drv_priv;
664 struct besra_vif *mvif = (struct besra_vif *)vif->drv_priv;
665 u8 phy_idx = besra_get_phy_id(mvif->phy);
developerb11a5392022-03-31 00:34:47 +0800666 int ret, idx;
667
developer7800b8d2022-06-23 22:15:56 +0800668 idx = mt76_wcid_alloc(dev->mt76.wcid_mask, BESRA_WTBL_STA);
developerb11a5392022-03-31 00:34:47 +0800669 if (idx < 0)
670 return -ENOSPC;
671
672 INIT_LIST_HEAD(&msta->rc_list);
673 INIT_LIST_HEAD(&msta->poll_list);
674 msta->vif = mvif;
675 msta->wcid.sta = 1;
676 msta->wcid.idx = idx;
677 msta->wcid.phy_idx = phy_idx;
678 msta->wcid.tx_info |= MT_WCID_TX_INFO_SET;
679 msta->jiffies = jiffies;
680
developer7800b8d2022-06-23 22:15:56 +0800681 besra_mac_wtbl_update(dev, idx,
developerb11a5392022-03-31 00:34:47 +0800682 MT_WTBL_UPDATE_ADM_COUNT_CLEAR);
683
developer7800b8d2022-06-23 22:15:56 +0800684 ret = besra_mcu_add_sta(dev, vif, sta, true);
developerb11a5392022-03-31 00:34:47 +0800685 if (ret)
686 return ret;
687
developer7800b8d2022-06-23 22:15:56 +0800688 return besra_mcu_add_rate_ctrl(dev, vif, sta, false);
developerb11a5392022-03-31 00:34:47 +0800689}
690
developer7800b8d2022-06-23 22:15:56 +0800691void besra_mac_sta_remove(struct mt76_dev *mdev, struct ieee80211_vif *vif,
developerb11a5392022-03-31 00:34:47 +0800692 struct ieee80211_sta *sta)
693{
developer7800b8d2022-06-23 22:15:56 +0800694 struct besra_dev *dev = container_of(mdev, struct besra_dev, mt76);
695 struct besra_sta *msta = (struct besra_sta *)sta->drv_priv;
developerb11a5392022-03-31 00:34:47 +0800696 int i;
697
developer7800b8d2022-06-23 22:15:56 +0800698 besra_mcu_add_sta(dev, vif, sta, false);
developerb11a5392022-03-31 00:34:47 +0800699
developer7800b8d2022-06-23 22:15:56 +0800700 besra_mac_wtbl_update(dev, msta->wcid.idx,
developerb11a5392022-03-31 00:34:47 +0800701 MT_WTBL_UPDATE_ADM_COUNT_CLEAR);
702
703 for (i = 0; i < ARRAY_SIZE(msta->twt.flow); i++)
developer7800b8d2022-06-23 22:15:56 +0800704 besra_mac_twt_teardown_flow(dev, msta, i);
developerb11a5392022-03-31 00:34:47 +0800705
706 spin_lock_bh(&dev->sta_poll_lock);
707 if (!list_empty(&msta->poll_list))
708 list_del_init(&msta->poll_list);
709 if (!list_empty(&msta->rc_list))
710 list_del_init(&msta->rc_list);
711 spin_unlock_bh(&dev->sta_poll_lock);
712}
713
developer7800b8d2022-06-23 22:15:56 +0800714static void besra_tx(struct ieee80211_hw *hw,
developerb11a5392022-03-31 00:34:47 +0800715 struct ieee80211_tx_control *control,
716 struct sk_buff *skb)
717{
developer7800b8d2022-06-23 22:15:56 +0800718 struct besra_dev *dev = besra_hw_dev(hw);
developerb11a5392022-03-31 00:34:47 +0800719 struct mt76_phy *mphy = hw->priv;
720 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
721 struct ieee80211_vif *vif = info->control.vif;
722 struct mt76_wcid *wcid = &dev->mt76.global_wcid;
723
724 if (control->sta) {
developer7800b8d2022-06-23 22:15:56 +0800725 struct besra_sta *sta;
developerb11a5392022-03-31 00:34:47 +0800726
developer7800b8d2022-06-23 22:15:56 +0800727 sta = (struct besra_sta *)control->sta->drv_priv;
developerb11a5392022-03-31 00:34:47 +0800728 wcid = &sta->wcid;
729 }
730
731 if (vif && !control->sta) {
developer7800b8d2022-06-23 22:15:56 +0800732 struct besra_vif *mvif;
developerb11a5392022-03-31 00:34:47 +0800733
developer7800b8d2022-06-23 22:15:56 +0800734 mvif = (struct besra_vif *)vif->drv_priv;
developerb11a5392022-03-31 00:34:47 +0800735 wcid = &mvif->sta.wcid;
736 }
737
738 mt76_tx(mphy, control->sta, wcid, skb);
739}
740
developer7800b8d2022-06-23 22:15:56 +0800741static int besra_set_rts_threshold(struct ieee80211_hw *hw, u32 val)
developerb11a5392022-03-31 00:34:47 +0800742{
developer7800b8d2022-06-23 22:15:56 +0800743 struct besra_dev *dev = besra_hw_dev(hw);
744 struct besra_phy *phy = besra_hw_phy(hw);
developerb11a5392022-03-31 00:34:47 +0800745 int ret;
746
747 mutex_lock(&dev->mt76.mutex);
developer7800b8d2022-06-23 22:15:56 +0800748 ret = besra_mcu_set_rts_thresh(phy, val);
developerb11a5392022-03-31 00:34:47 +0800749 mutex_unlock(&dev->mt76.mutex);
750
751 return ret;
752}
753
754static int
developer7800b8d2022-06-23 22:15:56 +0800755besra_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
developerb11a5392022-03-31 00:34:47 +0800756 struct ieee80211_ampdu_params *params)
757{
758 enum ieee80211_ampdu_mlme_action action = params->action;
developer7800b8d2022-06-23 22:15:56 +0800759 struct besra_dev *dev = besra_hw_dev(hw);
developerb11a5392022-03-31 00:34:47 +0800760 struct ieee80211_sta *sta = params->sta;
761 struct ieee80211_txq *txq = sta->txq[params->tid];
developer7800b8d2022-06-23 22:15:56 +0800762 struct besra_sta *msta = (struct besra_sta *)sta->drv_priv;
developerb11a5392022-03-31 00:34:47 +0800763 u16 tid = params->tid;
764 u16 ssn = params->ssn;
765 struct mt76_txq *mtxq;
766 int ret = 0;
767
768 if (!txq)
769 return -EINVAL;
770
771 mtxq = (struct mt76_txq *)txq->drv_priv;
772
773 mutex_lock(&dev->mt76.mutex);
774 switch (action) {
775 case IEEE80211_AMPDU_RX_START:
776 mt76_rx_aggr_start(&dev->mt76, &msta->wcid, tid, ssn,
777 params->buf_size);
developer7800b8d2022-06-23 22:15:56 +0800778 ret = besra_mcu_add_rx_ba(dev, params, true);
developerb11a5392022-03-31 00:34:47 +0800779 break;
780 case IEEE80211_AMPDU_RX_STOP:
781 mt76_rx_aggr_stop(&dev->mt76, &msta->wcid, tid);
developer7800b8d2022-06-23 22:15:56 +0800782 ret = besra_mcu_add_rx_ba(dev, params, false);
developerb11a5392022-03-31 00:34:47 +0800783 break;
784 case IEEE80211_AMPDU_TX_OPERATIONAL:
785 mtxq->aggr = true;
786 mtxq->send_bar = false;
developer7800b8d2022-06-23 22:15:56 +0800787 ret = besra_mcu_add_tx_ba(dev, params, true);
developerb11a5392022-03-31 00:34:47 +0800788 break;
789 case IEEE80211_AMPDU_TX_STOP_FLUSH:
790 case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
791 mtxq->aggr = false;
792 clear_bit(tid, &msta->ampdu_state);
developer7800b8d2022-06-23 22:15:56 +0800793 ret = besra_mcu_add_tx_ba(dev, params, false);
developerb11a5392022-03-31 00:34:47 +0800794 break;
795 case IEEE80211_AMPDU_TX_START:
796 set_bit(tid, &msta->ampdu_state);
797 ret = IEEE80211_AMPDU_TX_START_IMMEDIATE;
798 break;
799 case IEEE80211_AMPDU_TX_STOP_CONT:
800 mtxq->aggr = false;
801 clear_bit(tid, &msta->ampdu_state);
developer7800b8d2022-06-23 22:15:56 +0800802 ret = besra_mcu_add_tx_ba(dev, params, false);
developerb11a5392022-03-31 00:34:47 +0800803 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
804 break;
805 }
806 mutex_unlock(&dev->mt76.mutex);
807
808 return ret;
809}
810
811static int
developer7800b8d2022-06-23 22:15:56 +0800812besra_sta_add(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
developerb11a5392022-03-31 00:34:47 +0800813 struct ieee80211_sta *sta)
814{
815 return mt76_sta_state(hw, vif, sta, IEEE80211_STA_NOTEXIST,
816 IEEE80211_STA_NONE);
817}
818
819static int
developer7800b8d2022-06-23 22:15:56 +0800820besra_sta_remove(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
developerb11a5392022-03-31 00:34:47 +0800821 struct ieee80211_sta *sta)
822{
823 return mt76_sta_state(hw, vif, sta, IEEE80211_STA_NONE,
824 IEEE80211_STA_NOTEXIST);
825}
826
827static int
developer7800b8d2022-06-23 22:15:56 +0800828besra_get_stats(struct ieee80211_hw *hw,
developerb11a5392022-03-31 00:34:47 +0800829 struct ieee80211_low_level_stats *stats)
830{
developer7800b8d2022-06-23 22:15:56 +0800831 struct besra_phy *phy = besra_hw_phy(hw);
832 struct besra_dev *dev = besra_hw_dev(hw);
developerb11a5392022-03-31 00:34:47 +0800833 struct mib_stats *mib = &phy->mib;
834
835 mutex_lock(&dev->mt76.mutex);
836
837 stats->dot11RTSSuccessCount = mib->rts_cnt;
838 stats->dot11RTSFailureCount = mib->rts_retries_cnt;
839 stats->dot11FCSErrorCount = mib->fcs_err_cnt;
840 stats->dot11ACKFailureCount = mib->ack_fail_cnt;
841
842 mutex_unlock(&dev->mt76.mutex);
843
844 return 0;
845}
846
developer7800b8d2022-06-23 22:15:56 +0800847u64 __besra_get_tsf(struct ieee80211_hw *hw, struct besra_vif *mvif)
developerb11a5392022-03-31 00:34:47 +0800848{
developer7800b8d2022-06-23 22:15:56 +0800849 struct besra_dev *dev = besra_hw_dev(hw);
850 struct besra_phy *phy = besra_hw_phy(hw);
developerb11a5392022-03-31 00:34:47 +0800851 union {
852 u64 t64;
853 u32 t32[2];
854 } tsf;
855 u16 n;
856
857 lockdep_assert_held(&dev->mt76.mutex);
858
859 n = mvif->mt76.omac_idx > HW_BSSID_MAX ? HW_BSSID_0
860 : mvif->mt76.omac_idx;
861 /* TSF software read */
862 mt76_rmw(dev, MT_LPON_TCR(phy->band_idx, n), MT_LPON_TCR_SW_MODE,
863 MT_LPON_TCR_SW_READ);
864 tsf.t32[0] = mt76_rr(dev, MT_LPON_UTTR0(phy->band_idx));
865 tsf.t32[1] = mt76_rr(dev, MT_LPON_UTTR1(phy->band_idx));
866
867 return tsf.t64;
868}
869
870static u64
developer7800b8d2022-06-23 22:15:56 +0800871besra_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
developerb11a5392022-03-31 00:34:47 +0800872{
developer7800b8d2022-06-23 22:15:56 +0800873 struct besra_vif *mvif = (struct besra_vif *)vif->drv_priv;
874 struct besra_dev *dev = besra_hw_dev(hw);
developerb11a5392022-03-31 00:34:47 +0800875 u64 ret;
876
877 mutex_lock(&dev->mt76.mutex);
developer7800b8d2022-06-23 22:15:56 +0800878 ret = __besra_get_tsf(hw, mvif);
developerb11a5392022-03-31 00:34:47 +0800879 mutex_unlock(&dev->mt76.mutex);
880
881 return ret;
882}
883
884static void
developer7800b8d2022-06-23 22:15:56 +0800885besra_set_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
developerb11a5392022-03-31 00:34:47 +0800886 u64 timestamp)
887{
developer7800b8d2022-06-23 22:15:56 +0800888 struct besra_vif *mvif = (struct besra_vif *)vif->drv_priv;
889 struct besra_dev *dev = besra_hw_dev(hw);
890 struct besra_phy *phy = besra_hw_phy(hw);
developerb11a5392022-03-31 00:34:47 +0800891 union {
892 u64 t64;
893 u32 t32[2];
894 } tsf = { .t64 = timestamp, };
895 u16 n;
896
897 mutex_lock(&dev->mt76.mutex);
898
899 n = mvif->mt76.omac_idx > HW_BSSID_MAX ? HW_BSSID_0
900 : mvif->mt76.omac_idx;
901 mt76_wr(dev, MT_LPON_UTTR0(phy->band_idx), tsf.t32[0]);
902 mt76_wr(dev, MT_LPON_UTTR1(phy->band_idx), tsf.t32[1]);
903 /* TSF software overwrite */
904 mt76_rmw(dev, MT_LPON_TCR(phy->band_idx, n), MT_LPON_TCR_SW_MODE,
905 MT_LPON_TCR_SW_WRITE);
906
907 mutex_unlock(&dev->mt76.mutex);
908}
909
910static void
developer7800b8d2022-06-23 22:15:56 +0800911besra_offset_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
developerb11a5392022-03-31 00:34:47 +0800912 s64 timestamp)
913{
developer7800b8d2022-06-23 22:15:56 +0800914 struct besra_vif *mvif = (struct besra_vif *)vif->drv_priv;
915 struct besra_dev *dev = besra_hw_dev(hw);
916 struct besra_phy *phy = besra_hw_phy(hw);
developerb11a5392022-03-31 00:34:47 +0800917 union {
918 u64 t64;
919 u32 t32[2];
920 } tsf = { .t64 = timestamp, };
921 u16 n;
922
923 mutex_lock(&dev->mt76.mutex);
924
925 n = mvif->mt76.omac_idx > HW_BSSID_MAX ? HW_BSSID_0
926 : mvif->mt76.omac_idx;
927 mt76_wr(dev, MT_LPON_UTTR0(phy->band_idx), tsf.t32[0]);
928 mt76_wr(dev, MT_LPON_UTTR1(phy->band_idx), tsf.t32[1]);
929 /* TSF software adjust*/
930 mt76_rmw(dev, MT_LPON_TCR(phy->band_idx, n), MT_LPON_TCR_SW_MODE,
931 MT_LPON_TCR_SW_ADJUST);
932
933 mutex_unlock(&dev->mt76.mutex);
934}
935
936static void
developer7800b8d2022-06-23 22:15:56 +0800937besra_set_coverage_class(struct ieee80211_hw *hw, s16 coverage_class)
developerb11a5392022-03-31 00:34:47 +0800938{
developer7800b8d2022-06-23 22:15:56 +0800939 struct besra_phy *phy = besra_hw_phy(hw);
940 struct besra_dev *dev = phy->dev;
developerb11a5392022-03-31 00:34:47 +0800941
942 mutex_lock(&dev->mt76.mutex);
943 phy->coverage_class = max_t(s16, coverage_class, 0);
developer7800b8d2022-06-23 22:15:56 +0800944 besra_mac_set_timing(phy);
developerb11a5392022-03-31 00:34:47 +0800945 mutex_unlock(&dev->mt76.mutex);
946}
947
948static int
developer7800b8d2022-06-23 22:15:56 +0800949besra_set_antenna(struct ieee80211_hw *hw, u32 tx_ant, u32 rx_ant)
developerb11a5392022-03-31 00:34:47 +0800950{
developer7800b8d2022-06-23 22:15:56 +0800951 struct besra_dev *dev = besra_hw_dev(hw);
952 struct besra_phy *phy = besra_hw_phy(hw);
developerb11a5392022-03-31 00:34:47 +0800953 int max_nss = hweight8(hw->wiphy->available_antennas_tx);
developer7800b8d2022-06-23 22:15:56 +0800954 u8 phy_idx = besra_get_phy_id(phy);
developerb11a5392022-03-31 00:34:47 +0800955 u16 chainshift;
956
957 if (!tx_ant || tx_ant != rx_ant || ffs(tx_ant) > max_nss)
958 return -EINVAL;
959
960 if ((BIT(hweight8(tx_ant)) - 1) != tx_ant)
961 tx_ant = BIT(ffs(tx_ant) - 1) - 1;
962
963 mutex_lock(&dev->mt76.mutex);
964
965 phy->mt76->antenna_mask = tx_ant;
966
967 if (phy_idx == MT_MAIN_PHY)
968 chainshift = 0;
969 else if (phy_idx == MT_EXT_PHY)
970 chainshift = dev->chain_shift_ext;
971 else
972 chainshift = dev->chain_shift_tri;
973
974 tx_ant <<= chainshift;
975
976 phy->mt76->chainmask = tx_ant;
977
978 mt76_set_stream_caps(phy->mt76, true);
developer7800b8d2022-06-23 22:15:56 +0800979 besra_set_stream_vht_txbf_caps(phy);
980 besra_set_stream_he_caps(phy);
developerb11a5392022-03-31 00:34:47 +0800981
982 mutex_unlock(&dev->mt76.mutex);
983
984 return 0;
985}
986
developer7800b8d2022-06-23 22:15:56 +0800987static void besra_sta_statistics(struct ieee80211_hw *hw,
developerb11a5392022-03-31 00:34:47 +0800988 struct ieee80211_vif *vif,
989 struct ieee80211_sta *sta,
990 struct station_info *sinfo)
991{
developer7800b8d2022-06-23 22:15:56 +0800992 struct besra_sta *msta = (struct besra_sta *)sta->drv_priv;
developerb11a5392022-03-31 00:34:47 +0800993 struct rate_info *txrate = &msta->wcid.rate;
994
995 if (!txrate->legacy && !txrate->flags)
996 return;
997
998 if (txrate->legacy) {
999 sinfo->txrate.legacy = txrate->legacy;
1000 } else {
1001 sinfo->txrate.mcs = txrate->mcs;
1002 sinfo->txrate.nss = txrate->nss;
1003 sinfo->txrate.bw = txrate->bw;
1004 sinfo->txrate.he_gi = txrate->he_gi;
1005 sinfo->txrate.he_dcm = txrate->he_dcm;
1006 sinfo->txrate.he_ru_alloc = txrate->he_ru_alloc;
1007 }
1008 sinfo->txrate.flags = txrate->flags;
1009 sinfo->filled |= BIT_ULL(NL80211_STA_INFO_TX_BITRATE);
1010}
1011
developer7800b8d2022-06-23 22:15:56 +08001012static void besra_sta_rc_work(void *data, struct ieee80211_sta *sta)
developerb11a5392022-03-31 00:34:47 +08001013{
developer7800b8d2022-06-23 22:15:56 +08001014 struct besra_sta *msta = (struct besra_sta *)sta->drv_priv;
1015 struct besra_dev *dev = msta->vif->phy->dev;
developerb11a5392022-03-31 00:34:47 +08001016 u32 *changed = data;
1017
1018 spin_lock_bh(&dev->sta_poll_lock);
1019 msta->changed |= *changed;
1020 if (list_empty(&msta->rc_list))
1021 list_add_tail(&msta->rc_list, &dev->sta_rc_list);
1022 spin_unlock_bh(&dev->sta_poll_lock);
1023}
1024
developer7800b8d2022-06-23 22:15:56 +08001025static void besra_sta_rc_update(struct ieee80211_hw *hw,
developerb11a5392022-03-31 00:34:47 +08001026 struct ieee80211_vif *vif,
1027 struct ieee80211_sta *sta,
1028 u32 changed)
1029{
developer7800b8d2022-06-23 22:15:56 +08001030 struct besra_phy *phy = besra_hw_phy(hw);
1031 struct besra_dev *dev = phy->dev;
developerb11a5392022-03-31 00:34:47 +08001032
developer7800b8d2022-06-23 22:15:56 +08001033 besra_sta_rc_work(&changed, sta);
developerb11a5392022-03-31 00:34:47 +08001034 ieee80211_queue_work(hw, &dev->rc_work);
1035}
1036
1037static int
developer7800b8d2022-06-23 22:15:56 +08001038besra_set_bitrate_mask(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
developerb11a5392022-03-31 00:34:47 +08001039 const struct cfg80211_bitrate_mask *mask)
1040{
developer7800b8d2022-06-23 22:15:56 +08001041 struct besra_vif *mvif = (struct besra_vif *)vif->drv_priv;
1042 struct besra_phy *phy = besra_hw_phy(hw);
1043 struct besra_dev *dev = phy->dev;
developerb11a5392022-03-31 00:34:47 +08001044 u32 changed = IEEE80211_RC_SUPP_RATES_CHANGED;
1045
1046 mvif->bitrate_mask = *mask;
1047
1048 /* if multiple rates across different preambles are given we can
1049 * reconfigure this info with all peers using sta_rec command with
1050 * the below exception cases.
1051 * - single rate : if a rate is passed along with different preambles,
1052 * we select the highest one as fixed rate. i.e VHT MCS for VHT peers.
1053 * - multiple rates: if it's not in range format i.e 0-{7,8,9} for VHT
1054 * then multiple MCS setting (MCS 4,5,6) is not supported.
1055 */
developer7800b8d2022-06-23 22:15:56 +08001056 ieee80211_iterate_stations_atomic(hw, besra_sta_rc_work, &changed);
developerb11a5392022-03-31 00:34:47 +08001057 ieee80211_queue_work(hw, &dev->rc_work);
1058
1059 return 0;
1060}
1061
developer7800b8d2022-06-23 22:15:56 +08001062static void besra_sta_set_4addr(struct ieee80211_hw *hw,
developerb11a5392022-03-31 00:34:47 +08001063 struct ieee80211_vif *vif,
1064 struct ieee80211_sta *sta,
1065 bool enabled)
1066{
developer7800b8d2022-06-23 22:15:56 +08001067 struct besra_dev *dev = besra_hw_dev(hw);
1068 struct besra_sta *msta = (struct besra_sta *)sta->drv_priv;
developerb11a5392022-03-31 00:34:47 +08001069
1070 if (enabled)
1071 set_bit(MT_WCID_FLAG_4ADDR, &msta->wcid.flags);
1072 else
1073 clear_bit(MT_WCID_FLAG_4ADDR, &msta->wcid.flags);
1074
developer7800b8d2022-06-23 22:15:56 +08001075 besra_mcu_wtbl_update_hdr_trans(dev, vif, sta);
developerb11a5392022-03-31 00:34:47 +08001076}
1077
developer7800b8d2022-06-23 22:15:56 +08001078static void besra_sta_set_decap_offload(struct ieee80211_hw *hw,
developerb11a5392022-03-31 00:34:47 +08001079 struct ieee80211_vif *vif,
1080 struct ieee80211_sta *sta,
1081 bool enabled)
1082{
developer7800b8d2022-06-23 22:15:56 +08001083 struct besra_dev *dev = besra_hw_dev(hw);
1084 struct besra_sta *msta = (struct besra_sta *)sta->drv_priv;
developerb11a5392022-03-31 00:34:47 +08001085
1086 if (enabled)
1087 set_bit(MT_WCID_FLAG_HDR_TRANS, &msta->wcid.flags);
1088 else
1089 clear_bit(MT_WCID_FLAG_HDR_TRANS, &msta->wcid.flags);
1090
developer7800b8d2022-06-23 22:15:56 +08001091 besra_mcu_wtbl_update_hdr_trans(dev, vif, sta);
developerb11a5392022-03-31 00:34:47 +08001092}
1093
developer7800b8d2022-06-23 22:15:56 +08001094static const char besra_gstrings_stats[][ETH_GSTRING_LEN] = {
developerb11a5392022-03-31 00:34:47 +08001095 "tx_ampdu_cnt",
1096 "tx_stop_q_empty_cnt",
1097 "tx_mpdu_attempts",
1098 "tx_mpdu_success",
1099 "tx_rwp_fail_cnt",
1100 "tx_rwp_need_cnt",
1101 "tx_pkt_ebf_cnt",
1102 "tx_pkt_ibf_cnt",
1103 "tx_ampdu_len:0-1",
1104 "tx_ampdu_len:2-10",
1105 "tx_ampdu_len:11-19",
1106 "tx_ampdu_len:20-28",
1107 "tx_ampdu_len:29-37",
1108 "tx_ampdu_len:38-46",
1109 "tx_ampdu_len:47-55",
1110 "tx_ampdu_len:56-79",
1111 "tx_ampdu_len:80-103",
1112 "tx_ampdu_len:104-127",
1113 "tx_ampdu_len:128-151",
1114 "tx_ampdu_len:152-175",
1115 "tx_ampdu_len:176-199",
1116 "tx_ampdu_len:200-223",
1117 "tx_ampdu_len:224-247",
1118 "ba_miss_count",
1119 "tx_beamformer_ppdu_iBF",
1120 "tx_beamformer_ppdu_eBF",
1121 "tx_beamformer_rx_feedback_all",
1122 "tx_beamformer_rx_feedback_he",
1123 "tx_beamformer_rx_feedback_vht",
1124 "tx_beamformer_rx_feedback_ht",
1125 "tx_beamformer_rx_feedback_bw", /* zero based idx: 20, 40, 80, 160 */
1126 "tx_beamformer_rx_feedback_nc",
1127 "tx_beamformer_rx_feedback_nr",
1128 "tx_beamformee_ok_feedback_pkts",
1129 "tx_beamformee_feedback_trig",
1130 "tx_mu_beamforming",
1131 "tx_mu_mpdu",
1132 "tx_mu_successful_mpdu",
1133 "tx_su_successful_mpdu",
1134 "tx_msdu_pack_1",
1135 "tx_msdu_pack_2",
1136 "tx_msdu_pack_3",
1137 "tx_msdu_pack_4",
1138 "tx_msdu_pack_5",
1139 "tx_msdu_pack_6",
1140 "tx_msdu_pack_7",
1141 "tx_msdu_pack_8",
1142
1143 /* rx counters */
1144 "rx_fifo_full_cnt",
1145 "rx_mpdu_cnt",
1146 "channel_idle_cnt",
1147 "rx_vector_mismatch_cnt",
1148 "rx_delimiter_fail_cnt",
1149 "rx_len_mismatch_cnt",
1150 "rx_ampdu_cnt",
1151 "rx_ampdu_bytes_cnt",
1152 "rx_ampdu_valid_subframe_cnt",
1153 "rx_ampdu_valid_subframe_b_cnt",
1154 "rx_pfdrop_cnt",
1155 "rx_vec_queue_overflow_drop_cnt",
1156 "rx_ba_cnt",
1157
1158 /* per vif counters */
1159 "v_tx_mode_cck",
1160 "v_tx_mode_ofdm",
1161 "v_tx_mode_ht",
1162 "v_tx_mode_ht_gf",
1163 "v_tx_mode_vht",
1164 "v_tx_mode_he_su",
1165 "v_tx_mode_he_ext_su",
1166 "v_tx_mode_he_tb",
1167 "v_tx_mode_he_mu",
1168 "v_tx_bw_20",
1169 "v_tx_bw_40",
1170 "v_tx_bw_80",
1171 "v_tx_bw_160",
1172 "v_tx_mcs_0",
1173 "v_tx_mcs_1",
1174 "v_tx_mcs_2",
1175 "v_tx_mcs_3",
1176 "v_tx_mcs_4",
1177 "v_tx_mcs_5",
1178 "v_tx_mcs_6",
1179 "v_tx_mcs_7",
1180 "v_tx_mcs_8",
1181 "v_tx_mcs_9",
1182 "v_tx_mcs_10",
1183 "v_tx_mcs_11",
1184};
1185
developer7800b8d2022-06-23 22:15:56 +08001186#define BESRA_SSTATS_LEN ARRAY_SIZE(besra_gstrings_stats)
developerb11a5392022-03-31 00:34:47 +08001187
1188/* Ethtool related API */
1189static
developer7800b8d2022-06-23 22:15:56 +08001190void besra_get_et_strings(struct ieee80211_hw *hw,
developerb11a5392022-03-31 00:34:47 +08001191 struct ieee80211_vif *vif,
1192 u32 sset, u8 *data)
1193{
1194 if (sset == ETH_SS_STATS)
developer7800b8d2022-06-23 22:15:56 +08001195 memcpy(data, *besra_gstrings_stats,
1196 sizeof(besra_gstrings_stats));
developerb11a5392022-03-31 00:34:47 +08001197}
1198
1199static
developer7800b8d2022-06-23 22:15:56 +08001200int besra_get_et_sset_count(struct ieee80211_hw *hw,
developerb11a5392022-03-31 00:34:47 +08001201 struct ieee80211_vif *vif, int sset)
1202{
1203 if (sset == ETH_SS_STATS)
developer7800b8d2022-06-23 22:15:56 +08001204 return BESRA_SSTATS_LEN;
developerb11a5392022-03-31 00:34:47 +08001205
1206 return 0;
1207}
1208
developer7800b8d2022-06-23 22:15:56 +08001209static void besra_ethtool_worker(void *wi_data, struct ieee80211_sta *sta)
developerb11a5392022-03-31 00:34:47 +08001210{
1211 struct mt76_ethtool_worker_info *wi = wi_data;
developer7800b8d2022-06-23 22:15:56 +08001212 struct besra_sta *msta = (struct besra_sta *)sta->drv_priv;
developerb11a5392022-03-31 00:34:47 +08001213
1214 if (msta->vif->mt76.idx != wi->idx)
1215 return;
1216
1217 mt76_ethtool_worker(wi, &msta->stats);
1218}
1219
1220static
developer7800b8d2022-06-23 22:15:56 +08001221void besra_get_et_stats(struct ieee80211_hw *hw,
developerb11a5392022-03-31 00:34:47 +08001222 struct ieee80211_vif *vif,
1223 struct ethtool_stats *stats, u64 *data)
1224{
developer7800b8d2022-06-23 22:15:56 +08001225 struct besra_dev *dev = besra_hw_dev(hw);
1226 struct besra_phy *phy = besra_hw_phy(hw);
1227 struct besra_vif *mvif = (struct besra_vif *)vif->drv_priv;
developerb11a5392022-03-31 00:34:47 +08001228 struct mt76_ethtool_worker_info wi = {
1229 .data = data,
1230 .idx = mvif->mt76.idx,
1231 };
1232 struct mib_stats *mib = &phy->mib;
developer7800b8d2022-06-23 22:15:56 +08001233 /* See besra_ampdu_stat_read_phy, etc */
developerb11a5392022-03-31 00:34:47 +08001234 int i, n, ei = 0;
1235
1236 mutex_lock(&dev->mt76.mutex);
1237
developer7800b8d2022-06-23 22:15:56 +08001238 besra_mac_update_stats(phy);
developerb11a5392022-03-31 00:34:47 +08001239
1240 data[ei++] = mib->tx_ampdu_cnt;
1241 data[ei++] = mib->tx_stop_q_empty_cnt;
1242 data[ei++] = mib->tx_mpdu_attempts_cnt;
1243 data[ei++] = mib->tx_mpdu_success_cnt;
1244 data[ei++] = mib->tx_rwp_fail_cnt;
1245 data[ei++] = mib->tx_rwp_need_cnt;
1246 data[ei++] = mib->tx_pkt_ebf_cnt;
1247 data[ei++] = mib->tx_pkt_ibf_cnt;
1248
1249 /* Tx ampdu stat */
1250 n = phy->band_idx ? ARRAY_SIZE(dev->mt76.aggr_stats) / 2 : 0;
1251 for (i = 0; i < 15 /*ARRAY_SIZE(bound)*/; i++)
1252 data[ei++] = dev->mt76.aggr_stats[i + n];
1253
1254 data[ei++] = phy->mib.ba_miss_cnt;
1255
1256 /* Tx Beamformer monitor */
1257 data[ei++] = mib->tx_bf_ibf_ppdu_cnt;
1258 data[ei++] = mib->tx_bf_ebf_ppdu_cnt;
1259
1260 /* Tx Beamformer Rx feedback monitor */
1261 data[ei++] = mib->tx_bf_rx_fb_all_cnt;
1262 data[ei++] = mib->tx_bf_rx_fb_he_cnt;
1263 data[ei++] = mib->tx_bf_rx_fb_vht_cnt;
1264 data[ei++] = mib->tx_bf_rx_fb_ht_cnt;
1265
1266 data[ei++] = mib->tx_bf_rx_fb_bw;
1267 data[ei++] = mib->tx_bf_rx_fb_nc_cnt;
1268 data[ei++] = mib->tx_bf_rx_fb_nr_cnt;
1269
1270 /* Tx Beamformee Rx NDPA & Tx feedback report */
1271 data[ei++] = mib->tx_bf_fb_cpl_cnt;
1272 data[ei++] = mib->tx_bf_fb_trig_cnt;
1273
1274 /* Tx SU & MU counters */
1275 data[ei++] = mib->tx_bf_cnt;
1276 data[ei++] = mib->tx_mu_mpdu_cnt;
1277 data[ei++] = mib->tx_mu_acked_mpdu_cnt;
1278 data[ei++] = mib->tx_su_acked_mpdu_cnt;
1279
1280 /* Tx amsdu info (pack-count histogram) */
1281 for (i = 0; i < ARRAY_SIZE(mib->tx_amsdu); i++)
1282 data[ei++] = mib->tx_amsdu[i];
1283
1284 /* rx counters */
1285 data[ei++] = mib->rx_fifo_full_cnt;
1286 data[ei++] = mib->rx_mpdu_cnt;
1287 data[ei++] = mib->channel_idle_cnt;
1288 data[ei++] = mib->rx_vector_mismatch_cnt;
1289 data[ei++] = mib->rx_delimiter_fail_cnt;
1290 data[ei++] = mib->rx_len_mismatch_cnt;
1291 data[ei++] = mib->rx_ampdu_cnt;
1292 data[ei++] = mib->rx_ampdu_bytes_cnt;
1293 data[ei++] = mib->rx_ampdu_valid_subframe_cnt;
1294 data[ei++] = mib->rx_ampdu_valid_subframe_bytes_cnt;
1295 data[ei++] = mib->rx_pfdrop_cnt;
1296 data[ei++] = mib->rx_vec_queue_overflow_drop_cnt;
1297 data[ei++] = mib->rx_ba_cnt;
1298
1299 /* Add values for all stations owned by this vif */
1300 wi.initial_stat_idx = ei;
developer7800b8d2022-06-23 22:15:56 +08001301 ieee80211_iterate_stations_atomic(hw, besra_ethtool_worker, &wi);
developerb11a5392022-03-31 00:34:47 +08001302
1303 mutex_unlock(&dev->mt76.mutex);
1304
1305 if (wi.sta_count == 0)
1306 return;
1307
1308 ei += wi.worker_stat_count;
developer7800b8d2022-06-23 22:15:56 +08001309 if (ei != BESRA_SSTATS_LEN)
1310 dev_err(dev->mt76.dev, "ei: %d BESRA_SSTATS_LEN: %d",
1311 ei, (int)BESRA_SSTATS_LEN);
developerb11a5392022-03-31 00:34:47 +08001312}
1313
1314static void
developer7800b8d2022-06-23 22:15:56 +08001315besra_twt_teardown_request(struct ieee80211_hw *hw,
developerb11a5392022-03-31 00:34:47 +08001316 struct ieee80211_sta *sta,
1317 u8 flowid)
1318{
developer7800b8d2022-06-23 22:15:56 +08001319 struct besra_sta *msta = (struct besra_sta *)sta->drv_priv;
1320 struct besra_dev *dev = besra_hw_dev(hw);
developerb11a5392022-03-31 00:34:47 +08001321
1322 mutex_lock(&dev->mt76.mutex);
developer7800b8d2022-06-23 22:15:56 +08001323 besra_mac_twt_teardown_flow(dev, msta, flowid);
developerb11a5392022-03-31 00:34:47 +08001324 mutex_unlock(&dev->mt76.mutex);
1325}
1326
1327static int
developer7800b8d2022-06-23 22:15:56 +08001328besra_set_radar_background(struct ieee80211_hw *hw,
developerb11a5392022-03-31 00:34:47 +08001329 struct cfg80211_chan_def *chandef)
1330{
developer7800b8d2022-06-23 22:15:56 +08001331 struct besra_phy *phy = besra_hw_phy(hw);
1332 struct besra_dev *dev = phy->dev;
developerb11a5392022-03-31 00:34:47 +08001333 int ret = -EINVAL;
1334 bool running;
1335
1336 mutex_lock(&dev->mt76.mutex);
1337
1338 if (dev->mt76.region == NL80211_DFS_UNSET)
1339 goto out;
1340
1341 if (dev->rdd2_phy && dev->rdd2_phy != phy) {
1342 /* rdd2 is already locked */
1343 ret = -EBUSY;
1344 goto out;
1345 }
1346
1347 /* rdd2 already configured on a radar channel */
1348 running = dev->rdd2_phy &&
1349 cfg80211_chandef_valid(&dev->rdd2_chandef) &&
1350 !!(dev->rdd2_chandef.chan->flags & IEEE80211_CHAN_RADAR);
1351
1352 if (!chandef || running ||
1353 !(chandef->chan->flags & IEEE80211_CHAN_RADAR)) {
developer7800b8d2022-06-23 22:15:56 +08001354 ret = besra_mcu_rdd_background_enable(phy, NULL);
developerb11a5392022-03-31 00:34:47 +08001355 if (ret)
1356 goto out;
1357
1358 if (!running)
1359 goto update_phy;
1360 }
1361
developer7800b8d2022-06-23 22:15:56 +08001362 ret = besra_mcu_rdd_background_enable(phy, chandef);
developerb11a5392022-03-31 00:34:47 +08001363 if (ret)
1364 goto out;
1365
1366update_phy:
1367 dev->rdd2_phy = chandef ? phy : NULL;
1368 if (chandef)
1369 dev->rdd2_chandef = *chandef;
1370out:
1371 mutex_unlock(&dev->mt76.mutex);
1372
1373 return ret;
1374}
1375
developer7800b8d2022-06-23 22:15:56 +08001376const struct ieee80211_ops besra_ops = {
1377 .tx = besra_tx,
1378 .start = besra_start,
1379 .stop = besra_stop,
1380 .add_interface = besra_add_interface,
1381 .remove_interface = besra_remove_interface,
1382 .config = besra_config,
1383 .conf_tx = besra_conf_tx,
1384 .configure_filter = besra_configure_filter,
1385 .bss_info_changed = besra_bss_info_changed,
1386 .sta_add = besra_sta_add,
1387 .sta_remove = besra_sta_remove,
developerb11a5392022-03-31 00:34:47 +08001388 .sta_pre_rcu_remove = mt76_sta_pre_rcu_remove,
developer7800b8d2022-06-23 22:15:56 +08001389 .sta_rc_update = besra_sta_rc_update,
1390 .set_key = besra_set_key,
1391 .ampdu_action = besra_ampdu_action,
1392 .set_rts_threshold = besra_set_rts_threshold,
developerb11a5392022-03-31 00:34:47 +08001393 .wake_tx_queue = mt76_wake_tx_queue,
1394 .sw_scan_start = mt76_sw_scan,
1395 .sw_scan_complete = mt76_sw_scan_complete,
1396 .release_buffered_frames = mt76_release_buffered_frames,
1397 .get_txpower = mt76_get_txpower,
developer7800b8d2022-06-23 22:15:56 +08001398 .set_sar_specs = besra_set_sar_specs,
1399 .channel_switch_beacon = besra_channel_switch_beacon,
1400 .get_stats = besra_get_stats,
1401 .get_et_sset_count = besra_get_et_sset_count,
1402 .get_et_stats = besra_get_et_stats,
1403 .get_et_strings = besra_get_et_strings,
1404 .get_tsf = besra_get_tsf,
1405 .set_tsf = besra_set_tsf,
1406 .offset_tsf = besra_offset_tsf,
developerb11a5392022-03-31 00:34:47 +08001407 .get_survey = mt76_get_survey,
1408 .get_antenna = mt76_get_antenna,
developer7800b8d2022-06-23 22:15:56 +08001409 .set_antenna = besra_set_antenna,
1410 .set_bitrate_mask = besra_set_bitrate_mask,
1411 .set_coverage_class = besra_set_coverage_class,
1412 .sta_statistics = besra_sta_statistics,
1413 .sta_set_4addr = besra_sta_set_4addr,
1414 .sta_set_decap_offload = besra_sta_set_decap_offload,
1415 .add_twt_setup = besra_mac_add_twt_setup,
1416 .twt_teardown_request = besra_twt_teardown_request,
developerb11a5392022-03-31 00:34:47 +08001417 CFG80211_TESTMODE_CMD(mt76_testmode_cmd)
1418 CFG80211_TESTMODE_DUMP(mt76_testmode_dump)
1419#ifdef CONFIG_MAC80211_DEBUGFS
developer7800b8d2022-06-23 22:15:56 +08001420 .sta_add_debugfs = besra_sta_add_debugfs,
developerb11a5392022-03-31 00:34:47 +08001421#endif
developer7800b8d2022-06-23 22:15:56 +08001422 .set_radar_background = besra_set_radar_background,
developerb11a5392022-03-31 00:34:47 +08001423};