developer | d8e6faf | 2022-11-10 18:00:47 +0800 | [diff] [blame] | 1 | diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c |
| 2 | index 4075ec2..524c5d9 100644 |
| 3 | --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c |
| 4 | +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c |
| 5 | @@ -1796,17 +1796,17 @@ static int mtk_poll_rx(struct napi_struct *napi, int budget, |
| 6 | skb_checksum_none_assert(skb); |
| 7 | skb->protocol = eth_type_trans(skb, netdev); |
| 8 | |
| 9 | -#if defined(CONFIG_MEDIATEK_NETSYS_V2) |
| 10 | - hash = trxd.rxd5 & MTK_RXD5_FOE_ENTRY_V2; |
| 11 | +#if defined(CONFIG_MEDIATEK_NETSYS_V2) || defined(CONFIG_MEDIATEK_NETSYS_V3) |
| 12 | + hash = trxd.rxd5 & MTK_RXD5_FOE_ENTRY_V2; |
| 13 | #else |
| 14 | - hash = trxd.rxd4 & MTK_RXD4_FOE_ENTRY; |
| 15 | + hash = trxd.rxd4 & MTK_RXD4_FOE_ENTRY; |
| 16 | #endif |
| 17 | if (hash != MTK_RXD4_FOE_ENTRY) { |
| 18 | hash = jhash_1word(hash, 0); |
| 19 | skb_set_hash(skb, hash, PKT_HASH_TYPE_L4); |
| 20 | } |
| 21 | |
| 22 | -#if defined(CONFIG_MEDIATEK_NETSYS_V2) |
| 23 | +#if defined(CONFIG_MEDIATEK_NETSYS_V2) || defined(CONFIG_MEDIATEK_NETSYS_V3) |
| 24 | reason = FIELD_GET(MTK_RXD5_PPE_CPU_REASON_V2, trxd.rxd5); |
| 25 | if (reason == MTK_PPE_CPU_REASON_HIT_UNBIND_RATE_REACHED) { |
| 26 | for (i = 0; i < eth->ppe_num; i++) { |
developer | c693c15 | 2022-12-02 09:38:46 +0800 | [diff] [blame] | 27 | @@ -4448,7 +4448,8 @@ static int mtk_probe(struct platform_device *pdev) |
| 28 | |
| 29 | for (i = 0; i < eth->ppe_num; i++) { |
| 30 | eth->ppe[i] = mtk_ppe_init(eth, |
| 31 | - eth->base + MTK_ETH_PPE_BASE + i * 0x400, |
| 32 | + eth->base + MTK_ETH_PPE_BASE + |
| 33 | + (i == 2 ? 0xC00 : i * 0x400), |
| 34 | 2, eth->soc->hash_way, i, |
| 35 | eth->soc->has_accounting); |
| 36 | if (!eth->ppe[i]) { |
developer | d8e6faf | 2022-11-10 18:00:47 +0800 | [diff] [blame] | 37 | @@ -4626,11 +4626,15 @@ static const struct mtk_soc_data mt7988_data = { |
| 38 | .required_clks = MT7988_CLKS_BITMAP, |
| 39 | .required_pctl = false, |
| 40 | .has_sram = true, |
| 41 | + .has_accounting = true, |
| 42 | + .hash_way = 4, |
| 43 | + .offload_version = 2, |
| 44 | .txrx = { |
| 45 | .txd_size = sizeof(struct mtk_tx_dma_v2), |
| 46 | .rxd_size = sizeof(struct mtk_rx_dma_v2), |
| 47 | .dma_max_len = MTK_TX_DMA_BUF_LEN_V2, |
| 48 | .dma_len_offset = MTK_TX_DMA_BUF_SHIFT_V2, |
| 49 | + .qdma_tx_sch = 4, |
| 50 | }, |
| 51 | }; |
| 52 | |
| 53 | diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/drivers/net/ethernet/mediatek/mtk_eth_soc.h |
| 54 | index 5b39d87..94bd423 100644 |
| 55 | --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h |
| 56 | +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h |
developer | c693c15 | 2022-12-02 09:38:46 +0800 | [diff] [blame] | 57 | @@ -118,7 +118,8 @@ |
developer | d8e6faf | 2022-11-10 18:00:47 +0800 | [diff] [blame] | 58 | #define MTK_GDMA_UCS_EN BIT(20) |
| 59 | #define MTK_GDMA_STRP_CRC BIT(16) |
| 60 | #define MTK_GDMA_TO_PDMA 0x0 |
| 61 | -#if defined(CONFIG_MEDIATEK_NETSYS_V2) |
| 62 | +#if defined(CONFIG_MEDIATEK_NETSYS_V2) || defined(CONFIG_MEDIATEK_NETSYS_V3) |
| 63 | #define MTK_GDMA_TO_PPE0 0x3333 |
| 64 | #define MTK_GDMA_TO_PPE1 0x4444 |
developer | c693c15 | 2022-12-02 09:38:46 +0800 | [diff] [blame] | 65 | +#define MTK_GMAC_TO_PPE2 0xcccc |
developer | d8e6faf | 2022-11-10 18:00:47 +0800 | [diff] [blame] | 66 | #else |
| 67 | diff --git a/drivers/net/ethernet/mediatek/mtk_ppe.c b/drivers/net/ethernet/mediatek/mtk_ppe.c |
| 68 | index 98f61fe..bd504d4 100755 |
| 69 | --- a/drivers/net/ethernet/mediatek/mtk_ppe.c |
| 70 | +++ b/drivers/net/ethernet/mediatek/mtk_ppe.c |
| 71 | @@ -211,7 +211,7 @@ int mtk_foe_entry_prepare(struct mtk_foe_entry *entry, int type, int l4proto, |
| 72 | MTK_FOE_IB1_BIND_CACHE; |
| 73 | entry->ib1 = val; |
| 74 | |
| 75 | -#if defined(CONFIG_MEDIATEK_NETSYS_V2) |
| 76 | +#if defined(CONFIG_MEDIATEK_NETSYS_V2) || defined(CONFIG_MEDIATEK_NETSYS_V3) |
| 77 | val = FIELD_PREP(MTK_FOE_IB2_PORT_AG, 0xf) | |
| 78 | #else |
| 79 | val = FIELD_PREP(MTK_FOE_IB2_PORT_MG, 0x3f) | |
| 80 | @@ -403,7 +403,7 @@ int mtk_foe_entry_set_wdma(struct mtk_foe_entry *entry, int wdma_idx, int txq, |
| 81 | |
| 82 | *ib2 &= ~MTK_FOE_IB2_PORT_MG; |
| 83 | *ib2 |= MTK_FOE_IB2_WDMA_WINFO; |
| 84 | -#if defined(CONFIG_MEDIATEK_NETSYS_V2) |
| 85 | +#if defined(CONFIG_MEDIATEK_NETSYS_V2) || defined(CONFIG_MEDIATEK_NETSYS_V3) |
| 86 | *ib2 |= FIELD_PREP(MTK_FOE_IB2_RX_IDX, txq); |
| 87 | |
| 88 | l2->winfo = FIELD_PREP(MTK_FOE_WINFO_WCID, wcid) | |
developer | c693c15 | 2022-12-02 09:38:46 +0800 | [diff] [blame] | 89 | @@ -422,11 +422,16 @@ int mtk_foe_entry_set_wdma(struct mtk_foe_entry *entry, int wdma_idx, int txq, |
| 90 | |
| 91 | int mtk_foe_entry_set_qid(struct mtk_foe_entry *entry, int qid) |
| 92 | { |
| 93 | + struct mtk_foe_mac_info *l2 = mtk_foe_entry_l2(entry); |
| 94 | u32 *ib2 = mtk_foe_entry_ib2(entry); |
| 95 | |
| 96 | *ib2 &= ~MTK_FOE_IB2_QID; |
| 97 | *ib2 |= FIELD_PREP(MTK_FOE_IB2_QID, qid); |
| 98 | +#if defined(CONFIG_MEDIATEK_NETSYS_V3) |
| 99 | + l2->tport_id = 1; |
| 100 | +#else |
| 101 | *ib2 |= MTK_FOE_IB2_PSE_QOS; |
| 102 | +#endif |
| 103 | |
| 104 | return 0; |
| 105 | } |
developer | d8e6faf | 2022-11-10 18:00:47 +0800 | [diff] [blame] | 106 | @@ -867,13 +867,16 @@ int mtk_ppe_start(struct mtk_ppe *ppe) |
| 107 | mtk_ppe_init_foe_table(ppe); |
| 108 | ppe_w32(ppe, MTK_PPE_TB_BASE, ppe->foe_phys); |
| 109 | |
| 110 | - val = MTK_PPE_TB_CFG_ENTRY_80B | |
| 111 | + val = |
| 112 | +#if !defined(CONFIG_MEDIATEK_NETSYS_V3) |
| 113 | + MTK_PPE_TB_CFG_ENTRY_80B | |
| 114 | +#endif |
| 115 | MTK_PPE_TB_CFG_AGE_NON_L4 | |
| 116 | MTK_PPE_TB_CFG_AGE_UNBIND | |
| 117 | MTK_PPE_TB_CFG_AGE_TCP | |
| 118 | MTK_PPE_TB_CFG_AGE_UDP | |
| 119 | MTK_PPE_TB_CFG_AGE_TCP_FIN | |
| 120 | -#if defined(CONFIG_MEDIATEK_NETSYS_V2) |
| 121 | +#if defined(CONFIG_MEDIATEK_NETSYS_V2) || defined(CONFIG_MEDIATEK_NETSYS_V3) |
| 122 | MTK_PPE_TB_CFG_INFO_SEL | |
| 123 | #endif |
| 124 | FIELD_PREP(MTK_PPE_TB_CFG_SEARCH_MISS, |
| 125 | @@ -937,7 +940,7 @@ int mtk_ppe_start(struct mtk_ppe *ppe) |
| 126 | |
| 127 | ppe_w32(ppe, MTK_PPE_DEFAULT_CPU_PORT, 0); |
| 128 | |
| 129 | -#if defined(CONFIG_MEDIATEK_NETSYS_V2) |
| 130 | +#if defined(CONFIG_MEDIATEK_NETSYS_V2) || defined(CONFIG_MEDIATEK_NETSYS_V3) |
| 131 | ppe_w32(ppe, MTK_PPE_DEFAULT_CPU_PORT1, 0xcb777); |
| 132 | ppe_w32(ppe, MTK_PPE_SBW_CTRL, 0x7f); |
| 133 | #endif |
| 134 | diff --git a/drivers/net/ethernet/mediatek/mtk_ppe.h b/drivers/net/ethernet/mediatek/mtk_ppe.h |
| 135 | index 703b2bd..03b4dfb 100644 |
| 136 | --- a/drivers/net/ethernet/mediatek/mtk_ppe.h |
| 137 | +++ b/drivers/net/ethernet/mediatek/mtk_ppe.h |
developer | c693c15 | 2022-12-02 09:38:46 +0800 | [diff] [blame] | 138 | @@ -8,7 +8,10 @@ |
developer | d8e6faf | 2022-11-10 18:00:47 +0800 | [diff] [blame] | 139 | #include <linux/bitfield.h> |
| 140 | #include <linux/rhashtable.h> |
| 141 | |
| 142 | -#if defined(CONFIG_MEDIATEK_NETSYS_V2) |
developer | c693c15 | 2022-12-02 09:38:46 +0800 | [diff] [blame] | 143 | +#if defined(CONFIG_MEDIATEK_NETSYS_V3) |
| 144 | +#define MTK_MAX_PPE_NUM 3 |
| 145 | +#define MTK_ETH_PPE_BASE 0x2000 |
| 146 | +#elif defined(CONFIG_MEDIATEK_NETSYS_V2) |
developer | d8e6faf | 2022-11-10 18:00:47 +0800 | [diff] [blame] | 147 | #define MTK_MAX_PPE_NUM 2 |
| 148 | #define MTK_ETH_PPE_BASE 0x2000 |
| 149 | #else |
| 150 | @@ -22,7 +22,7 @@ |
| 151 | #define MTK_PPE_WAIT_TIMEOUT_US 1000000 |
| 152 | |
| 153 | #define MTK_FOE_IB1_UNBIND_TIMESTAMP GENMASK(7, 0) |
| 154 | -#if defined(CONFIG_MEDIATEK_NETSYS_V2) |
| 155 | +#if defined(CONFIG_MEDIATEK_NETSYS_V2) || defined(CONFIG_MEDIATEK_NETSYS_V3) |
| 156 | #define MTK_FOE_IB1_UNBIND_SRC_PORT GENMASK(11, 8) |
| 157 | #define MTK_FOE_IB1_UNBIND_PACKETS GENMASK(19, 12) |
| 158 | #define MTK_FOE_IB1_UNBIND_PREBIND BIT(22) |
| 159 | @@ -70,7 +70,7 @@ enum { |
| 160 | MTK_PPE_PKT_TYPE_IPV6_6RD = 7, |
| 161 | }; |
| 162 | |
| 163 | -#if defined(CONFIG_MEDIATEK_NETSYS_V2) |
| 164 | +#if defined(CONFIG_MEDIATEK_NETSYS_V2) || defined(CONFIG_MEDIATEK_NETSYS_V3) |
| 165 | #define MTK_FOE_IB2_QID GENMASK(6, 0) |
| 166 | #define MTK_FOE_IB2_PORT_MG BIT(7) |
| 167 | #define MTK_FOE_IB2_PSE_QOS BIT(8) |
| 168 | @@ -98,7 +98,18 @@ enum { |
| 169 | |
| 170 | #define MTK_FOE_IB2_DSCP GENMASK(31, 24) |
| 171 | |
| 172 | -#if defined(CONFIG_MEDIATEK_NETSYS_V2) |
| 173 | +#if defined(CONFIG_MEDIATEK_NETSYS_V3) |
| 174 | +#define MTK_FOE_WINFO_WCID GENMASK(15, 0) |
| 175 | +#define MTK_FOE_WINFO_BSS GENMASK(23, 16) |
| 176 | + |
| 177 | +#define MTK_FOE_WINFO_PAO_USR_INFO GENMASK(15, 0) |
| 178 | +#define MTK_FOE_WINFO_PAO_TID GENMASK(19, 16) |
| 179 | +#define MTK_FOE_WINFO_PAO_IS_FIXEDRATE BIT(20) |
| 180 | +#define MTK_FOE_WINFO_PAO_IS_PRIOR BIT(21) |
| 181 | +#define MTK_FOE_WINFO_PAO_IS_SP BIT(22) |
| 182 | +#define MTK_FOE_WINFO_PAO_HF BIT(23) |
| 183 | +#define MTK_FOE_WINFO_PAO_AMSDU_EN BIT(24) |
| 184 | +#elif defined(CONFIG_MEDIATEK_NETSYS_V2) |
| 185 | #define MTK_FOE_WINFO_BSS GENMASK(5, 0) |
| 186 | #define MTK_FOE_WINFO_WCID GENMASK(15, 6) |
| 187 | #else |
developer | c693c15 | 2022-12-02 09:38:46 +0800 | [diff] [blame] | 188 | @@ -128,7 +139,17 @@ struct mtk_foe_mac_info { |
developer | d8e6faf | 2022-11-10 18:00:47 +0800 | [diff] [blame] | 189 | u16 pppoe_id; |
| 190 | u16 src_mac_lo; |
| 191 | |
| 192 | -#if defined(CONFIG_MEDIATEK_NETSYS_V2) |
| 193 | +#if defined(CONFIG_MEDIATEK_NETSYS_V3) |
| 194 | + u16 minfo; |
| 195 | + u16 resv1; |
| 196 | + u32 winfo; |
| 197 | + u32 winfo_pao; |
developer | c693c15 | 2022-12-02 09:38:46 +0800 | [diff] [blame] | 198 | + u16 cdrt_id:8; |
| 199 | + u16 tops_entry:6; |
| 200 | + u16 resv3:2; |
| 201 | + u16 tport_id:4; |
| 202 | + u16 resv4:12; |
developer | d8e6faf | 2022-11-10 18:00:47 +0800 | [diff] [blame] | 203 | +#elif defined(CONFIG_MEDIATEK_NETSYS_V2) |
| 204 | u16 minfo; |
| 205 | u16 winfo; |
| 206 | #endif |
| 207 | @@ -249,7 +265,9 @@ struct mtk_foe_entry { |
| 208 | struct mtk_foe_ipv4_dslite dslite; |
| 209 | struct mtk_foe_ipv6 ipv6; |
| 210 | struct mtk_foe_ipv6_6rd ipv6_6rd; |
| 211 | -#if defined(CONFIG_MEDIATEK_NETSYS_V2) |
| 212 | +#if defined(CONFIG_MEDIATEK_NETSYS_V3) |
| 213 | + u32 data[31]; |
| 214 | +#elif defined(CONFIG_MEDIATEK_NETSYS_V2) |
| 215 | u32 data[23]; |
| 216 | #else |
| 217 | u32 data[19]; |
| 218 | diff --git a/drivers/net/ethernet/mediatek/mtk_ppe_offload.c b/drivers/net/ethernet/mediatek/mtk_ppe_offload.c |
| 219 | index a5bf090..0e41ff2 100755 |
| 220 | --- a/drivers/net/ethernet/mediatek/mtk_ppe_offload.c |
| 221 | +++ b/drivers/net/ethernet/mediatek/mtk_ppe_offload.c |
| 222 | @@ -195,7 +195,7 @@ mtk_flow_set_output_device(struct mtk_eth *eth, struct mtk_foe_entry *foe, |
| 223 | mtk_foe_entry_set_wdma(foe, info.wdma_idx, info.queue, info.bss, |
| 224 | info.wcid); |
developer | c693c15 | 2022-12-02 09:38:46 +0800 | [diff] [blame] | 225 | pse_port = PSE_PPE0_PORT; |
developer | d8e6faf | 2022-11-10 18:00:47 +0800 | [diff] [blame] | 226 | -#if defined(CONFIG_MEDIATEK_NETSYS_V2) |
| 227 | +#if defined(CONFIG_MEDIATEK_NETSYS_V2) || defined(CONFIG_MEDIATEK_NETSYS_V3) |
| 228 | if (info.wdma_idx == 0) |
developer | c693c15 | 2022-12-02 09:38:46 +0800 | [diff] [blame] | 229 | pse_port = PSE_WDMA0_PORT; |
developer | d8e6faf | 2022-11-10 18:00:47 +0800 | [diff] [blame] | 230 | else if (info.wdma_idx == 1) |
developer | c693c15 | 2022-12-02 09:38:46 +0800 | [diff] [blame] | 231 | @@ -220,6 +220,8 @@ mtk_flow_set_output_device(struct mtk_eth *eth, struct mtk_foe_entry *foe, |
| 232 | pse_port = PSE_GDM1_PORT; |
| 233 | else if (dev == eth->netdev[1]) |
| 234 | pse_port = PSE_GDM2_PORT; |
| 235 | + else if (dev == eth->netdev[2]) |
| 236 | + pse_port = PSE_GDM3_PORT; |
| 237 | else |
| 238 | return -EOPNOTSUPP; |
| 239 | |
developer | d8e6faf | 2022-11-10 18:00:47 +0800 | [diff] [blame] | 240 | @@ -452,7 +452,7 @@ mtk_flow_offload_replace(struct mtk_eth *eth, struct flow_cls_offload *f) |
| 241 | return -ENOMEM; |
| 242 | |
| 243 | i = 0; |
| 244 | -#if defined(CONFIG_MEDIATEK_NETSYS_V2) |
| 245 | +#if defined(CONFIG_MEDIATEK_NETSYS_V2) || defined(CONFIG_MEDIATEK_NETSYS_V3) |
| 246 | if (idev && idev->netdev_ops->ndo_fill_receive_path) { |
| 247 | ctx.dev = idev; |
| 248 | idev->netdev_ops->ndo_fill_receive_path(&ctx, &path); |