developer | 1d1e456 | 2022-03-17 00:06:34 +0800 | [diff] [blame^] | 1 | /* |
| 2 | * Copyright (c) 2018 MediaTek Inc. |
| 3 | * Author: Ryder Lee <ryder.lee@mediatek.com> |
| 4 | * |
| 5 | * SPDX-License-Identifier: (GPL-2.0 OR MIT) |
| 6 | */ |
| 7 | |
| 8 | /dts-v1/; |
| 9 | #include <dt-bindings/input/input.h> |
| 10 | #include <dt-bindings/gpio/gpio.h> |
| 11 | |
| 12 | #include "mt7622.dtsi" |
| 13 | #include "mt6380.dtsi" |
| 14 | |
| 15 | / { |
| 16 | model = "MT7622_MT7531 RFB"; |
| 17 | compatible = "mediatek,mt7622-rfb1", "mediatek,mt7622"; |
| 18 | |
| 19 | aliases { |
| 20 | serial0 = &uart0; |
| 21 | }; |
| 22 | |
| 23 | chosen { |
| 24 | stdout-path = "serial0:115200n8"; |
| 25 | bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n1 swiotlb=512"; |
| 26 | }; |
| 27 | |
| 28 | cpus { |
| 29 | cpu@0 { |
| 30 | proc-supply = <&mt6380_vcpu_reg>; |
| 31 | sram-supply = <&mt6380_vm_reg>; |
| 32 | }; |
| 33 | |
| 34 | cpu@1 { |
| 35 | proc-supply = <&mt6380_vcpu_reg>; |
| 36 | sram-supply = <&mt6380_vm_reg>; |
| 37 | }; |
| 38 | }; |
| 39 | |
| 40 | gpio-keys { |
| 41 | compatible = "gpio-keys"; |
| 42 | |
| 43 | factory { |
| 44 | label = "factory"; |
| 45 | linux,code = <BTN_0>; |
| 46 | gpios = <&pio 0 GPIO_ACTIVE_LOW>; |
| 47 | }; |
| 48 | |
| 49 | wps { |
| 50 | label = "wps"; |
| 51 | linux,code = <KEY_WPS_BUTTON>; |
| 52 | gpios = <&pio 102 GPIO_ACTIVE_LOW>; |
| 53 | }; |
| 54 | }; |
| 55 | |
| 56 | leds { |
| 57 | compatible = "gpio-leds"; |
| 58 | |
| 59 | green { |
| 60 | label = "bpi-r64:pio:green"; |
| 61 | gpios = <&pio 89 GPIO_ACTIVE_HIGH>; |
| 62 | }; |
| 63 | |
| 64 | red { |
| 65 | label = "bpi-r64:pio:red"; |
| 66 | gpios = <&pio 88 GPIO_ACTIVE_HIGH>; |
| 67 | }; |
| 68 | }; |
| 69 | |
| 70 | memory { |
| 71 | reg = <0 0x40000000 0 0x40000000>; |
| 72 | }; |
| 73 | |
| 74 | reg_1p8v: regulator-1p8v { |
| 75 | compatible = "regulator-fixed"; |
| 76 | regulator-name = "fixed-1.8V"; |
| 77 | regulator-min-microvolt = <1800000>; |
| 78 | regulator-max-microvolt = <1800000>; |
| 79 | regulator-always-on; |
| 80 | }; |
| 81 | |
| 82 | reg_3p3v: regulator-3p3v { |
| 83 | compatible = "regulator-fixed"; |
| 84 | regulator-name = "fixed-3.3V"; |
| 85 | regulator-min-microvolt = <3300000>; |
| 86 | regulator-max-microvolt = <3300000>; |
| 87 | regulator-boot-on; |
| 88 | regulator-always-on; |
| 89 | }; |
| 90 | |
| 91 | reg_5v: regulator-5v { |
| 92 | compatible = "regulator-fixed"; |
| 93 | regulator-name = "fixed-5V"; |
| 94 | regulator-min-microvolt = <5000000>; |
| 95 | regulator-max-microvolt = <5000000>; |
| 96 | regulator-boot-on; |
| 97 | regulator-always-on; |
| 98 | }; |
| 99 | }; |
| 100 | |
| 101 | &bch { |
| 102 | status = "okay"; |
| 103 | }; |
| 104 | |
| 105 | &btif { |
| 106 | status = "okay"; |
| 107 | }; |
| 108 | |
| 109 | &cir { |
| 110 | pinctrl-names = "default"; |
| 111 | pinctrl-0 = <&irrx_pins>; |
| 112 | status = "okay"; |
| 113 | }; |
| 114 | |
| 115 | ð { |
| 116 | status = "okay"; |
| 117 | gmac0: mac@0 { |
| 118 | compatible = "mediatek,eth-mac"; |
| 119 | reg = <0>; |
| 120 | phy-mode = "2500base-x"; |
| 121 | |
| 122 | fixed-link { |
| 123 | speed = <2500>; |
| 124 | full-duplex; |
| 125 | pause; |
| 126 | }; |
| 127 | }; |
| 128 | |
| 129 | gmac1: mac@1 { |
| 130 | compatible = "mediatek,eth-mac"; |
| 131 | reg = <1>; |
| 132 | phy-mode = "rgmii"; |
| 133 | |
| 134 | fixed-link { |
| 135 | speed = <1000>; |
| 136 | full-duplex; |
| 137 | pause; |
| 138 | }; |
| 139 | }; |
| 140 | |
| 141 | mdio: mdio-bus { |
| 142 | #address-cells = <1>; |
| 143 | #size-cells = <0>; |
| 144 | |
| 145 | switch@0 { |
| 146 | compatible = "mediatek,mt7531"; |
| 147 | reg = <0>; |
| 148 | reset-gpios = <&pio 54 0>; |
| 149 | |
| 150 | ports { |
| 151 | #address-cells = <1>; |
| 152 | #size-cells = <0>; |
| 153 | |
| 154 | port@0 { |
| 155 | reg = <0>; |
| 156 | label = "lan1"; |
| 157 | }; |
| 158 | |
| 159 | port@1 { |
| 160 | reg = <1>; |
| 161 | label = "lan2"; |
| 162 | }; |
| 163 | |
| 164 | port@2 { |
| 165 | reg = <2>; |
| 166 | label = "lan3"; |
| 167 | }; |
| 168 | |
| 169 | port@3 { |
| 170 | reg = <3>; |
| 171 | label = "lan4"; |
| 172 | }; |
| 173 | |
| 174 | port@4 { |
| 175 | reg = <4>; |
| 176 | label = "wan"; |
| 177 | }; |
| 178 | |
| 179 | port@6 { |
| 180 | reg = <6>; |
| 181 | label = "cpu"; |
| 182 | ethernet = <&gmac0>; |
| 183 | phy-mode = "2500base-x"; |
| 184 | |
| 185 | fixed-link { |
| 186 | speed = <2500>; |
| 187 | full-duplex; |
| 188 | pause; |
| 189 | }; |
| 190 | }; |
| 191 | }; |
| 192 | }; |
| 193 | }; |
| 194 | }; |
| 195 | |
| 196 | &i2c1 { |
| 197 | pinctrl-names = "default"; |
| 198 | pinctrl-0 = <&i2c1_pins>; |
| 199 | status = "okay"; |
| 200 | }; |
| 201 | |
| 202 | &i2c2 { |
| 203 | pinctrl-names = "default"; |
| 204 | pinctrl-0 = <&i2c2_pins>; |
| 205 | status = "okay"; |
| 206 | }; |
| 207 | |
| 208 | &mmc0 { |
| 209 | pinctrl-names = "default", "state_uhs"; |
| 210 | pinctrl-0 = <&emmc_pins_default>; |
| 211 | pinctrl-1 = <&emmc_pins_uhs>; |
| 212 | status = "okay"; |
| 213 | bus-width = <8>; |
| 214 | max-frequency = <50000000>; |
| 215 | cap-mmc-highspeed; |
| 216 | mmc-hs200-1_8v; |
| 217 | vmmc-supply = <®_3p3v>; |
| 218 | vqmmc-supply = <®_1p8v>; |
| 219 | assigned-clocks = <&topckgen CLK_TOP_MSDC30_0_SEL>; |
| 220 | assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>; |
| 221 | non-removable; |
| 222 | }; |
| 223 | |
| 224 | &mmc1 { |
| 225 | pinctrl-names = "default", "state_uhs"; |
| 226 | pinctrl-0 = <&sd0_pins_default>; |
| 227 | pinctrl-1 = <&sd0_pins_uhs>; |
| 228 | status = "okay"; |
| 229 | bus-width = <4>; |
| 230 | max-frequency = <50000000>; |
| 231 | cap-sd-highspeed; |
| 232 | r_smpl = <1>; |
| 233 | cd-gpios = <&pio 81 GPIO_ACTIVE_LOW>; |
| 234 | vmmc-supply = <®_3p3v>; |
| 235 | vqmmc-supply = <®_3p3v>; |
| 236 | assigned-clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>; |
| 237 | assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>; |
| 238 | }; |
| 239 | |
| 240 | &nandc { |
| 241 | pinctrl-names = "default"; |
| 242 | pinctrl-0 = <¶llel_nand_pins>; |
| 243 | status = "disabled"; |
| 244 | }; |
| 245 | |
| 246 | &nor_flash { |
| 247 | pinctrl-names = "default"; |
| 248 | pinctrl-0 = <&spi_nor_pins>; |
| 249 | status = "disabled"; |
| 250 | |
| 251 | flash@0 { |
| 252 | compatible = "jedec,spi-nor"; |
| 253 | reg = <0>; |
| 254 | }; |
| 255 | }; |
| 256 | |
| 257 | &pcie0 { |
| 258 | pinctrl-names = "default"; |
| 259 | pinctrl-0 = <&pcie0_pins>; |
| 260 | status = "okay"; |
| 261 | }; |
| 262 | |
| 263 | &pcie1 { |
| 264 | pinctrl-names = "default"; |
| 265 | pinctrl-0 = <&pcie1_pins>; |
| 266 | status = "okay"; |
| 267 | }; |
| 268 | |
| 269 | &pio { |
| 270 | /* Attention: GPIO 90 is used to switch between PCIe@1,0 and |
| 271 | * SATA functions. i.e. output-high: PCIe, output-low: SATA |
| 272 | */ |
| 273 | asm_sel { |
| 274 | gpio-hog; |
| 275 | gpios = <90 GPIO_ACTIVE_HIGH>; |
| 276 | output-high; |
| 277 | }; |
| 278 | |
| 279 | /* eMMC is shared pin with parallel NAND */ |
| 280 | emmc_pins_default: emmc-pins-default { |
| 281 | mux { |
| 282 | function = "emmc", "emmc_rst"; |
| 283 | groups = "emmc"; |
| 284 | }; |
| 285 | |
| 286 | /* "NDL0","NDL1","NDL2","NDL3","NDL4","NDL5","NDL6","NDL7", |
| 287 | * "NRB","NCLE" pins are used as DAT0,DAT1,DAT2,DAT3,DAT4, |
| 288 | * DAT5,DAT6,DAT7,CMD,CLK for eMMC respectively |
| 289 | */ |
| 290 | conf-cmd-dat { |
| 291 | pins = "NDL0", "NDL1", "NDL2", |
| 292 | "NDL3", "NDL4", "NDL5", |
| 293 | "NDL6", "NDL7", "NRB"; |
| 294 | input-enable; |
| 295 | bias-pull-up; |
| 296 | }; |
| 297 | |
| 298 | conf-clk { |
| 299 | pins = "NCLE"; |
| 300 | bias-pull-down; |
| 301 | }; |
| 302 | }; |
| 303 | |
| 304 | emmc_pins_uhs: emmc-pins-uhs { |
| 305 | mux { |
| 306 | function = "emmc"; |
| 307 | groups = "emmc"; |
| 308 | }; |
| 309 | |
| 310 | conf-cmd-dat { |
| 311 | pins = "NDL0", "NDL1", "NDL2", |
| 312 | "NDL3", "NDL4", "NDL5", |
| 313 | "NDL6", "NDL7", "NRB"; |
| 314 | input-enable; |
| 315 | drive-strength = <4>; |
| 316 | bias-pull-up; |
| 317 | }; |
| 318 | |
| 319 | conf-clk { |
| 320 | pins = "NCLE"; |
| 321 | drive-strength = <4>; |
| 322 | bias-pull-down; |
| 323 | }; |
| 324 | }; |
| 325 | |
| 326 | eth_pins: eth-pins { |
| 327 | mux { |
| 328 | function = "eth"; |
| 329 | groups = "mdc_mdio", "rgmii_via_gmac2"; |
| 330 | }; |
| 331 | }; |
| 332 | |
| 333 | i2c1_pins: i2c1-pins { |
| 334 | mux { |
| 335 | function = "i2c"; |
| 336 | groups = "i2c1_0"; |
| 337 | }; |
| 338 | }; |
| 339 | |
| 340 | i2c2_pins: i2c2-pins { |
| 341 | mux { |
| 342 | function = "i2c"; |
| 343 | groups = "i2c2_0"; |
| 344 | }; |
| 345 | }; |
| 346 | |
| 347 | i2s1_pins: i2s1-pins { |
| 348 | mux { |
| 349 | function = "i2s"; |
| 350 | groups = "i2s_out_mclk_bclk_ws", |
| 351 | "i2s1_in_data", |
| 352 | "i2s1_out_data"; |
| 353 | }; |
| 354 | |
| 355 | conf { |
| 356 | pins = "I2S1_IN", "I2S1_OUT", "I2S_BCLK", |
| 357 | "I2S_WS", "I2S_MCLK"; |
| 358 | drive-strength = <12>; |
| 359 | bias-pull-down; |
| 360 | }; |
| 361 | }; |
| 362 | |
| 363 | irrx_pins: irrx-pins { |
| 364 | mux { |
| 365 | function = "ir"; |
| 366 | groups = "ir_1_rx"; |
| 367 | }; |
| 368 | }; |
| 369 | |
| 370 | irtx_pins: irtx-pins { |
| 371 | mux { |
| 372 | function = "ir"; |
| 373 | groups = "ir_1_tx"; |
| 374 | }; |
| 375 | }; |
| 376 | |
| 377 | /* Parallel nand is shared pin with eMMC */ |
| 378 | parallel_nand_pins: parallel-nand-pins { |
| 379 | mux { |
| 380 | function = "flash"; |
| 381 | groups = "par_nand"; |
| 382 | }; |
| 383 | }; |
| 384 | |
| 385 | pcie0_pins: pcie0-pins { |
| 386 | mux { |
| 387 | function = "pcie"; |
| 388 | groups = "pcie0_pad_perst", |
| 389 | "pcie0_1_waken", |
| 390 | "pcie0_1_clkreq"; |
| 391 | }; |
| 392 | }; |
| 393 | |
| 394 | pcie1_pins: pcie1-pins { |
| 395 | mux { |
| 396 | function = "pcie"; |
| 397 | groups = "pcie1_pad_perst", |
| 398 | "pcie1_0_waken", |
| 399 | "pcie1_0_clkreq"; |
| 400 | }; |
| 401 | }; |
| 402 | |
| 403 | pmic_bus_pins: pmic-bus-pins { |
| 404 | mux { |
| 405 | function = "pmic"; |
| 406 | groups = "pmic_bus"; |
| 407 | }; |
| 408 | }; |
| 409 | |
| 410 | pwm7_pins: pwm1-2-pins { |
| 411 | mux { |
| 412 | function = "pwm"; |
| 413 | groups = "pwm_ch7_2"; |
| 414 | }; |
| 415 | }; |
| 416 | |
| 417 | wled_pins: wled-pins { |
| 418 | mux { |
| 419 | function = "led"; |
| 420 | groups = "wled"; |
| 421 | }; |
| 422 | }; |
| 423 | |
| 424 | sd0_pins_default: sd0-pins-default { |
| 425 | mux { |
| 426 | function = "sd"; |
| 427 | groups = "sd_0"; |
| 428 | }; |
| 429 | |
| 430 | /* "I2S2_OUT, "I2S4_IN"", "I2S3_IN", "I2S2_IN", |
| 431 | * "I2S4_OUT", "I2S3_OUT" are used as DAT0, DAT1, |
| 432 | * DAT2, DAT3, CMD, CLK for SD respectively. |
| 433 | */ |
| 434 | conf-cmd-data { |
| 435 | pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN", |
| 436 | "I2S2_IN","I2S4_OUT"; |
| 437 | input-enable; |
| 438 | drive-strength = <8>; |
| 439 | bias-pull-up; |
| 440 | }; |
| 441 | conf-clk { |
| 442 | pins = "I2S3_OUT"; |
| 443 | drive-strength = <12>; |
| 444 | bias-pull-down; |
| 445 | }; |
| 446 | conf-cd { |
| 447 | pins = "TXD3"; |
| 448 | bias-pull-up; |
| 449 | }; |
| 450 | }; |
| 451 | |
| 452 | sd0_pins_uhs: sd0-pins-uhs { |
| 453 | mux { |
| 454 | function = "sd"; |
| 455 | groups = "sd_0"; |
| 456 | }; |
| 457 | |
| 458 | conf-cmd-data { |
| 459 | pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN", |
| 460 | "I2S2_IN","I2S4_OUT"; |
| 461 | input-enable; |
| 462 | bias-pull-up; |
| 463 | }; |
| 464 | |
| 465 | conf-clk { |
| 466 | pins = "I2S3_OUT"; |
| 467 | bias-pull-down; |
| 468 | }; |
| 469 | }; |
| 470 | |
| 471 | /* Serial NAND is shared pin with SPI-NOR */ |
| 472 | serial_nand_pins: serial-nand-pins { |
| 473 | mux { |
| 474 | function = "flash"; |
| 475 | groups = "snfi"; |
| 476 | }; |
| 477 | }; |
| 478 | |
| 479 | spic0_pins: spic0-pins { |
| 480 | mux { |
| 481 | function = "spi"; |
| 482 | groups = "spic0_0"; |
| 483 | }; |
| 484 | }; |
| 485 | |
| 486 | spic1_pins: spic1-pins { |
| 487 | mux { |
| 488 | function = "spi"; |
| 489 | groups = "spic1_0"; |
| 490 | }; |
| 491 | }; |
| 492 | |
| 493 | /* SPI-NOR is shared pin with serial NAND */ |
| 494 | spi_nor_pins: spi-nor-pins { |
| 495 | mux { |
| 496 | function = "flash"; |
| 497 | groups = "spi_nor"; |
| 498 | }; |
| 499 | }; |
| 500 | |
| 501 | /* serial NAND is shared pin with SPI-NOR */ |
| 502 | serial_nand_pins: serial-nand-pins { |
| 503 | mux { |
| 504 | function = "flash"; |
| 505 | groups = "snfi"; |
| 506 | }; |
| 507 | }; |
| 508 | |
| 509 | uart0_pins: uart0-pins { |
| 510 | mux { |
| 511 | function = "uart"; |
| 512 | groups = "uart0_0_tx_rx" ; |
| 513 | }; |
| 514 | }; |
| 515 | |
| 516 | uart2_pins: uart2-pins { |
| 517 | mux { |
| 518 | function = "uart"; |
| 519 | groups = "uart2_1_tx_rx" ; |
| 520 | }; |
| 521 | }; |
| 522 | |
| 523 | watchdog_pins: watchdog-pins { |
| 524 | mux { |
| 525 | function = "watchdog"; |
| 526 | groups = "watchdog"; |
| 527 | }; |
| 528 | }; |
| 529 | }; |
| 530 | |
| 531 | &pwm { |
| 532 | pinctrl-names = "default"; |
| 533 | pinctrl-0 = <&pwm7_pins>; |
| 534 | status = "okay"; |
| 535 | }; |
| 536 | |
| 537 | &pwrap { |
| 538 | pinctrl-names = "default"; |
| 539 | pinctrl-0 = <&pmic_bus_pins>; |
| 540 | |
| 541 | status = "okay"; |
| 542 | }; |
| 543 | |
| 544 | &sata { |
| 545 | status = "disable"; |
| 546 | }; |
| 547 | |
| 548 | &sata_phy { |
| 549 | status = "disable"; |
| 550 | }; |
| 551 | |
| 552 | &snfi { |
| 553 | pinctrl-names = "default"; |
| 554 | pinctrl-0 = <&serial_nand_pins>; |
| 555 | status = "okay"; |
| 556 | |
| 557 | spi_nand@0 { |
| 558 | #address-cells = <1>; |
| 559 | #size-cells = <1>; |
| 560 | compatible = "spi-nand"; |
| 561 | spi-max-frequency = <104000000>; |
| 562 | reg = <0>; |
| 563 | |
| 564 | partitions { |
| 565 | compatible = "fixed-partitions"; |
| 566 | #address-cells = <1>; |
| 567 | #size-cells = <1>; |
| 568 | |
| 569 | partition@0 { |
| 570 | label = "Preloader"; |
| 571 | reg = <0x00000 0x0080000>; |
| 572 | read-only; |
| 573 | }; |
| 574 | |
| 575 | partition@80000 { |
| 576 | label = "ATF"; |
| 577 | reg = <0x80000 0x0040000>; |
| 578 | }; |
| 579 | |
| 580 | partition@c0000 { |
| 581 | label = "Bootloader"; |
| 582 | reg = <0xc0000 0x0080000>; |
| 583 | }; |
| 584 | |
| 585 | partition@140000 { |
| 586 | label = "Config"; |
| 587 | reg = <0x140000 0x0080000>; |
| 588 | }; |
| 589 | |
| 590 | factory: partition@1c0000 { |
| 591 | label = "Factory"; |
| 592 | reg = <0x1c0000 0x0100000>; |
| 593 | }; |
| 594 | |
| 595 | partition@200000 { |
| 596 | label = "firmware"; |
| 597 | reg = <0x2c0000 0x2000000>; |
| 598 | }; |
| 599 | |
| 600 | partition@2200000 { |
| 601 | label = "User_data"; |
| 602 | reg = <0x22c0000 0x4000000>; |
| 603 | }; |
| 604 | }; |
| 605 | }; |
| 606 | }; |
| 607 | |
| 608 | &spi0 { |
| 609 | pinctrl-names = "default"; |
| 610 | pinctrl-0 = <&spic0_pins>; |
| 611 | status = "okay"; |
| 612 | }; |
| 613 | |
| 614 | &spi1 { |
| 615 | pinctrl-names = "default"; |
| 616 | pinctrl-0 = <&spic1_pins>; |
| 617 | status = "okay"; |
| 618 | }; |
| 619 | |
| 620 | &ssusb { |
| 621 | vusb33-supply = <®_3p3v>; |
| 622 | vbus-supply = <®_5v>; |
| 623 | status = "okay"; |
| 624 | }; |
| 625 | |
| 626 | &u3phy { |
| 627 | status = "okay"; |
| 628 | }; |
| 629 | |
| 630 | &uart0 { |
| 631 | pinctrl-names = "default"; |
| 632 | pinctrl-0 = <&uart0_pins>; |
| 633 | status = "okay"; |
| 634 | }; |
| 635 | |
| 636 | &uart2 { |
| 637 | pinctrl-names = "default"; |
| 638 | pinctrl-0 = <&uart2_pins>; |
| 639 | status = "okay"; |
| 640 | }; |
| 641 | |
| 642 | &watchdog { |
| 643 | pinctrl-names = "default"; |
| 644 | pinctrl-0 = <&watchdog_pins>; |
| 645 | status = "okay"; |
| 646 | }; |