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git01.mediatek.com / openwrt / feeds / mtk-openwrt-feeds / 1ad6fe4d765cdc9686dd83fef5f694254ed072d9 / . / autobuild_mac80211_release / mt7988_mt7996_mac80211 / package / kernel / mt76 / src / mt7996 / dma.c
blob: 4d45dc5ec02fcc7a997466a9da89f742b100a883 [file] [log] [blame]
developer0f312e82022-11-01 12:31:52 +0800[diff] [blame]1// SPDX-License-Identifier: ISC
2/*
3 * Copyright (C) 2022 MediaTek Inc.
4 */
5
6#include "mt7996.h"
7#include "../dma.h"
8#include "mac.h"
9
10static int mt7996_poll_tx(struct napi_struct *napi, int budget)
11{
12 struct mt7996_dev *dev;
13
14 dev = container_of(napi, struct mt7996_dev, mt76.tx_napi);
15
16 mt76_connac_tx_cleanup(&dev->mt76);
17 if (napi_complete_done(napi, 0))
18 mt7996_irq_enable(dev, MT_INT_TX_DONE_MCU);
19
20 return 0;
21}
22
23static void mt7996_dma_config(struct mt7996_dev *dev)
24{
25#define Q_CONFIG(q, wfdma, int, id) do { \
26 if (wfdma) \
27 dev->q_wfdma_mask |= (1 << (q)); \
28 dev->q_int_mask[(q)] = int; \
29 dev->q_id[(q)] = id; \
30 } while (0)
31
32#define MCUQ_CONFIG(q, wfdma, int, id) Q_CONFIG(q, (wfdma), (int), (id))
33#define RXQ_CONFIG(q, wfdma, int, id) Q_CONFIG(__RXQ(q), (wfdma), (int), (id))
34#define TXQ_CONFIG(q, wfdma, int, id) Q_CONFIG(__TXQ(q), (wfdma), (int), (id))
35
36 /* rx queue */
37 RXQ_CONFIG(MT_RXQ_MCU, WFDMA0, MT_INT_RX_DONE_WM, MT7996_RXQ_MCU_WM);
38 RXQ_CONFIG(MT_RXQ_MCU_WA, WFDMA0, MT_INT_RX_DONE_WA, MT7996_RXQ_MCU_WA);
39
40 /* band0/band1 */
41 RXQ_CONFIG(MT_RXQ_MAIN, WFDMA0, MT_INT_RX_DONE_BAND0, MT7996_RXQ_BAND0);
42 RXQ_CONFIG(MT_RXQ_MAIN_WA, WFDMA0, MT_INT_RX_DONE_WA_MAIN, MT7996_RXQ_MCU_WA_MAIN);
43
44 /* band2 */
45 RXQ_CONFIG(MT_RXQ_BAND2, WFDMA0, MT_INT_RX_DONE_BAND2, MT7996_RXQ_BAND2);
46 RXQ_CONFIG(MT_RXQ_BAND2_WA, WFDMA0, MT_INT_RX_DONE_WA_TRI, MT7996_RXQ_MCU_WA_TRI);
47
48 /* data tx queue */
49 TXQ_CONFIG(0, WFDMA0, MT_INT_TX_DONE_BAND0, MT7996_TXQ_BAND0);
50 TXQ_CONFIG(1, WFDMA0, MT_INT_TX_DONE_BAND1, MT7996_TXQ_BAND1);
51 TXQ_CONFIG(2, WFDMA0, MT_INT_TX_DONE_BAND2, MT7996_TXQ_BAND2);
52
53 /* mcu tx queue */
54 MCUQ_CONFIG(MT_MCUQ_WM, WFDMA0, MT_INT_TX_DONE_MCU_WM, MT7996_TXQ_MCU_WM);
55 MCUQ_CONFIG(MT_MCUQ_WA, WFDMA0, MT_INT_TX_DONE_MCU_WA, MT7996_TXQ_MCU_WA);
56 MCUQ_CONFIG(MT_MCUQ_FWDL, WFDMA0, MT_INT_TX_DONE_FWDL, MT7996_TXQ_FWDL);
57}
58
59static void __mt7996_dma_prefetch(struct mt7996_dev *dev, u32 ofs)
60{
61#define PREFETCH(_base, _depth) ((_base) << 16 | (_depth))
62 /* prefetch SRAM wrapping boundary for tx/rx ring. */
63 mt76_wr(dev, MT_MCUQ_EXT_CTRL(MT_MCUQ_FWDL) + ofs, PREFETCH(0x0, 0x2));
64 mt76_wr(dev, MT_MCUQ_EXT_CTRL(MT_MCUQ_WM) + ofs, PREFETCH(0x20, 0x2));
65 mt76_wr(dev, MT_TXQ_EXT_CTRL(0) + ofs, PREFETCH(0x40, 0x4));
66 mt76_wr(dev, MT_TXQ_EXT_CTRL(1) + ofs, PREFETCH(0x80, 0x4));
67 mt76_wr(dev, MT_MCUQ_EXT_CTRL(MT_MCUQ_WA) + ofs, PREFETCH(0xc0, 0x2));
68 mt76_wr(dev, MT_TXQ_EXT_CTRL(2) + ofs, PREFETCH(0xe0, 0x4));
69 mt76_wr(dev, MT_RXQ_BAND1_CTRL(MT_RXQ_MCU) + ofs, PREFETCH(0x120, 0x2));
70 mt76_wr(dev, MT_RXQ_BAND1_CTRL(MT_RXQ_MCU_WA) + ofs, PREFETCH(0x140, 0x2));
71 mt76_wr(dev, MT_RXQ_BAND1_CTRL(MT_RXQ_MAIN_WA) + ofs, PREFETCH(0x160, 0x2));
72 mt76_wr(dev, MT_RXQ_BAND1_CTRL(MT_RXQ_BAND2_WA) + ofs, PREFETCH(0x180, 0x2));
73 mt76_wr(dev, MT_RXQ_BAND1_CTRL(MT_RXQ_MAIN) + ofs, PREFETCH(0x1a0, 0x10));
74 mt76_wr(dev, MT_RXQ_BAND1_CTRL(MT_RXQ_BAND2) + ofs, PREFETCH(0x2a0, 0x10));
75
76 mt76_set(dev, WF_WFDMA0_GLO_CFG_EXT1 + ofs, WF_WFDMA0_GLO_CFG_EXT1_CALC_MODE);
77}
78
79void mt7996_dma_prefetch(struct mt7996_dev *dev)
80{
81 __mt7996_dma_prefetch(dev, 0);
82 if (dev->hif2)
83 __mt7996_dma_prefetch(dev, MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0));
84}
85
86static void mt7996_dma_disable(struct mt7996_dev *dev, bool reset)
87{
88 u32 hif1_ofs = 0;
89
90 if (dev->hif2)
91 hif1_ofs = MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0);
92
93 if (reset) {
94 mt76_clear(dev, MT_WFDMA0_RST,
95 MT_WFDMA0_RST_DMASHDL_ALL_RST |
96 MT_WFDMA0_RST_LOGIC_RST);
97
98 mt76_set(dev, MT_WFDMA0_RST,
99 MT_WFDMA0_RST_DMASHDL_ALL_RST |
100 MT_WFDMA0_RST_LOGIC_RST);
101
102 if (dev->hif2) {
103 mt76_clear(dev, MT_WFDMA0_RST + hif1_ofs,
104 MT_WFDMA0_RST_DMASHDL_ALL_RST |
105 MT_WFDMA0_RST_LOGIC_RST);
106
107 mt76_set(dev, MT_WFDMA0_RST + hif1_ofs,
108 MT_WFDMA0_RST_DMASHDL_ALL_RST |
109 MT_WFDMA0_RST_LOGIC_RST);
110 }
111 }
112
113 /* disable */
114 mt76_clear(dev, MT_WFDMA0_GLO_CFG,
115 MT_WFDMA0_GLO_CFG_TX_DMA_EN |
116 MT_WFDMA0_GLO_CFG_RX_DMA_EN |
117 MT_WFDMA0_GLO_CFG_OMIT_TX_INFO |
118 MT_WFDMA0_GLO_CFG_OMIT_RX_INFO |
119 MT_WFDMA0_GLO_CFG_OMIT_RX_INFO_PFET2);
120
121 if (dev->hif2) {
122 mt76_clear(dev, MT_WFDMA0_GLO_CFG + hif1_ofs,
123 MT_WFDMA0_GLO_CFG_TX_DMA_EN |
124 MT_WFDMA0_GLO_CFG_RX_DMA_EN |
125 MT_WFDMA0_GLO_CFG_OMIT_TX_INFO |
126 MT_WFDMA0_GLO_CFG_OMIT_RX_INFO |
127 MT_WFDMA0_GLO_CFG_OMIT_RX_INFO_PFET2);
128 }
129}
130
131static int mt7996_dma_enable(struct mt7996_dev *dev)
132{
133 u32 hif1_ofs = 0;
134 u32 irq_mask;
135
136 if (dev->hif2)
137 hif1_ofs = MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0);
138
139 /* reset dma idx */
140 mt76_wr(dev, MT_WFDMA0_RST_DTX_PTR, ~0);
141 if (dev->hif2)
142 mt76_wr(dev, MT_WFDMA0_RST_DTX_PTR + hif1_ofs, ~0);
143
144 /* configure delay interrupt off */
145 mt76_wr(dev, MT_WFDMA0_PRI_DLY_INT_CFG0, 0);
146 mt76_wr(dev, MT_WFDMA0_PRI_DLY_INT_CFG1, 0);
147 mt76_wr(dev, MT_WFDMA0_PRI_DLY_INT_CFG2, 0);
148
149 if (dev->hif2) {
150 mt76_wr(dev, MT_WFDMA0_PRI_DLY_INT_CFG0 + hif1_ofs, 0);
151 mt76_wr(dev, MT_WFDMA0_PRI_DLY_INT_CFG1 + hif1_ofs, 0);
152 mt76_wr(dev, MT_WFDMA0_PRI_DLY_INT_CFG2 + hif1_ofs, 0);
153 }
154
155 /* configure perfetch settings */
156 mt7996_dma_prefetch(dev);
157
158 /* hif wait WFDMA idle */
159 mt76_set(dev, MT_WFDMA0_BUSY_ENA,
160 MT_WFDMA0_BUSY_ENA_TX_FIFO0 |
161 MT_WFDMA0_BUSY_ENA_TX_FIFO1 |
162 MT_WFDMA0_BUSY_ENA_RX_FIFO);
163
164 if (dev->hif2)
165 mt76_set(dev, MT_WFDMA0_BUSY_ENA + hif1_ofs,
166 MT_WFDMA0_PCIE1_BUSY_ENA_TX_FIFO0 |
167 MT_WFDMA0_PCIE1_BUSY_ENA_TX_FIFO1 |
168 MT_WFDMA0_PCIE1_BUSY_ENA_RX_FIFO);
169
170 mt76_poll(dev, MT_WFDMA_EXT_CSR_HIF_MISC,
171 MT_WFDMA_EXT_CSR_HIF_MISC_BUSY, 0, 1000);
172
173 /* set WFDMA Tx/Rx */
174 mt76_set(dev, MT_WFDMA0_GLO_CFG,
175 MT_WFDMA0_GLO_CFG_TX_DMA_EN |
176 MT_WFDMA0_GLO_CFG_RX_DMA_EN |
177 MT_WFDMA0_GLO_CFG_OMIT_TX_INFO |
178 MT_WFDMA0_GLO_CFG_OMIT_RX_INFO_PFET2);
179
180 /* GLO_CFG_EXT0 */
181 mt76_set(dev, WF_WFDMA0_GLO_CFG_EXT0,
182 WF_WFDMA0_GLO_CFG_EXT0_RX_WB_RXD |
183 WF_WFDMA0_GLO_CFG_EXT0_WED_MERGE_MODE);
184
185 /* GLO_CFG_EXT1 */
186 mt76_set(dev, WF_WFDMA0_GLO_CFG_EXT1,
187 WF_WFDMA0_GLO_CFG_EXT1_TX_FCTRL_MODE);
188
189 if (dev->hif2) {
190 mt76_set(dev, MT_WFDMA0_GLO_CFG + hif1_ofs,
191 MT_WFDMA0_GLO_CFG_TX_DMA_EN |
192 MT_WFDMA0_GLO_CFG_RX_DMA_EN |
193 MT_WFDMA0_GLO_CFG_OMIT_TX_INFO |
194 MT_WFDMA0_GLO_CFG_OMIT_RX_INFO_PFET2);
195
196 /* GLO_CFG_EXT0 */
197 mt76_set(dev, WF_WFDMA0_GLO_CFG_EXT0 + hif1_ofs,
198 WF_WFDMA0_GLO_CFG_EXT0_RX_WB_RXD |
199 WF_WFDMA0_GLO_CFG_EXT0_WED_MERGE_MODE);
200
201 /* GLO_CFG_EXT1 */
202 mt76_set(dev, WF_WFDMA0_GLO_CFG_EXT1 + hif1_ofs,
203 WF_WFDMA0_GLO_CFG_EXT1_TX_FCTRL_MODE);
204
205 mt76_set(dev, MT_WFDMA_HOST_CONFIG,
206 MT_WFDMA_HOST_CONFIG_PDMA_BAND);
207 }
208
209 if (dev->hif2) {
210 /* fix hardware limitation, pcie1's rx ring3 is not available
211 * so, redirect pcie0 rx ring3 interrupt to pcie1
212 */
213 mt76_set(dev, MT_WFDMA0_RX_INT_PCIE_SEL,
214 MT_WFDMA0_RX_INT_SEL_RING3);
215
216 /* TODO: redirect rx ring6 interrupt to pcie0 for wed function */
217 }
218
219 /* enable interrupts for TX/RX rings */
220 irq_mask = MT_INT_RX_DONE_MCU |
221 MT_INT_TX_DONE_MCU |
222 MT_INT_MCU_CMD;
223
224 if (!dev->mphy.band_idx)
225 irq_mask |= MT_INT_BAND0_RX_DONE;
226
227 if (dev->dbdc_support)
228 irq_mask |= MT_INT_BAND1_RX_DONE;
229
230 if (dev->tbtc_support)
231 irq_mask |= MT_INT_BAND2_RX_DONE;
232
233 mt7996_irq_enable(dev, irq_mask);
234
235 return 0;
236}
237
238int mt7996_dma_init(struct mt7996_dev *dev)
239{
240 u32 hif1_ofs = 0;
241 int ret;
242
243 mt7996_dma_config(dev);
244
245 mt76_dma_attach(&dev->mt76);
246
247 if (dev->hif2)
248 hif1_ofs = MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0);
249
250 mt7996_dma_disable(dev, true);
251
252 /* init tx queue */
253 ret = mt76_connac_init_tx_queues(dev->phy.mt76,
254 MT_TXQ_ID(dev->mphy.band_idx),
255 MT7996_TX_RING_SIZE,
256 MT_TXQ_RING_BASE(0), 0);
257 if (ret)
258 return ret;
259
260 /* command to WM */
261 ret = mt76_init_mcu_queue(&dev->mt76, MT_MCUQ_WM,
262 MT_MCUQ_ID(MT_MCUQ_WM),
263 MT7996_TX_MCU_RING_SIZE,
264 MT_MCUQ_RING_BASE(MT_MCUQ_WM));
265 if (ret)
266 return ret;
267
268 /* command to WA */
269 ret = mt76_init_mcu_queue(&dev->mt76, MT_MCUQ_WA,
270 MT_MCUQ_ID(MT_MCUQ_WA),
271 MT7996_TX_MCU_RING_SIZE,
272 MT_MCUQ_RING_BASE(MT_MCUQ_WA));
273 if (ret)
274 return ret;
275
276 /* firmware download */
277 ret = mt76_init_mcu_queue(&dev->mt76, MT_MCUQ_FWDL,
278 MT_MCUQ_ID(MT_MCUQ_FWDL),
279 MT7996_TX_FWDL_RING_SIZE,
280 MT_MCUQ_RING_BASE(MT_MCUQ_FWDL));
281 if (ret)
282 return ret;
283
284 /* event from WM */
285 ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MCU],
286 MT_RXQ_ID(MT_RXQ_MCU),
287 MT7996_RX_MCU_RING_SIZE,
288 MT_RX_BUF_SIZE,
289 MT_RXQ_RING_BASE(MT_RXQ_MCU));
290 if (ret)
291 return ret;
292
293 /* event from WA */
294 ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MCU_WA],
295 MT_RXQ_ID(MT_RXQ_MCU_WA),
296 MT7996_RX_MCU_RING_SIZE,
297 MT_RX_BUF_SIZE,
298 MT_RXQ_RING_BASE(MT_RXQ_MCU_WA));
299 if (ret)
300 return ret;
301
302 /* rx data queue for band0 and band1 */
303 ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MAIN],
304 MT_RXQ_ID(MT_RXQ_MAIN),
305 MT7996_RX_RING_SIZE,
306 MT_RX_BUF_SIZE,
307 MT_RXQ_RING_BASE(MT_RXQ_MAIN));
308 if (ret)
309 return ret;
310
311 /* tx free notify event from WA for band0 */
312 ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MAIN_WA],
313 MT_RXQ_ID(MT_RXQ_MAIN_WA),
314 MT7996_RX_MCU_RING_SIZE,
315 MT_RX_BUF_SIZE,
316 MT_RXQ_RING_BASE(MT_RXQ_MAIN_WA));
317 if (ret)
318 return ret;
319
320 if (dev->tbtc_support || (dev->mphy.band_idx == MT_BAND2)) {
321 /* rx data queue for band2 */
322 ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_BAND2],
323 MT_RXQ_ID(MT_RXQ_BAND2),
324 MT7996_RX_RING_SIZE,
325 MT_RX_BUF_SIZE,
326 MT_RXQ_RING_BASE(MT_RXQ_BAND2) + hif1_ofs);
327 if (ret)
328 return ret;
329
330 /* tx free notify event from WA for band2
331 * use pcie0's rx ring3, but, redirect pcie0 rx ring3 interrupt to pcie1
332 */
333 ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_BAND2_WA],
334 MT_RXQ_ID(MT_RXQ_BAND2_WA),
335 MT7996_RX_MCU_RING_SIZE,
336 MT_RX_BUF_SIZE,
337 MT_RXQ_RING_BASE(MT_RXQ_BAND2_WA));
338 if (ret)
339 return ret;
340 }
341
342 ret = mt76_init_queues(dev, mt76_dma_rx_poll);
343 if (ret < 0)
344 return ret;
345
346 netif_tx_napi_add(&dev->mt76.tx_napi_dev, &dev->mt76.tx_napi,
347 mt7996_poll_tx, NAPI_POLL_WEIGHT);
348 napi_enable(&dev->mt76.tx_napi);
349
350 mt7996_dma_enable(dev);
351
352 return 0;
353}
354
355void mt7996_dma_cleanup(struct mt7996_dev *dev)
356{
357 mt7996_dma_disable(dev, true);
358
359 mt76_dma_cleanup(&dev->mt76);
360}