developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 1 | // SPDX-License-Identifier: ISC |
| 2 | |
| 3 | #include <linux/etherdevice.h> |
| 4 | #include "mt7603.h" |
| 5 | #include "mac.h" |
| 6 | #include "eeprom.h" |
| 7 | |
| 8 | const struct mt76_driver_ops mt7603_drv_ops = { |
| 9 | .txwi_size = MT_TXD_SIZE, |
| 10 | .drv_flags = MT_DRV_SW_RX_AIRTIME, |
| 11 | .survey_flags = SURVEY_INFO_TIME_TX, |
| 12 | .tx_prepare_skb = mt7603_tx_prepare_skb, |
| 13 | .tx_complete_skb = mt7603_tx_complete_skb, |
| 14 | .rx_skb = mt7603_queue_rx_skb, |
| 15 | .rx_poll_complete = mt7603_rx_poll_complete, |
| 16 | .sta_ps = mt7603_sta_ps, |
| 17 | .sta_add = mt7603_sta_add, |
| 18 | .sta_assoc = mt7603_sta_assoc, |
| 19 | .sta_remove = mt7603_sta_remove, |
| 20 | .update_survey = mt7603_update_channel, |
| 21 | }; |
| 22 | |
| 23 | static void |
| 24 | mt7603_set_tmac_template(struct mt7603_dev *dev) |
| 25 | { |
| 26 | u32 desc[5] = { |
| 27 | [1] = FIELD_PREP(MT_TXD3_REM_TX_COUNT, 0xf), |
| 28 | [3] = MT_TXD5_SW_POWER_MGMT |
| 29 | }; |
| 30 | u32 addr; |
| 31 | int i; |
| 32 | |
| 33 | addr = mt7603_reg_map(dev, MT_CLIENT_BASE_PHYS_ADDR); |
| 34 | addr += MT_CLIENT_TMAC_INFO_TEMPLATE; |
| 35 | for (i = 0; i < ARRAY_SIZE(desc); i++) |
| 36 | mt76_wr(dev, addr + 4 * i, desc[i]); |
| 37 | } |
| 38 | |
| 39 | static void |
| 40 | mt7603_dma_sched_init(struct mt7603_dev *dev) |
| 41 | { |
| 42 | int page_size = 128; |
| 43 | int page_count; |
| 44 | int max_len = 1792; |
| 45 | int max_amsdu_pages = 4096 / page_size; |
| 46 | int max_mcu_len = 4096; |
| 47 | int max_beacon_len = 512 * 4 + max_len; |
| 48 | int max_mcast_pages = 4 * max_len / page_size; |
| 49 | int reserved_count = 0; |
| 50 | int beacon_pages; |
| 51 | int mcu_pages; |
| 52 | int i; |
| 53 | |
| 54 | page_count = mt76_get_field(dev, MT_PSE_FC_P0, |
| 55 | MT_PSE_FC_P0_MAX_QUOTA); |
| 56 | beacon_pages = 4 * (max_beacon_len / page_size); |
| 57 | mcu_pages = max_mcu_len / page_size; |
| 58 | |
| 59 | mt76_wr(dev, MT_PSE_FRP, |
| 60 | FIELD_PREP(MT_PSE_FRP_P0, 7) | |
| 61 | FIELD_PREP(MT_PSE_FRP_P1, 6) | |
| 62 | FIELD_PREP(MT_PSE_FRP_P2_RQ2, 4)); |
| 63 | |
| 64 | mt76_wr(dev, MT_HIGH_PRIORITY_1, 0x55555553); |
| 65 | mt76_wr(dev, MT_HIGH_PRIORITY_2, 0x78555555); |
| 66 | |
| 67 | mt76_wr(dev, MT_QUEUE_PRIORITY_1, 0x2b1a096e); |
| 68 | mt76_wr(dev, MT_QUEUE_PRIORITY_2, 0x785f4d3c); |
| 69 | |
| 70 | mt76_wr(dev, MT_PRIORITY_MASK, 0xffffffff); |
| 71 | |
| 72 | mt76_wr(dev, MT_SCH_1, page_count | (2 << 28)); |
| 73 | mt76_wr(dev, MT_SCH_2, max_amsdu_pages); |
| 74 | |
| 75 | for (i = 0; i <= 4; i++) |
| 76 | mt76_wr(dev, MT_PAGE_COUNT(i), max_amsdu_pages); |
| 77 | reserved_count += 5 * max_amsdu_pages; |
| 78 | |
| 79 | mt76_wr(dev, MT_PAGE_COUNT(5), mcu_pages); |
| 80 | reserved_count += mcu_pages; |
| 81 | |
| 82 | mt76_wr(dev, MT_PAGE_COUNT(7), beacon_pages); |
| 83 | reserved_count += beacon_pages; |
| 84 | |
| 85 | mt76_wr(dev, MT_PAGE_COUNT(8), max_mcast_pages); |
| 86 | reserved_count += max_mcast_pages; |
| 87 | |
| 88 | if (is_mt7603(dev)) |
| 89 | reserved_count = 0; |
| 90 | |
| 91 | mt76_wr(dev, MT_RSV_MAX_THRESH, page_count - reserved_count); |
| 92 | |
| 93 | if (is_mt7603(dev) && mt76xx_rev(dev) >= MT7603_REV_E2) { |
| 94 | mt76_wr(dev, MT_GROUP_THRESH(0), |
| 95 | page_count - beacon_pages - mcu_pages); |
| 96 | mt76_wr(dev, MT_GROUP_THRESH(1), beacon_pages); |
| 97 | mt76_wr(dev, MT_BMAP_0, 0x0080ff5f); |
| 98 | mt76_wr(dev, MT_GROUP_THRESH(2), mcu_pages); |
| 99 | mt76_wr(dev, MT_BMAP_1, 0x00000020); |
| 100 | } else { |
| 101 | mt76_wr(dev, MT_GROUP_THRESH(0), page_count); |
| 102 | mt76_wr(dev, MT_BMAP_0, 0xffff); |
| 103 | } |
| 104 | |
| 105 | mt76_wr(dev, MT_SCH_4, 0); |
| 106 | |
| 107 | for (i = 0; i <= 15; i++) |
| 108 | mt76_wr(dev, MT_TXTIME_THRESH(i), 0xfffff); |
| 109 | |
| 110 | mt76_set(dev, MT_SCH_4, BIT(6)); |
| 111 | } |
| 112 | |
| 113 | static void |
| 114 | mt7603_phy_init(struct mt7603_dev *dev) |
| 115 | { |
| 116 | int rx_chains = dev->mphy.antenna_mask; |
| 117 | int tx_chains = hweight8(rx_chains) - 1; |
| 118 | |
| 119 | mt76_rmw(dev, MT_WF_RMAC_RMCR, |
| 120 | (MT_WF_RMAC_RMCR_SMPS_MODE | |
| 121 | MT_WF_RMAC_RMCR_RX_STREAMS), |
| 122 | (FIELD_PREP(MT_WF_RMAC_RMCR_SMPS_MODE, 3) | |
| 123 | FIELD_PREP(MT_WF_RMAC_RMCR_RX_STREAMS, rx_chains))); |
| 124 | |
| 125 | mt76_rmw_field(dev, MT_TMAC_TCR, MT_TMAC_TCR_TX_STREAMS, |
| 126 | tx_chains); |
| 127 | |
| 128 | dev->agc0 = mt76_rr(dev, MT_AGC(0)); |
| 129 | dev->agc3 = mt76_rr(dev, MT_AGC(3)); |
| 130 | } |
| 131 | |
| 132 | static void |
| 133 | mt7603_mac_init(struct mt7603_dev *dev) |
| 134 | { |
| 135 | u8 bc_addr[ETH_ALEN]; |
| 136 | u32 addr; |
| 137 | int i; |
| 138 | |
| 139 | mt76_wr(dev, MT_AGG_BA_SIZE_LIMIT_0, |
| 140 | (MT_AGG_SIZE_LIMIT(0) << 0 * MT_AGG_BA_SIZE_LIMIT_SHIFT) | |
| 141 | (MT_AGG_SIZE_LIMIT(1) << 1 * MT_AGG_BA_SIZE_LIMIT_SHIFT) | |
| 142 | (MT_AGG_SIZE_LIMIT(2) << 2 * MT_AGG_BA_SIZE_LIMIT_SHIFT) | |
| 143 | (MT_AGG_SIZE_LIMIT(3) << 3 * MT_AGG_BA_SIZE_LIMIT_SHIFT)); |
| 144 | |
| 145 | mt76_wr(dev, MT_AGG_BA_SIZE_LIMIT_1, |
| 146 | (MT_AGG_SIZE_LIMIT(4) << 0 * MT_AGG_BA_SIZE_LIMIT_SHIFT) | |
| 147 | (MT_AGG_SIZE_LIMIT(5) << 1 * MT_AGG_BA_SIZE_LIMIT_SHIFT) | |
| 148 | (MT_AGG_SIZE_LIMIT(6) << 2 * MT_AGG_BA_SIZE_LIMIT_SHIFT) | |
| 149 | (MT_AGG_SIZE_LIMIT(7) << 3 * MT_AGG_BA_SIZE_LIMIT_SHIFT)); |
| 150 | |
| 151 | mt76_wr(dev, MT_AGG_LIMIT, |
| 152 | FIELD_PREP(MT_AGG_LIMIT_AC(0), 24) | |
| 153 | FIELD_PREP(MT_AGG_LIMIT_AC(1), 24) | |
| 154 | FIELD_PREP(MT_AGG_LIMIT_AC(2), 24) | |
| 155 | FIELD_PREP(MT_AGG_LIMIT_AC(3), 24)); |
| 156 | |
| 157 | mt76_wr(dev, MT_AGG_LIMIT_1, |
| 158 | FIELD_PREP(MT_AGG_LIMIT_AC(0), 24) | |
| 159 | FIELD_PREP(MT_AGG_LIMIT_AC(1), 24) | |
| 160 | FIELD_PREP(MT_AGG_LIMIT_AC(2), 24) | |
| 161 | FIELD_PREP(MT_AGG_LIMIT_AC(3), 24)); |
| 162 | |
| 163 | mt76_wr(dev, MT_AGG_CONTROL, |
| 164 | FIELD_PREP(MT_AGG_CONTROL_BAR_RATE, 0x4b) | |
| 165 | FIELD_PREP(MT_AGG_CONTROL_CFEND_RATE, 0x69) | |
| 166 | MT_AGG_CONTROL_NO_BA_AR_RULE); |
| 167 | |
| 168 | mt76_wr(dev, MT_AGG_RETRY_CONTROL, |
| 169 | FIELD_PREP(MT_AGG_RETRY_CONTROL_BAR_LIMIT, 1) | |
| 170 | FIELD_PREP(MT_AGG_RETRY_CONTROL_RTS_LIMIT, 15)); |
| 171 | |
| 172 | mt76_wr(dev, MT_DMA_DCR0, MT_DMA_DCR0_RX_VEC_DROP | |
| 173 | FIELD_PREP(MT_DMA_DCR0_MAX_RX_LEN, 4096)); |
| 174 | |
| 175 | mt76_rmw(dev, MT_DMA_VCFR0, BIT(0), BIT(13)); |
| 176 | mt76_rmw(dev, MT_DMA_TMCFR0, BIT(0) | BIT(1), BIT(13)); |
| 177 | |
| 178 | mt76_clear(dev, MT_WF_RMAC_TMR_PA, BIT(31)); |
| 179 | |
| 180 | mt76_set(dev, MT_WF_RMACDR, MT_WF_RMACDR_MAXLEN_20BIT); |
| 181 | mt76_rmw(dev, MT_WF_RMAC_MAXMINLEN, 0xffffff, 0x19000); |
| 182 | |
| 183 | mt76_wr(dev, MT_WF_RFCR1, 0); |
| 184 | |
| 185 | mt76_set(dev, MT_TMAC_TCR, MT_TMAC_TCR_RX_RIFS_MODE); |
| 186 | |
| 187 | mt7603_set_tmac_template(dev); |
| 188 | |
| 189 | /* Enable RX group to HIF */ |
| 190 | addr = mt7603_reg_map(dev, MT_CLIENT_BASE_PHYS_ADDR); |
| 191 | mt76_set(dev, addr + MT_CLIENT_RXINF, MT_CLIENT_RXINF_RXSH_GROUPS); |
| 192 | |
| 193 | /* Enable RX group to MCU */ |
| 194 | mt76_set(dev, MT_DMA_DCR1, GENMASK(13, 11)); |
| 195 | |
| 196 | mt76_rmw_field(dev, MT_AGG_PCR_RTS, MT_AGG_PCR_RTS_PKT_THR, 3); |
| 197 | mt76_set(dev, MT_TMAC_PCR, MT_TMAC_PCR_SPE_EN); |
| 198 | |
| 199 | /* include preamble detection in CCA trigger signal */ |
| 200 | mt76_rmw_field(dev, MT_TXREQ, MT_TXREQ_CCA_SRC_SEL, 2); |
| 201 | |
| 202 | mt76_wr(dev, MT_RXREQ, 4); |
| 203 | |
| 204 | /* Configure all rx packets to HIF */ |
| 205 | mt76_wr(dev, MT_DMA_RCFR0, 0xc0000000); |
| 206 | |
| 207 | /* Configure MCU txs selection with aggregation */ |
| 208 | mt76_wr(dev, MT_DMA_TCFR0, |
| 209 | FIELD_PREP(MT_DMA_TCFR_TXS_AGGR_TIMEOUT, 1) | /* 32 us */ |
| 210 | MT_DMA_TCFR_TXS_AGGR_COUNT); |
| 211 | |
| 212 | /* Configure HIF txs selection with aggregation */ |
| 213 | mt76_wr(dev, MT_DMA_TCFR1, |
| 214 | FIELD_PREP(MT_DMA_TCFR_TXS_AGGR_TIMEOUT, 1) | /* 32 us */ |
| 215 | MT_DMA_TCFR_TXS_AGGR_COUNT | /* Maximum count */ |
| 216 | MT_DMA_TCFR_TXS_BIT_MAP); |
| 217 | |
| 218 | mt76_wr(dev, MT_MCU_PCIE_REMAP_1, MT_PSE_WTBL_2_PHYS_ADDR); |
| 219 | |
| 220 | for (i = 0; i < MT7603_WTBL_SIZE; i++) |
| 221 | mt7603_wtbl_clear(dev, i); |
| 222 | |
| 223 | eth_broadcast_addr(bc_addr); |
| 224 | mt7603_wtbl_init(dev, MT7603_WTBL_RESERVED, -1, bc_addr); |
| 225 | dev->global_sta.wcid.idx = MT7603_WTBL_RESERVED; |
| 226 | rcu_assign_pointer(dev->mt76.wcid[MT7603_WTBL_RESERVED], |
| 227 | &dev->global_sta.wcid); |
| 228 | |
| 229 | mt76_rmw_field(dev, MT_LPON_BTEIR, MT_LPON_BTEIR_MBSS_MODE, 2); |
| 230 | mt76_rmw_field(dev, MT_WF_RMACDR, MT_WF_RMACDR_MBSSID_MASK, 2); |
| 231 | |
| 232 | mt76_wr(dev, MT_AGG_ARUCR, |
| 233 | FIELD_PREP(MT_AGG_ARxCR_LIMIT(0), 7) | |
| 234 | FIELD_PREP(MT_AGG_ARxCR_LIMIT(1), 2) | |
| 235 | FIELD_PREP(MT_AGG_ARxCR_LIMIT(2), 2) | |
| 236 | FIELD_PREP(MT_AGG_ARxCR_LIMIT(3), 2) | |
| 237 | FIELD_PREP(MT_AGG_ARxCR_LIMIT(4), 1) | |
| 238 | FIELD_PREP(MT_AGG_ARxCR_LIMIT(5), 1) | |
| 239 | FIELD_PREP(MT_AGG_ARxCR_LIMIT(6), 1) | |
| 240 | FIELD_PREP(MT_AGG_ARxCR_LIMIT(7), 1)); |
| 241 | |
| 242 | mt76_wr(dev, MT_AGG_ARDCR, |
| 243 | FIELD_PREP(MT_AGG_ARxCR_LIMIT(0), MT7603_RATE_RETRY - 1) | |
| 244 | FIELD_PREP(MT_AGG_ARxCR_LIMIT(1), MT7603_RATE_RETRY - 1) | |
| 245 | FIELD_PREP(MT_AGG_ARxCR_LIMIT(2), MT7603_RATE_RETRY - 1) | |
| 246 | FIELD_PREP(MT_AGG_ARxCR_LIMIT(3), MT7603_RATE_RETRY - 1) | |
| 247 | FIELD_PREP(MT_AGG_ARxCR_LIMIT(4), MT7603_RATE_RETRY - 1) | |
| 248 | FIELD_PREP(MT_AGG_ARxCR_LIMIT(5), MT7603_RATE_RETRY - 1) | |
| 249 | FIELD_PREP(MT_AGG_ARxCR_LIMIT(6), MT7603_RATE_RETRY - 1) | |
| 250 | FIELD_PREP(MT_AGG_ARxCR_LIMIT(7), MT7603_RATE_RETRY - 1)); |
| 251 | |
| 252 | mt76_wr(dev, MT_AGG_ARCR, |
| 253 | (FIELD_PREP(MT_AGG_ARCR_RTS_RATE_THR, 2) | |
| 254 | MT_AGG_ARCR_RATE_DOWN_RATIO_EN | |
| 255 | FIELD_PREP(MT_AGG_ARCR_RATE_DOWN_RATIO, 1) | |
| 256 | FIELD_PREP(MT_AGG_ARCR_RATE_UP_EXTRA_TH, 4))); |
| 257 | |
| 258 | mt76_set(dev, MT_WTBL_RMVTCR, MT_WTBL_RMVTCR_RX_MV_MODE); |
| 259 | |
| 260 | mt76_clear(dev, MT_SEC_SCR, MT_SEC_SCR_MASK_ORDER); |
| 261 | mt76_clear(dev, MT_SEC_SCR, BIT(18)); |
| 262 | |
| 263 | /* Set secondary beacon time offsets */ |
| 264 | for (i = 0; i <= 4; i++) |
| 265 | mt76_rmw_field(dev, MT_LPON_SBTOR(i), MT_LPON_SBTOR_TIME_OFFSET, |
| 266 | (i + 1) * (20 + 4096)); |
| 267 | } |
| 268 | |
| 269 | static int |
| 270 | mt7603_init_hardware(struct mt7603_dev *dev) |
| 271 | { |
| 272 | int i, ret; |
| 273 | |
| 274 | mt76_wr(dev, MT_INT_SOURCE_CSR, ~0); |
| 275 | |
| 276 | ret = mt7603_eeprom_init(dev); |
| 277 | if (ret < 0) |
| 278 | return ret; |
| 279 | |
| 280 | ret = mt7603_dma_init(dev); |
| 281 | if (ret) |
| 282 | return ret; |
| 283 | |
| 284 | mt76_wr(dev, MT_WPDMA_GLO_CFG, 0x52000850); |
| 285 | mt7603_mac_dma_start(dev); |
| 286 | dev->rxfilter = mt76_rr(dev, MT_WF_RFCR); |
| 287 | set_bit(MT76_STATE_INITIALIZED, &dev->mphy.state); |
| 288 | |
| 289 | for (i = 0; i < MT7603_WTBL_SIZE; i++) { |
| 290 | mt76_wr(dev, MT_PSE_RTA, MT_PSE_RTA_BUSY | MT_PSE_RTA_WRITE | |
| 291 | FIELD_PREP(MT_PSE_RTA_TAG_ID, i)); |
| 292 | mt76_poll(dev, MT_PSE_RTA, MT_PSE_RTA_BUSY, 0, 5000); |
| 293 | } |
| 294 | |
| 295 | ret = mt7603_mcu_init(dev); |
| 296 | if (ret) |
| 297 | return ret; |
| 298 | |
| 299 | mt7603_dma_sched_init(dev); |
| 300 | mt7603_mcu_set_eeprom(dev); |
| 301 | mt7603_phy_init(dev); |
| 302 | mt7603_mac_init(dev); |
| 303 | |
| 304 | return 0; |
| 305 | } |
| 306 | |
| 307 | static const struct ieee80211_iface_limit if_limits[] = { |
| 308 | { |
| 309 | .max = 1, |
| 310 | .types = BIT(NL80211_IFTYPE_ADHOC) |
| 311 | }, { |
| 312 | .max = MT7603_MAX_INTERFACES, |
| 313 | .types = BIT(NL80211_IFTYPE_STATION) | |
| 314 | #ifdef CONFIG_MAC80211_MESH |
| 315 | BIT(NL80211_IFTYPE_MESH_POINT) | |
| 316 | #endif |
| 317 | BIT(NL80211_IFTYPE_P2P_CLIENT) | |
| 318 | BIT(NL80211_IFTYPE_P2P_GO) | |
| 319 | BIT(NL80211_IFTYPE_AP) |
| 320 | }, |
| 321 | }; |
| 322 | |
| 323 | static const struct ieee80211_iface_combination if_comb[] = { |
| 324 | { |
| 325 | .limits = if_limits, |
| 326 | .n_limits = ARRAY_SIZE(if_limits), |
| 327 | .max_interfaces = 4, |
| 328 | .num_different_channels = 1, |
| 329 | .beacon_int_infra_match = true, |
| 330 | } |
| 331 | }; |
| 332 | |
| 333 | static void mt7603_led_set_config(struct mt76_dev *mt76, u8 delay_on, |
| 334 | u8 delay_off) |
| 335 | { |
| 336 | struct mt7603_dev *dev = container_of(mt76, struct mt7603_dev, |
| 337 | mt76); |
| 338 | u32 val, addr; |
| 339 | |
| 340 | val = FIELD_PREP(MT_LED_STATUS_DURATION, 0xffff) | |
| 341 | FIELD_PREP(MT_LED_STATUS_OFF, delay_off) | |
| 342 | FIELD_PREP(MT_LED_STATUS_ON, delay_on); |
| 343 | |
| 344 | addr = mt7603_reg_map(dev, MT_LED_STATUS_0(mt76->led_pin)); |
| 345 | mt76_wr(dev, addr, val); |
| 346 | addr = mt7603_reg_map(dev, MT_LED_STATUS_1(mt76->led_pin)); |
| 347 | mt76_wr(dev, addr, val); |
| 348 | |
| 349 | val = MT_LED_CTRL_REPLAY(mt76->led_pin) | |
| 350 | MT_LED_CTRL_KICK(mt76->led_pin); |
| 351 | if (mt76->led_al) |
| 352 | val |= MT_LED_CTRL_POLARITY(mt76->led_pin); |
| 353 | addr = mt7603_reg_map(dev, MT_LED_CTRL); |
| 354 | mt76_wr(dev, addr, val); |
| 355 | } |
| 356 | |
| 357 | static int mt7603_led_set_blink(struct led_classdev *led_cdev, |
| 358 | unsigned long *delay_on, |
| 359 | unsigned long *delay_off) |
| 360 | { |
| 361 | struct mt76_dev *mt76 = container_of(led_cdev, struct mt76_dev, |
| 362 | led_cdev); |
| 363 | u8 delta_on, delta_off; |
| 364 | |
| 365 | delta_off = max_t(u8, *delay_off / 10, 1); |
| 366 | delta_on = max_t(u8, *delay_on / 10, 1); |
| 367 | |
| 368 | mt7603_led_set_config(mt76, delta_on, delta_off); |
| 369 | return 0; |
| 370 | } |
| 371 | |
| 372 | static void mt7603_led_set_brightness(struct led_classdev *led_cdev, |
| 373 | enum led_brightness brightness) |
| 374 | { |
| 375 | struct mt76_dev *mt76 = container_of(led_cdev, struct mt76_dev, |
| 376 | led_cdev); |
| 377 | |
| 378 | if (!brightness) |
| 379 | mt7603_led_set_config(mt76, 0, 0xff); |
| 380 | else |
| 381 | mt7603_led_set_config(mt76, 0xff, 0); |
| 382 | } |
| 383 | |
| 384 | static u32 __mt7603_reg_addr(struct mt7603_dev *dev, u32 addr) |
| 385 | { |
| 386 | if (addr < 0x100000) |
| 387 | return addr; |
| 388 | |
| 389 | return mt7603_reg_map(dev, addr); |
| 390 | } |
| 391 | |
| 392 | static u32 mt7603_rr(struct mt76_dev *mdev, u32 offset) |
| 393 | { |
| 394 | struct mt7603_dev *dev = container_of(mdev, struct mt7603_dev, mt76); |
| 395 | u32 addr = __mt7603_reg_addr(dev, offset); |
| 396 | |
| 397 | return dev->bus_ops->rr(mdev, addr); |
| 398 | } |
| 399 | |
| 400 | static void mt7603_wr(struct mt76_dev *mdev, u32 offset, u32 val) |
| 401 | { |
| 402 | struct mt7603_dev *dev = container_of(mdev, struct mt7603_dev, mt76); |
| 403 | u32 addr = __mt7603_reg_addr(dev, offset); |
| 404 | |
| 405 | dev->bus_ops->wr(mdev, addr, val); |
| 406 | } |
| 407 | |
| 408 | static u32 mt7603_rmw(struct mt76_dev *mdev, u32 offset, u32 mask, u32 val) |
| 409 | { |
| 410 | struct mt7603_dev *dev = container_of(mdev, struct mt7603_dev, mt76); |
| 411 | u32 addr = __mt7603_reg_addr(dev, offset); |
| 412 | |
| 413 | return dev->bus_ops->rmw(mdev, addr, mask, val); |
| 414 | } |
| 415 | |
| 416 | static void |
| 417 | mt7603_regd_notifier(struct wiphy *wiphy, |
| 418 | struct regulatory_request *request) |
| 419 | { |
| 420 | struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy); |
| 421 | struct mt7603_dev *dev = hw->priv; |
| 422 | |
| 423 | dev->mt76.region = request->dfs_region; |
| 424 | dev->ed_monitor = dev->ed_monitor_enabled && |
| 425 | dev->mt76.region == NL80211_DFS_ETSI; |
| 426 | } |
| 427 | |
| 428 | static int |
| 429 | mt7603_txpower_signed(int val) |
| 430 | { |
| 431 | bool sign = val & BIT(6); |
| 432 | |
| 433 | if (!(val & BIT(7))) |
| 434 | return 0; |
| 435 | |
| 436 | val &= GENMASK(5, 0); |
| 437 | if (!sign) |
| 438 | val = -val; |
| 439 | |
| 440 | return val; |
| 441 | } |
| 442 | |
| 443 | static void |
| 444 | mt7603_init_txpower(struct mt7603_dev *dev, |
| 445 | struct ieee80211_supported_band *sband) |
| 446 | { |
| 447 | struct ieee80211_channel *chan; |
| 448 | u8 *eeprom = (u8 *)dev->mt76.eeprom.data; |
| 449 | int target_power = eeprom[MT_EE_TX_POWER_0_START_2G + 2] & ~BIT(7); |
| 450 | u8 *rate_power = &eeprom[MT_EE_TX_POWER_CCK]; |
| 451 | bool ext_pa = eeprom[MT_EE_NIC_CONF_0 + 1] & BIT(1); |
| 452 | int max_offset, cur_offset; |
| 453 | int i; |
| 454 | |
| 455 | if (ext_pa && is_mt7603(dev)) |
| 456 | target_power = eeprom[MT_EE_TX_POWER_TSSI_OFF] & ~BIT(7); |
| 457 | |
| 458 | if (target_power & BIT(6)) |
| 459 | target_power = -(target_power & GENMASK(5, 0)); |
| 460 | |
| 461 | max_offset = 0; |
| 462 | for (i = 0; i < 14; i++) { |
| 463 | cur_offset = mt7603_txpower_signed(rate_power[i]); |
| 464 | max_offset = max(max_offset, cur_offset); |
| 465 | } |
| 466 | |
| 467 | target_power += max_offset; |
| 468 | |
| 469 | dev->tx_power_limit = target_power; |
| 470 | dev->mphy.txpower_cur = target_power; |
| 471 | |
| 472 | target_power = DIV_ROUND_UP(target_power, 2); |
| 473 | |
| 474 | /* add 3 dBm for 2SS devices (combined output) */ |
| 475 | if (dev->mphy.antenna_mask & BIT(1)) |
| 476 | target_power += 3; |
| 477 | |
| 478 | for (i = 0; i < sband->n_channels; i++) { |
| 479 | chan = &sband->channels[i]; |
| 480 | chan->max_power = min_t(int, chan->max_reg_power, target_power); |
| 481 | chan->orig_mpwr = target_power; |
| 482 | } |
| 483 | } |
| 484 | |
| 485 | int mt7603_register_device(struct mt7603_dev *dev) |
| 486 | { |
| 487 | struct mt76_bus_ops *bus_ops; |
| 488 | struct ieee80211_hw *hw = mt76_hw(dev); |
| 489 | struct wiphy *wiphy = hw->wiphy; |
| 490 | int ret; |
| 491 | |
| 492 | dev->bus_ops = dev->mt76.bus; |
| 493 | bus_ops = devm_kmemdup(dev->mt76.dev, dev->bus_ops, sizeof(*bus_ops), |
| 494 | GFP_KERNEL); |
| 495 | if (!bus_ops) |
| 496 | return -ENOMEM; |
| 497 | |
| 498 | bus_ops->rr = mt7603_rr; |
| 499 | bus_ops->wr = mt7603_wr; |
| 500 | bus_ops->rmw = mt7603_rmw; |
| 501 | dev->mt76.bus = bus_ops; |
| 502 | |
| 503 | INIT_LIST_HEAD(&dev->sta_poll_list); |
| 504 | spin_lock_init(&dev->sta_poll_lock); |
| 505 | spin_lock_init(&dev->ps_lock); |
| 506 | |
| 507 | INIT_DELAYED_WORK(&dev->mphy.mac_work, mt7603_mac_work); |
| 508 | tasklet_setup(&dev->mt76.pre_tbtt_tasklet, mt7603_pre_tbtt_tasklet); |
| 509 | |
| 510 | dev->slottime = 9; |
| 511 | dev->sensitivity_limit = 28; |
| 512 | dev->dynamic_sensitivity = true; |
| 513 | |
| 514 | ret = mt7603_init_hardware(dev); |
| 515 | if (ret) |
| 516 | return ret; |
| 517 | |
| 518 | hw->queues = 4; |
| 519 | hw->max_rates = 3; |
| 520 | hw->max_report_rates = 7; |
| 521 | hw->max_rate_tries = 11; |
| 522 | |
| 523 | hw->radiotap_timestamp.units_pos = |
| 524 | IEEE80211_RADIOTAP_TIMESTAMP_UNIT_US; |
| 525 | |
| 526 | hw->sta_data_size = sizeof(struct mt7603_sta); |
| 527 | hw->vif_data_size = sizeof(struct mt7603_vif); |
| 528 | |
| 529 | wiphy->iface_combinations = if_comb; |
| 530 | wiphy->n_iface_combinations = ARRAY_SIZE(if_comb); |
| 531 | |
| 532 | ieee80211_hw_set(hw, TX_STATUS_NO_AMPDU_LEN); |
| 533 | ieee80211_hw_set(hw, HOST_BROADCAST_PS_BUFFERING); |
| 534 | ieee80211_hw_set(hw, NEEDS_UNIQUE_STA_ADDR); |
| 535 | |
| 536 | /* init led callbacks */ |
| 537 | if (IS_ENABLED(CONFIG_MT76_LEDS)) { |
| 538 | dev->mt76.led_cdev.brightness_set = mt7603_led_set_brightness; |
| 539 | dev->mt76.led_cdev.blink_set = mt7603_led_set_blink; |
| 540 | } |
| 541 | |
| 542 | wiphy->reg_notifier = mt7603_regd_notifier; |
| 543 | |
| 544 | ret = mt76_register_device(&dev->mt76, true, mt76_rates, |
| 545 | ARRAY_SIZE(mt76_rates)); |
| 546 | if (ret) |
| 547 | return ret; |
| 548 | |
| 549 | mt7603_init_debugfs(dev); |
| 550 | mt7603_init_txpower(dev, &dev->mphy.sband_2g.sband); |
| 551 | |
| 552 | return 0; |
| 553 | } |
| 554 | |
| 555 | void mt7603_unregister_device(struct mt7603_dev *dev) |
| 556 | { |
| 557 | tasklet_disable(&dev->mt76.pre_tbtt_tasklet); |
| 558 | mt76_unregister_device(&dev->mt76); |
| 559 | mt7603_mcu_exit(dev); |
| 560 | mt7603_dma_cleanup(dev); |
| 561 | mt76_free_device(&dev->mt76); |
| 562 | } |