developer | b11a539 | 2022-03-31 00:34:47 +0800 | [diff] [blame] | 1 | /* SPDX-License-Identifier: ISC */ |
| 2 | /* |
| 3 | * Copyright (C) 2016 Felix Fietkau <nbd@nbd.name> |
| 4 | */ |
| 5 | |
| 6 | #ifndef __MT76X02_REGS_H |
| 7 | #define __MT76X02_REGS_H |
| 8 | |
| 9 | #define MT_ASIC_VERSION 0x0000 |
| 10 | |
| 11 | #define MT76XX_REV_E3 0x22 |
| 12 | #define MT76XX_REV_E4 0x33 |
| 13 | |
| 14 | #define MT_CMB_CTRL 0x0020 |
| 15 | #define MT_CMB_CTRL_XTAL_RDY BIT(22) |
| 16 | #define MT_CMB_CTRL_PLL_LD BIT(23) |
| 17 | |
| 18 | #define MT_EFUSE_CTRL 0x0024 |
| 19 | #define MT_EFUSE_CTRL_AOUT GENMASK(5, 0) |
| 20 | #define MT_EFUSE_CTRL_MODE GENMASK(7, 6) |
| 21 | #define MT_EFUSE_CTRL_LDO_OFF_TIME GENMASK(13, 8) |
| 22 | #define MT_EFUSE_CTRL_LDO_ON_TIME GENMASK(15, 14) |
| 23 | #define MT_EFUSE_CTRL_AIN GENMASK(25, 16) |
| 24 | #define MT_EFUSE_CTRL_KICK BIT(30) |
| 25 | #define MT_EFUSE_CTRL_SEL BIT(31) |
| 26 | |
| 27 | #define MT_EFUSE_DATA_BASE 0x0028 |
| 28 | #define MT_EFUSE_DATA(_n) (MT_EFUSE_DATA_BASE + ((_n) << 2)) |
| 29 | |
| 30 | #define MT_COEXCFG0 0x0040 |
| 31 | #define MT_COEXCFG0_COEX_EN BIT(0) |
| 32 | |
| 33 | #define MT_WLAN_FUN_CTRL 0x0080 |
| 34 | #define MT_WLAN_FUN_CTRL_WLAN_EN BIT(0) |
| 35 | #define MT_WLAN_FUN_CTRL_WLAN_CLK_EN BIT(1) |
| 36 | #define MT_WLAN_FUN_CTRL_WLAN_RESET_RF BIT(2) |
| 37 | |
| 38 | #define MT_COEXCFG3 0x004c |
| 39 | |
| 40 | #define MT_LDO_CTRL_0 0x006c |
| 41 | #define MT_LDO_CTRL_1 0x0070 |
| 42 | |
| 43 | #define MT_WLAN_FUN_CTRL_WLAN_RESET BIT(3) /* MT76x0 */ |
| 44 | #define MT_WLAN_FUN_CTRL_CSR_F20M_CKEN BIT(3) /* MT76x2 */ |
| 45 | |
| 46 | #define MT_WLAN_FUN_CTRL_PCIE_CLK_REQ BIT(4) |
| 47 | #define MT_WLAN_FUN_CTRL_FRC_WL_ANT_SEL BIT(5) |
| 48 | #define MT_WLAN_FUN_CTRL_INV_ANT_SEL BIT(6) |
| 49 | #define MT_WLAN_FUN_CTRL_WAKE_HOST BIT(7) |
| 50 | |
| 51 | #define MT_WLAN_FUN_CTRL_THERM_RST BIT(8) /* MT76x2 */ |
| 52 | #define MT_WLAN_FUN_CTRL_THERM_CKEN BIT(9) /* MT76x2 */ |
| 53 | |
| 54 | #define MT_WLAN_FUN_CTRL_GPIO_IN GENMASK(15, 8) /* MT76x0 */ |
| 55 | #define MT_WLAN_FUN_CTRL_GPIO_OUT GENMASK(23, 16) /* MT76x0 */ |
| 56 | #define MT_WLAN_FUN_CTRL_GPIO_OUT_EN GENMASK(31, 24) /* MT76x0 */ |
| 57 | |
| 58 | /* MT76x0 */ |
| 59 | #define MT_CSR_EE_CFG1 0x0104 |
| 60 | |
| 61 | #define MT_XO_CTRL0 0x0100 |
| 62 | #define MT_XO_CTRL1 0x0104 |
| 63 | #define MT_XO_CTRL2 0x0108 |
| 64 | #define MT_XO_CTRL3 0x010c |
| 65 | #define MT_XO_CTRL4 0x0110 |
| 66 | |
| 67 | #define MT_XO_CTRL5 0x0114 |
| 68 | #define MT_XO_CTRL5_C2_VAL GENMASK(14, 8) |
| 69 | |
| 70 | #define MT_XO_CTRL6 0x0118 |
| 71 | #define MT_XO_CTRL6_C2_CTRL GENMASK(14, 8) |
| 72 | |
| 73 | #define MT_XO_CTRL7 0x011c |
| 74 | |
| 75 | #define MT_IOCFG_6 0x0124 |
| 76 | |
| 77 | #define MT_USB_U3DMA_CFG 0x9018 |
| 78 | #define MT_USB_DMA_CFG_RX_BULK_AGG_TOUT GENMASK(7, 0) |
| 79 | #define MT_USB_DMA_CFG_RX_BULK_AGG_LMT GENMASK(15, 8) |
| 80 | #define MT_USB_DMA_CFG_UDMA_TX_WL_DROP BIT(16) |
| 81 | #define MT_USB_DMA_CFG_WAKE_UP_EN BIT(17) |
| 82 | #define MT_USB_DMA_CFG_RX_DROP_OR_PAD BIT(18) |
| 83 | #define MT_USB_DMA_CFG_TX_CLR BIT(19) |
| 84 | #define MT_USB_DMA_CFG_TXOP_HALT BIT(20) |
| 85 | #define MT_USB_DMA_CFG_RX_BULK_AGG_EN BIT(21) |
| 86 | #define MT_USB_DMA_CFG_RX_BULK_EN BIT(22) |
| 87 | #define MT_USB_DMA_CFG_TX_BULK_EN BIT(23) |
| 88 | #define MT_USB_DMA_CFG_EP_OUT_VALID GENMASK(29, 24) |
| 89 | #define MT_USB_DMA_CFG_RX_BUSY BIT(30) |
| 90 | #define MT_USB_DMA_CFG_TX_BUSY BIT(31) |
| 91 | |
| 92 | #define MT_WLAN_MTC_CTRL 0x10148 |
| 93 | #define MT_WLAN_MTC_CTRL_MTCMOS_PWR_UP BIT(0) |
| 94 | #define MT_WLAN_MTC_CTRL_PWR_ACK BIT(12) |
| 95 | #define MT_WLAN_MTC_CTRL_PWR_ACK_S BIT(13) |
| 96 | #define MT_WLAN_MTC_CTRL_BBP_MEM_PD GENMASK(19, 16) |
| 97 | #define MT_WLAN_MTC_CTRL_PBF_MEM_PD BIT(20) |
| 98 | #define MT_WLAN_MTC_CTRL_FCE_MEM_PD BIT(21) |
| 99 | #define MT_WLAN_MTC_CTRL_TSO_MEM_PD BIT(22) |
| 100 | #define MT_WLAN_MTC_CTRL_BBP_MEM_RB BIT(24) |
| 101 | #define MT_WLAN_MTC_CTRL_PBF_MEM_RB BIT(25) |
| 102 | #define MT_WLAN_MTC_CTRL_FCE_MEM_RB BIT(26) |
| 103 | #define MT_WLAN_MTC_CTRL_TSO_MEM_RB BIT(27) |
| 104 | #define MT_WLAN_MTC_CTRL_STATE_UP BIT(28) |
| 105 | |
| 106 | #define MT_INT_SOURCE_CSR 0x0200 |
| 107 | #define MT_INT_MASK_CSR 0x0204 |
| 108 | |
| 109 | #define MT_INT_RX_DONE(_n) BIT(_n) |
| 110 | #define MT_INT_RX_DONE_ALL GENMASK(1, 0) |
| 111 | #define MT_INT_TX_DONE_ALL GENMASK(13, 4) |
| 112 | #define MT_INT_TX_DONE(_n) BIT((_n) + 4) |
| 113 | #define MT_INT_RX_COHERENT BIT(16) |
| 114 | #define MT_INT_TX_COHERENT BIT(17) |
| 115 | #define MT_INT_ANY_COHERENT BIT(18) |
| 116 | #define MT_INT_MCU_CMD BIT(19) |
| 117 | #define MT_INT_TBTT BIT(20) |
| 118 | #define MT_INT_PRE_TBTT BIT(21) |
| 119 | #define MT_INT_TX_STAT BIT(22) |
| 120 | #define MT_INT_AUTO_WAKEUP BIT(23) |
| 121 | #define MT_INT_GPTIMER BIT(24) |
| 122 | #define MT_INT_RXDELAYINT BIT(26) |
| 123 | #define MT_INT_TXDELAYINT BIT(27) |
| 124 | |
| 125 | #define MT_WPDMA_GLO_CFG 0x0208 |
| 126 | #define MT_WPDMA_GLO_CFG_TX_DMA_EN BIT(0) |
| 127 | #define MT_WPDMA_GLO_CFG_TX_DMA_BUSY BIT(1) |
| 128 | #define MT_WPDMA_GLO_CFG_RX_DMA_EN BIT(2) |
| 129 | #define MT_WPDMA_GLO_CFG_RX_DMA_BUSY BIT(3) |
| 130 | #define MT_WPDMA_GLO_CFG_DMA_BURST_SIZE GENMASK(5, 4) |
| 131 | #define MT_WPDMA_GLO_CFG_TX_WRITEBACK_DONE BIT(6) |
| 132 | #define MT_WPDMA_GLO_CFG_BIG_ENDIAN BIT(7) |
| 133 | #define MT_WPDMA_GLO_CFG_HDR_SEG_LEN GENMASK(15, 8) |
| 134 | #define MT_WPDMA_GLO_CFG_CLK_GATE_DIS BIT(30) |
| 135 | #define MT_WPDMA_GLO_CFG_RX_2B_OFFSET BIT(31) |
| 136 | |
| 137 | #define MT_WPDMA_RST_IDX 0x020c |
| 138 | |
| 139 | #define MT_WPDMA_DELAY_INT_CFG 0x0210 |
| 140 | |
| 141 | #define MT_WMM_AIFSN 0x0214 |
| 142 | #define MT_WMM_AIFSN_MASK GENMASK(3, 0) |
| 143 | #define MT_WMM_AIFSN_SHIFT(_n) ((_n) * 4) |
| 144 | |
| 145 | #define MT_WMM_CWMIN 0x0218 |
| 146 | #define MT_WMM_CWMIN_MASK GENMASK(3, 0) |
| 147 | #define MT_WMM_CWMIN_SHIFT(_n) ((_n) * 4) |
| 148 | |
| 149 | #define MT_WMM_CWMAX 0x021c |
| 150 | #define MT_WMM_CWMAX_MASK GENMASK(3, 0) |
| 151 | #define MT_WMM_CWMAX_SHIFT(_n) ((_n) * 4) |
| 152 | |
| 153 | #define MT_WMM_TXOP_BASE 0x0220 |
| 154 | #define MT_WMM_TXOP(_n) (MT_WMM_TXOP_BASE + (((_n) / 2) << 2)) |
| 155 | #define MT_WMM_TXOP_SHIFT(_n) (((_n) & 1) * 16) |
| 156 | #define MT_WMM_TXOP_MASK GENMASK(15, 0) |
| 157 | |
| 158 | #define MT_WMM_CTRL 0x0230 /* MT76x0 */ |
| 159 | #define MT_FCE_DMA_ADDR 0x0230 |
| 160 | #define MT_FCE_DMA_LEN 0x0234 |
| 161 | #define MT_USB_DMA_CFG 0x0238 |
| 162 | |
| 163 | #define MT_TSO_CTRL 0x0250 |
| 164 | #define MT_HEADER_TRANS_CTRL_REG 0x0260 |
| 165 | |
| 166 | #define MT_US_CYC_CFG 0x02a4 |
| 167 | #define MT_US_CYC_CNT GENMASK(7, 0) |
| 168 | |
| 169 | #define MT_TX_RING_BASE 0x0300 |
| 170 | #define MT_RX_RING_BASE 0x03c0 |
| 171 | |
| 172 | #define MT_TX_HW_QUEUE_MCU 8 |
| 173 | #define MT_TX_HW_QUEUE_MGMT 9 |
| 174 | |
| 175 | #define MT_PBF_SYS_CTRL 0x0400 |
| 176 | #define MT_PBF_SYS_CTRL_MCU_RESET BIT(0) |
| 177 | #define MT_PBF_SYS_CTRL_DMA_RESET BIT(1) |
| 178 | #define MT_PBF_SYS_CTRL_MAC_RESET BIT(2) |
| 179 | #define MT_PBF_SYS_CTRL_PBF_RESET BIT(3) |
| 180 | #define MT_PBF_SYS_CTRL_ASY_RESET BIT(4) |
| 181 | |
| 182 | #define MT_PBF_CFG 0x0404 |
| 183 | #define MT_PBF_CFG_TX0Q_EN BIT(0) |
| 184 | #define MT_PBF_CFG_TX1Q_EN BIT(1) |
| 185 | #define MT_PBF_CFG_TX2Q_EN BIT(2) |
| 186 | #define MT_PBF_CFG_TX3Q_EN BIT(3) |
| 187 | #define MT_PBF_CFG_RX0Q_EN BIT(4) |
| 188 | #define MT_PBF_CFG_RX_DROP_EN BIT(8) |
| 189 | |
| 190 | #define MT_PBF_TX_MAX_PCNT 0x0408 |
| 191 | #define MT_PBF_RX_MAX_PCNT 0x040c |
| 192 | |
| 193 | #define MT_BCN_OFFSET_BASE 0x041c |
| 194 | #define MT_BCN_OFFSET(_n) (MT_BCN_OFFSET_BASE + ((_n) << 2)) |
| 195 | |
| 196 | #define MT_RXQ_STA 0x0430 |
| 197 | #define MT_TXQ_STA 0x0434 |
| 198 | #define MT_RF_CSR_CFG 0x0500 |
| 199 | #define MT_RF_CSR_CFG_DATA GENMASK(7, 0) |
| 200 | #define MT_RF_CSR_CFG_REG_ID GENMASK(14, 8) |
| 201 | #define MT_RF_CSR_CFG_REG_BANK GENMASK(17, 15) |
| 202 | #define MT_RF_CSR_CFG_WR BIT(30) |
| 203 | #define MT_RF_CSR_CFG_KICK BIT(31) |
| 204 | |
| 205 | #define MT_RF_BYPASS_0 0x0504 |
| 206 | #define MT_RF_BYPASS_1 0x0508 |
| 207 | #define MT_RF_SETTING_0 0x050c |
| 208 | |
| 209 | #define MT_RF_MISC 0x0518 |
| 210 | #define MT_RF_DATA_WRITE 0x0524 |
| 211 | |
| 212 | #define MT_RF_CTRL 0x0528 |
| 213 | #define MT_RF_CTRL_ADDR GENMASK(11, 0) |
| 214 | #define MT_RF_CTRL_WRITE BIT(12) |
| 215 | #define MT_RF_CTRL_BUSY BIT(13) |
| 216 | #define MT_RF_CTRL_IDX BIT(16) |
| 217 | |
| 218 | #define MT_RF_DATA_READ 0x052c |
| 219 | |
| 220 | #define MT_COM_REG0 0x0730 |
| 221 | #define MT_COM_REG1 0x0734 |
| 222 | #define MT_COM_REG2 0x0738 |
| 223 | #define MT_COM_REG3 0x073C |
| 224 | |
| 225 | #define MT_LED_CTRL 0x0770 |
| 226 | #define MT_LED_CTRL_REPLAY(_n) BIT(0 + (8 * (_n))) |
| 227 | #define MT_LED_CTRL_POLARITY(_n) BIT(1 + (8 * (_n))) |
| 228 | #define MT_LED_CTRL_TX_BLINK_MODE(_n) BIT(2 + (8 * (_n))) |
| 229 | #define MT_LED_CTRL_KICK(_n) BIT(7 + (8 * (_n))) |
| 230 | |
| 231 | #define MT_LED_TX_BLINK_0 0x0774 |
| 232 | #define MT_LED_TX_BLINK_1 0x0778 |
| 233 | |
| 234 | #define MT_LED_S0_BASE 0x077C |
| 235 | #define MT_LED_S0(_n) (MT_LED_S0_BASE + 8 * (_n)) |
| 236 | #define MT_LED_S1_BASE 0x0780 |
| 237 | #define MT_LED_S1(_n) (MT_LED_S1_BASE + 8 * (_n)) |
| 238 | #define MT_LED_STATUS_OFF GENMASK(31, 24) |
| 239 | #define MT_LED_STATUS_ON GENMASK(23, 16) |
| 240 | #define MT_LED_STATUS_DURATION GENMASK(15, 8) |
| 241 | |
| 242 | #define MT_FCE_PSE_CTRL 0x0800 |
| 243 | #define MT_FCE_PARAMETERS 0x0804 |
| 244 | #define MT_FCE_CSO 0x0808 |
| 245 | |
| 246 | #define MT_FCE_L2_STUFF 0x080c |
| 247 | #define MT_FCE_L2_STUFF_HT_L2_EN BIT(0) |
| 248 | #define MT_FCE_L2_STUFF_QOS_L2_EN BIT(1) |
| 249 | #define MT_FCE_L2_STUFF_RX_STUFF_EN BIT(2) |
| 250 | #define MT_FCE_L2_STUFF_TX_STUFF_EN BIT(3) |
| 251 | #define MT_FCE_L2_STUFF_WR_MPDU_LEN_EN BIT(4) |
| 252 | #define MT_FCE_L2_STUFF_MVINV_BSWAP BIT(5) |
| 253 | #define MT_FCE_L2_STUFF_TS_CMD_QSEL_EN GENMASK(15, 8) |
| 254 | #define MT_FCE_L2_STUFF_TS_LEN_EN GENMASK(23, 16) |
| 255 | #define MT_FCE_L2_STUFF_OTHER_PORT GENMASK(25, 24) |
| 256 | |
| 257 | #define MT_FCE_WLAN_FLOW_CONTROL1 0x0824 |
| 258 | |
| 259 | #define MT_TX_CPU_FROM_FCE_BASE_PTR 0x09a0 |
| 260 | #define MT_TX_CPU_FROM_FCE_MAX_COUNT 0x09a4 |
| 261 | #define MT_TX_CPU_FROM_FCE_CPU_DESC_IDX 0x09a8 |
| 262 | #define MT_FCE_PDMA_GLOBAL_CONF 0x09c4 |
| 263 | #define MT_FCE_SKIP_FS 0x0a6c |
| 264 | |
| 265 | #define MT_PAUSE_ENABLE_CONTROL1 0x0a38 |
| 266 | |
| 267 | #define MT_MAC_CSR0 0x1000 |
| 268 | |
| 269 | #define MT_MAC_SYS_CTRL 0x1004 |
| 270 | #define MT_MAC_SYS_CTRL_RESET_CSR BIT(0) |
| 271 | #define MT_MAC_SYS_CTRL_RESET_BBP BIT(1) |
| 272 | #define MT_MAC_SYS_CTRL_ENABLE_TX BIT(2) |
| 273 | #define MT_MAC_SYS_CTRL_ENABLE_RX BIT(3) |
| 274 | |
| 275 | #define MT_MAC_ADDR_DW0 0x1008 |
| 276 | #define MT_MAC_ADDR_DW1 0x100c |
| 277 | #define MT_MAC_ADDR_DW1_U2ME_MASK GENMASK(23, 16) |
| 278 | |
| 279 | #define MT_MAC_BSSID_DW0 0x1010 |
| 280 | #define MT_MAC_BSSID_DW1 0x1014 |
| 281 | #define MT_MAC_BSSID_DW1_ADDR GENMASK(15, 0) |
| 282 | #define MT_MAC_BSSID_DW1_MBSS_MODE GENMASK(17, 16) |
| 283 | #define MT_MAC_BSSID_DW1_MBEACON_N GENMASK(20, 18) |
| 284 | #define MT_MAC_BSSID_DW1_MBSS_LOCAL_BIT BIT(21) |
| 285 | #define MT_MAC_BSSID_DW1_MBSS_MODE_B2 BIT(22) |
| 286 | #define MT_MAC_BSSID_DW1_MBEACON_N_B3 BIT(23) |
| 287 | #define MT_MAC_BSSID_DW1_MBSS_IDX_BYTE GENMASK(26, 24) |
| 288 | |
| 289 | #define MT_MAX_LEN_CFG 0x1018 |
| 290 | #define MT_MAX_LEN_CFG_AMPDU GENMASK(13, 12) |
| 291 | |
| 292 | #define MT_LED_CFG 0x102c |
| 293 | |
| 294 | #define MT_AMPDU_MAX_LEN_20M1S 0x1030 |
| 295 | #define MT_AMPDU_MAX_LEN_20M2S 0x1034 |
| 296 | #define MT_AMPDU_MAX_LEN_40M1S 0x1038 |
| 297 | #define MT_AMPDU_MAX_LEN_40M2S 0x103c |
| 298 | #define MT_AMPDU_MAX_LEN 0x1040 |
| 299 | |
| 300 | #define MT_WCID_DROP_BASE 0x106c |
| 301 | #define MT_WCID_DROP(_n) (MT_WCID_DROP_BASE + ((_n) >> 5) * 4) |
| 302 | #define MT_WCID_DROP_MASK(_n) BIT((_n) % 32) |
| 303 | |
| 304 | #define MT_BCN_BYPASS_MASK 0x108c |
| 305 | |
| 306 | #define MT_MAC_APC_BSSID_BASE 0x1090 |
| 307 | #define MT_MAC_APC_BSSID_L(_n) (MT_MAC_APC_BSSID_BASE + ((_n) * 8)) |
| 308 | #define MT_MAC_APC_BSSID_H(_n) (MT_MAC_APC_BSSID_BASE + ((_n) * 8 + 4)) |
| 309 | #define MT_MAC_APC_BSSID_H_ADDR GENMASK(15, 0) |
| 310 | #define MT_MAC_APC_BSSID0_H_EN BIT(16) |
| 311 | |
| 312 | #define MT_XIFS_TIME_CFG 0x1100 |
| 313 | #define MT_XIFS_TIME_CFG_CCK_SIFS GENMASK(7, 0) |
| 314 | #define MT_XIFS_TIME_CFG_OFDM_SIFS GENMASK(15, 8) |
| 315 | #define MT_XIFS_TIME_CFG_OFDM_XIFS GENMASK(19, 16) |
| 316 | #define MT_XIFS_TIME_CFG_EIFS GENMASK(28, 20) |
| 317 | #define MT_XIFS_TIME_CFG_BB_RXEND_EN BIT(29) |
| 318 | |
| 319 | #define MT_BKOFF_SLOT_CFG 0x1104 |
| 320 | #define MT_BKOFF_SLOT_CFG_SLOTTIME GENMASK(7, 0) |
| 321 | #define MT_BKOFF_SLOT_CFG_CC_DELAY GENMASK(11, 8) |
| 322 | |
| 323 | #define MT_CH_TIME_CFG 0x110c |
| 324 | #define MT_CH_TIME_CFG_TIMER_EN BIT(0) |
| 325 | #define MT_CH_TIME_CFG_TX_AS_BUSY BIT(1) |
| 326 | #define MT_CH_TIME_CFG_RX_AS_BUSY BIT(2) |
| 327 | #define MT_CH_TIME_CFG_NAV_AS_BUSY BIT(3) |
| 328 | #define MT_CH_TIME_CFG_EIFS_AS_BUSY BIT(4) |
| 329 | #define MT_CH_TIME_CFG_MDRDY_CNT_EN BIT(5) |
| 330 | #define MT_CH_CCA_RC_EN BIT(6) |
| 331 | #define MT_CH_TIME_CFG_CH_TIMER_CLR GENMASK(9, 8) |
| 332 | #define MT_CH_TIME_CFG_MDRDY_CLR GENMASK(11, 10) |
| 333 | |
| 334 | #define MT_PBF_LIFE_TIMER 0x1110 |
| 335 | |
| 336 | #define MT_BEACON_TIME_CFG 0x1114 |
| 337 | #define MT_BEACON_TIME_CFG_INTVAL GENMASK(15, 0) |
| 338 | #define MT_BEACON_TIME_CFG_TIMER_EN BIT(16) |
| 339 | #define MT_BEACON_TIME_CFG_SYNC_MODE GENMASK(18, 17) |
| 340 | #define MT_BEACON_TIME_CFG_TBTT_EN BIT(19) |
| 341 | #define MT_BEACON_TIME_CFG_BEACON_TX BIT(20) |
| 342 | #define MT_BEACON_TIME_CFG_TSF_COMP GENMASK(31, 24) |
| 343 | |
| 344 | #define MT_TBTT_SYNC_CFG 0x1118 |
| 345 | #define MT_TSF_TIMER_DW0 0x111c |
| 346 | #define MT_TSF_TIMER_DW1 0x1120 |
| 347 | #define MT_TBTT_TIMER 0x1124 |
| 348 | #define MT_TBTT_TIMER_VAL GENMASK(16, 0) |
| 349 | |
| 350 | #define MT_INT_TIMER_CFG 0x1128 |
| 351 | #define MT_INT_TIMER_CFG_PRE_TBTT GENMASK(15, 0) |
| 352 | #define MT_INT_TIMER_CFG_GP_TIMER GENMASK(31, 16) |
| 353 | |
| 354 | #define MT_INT_TIMER_EN 0x112c |
| 355 | #define MT_INT_TIMER_EN_PRE_TBTT_EN BIT(0) |
| 356 | #define MT_INT_TIMER_EN_GP_TIMER_EN BIT(1) |
| 357 | |
| 358 | #define MT_CH_IDLE 0x1130 |
| 359 | #define MT_CH_BUSY 0x1134 |
| 360 | #define MT_EXT_CH_BUSY 0x1138 |
| 361 | #define MT_ED_CCA_TIMER 0x1140 |
| 362 | |
| 363 | #define MT_MAC_STATUS 0x1200 |
| 364 | #define MT_MAC_STATUS_TX BIT(0) |
| 365 | #define MT_MAC_STATUS_RX BIT(1) |
| 366 | |
| 367 | #define MT_PWR_PIN_CFG 0x1204 |
| 368 | #define MT_AUX_CLK_CFG 0x120c |
| 369 | |
| 370 | #define MT_BB_PA_MODE_CFG0 0x1214 |
| 371 | #define MT_BB_PA_MODE_CFG1 0x1218 |
| 372 | #define MT_RF_PA_MODE_CFG0 0x121c |
| 373 | #define MT_RF_PA_MODE_CFG1 0x1220 |
| 374 | |
| 375 | #define MT_RF_PA_MODE_ADJ0 0x1228 |
| 376 | #define MT_RF_PA_MODE_ADJ1 0x122c |
| 377 | |
| 378 | #define MT_DACCLK_EN_DLY_CFG 0x1264 |
| 379 | |
| 380 | #define MT_EDCA_CFG_BASE 0x1300 |
| 381 | #define MT_EDCA_CFG_AC(_n) (MT_EDCA_CFG_BASE + ((_n) << 2)) |
| 382 | #define MT_EDCA_CFG_TXOP GENMASK(7, 0) |
| 383 | #define MT_EDCA_CFG_AIFSN GENMASK(11, 8) |
| 384 | #define MT_EDCA_CFG_CWMIN GENMASK(15, 12) |
| 385 | #define MT_EDCA_CFG_CWMAX GENMASK(19, 16) |
| 386 | |
| 387 | #define MT_TX_PWR_CFG_0 0x1314 |
| 388 | #define MT_TX_PWR_CFG_1 0x1318 |
| 389 | #define MT_TX_PWR_CFG_2 0x131c |
| 390 | #define MT_TX_PWR_CFG_3 0x1320 |
| 391 | #define MT_TX_PWR_CFG_4 0x1324 |
| 392 | #define MT_TX_PIN_CFG 0x1328 |
| 393 | #define MT_TX_PIN_CFG_TXANT GENMASK(3, 0) |
| 394 | #define MT_TX_PIN_CFG_RXANT GENMASK(11, 8) |
| 395 | #define MT_TX_PIN_RFTR_EN BIT(16) |
| 396 | #define MT_TX_PIN_TRSW_EN BIT(18) |
| 397 | |
| 398 | #define MT_TX_BAND_CFG 0x132c |
| 399 | #define MT_TX_BAND_CFG_UPPER_40M BIT(0) |
| 400 | #define MT_TX_BAND_CFG_5G BIT(1) |
| 401 | #define MT_TX_BAND_CFG_2G BIT(2) |
| 402 | |
| 403 | #define MT_HT_FBK_TO_LEGACY 0x1384 |
| 404 | #define MT_TX_MPDU_ADJ_INT 0x1388 |
| 405 | |
| 406 | #define MT_TX_PWR_CFG_7 0x13d4 |
| 407 | #define MT_TX_PWR_CFG_8 0x13d8 |
| 408 | #define MT_TX_PWR_CFG_9 0x13dc |
| 409 | |
| 410 | #define MT_TX_SW_CFG0 0x1330 |
| 411 | #define MT_TX_SW_CFG1 0x1334 |
| 412 | #define MT_TX_SW_CFG2 0x1338 |
| 413 | |
| 414 | #define MT_TXOP_CTRL_CFG 0x1340 |
| 415 | #define MT_TXOP_TRUN_EN GENMASK(5, 0) |
| 416 | #define MT_TXOP_EXT_CCA_DLY GENMASK(15, 8) |
| 417 | #define MT_TXOP_ED_CCA_EN BIT(20) |
| 418 | |
| 419 | #define MT_TX_RTS_CFG 0x1344 |
| 420 | #define MT_TX_RTS_CFG_RETRY_LIMIT GENMASK(7, 0) |
| 421 | #define MT_TX_RTS_CFG_THRESH GENMASK(23, 8) |
| 422 | #define MT_TX_RTS_FALLBACK BIT(24) |
| 423 | |
| 424 | #define MT_TX_TIMEOUT_CFG 0x1348 |
| 425 | #define MT_TX_TIMEOUT_CFG_ACKTO GENMASK(15, 8) |
| 426 | |
| 427 | #define MT_TX_RETRY_CFG 0x134c |
| 428 | #define MT_TX_LINK_CFG 0x1350 |
| 429 | #define MT_TX_CFACK_EN BIT(12) |
| 430 | #define MT_VHT_HT_FBK_CFG0 0x1354 |
| 431 | #define MT_VHT_HT_FBK_CFG1 0x1358 |
| 432 | #define MT_LG_FBK_CFG0 0x135c |
| 433 | #define MT_LG_FBK_CFG1 0x1360 |
| 434 | |
| 435 | #define MT_PROT_CFG_RATE GENMASK(15, 0) |
| 436 | #define MT_PROT_CFG_CTRL GENMASK(17, 16) |
| 437 | #define MT_PROT_CFG_NAV GENMASK(19, 18) |
| 438 | #define MT_PROT_CFG_TXOP_ALLOW GENMASK(25, 20) |
| 439 | #define MT_PROT_CFG_RTS_THRESH BIT(26) |
| 440 | |
| 441 | #define MT_CCK_PROT_CFG 0x1364 |
| 442 | #define MT_OFDM_PROT_CFG 0x1368 |
| 443 | #define MT_MM20_PROT_CFG 0x136c |
| 444 | #define MT_MM40_PROT_CFG 0x1370 |
| 445 | #define MT_GF20_PROT_CFG 0x1374 |
| 446 | #define MT_GF40_PROT_CFG 0x1378 |
| 447 | |
| 448 | #define MT_PROT_RATE GENMASK(15, 0) |
| 449 | #define MT_PROT_CTRL_RTS_CTS BIT(16) |
| 450 | #define MT_PROT_CTRL_CTS2SELF BIT(17) |
| 451 | #define MT_PROT_NAV_SHORT BIT(18) |
| 452 | #define MT_PROT_NAV_LONG BIT(19) |
| 453 | #define MT_PROT_TXOP_ALLOW_CCK BIT(20) |
| 454 | #define MT_PROT_TXOP_ALLOW_OFDM BIT(21) |
| 455 | #define MT_PROT_TXOP_ALLOW_MM20 BIT(22) |
| 456 | #define MT_PROT_TXOP_ALLOW_MM40 BIT(23) |
| 457 | #define MT_PROT_TXOP_ALLOW_GF20 BIT(24) |
| 458 | #define MT_PROT_TXOP_ALLOW_GF40 BIT(25) |
| 459 | #define MT_PROT_RTS_THR_EN BIT(26) |
| 460 | #define MT_PROT_RATE_CCK_11 0x0003 |
| 461 | #define MT_PROT_RATE_OFDM_6 0x2000 |
| 462 | #define MT_PROT_RATE_OFDM_24 0x2004 |
| 463 | #define MT_PROT_RATE_DUP_OFDM_24 0x2084 |
| 464 | #define MT_PROT_RATE_SGI_OFDM_24 0x2104 |
| 465 | #define MT_PROT_TXOP_ALLOW_ALL GENMASK(25, 20) |
| 466 | #define MT_PROT_TXOP_ALLOW_BW20 (MT_PROT_TXOP_ALLOW_ALL & \ |
| 467 | ~MT_PROT_TXOP_ALLOW_MM40 & \ |
| 468 | ~MT_PROT_TXOP_ALLOW_GF40) |
| 469 | |
| 470 | #define MT_EXP_ACK_TIME 0x1380 |
| 471 | |
| 472 | #define MT_TX_PWR_CFG_0_EXT 0x1390 |
| 473 | #define MT_TX_PWR_CFG_1_EXT 0x1394 |
| 474 | |
| 475 | #define MT_TX_FBK_LIMIT 0x1398 |
| 476 | #define MT_TX_FBK_LIMIT_MPDU_FBK GENMASK(7, 0) |
| 477 | #define MT_TX_FBK_LIMIT_AMPDU_FBK GENMASK(15, 8) |
| 478 | #define MT_TX_FBK_LIMIT_MPDU_UP_CLEAR BIT(16) |
| 479 | #define MT_TX_FBK_LIMIT_AMPDU_UP_CLEAR BIT(17) |
| 480 | #define MT_TX_FBK_LIMIT_RATE_LUT BIT(18) |
| 481 | |
| 482 | #define MT_TX0_RF_GAIN_CORR 0x13a0 |
| 483 | #define MT_TX1_RF_GAIN_CORR 0x13a4 |
| 484 | #define MT_TX0_RF_GAIN_ATTEN 0x13a8 |
| 485 | #define MT_TX0_RF_GAIN_ATTEN 0x13a8 /* MT76x0 */ |
| 486 | |
| 487 | #define MT_TX_ALC_CFG_0 0x13b0 |
| 488 | #define MT_TX_ALC_CFG_0_CH_INIT_0 GENMASK(5, 0) |
| 489 | #define MT_TX_ALC_CFG_0_CH_INIT_1 GENMASK(13, 8) |
| 490 | #define MT_TX_ALC_CFG_0_LIMIT_0 GENMASK(21, 16) |
| 491 | #define MT_TX_ALC_CFG_0_LIMIT_1 GENMASK(29, 24) |
| 492 | |
| 493 | #define MT_TX_ALC_CFG_1 0x13b4 |
| 494 | #define MT_TX_ALC_CFG_1_TEMP_COMP GENMASK(5, 0) |
| 495 | |
| 496 | #define MT_TX_ALC_CFG_2 0x13a8 |
| 497 | #define MT_TX_ALC_CFG_2_TEMP_COMP GENMASK(5, 0) |
| 498 | |
| 499 | #define MT_TX_ALC_CFG_3 0x13ac |
| 500 | #define MT_TX_ALC_CFG_4 0x13c0 |
| 501 | #define MT_TX_ALC_CFG_4_LOWGAIN_CH_EN BIT(31) |
| 502 | #define MT_TX0_BB_GAIN_ATTEN 0x13c0 /* MT76x0 */ |
| 503 | |
| 504 | #define MT_TX_ALC_VGA3 0x13c8 |
| 505 | |
| 506 | #define MT_TX_PROT_CFG6 0x13e0 |
| 507 | #define MT_TX_PROT_CFG7 0x13e4 |
| 508 | #define MT_TX_PROT_CFG8 0x13e8 |
| 509 | |
| 510 | #define MT_PIFS_TX_CFG 0x13ec |
| 511 | |
| 512 | #define MT_RX_FILTR_CFG 0x1400 |
| 513 | |
| 514 | #define MT_RX_FILTR_CFG_CRC_ERR BIT(0) |
| 515 | #define MT_RX_FILTR_CFG_PHY_ERR BIT(1) |
| 516 | #define MT_RX_FILTR_CFG_PROMISC BIT(2) |
| 517 | #define MT_RX_FILTR_CFG_OTHER_BSS BIT(3) |
| 518 | #define MT_RX_FILTR_CFG_VER_ERR BIT(4) |
| 519 | #define MT_RX_FILTR_CFG_MCAST BIT(5) |
| 520 | #define MT_RX_FILTR_CFG_BCAST BIT(6) |
| 521 | #define MT_RX_FILTR_CFG_DUP BIT(7) |
| 522 | #define MT_RX_FILTR_CFG_CFACK BIT(8) |
| 523 | #define MT_RX_FILTR_CFG_CFEND BIT(9) |
| 524 | #define MT_RX_FILTR_CFG_ACK BIT(10) |
| 525 | #define MT_RX_FILTR_CFG_CTS BIT(11) |
| 526 | #define MT_RX_FILTR_CFG_RTS BIT(12) |
| 527 | #define MT_RX_FILTR_CFG_PSPOLL BIT(13) |
| 528 | #define MT_RX_FILTR_CFG_BA BIT(14) |
| 529 | #define MT_RX_FILTR_CFG_BAR BIT(15) |
| 530 | #define MT_RX_FILTR_CFG_CTRL_RSV BIT(16) |
| 531 | |
| 532 | #define MT_AUTO_RSP_CFG 0x1404 |
| 533 | #define MT_AUTO_RSP_EN BIT(0) |
| 534 | #define MT_AUTO_RSP_PREAMB_SHORT BIT(4) |
| 535 | #define MT_LEGACY_BASIC_RATE 0x1408 |
| 536 | #define MT_HT_BASIC_RATE 0x140c |
| 537 | |
| 538 | #define MT_HT_CTRL_CFG 0x1410 |
| 539 | #define MT_RX_PARSER_CFG 0x1418 |
| 540 | #define MT_RX_PARSER_RX_SET_NAV_ALL BIT(0) |
| 541 | |
| 542 | #define MT_EXT_CCA_CFG 0x141c |
| 543 | #define MT_EXT_CCA_CFG_CCA0 GENMASK(1, 0) |
| 544 | #define MT_EXT_CCA_CFG_CCA1 GENMASK(3, 2) |
| 545 | #define MT_EXT_CCA_CFG_CCA2 GENMASK(5, 4) |
| 546 | #define MT_EXT_CCA_CFG_CCA3 GENMASK(7, 6) |
| 547 | #define MT_EXT_CCA_CFG_CCA_MASK GENMASK(11, 8) |
| 548 | #define MT_EXT_CCA_CFG_ED_CCA_MASK GENMASK(15, 12) |
| 549 | |
| 550 | #define MT_TX_SW_CFG3 0x1478 |
| 551 | |
| 552 | #define MT_PN_PAD_MODE 0x150c |
| 553 | |
| 554 | #define MT_TXOP_HLDR_ET 0x1608 |
| 555 | #define MT_TXOP_HLDR_TX40M_BLK_EN BIT(1) |
| 556 | |
| 557 | #define MT_PROT_AUTO_TX_CFG 0x1648 |
| 558 | #define MT_PROT_AUTO_TX_CFG_PROT_PADJ GENMASK(11, 8) |
| 559 | #define MT_PROT_AUTO_TX_CFG_AUTO_PADJ GENMASK(27, 24) |
| 560 | |
| 561 | #define MT_RX_STAT_0 0x1700 |
| 562 | #define MT_RX_STAT_0_CRC_ERRORS GENMASK(15, 0) |
| 563 | #define MT_RX_STAT_0_PHY_ERRORS GENMASK(31, 16) |
| 564 | |
| 565 | #define MT_RX_STAT_1 0x1704 |
| 566 | #define MT_RX_STAT_1_CCA_ERRORS GENMASK(15, 0) |
| 567 | #define MT_RX_STAT_1_PLCP_ERRORS GENMASK(31, 16) |
| 568 | |
| 569 | #define MT_RX_STAT_2 0x1708 |
| 570 | #define MT_RX_STAT_2_DUP_ERRORS GENMASK(15, 0) |
| 571 | #define MT_RX_STAT_2_OVERFLOW_ERRORS GENMASK(31, 16) |
| 572 | |
| 573 | #define MT_TX_STA_0 0x170c |
| 574 | #define MT_TX_STA_0_BEACONS GENMASK(31, 16) |
| 575 | |
| 576 | #define MT_TX_STA_1 0x1710 |
| 577 | #define MT_TX_STA_2 0x1714 |
| 578 | |
| 579 | #define MT_TX_STAT_FIFO 0x1718 |
| 580 | #define MT_TX_STAT_FIFO_VALID BIT(0) |
| 581 | #define MT_TX_STAT_FIFO_SUCCESS BIT(5) |
| 582 | #define MT_TX_STAT_FIFO_AGGR BIT(6) |
| 583 | #define MT_TX_STAT_FIFO_ACKREQ BIT(7) |
| 584 | #define MT_TX_STAT_FIFO_WCID GENMASK(15, 8) |
| 585 | #define MT_TX_STAT_FIFO_RATE GENMASK(31, 16) |
| 586 | |
| 587 | #define MT_TX_AGG_STAT 0x171c |
| 588 | |
| 589 | #define MT_TX_AGG_CNT_BASE0 0x1720 |
| 590 | #define MT_MPDU_DENSITY_CNT 0x1740 |
| 591 | #define MT_TX_AGG_CNT_BASE1 0x174c |
| 592 | |
| 593 | #define MT_TX_AGG_CNT(_id) ((_id) < 8 ? \ |
| 594 | MT_TX_AGG_CNT_BASE0 + ((_id) << 2) : \ |
| 595 | MT_TX_AGG_CNT_BASE1 + (((_id) - 8) << 2)) |
| 596 | |
| 597 | #define MT_TX_STAT_FIFO_EXT 0x1798 |
| 598 | #define MT_TX_STAT_FIFO_EXT_RETRY GENMASK(7, 0) |
| 599 | #define MT_TX_STAT_FIFO_EXT_PKTID GENMASK(15, 8) |
| 600 | |
| 601 | #define MT_WCID_TX_RATE_BASE 0x1c00 |
| 602 | #define MT_WCID_TX_RATE(_i) (MT_WCID_TX_RATE_BASE + ((_i) << 3)) |
| 603 | |
| 604 | #define MT_BBP_CORE_BASE 0x2000 |
| 605 | #define MT_BBP_IBI_BASE 0x2100 |
| 606 | #define MT_BBP_AGC_BASE 0x2300 |
| 607 | #define MT_BBP_TXC_BASE 0x2400 |
| 608 | #define MT_BBP_RXC_BASE 0x2500 |
| 609 | #define MT_BBP_TXO_BASE 0x2600 |
| 610 | #define MT_BBP_TXBE_BASE 0x2700 |
| 611 | #define MT_BBP_RXFE_BASE 0x2800 |
| 612 | #define MT_BBP_RXO_BASE 0x2900 |
| 613 | #define MT_BBP_DFS_BASE 0x2a00 |
| 614 | #define MT_BBP_TR_BASE 0x2b00 |
| 615 | #define MT_BBP_CAL_BASE 0x2c00 |
| 616 | #define MT_BBP_DSC_BASE 0x2e00 |
| 617 | #define MT_BBP_PFMU_BASE 0x2f00 |
| 618 | |
| 619 | #define MT_BBP(_type, _n) (MT_BBP_##_type##_BASE + ((_n) << 2)) |
| 620 | |
| 621 | #define MT_BBP_CORE_R1_BW GENMASK(4, 3) |
| 622 | |
| 623 | #define MT_BBP_AGC_R0_CTRL_CHAN GENMASK(9, 8) |
| 624 | #define MT_BBP_AGC_R0_BW GENMASK(14, 12) |
| 625 | |
| 626 | /* AGC, R4/R5 */ |
| 627 | #define MT_BBP_AGC_LNA_HIGH_GAIN GENMASK(21, 16) |
| 628 | #define MT_BBP_AGC_LNA_MID_GAIN GENMASK(13, 8) |
| 629 | #define MT_BBP_AGC_LNA_LOW_GAIN GENMASK(5, 0) |
| 630 | |
| 631 | /* AGC, R6/R7 */ |
| 632 | #define MT_BBP_AGC_LNA_ULOW_GAIN GENMASK(5, 0) |
| 633 | |
| 634 | /* AGC, R8/R9 */ |
| 635 | #define MT_BBP_AGC_LNA_GAIN_MODE GENMASK(7, 6) |
| 636 | #define MT_BBP_AGC_GAIN GENMASK(14, 8) |
| 637 | |
| 638 | #define MT_BBP_AGC20_RSSI0 GENMASK(7, 0) |
| 639 | #define MT_BBP_AGC20_RSSI1 GENMASK(15, 8) |
| 640 | |
| 641 | #define MT_BBP_TXBE_R0_CTRL_CHAN GENMASK(1, 0) |
| 642 | |
| 643 | #define MT_WCID_ADDR_BASE 0x1800 |
| 644 | #define MT_WCID_ADDR(_n) (MT_WCID_ADDR_BASE + (_n) * 8) |
| 645 | |
| 646 | #define MT_SRAM_BASE 0x4000 |
| 647 | |
| 648 | #define MT_WCID_KEY_BASE 0x8000 |
| 649 | #define MT_WCID_KEY(_n) (MT_WCID_KEY_BASE + (_n) * 32) |
| 650 | |
| 651 | #define MT_WCID_IV_BASE 0xa000 |
| 652 | #define MT_WCID_IV(_n) (MT_WCID_IV_BASE + (_n) * 8) |
| 653 | |
| 654 | #define MT_WCID_ATTR_BASE 0xa800 |
| 655 | #define MT_WCID_ATTR(_n) (MT_WCID_ATTR_BASE + (_n) * 4) |
| 656 | |
| 657 | #define MT_WCID_ATTR_PAIRWISE BIT(0) |
| 658 | #define MT_WCID_ATTR_PKEY_MODE GENMASK(3, 1) |
| 659 | #define MT_WCID_ATTR_BSS_IDX GENMASK(6, 4) |
| 660 | #define MT_WCID_ATTR_RXWI_UDF GENMASK(9, 7) |
| 661 | #define MT_WCID_ATTR_PKEY_MODE_EXT BIT(10) |
| 662 | #define MT_WCID_ATTR_BSS_IDX_EXT BIT(11) |
| 663 | #define MT_WCID_ATTR_WAPI_MCBC BIT(15) |
| 664 | #define MT_WCID_ATTR_WAPI_KEYID GENMASK(31, 24) |
| 665 | |
| 666 | #define MT_SKEY_BASE_0 0xac00 |
| 667 | #define MT_SKEY_BASE_1 0xb400 |
| 668 | #define MT_SKEY_0(_bss, _idx) (MT_SKEY_BASE_0 + (4 * (_bss) + (_idx)) * 32) |
| 669 | #define MT_SKEY_1(_bss, _idx) (MT_SKEY_BASE_1 + (4 * ((_bss) & 7) + (_idx)) * 32) |
| 670 | #define MT_SKEY(_bss, _idx) (((_bss) & 8) ? MT_SKEY_1(_bss, _idx) : MT_SKEY_0(_bss, _idx)) |
| 671 | |
| 672 | #define MT_SKEY_MODE_BASE_0 0xb000 |
| 673 | #define MT_SKEY_MODE_BASE_1 0xb3f0 |
| 674 | #define MT_SKEY_MODE_0(_bss) (MT_SKEY_MODE_BASE_0 + (((_bss) / 2) << 2)) |
| 675 | #define MT_SKEY_MODE_1(_bss) (MT_SKEY_MODE_BASE_1 + ((((_bss) & 7) / 2) << 2)) |
| 676 | #define MT_SKEY_MODE(_bss) (((_bss) & 8) ? MT_SKEY_MODE_1(_bss) : MT_SKEY_MODE_0(_bss)) |
| 677 | #define MT_SKEY_MODE_MASK GENMASK(3, 0) |
| 678 | #define MT_SKEY_MODE_SHIFT(_bss, _idx) (4 * ((_idx) + 4 * ((_bss) & 1))) |
| 679 | |
| 680 | #define MT_BEACON_BASE 0xc000 |
| 681 | |
| 682 | #define MT_TEMP_SENSOR 0x1d000 |
| 683 | #define MT_TEMP_SENSOR_VAL GENMASK(6, 0) |
| 684 | |
| 685 | struct mt76_wcid_addr { |
| 686 | u8 macaddr[6]; |
| 687 | __le16 ba_mask; |
| 688 | } __packed __aligned(4); |
| 689 | |
| 690 | struct mt76_wcid_key { |
| 691 | u8 key[16]; |
| 692 | u8 tx_mic[8]; |
| 693 | u8 rx_mic[8]; |
| 694 | } __packed __aligned(4); |
| 695 | |
| 696 | enum mt76x02_cipher_type { |
| 697 | MT76X02_CIPHER_NONE, |
| 698 | MT76X02_CIPHER_WEP40, |
| 699 | MT76X02_CIPHER_WEP104, |
| 700 | MT76X02_CIPHER_TKIP, |
| 701 | MT76X02_CIPHER_AES_CCMP, |
| 702 | MT76X02_CIPHER_CKIP40, |
| 703 | MT76X02_CIPHER_CKIP104, |
| 704 | MT76X02_CIPHER_CKIP128, |
| 705 | MT76X02_CIPHER_WAPI, |
| 706 | }; |
| 707 | |
| 708 | #endif |