blob: 37f93c0783cbf3ef1b72db18f7b401f766d28fa8 [file] [log] [blame]
developerfd40db22021-04-29 10:08:25 +08001/dts-v1/;
2#include "mt7986-fpga.dtsi"
3/ {
4 model = "MediaTek MT7986 FPGA";
5 compatible = "mediatek,mt7986-fpga";
6 chosen {
7 bootargs = "console=ttyS0,115200n1 loglevel=8 \
8 earlycon=uart8250,mmio32,0x11002000";
9 };
10
11 memory {
12 // fpga ddr2: 128MB*2
13 reg = <0 0x40000000 0 0x10000000>;
14 };
developerfd40db22021-04-29 10:08:25 +080015};
16
17&uart0 {
18 status = "okay";
19};
20
21&spi0 {
22 pinctrl-names = "default";
23 pinctrl-0 = <&spi_flash_pins>;
24 status = "okay";
25 spi_nor@0 {
26 #address-cells = <1>;
27 #size-cells = <1>;
28 compatible = "jedec,spi-nor";
29 reg = <0>;
30 spi-max-frequency = <500000>;
31
32 partition@00000 {
33 label = "BL2";
34 reg = <0x00000 0x0060000>;
35 };
36 partition@60000 {
37 label = "u-boot-env";
38 reg = <0x60000 0x0010000>;
39 };
40 partition@70000 {
41 label = "Factory";
42 reg = <0x70000 0x00B0000>;
43 };
44 partition@120000 {
45 label = "BL31";
46 reg = <0x120000 0x0010000>;
47 };
48 partition@130000 {
49 label = "u-boot";
50 reg = <0x130000 0x00D0000>;
51 };
52 partition@200000 {
53 label = "firmware";
54 reg = <0x200000 0xE00000>;
55 };
56 };
57 spi_nand@1 {
58 #address-cells = <1>;
59 #size-cells = <1>;
60 compatible = "spi-nand";
61 reg = <1>;
62 spi-max-frequency = <500000>;
63
64 partition@00000 {
65 label = "BL2";
66 reg = <0x00000 0x0100000>;
67 };
68 partition@100000 {
69 label = "u-boot-env";
70 reg = <0x100000 0x0080000>;
71 };
72 partition@180000 {
73 label = "Factory";
74 reg = <0x180000 0x00200000>;
75 };
76 partition@380000 {
77 label = "BL31";
78 reg = <0x380000 0x0080000>;
79 };
80 partition@400000 {
81 label = "u-boot";
82 reg = <0x400000 0x0180000>;
83 };
84 partition@580000 {
85 label = "firmware";
86 reg = <0x580000 0x7a80000>;
87 };
88 };
89};
90
91&spi1 {
92 pinctrl-names = "default";
93 /* pin shared with snfi */
94 pinctrl-0 = <&spic_pins>;
95 status = "disabled";
96};
97
98&pio {
99 spi_flash_pins: spi0-pins {
100 mux {
101 function = "flash";
102 groups = "spi0", "spi0_wp_hold";
103 };
104 };
105
106 snfi_pins: snfi-pins {
107 mux {
108 function = "flash";
109 groups = "snfi";
110 };
111 };
112
113 spic_pins: spi1-pins {
114 mux {
115 function = "spi";
116 groups = "spi1_1";
117 };
118 };
119};
120
121&watchdog {
122 status = "disabled";
123};
124
125&snand {
126 pinctrl-names = "default";
127 /* pin shared with spic */
128 pinctrl-0 = <&snfi_pins>;
129 status = "okay";
130 mediatek,quad-spi;
131
132 partitions {
133 compatible = "fixed-partitions";
134 #address-cells = <1>;
135 #size-cells = <1>;
136
137 partition@0 {
138 label = "BL2";
139 reg = <0x00000 0x0080000>;
140 read-only;
141 };
142
143 partition@80000 {
144 label = "FIP";
145 reg = <0x80000 0x0200000>;
146 };
147
148 partition@280000 {
149 label = "u-boot-env";
150 reg = <0x280000 0x0080000>;
151 };
152
153 partition@300000 {
154 label = "Factory";
155 reg = <0x300000 0x0080000>;
156 };
157
158 partition@380000 {
159 label = "firmware";
160 reg = <0x380000 0x7c00000>;
161 };
162 };
163};