| developer | 24455dd | 2021-10-28 10:55:41 +0800 | [diff] [blame] | 1 | /dts-v1/; |
| 2 | #include "mt7981-fpga.dtsi" |
| 3 | / { |
| 4 | model = "MediaTek MT7981 FPGA"; |
| 5 | compatible = "mediatek,mt7981-fpga-spim-nand"; |
| 6 | chosen { |
| 7 | bootargs = "console=ttyS0,115200n1 loglevel=8 \ |
| 8 | earlycon=uart8250,mmio32,0x11002000"; |
| 9 | }; |
| 10 | |
| 11 | memory { |
| 12 | // fpga ddr2: 128MB*2 |
| 13 | reg = <0 0x40000000 0 0x10000000>; |
| 14 | }; |
| 15 | |
| 16 | nmbm_spim_nand { |
| 17 | compatible = "generic,nmbm"; |
| 18 | |
| 19 | #address-cells = <1>; |
| 20 | #size-cells = <1>; |
| 21 | |
| 22 | lower-mtd-device = <&spi_nand>; |
| 23 | forced-create; |
| 24 | |
| 25 | partitions { |
| 26 | compatible = "fixed-partitions"; |
| 27 | #address-cells = <1>; |
| 28 | #size-cells = <1>; |
| 29 | |
| 30 | partition@0 { |
| 31 | label = "BL2"; |
| 32 | reg = <0x00000 0x0100000>; |
| 33 | read-only; |
| 34 | }; |
| 35 | |
| 36 | partition@100000 { |
| 37 | label = "u-boot-env"; |
| 38 | reg = <0x0100000 0x0080000>; |
| 39 | }; |
| 40 | |
| 41 | partition@180000 { |
| 42 | label = "Factory"; |
| 43 | reg = <0x180000 0x0200000>; |
| 44 | }; |
| 45 | |
| 46 | partition@380000 { |
| 47 | label = "FIP"; |
| 48 | reg = <0x380000 0x0200000>; |
| 49 | }; |
| 50 | |
| 51 | partition@580000 { |
| 52 | label = "ubi"; |
| 53 | reg = <0x580000 0x4000000>; |
| 54 | }; |
| 55 | }; |
| 56 | }; |
| 57 | |
| 58 | wsys_adie: wsys_adie@0 { |
| 59 | // fpga cases need to manual change adie_id / sku_type for dvt only |
| 60 | compatible = "mediatek,rebb-mt7981-adie"; |
| 61 | adie_id = <7976>; |
| 62 | sku_type = <3000>; |
| 63 | }; |
| 64 | }; |
| 65 | |
| 66 | &uart0 { |
| 67 | status = "okay"; |
| 68 | }; |
| 69 | |
| 70 | &spi0 { |
| 71 | pinctrl-names = "default"; |
| 72 | pinctrl-0 = <&spi0_flash_pins>; |
| 73 | status = "okay"; |
| 74 | spi_nand: spi_nand@0 { |
| 75 | #address-cells = <1>; |
| 76 | #size-cells = <1>; |
| 77 | compatible = "spi-nand"; |
| 78 | reg = <0>; |
| 79 | spi-max-frequency = <3000000>; |
| 80 | }; |
| 81 | }; |
| 82 | |
| 83 | &spi1 { |
| 84 | pinctrl-names = "default"; |
| 85 | /* pin shared with snfi */ |
| 86 | pinctrl-0 = <&spic_pins>; |
| 87 | status = "disabled"; |
| 88 | }; |
| 89 | |
| 90 | &pcie { |
| 91 | pinctrl-names = "default"; |
| 92 | pinctrl-0 = <&pcie_pins>; |
| 93 | status = "okay"; |
| 94 | }; |
| 95 | |
| 96 | &pio { |
| 97 | pcie_pins: pcie-pins { |
| 98 | mux { |
| 99 | function = "pcie"; |
| 100 | groups = "pcie_pereset", "pcie_clk", "pcie_wake"; |
| 101 | }; |
| 102 | }; |
| 103 | |
| 104 | spi0_flash_pins: spi0-pins { |
| 105 | mux { |
| 106 | function = "spi"; |
| 107 | groups = "spi0", "spi0_wp_hold"; |
| 108 | }; |
| 109 | }; |
| 110 | |
| 111 | spic_pins: spi1-pins { |
| 112 | mux { |
| 113 | function = "spi"; |
| 114 | groups = "spi1_1"; |
| 115 | }; |
| 116 | }; |
| 117 | }; |
| 118 | |
| 119 | &watchdog { |
| 120 | status = "disabled"; |
| 121 | }; |
| 122 | |
| 123 | ð { |
| 124 | status = "okay"; |
| 125 | |
| 126 | gmac0: mac@0 { |
| 127 | compatible = "mediatek,eth-mac"; |
| 128 | reg = <0>; |
| 129 | phy-mode = "rgmii"; |
| 130 | |
| 131 | fixed-link { |
| 132 | speed = <100>; |
| 133 | full-duplex; |
| 134 | pause; |
| 135 | }; |
| 136 | }; |
| 137 | gmac1: mac@1 { |
| 138 | compatible = "mediatek,eth-mac"; |
| 139 | reg = <1>; |
| 140 | phy-mode = "rgmii"; |
| 141 | |
| 142 | fixed-link { |
| 143 | speed = <100>; |
| 144 | full-duplex; |
| 145 | pause; |
| 146 | }; |
| 147 | }; |
| 148 | |
| 149 | mdio: mdio-bus { |
| 150 | #address-cells = <1>; |
| 151 | #size-cells = <0>; |
| 152 | }; |
| 153 | |
| 154 | }; |
| 155 | |
| 156 | &hnat { |
| 157 | mtketh-wan = "eth1"; |
| 158 | mtketh-lan = "eth0"; |
| 159 | mtketh-max-gmac = <2>; |
| 160 | status = "okay"; |
| 161 | }; |