| developer | 0f312e8 | 2022-11-01 12:31:52 +0800 | [diff] [blame^] | 1 | /* SPDX-License-Identifier: ISC */ |
| 2 | /* |
| 3 | * Copyright (C) 2016 Felix Fietkau <nbd@nbd.name> |
| 4 | */ |
| 5 | #ifndef __MT76_DMA_H |
| 6 | #define __MT76_DMA_H |
| 7 | |
| 8 | #define DMA_DUMMY_DATA ((void *)~0) |
| 9 | |
| 10 | #define MT_RING_SIZE 0x10 |
| 11 | |
| 12 | #define MT_DMA_CTL_SD_LEN1 GENMASK(13, 0) |
| 13 | #define MT_DMA_CTL_LAST_SEC1 BIT(14) |
| 14 | #define MT_DMA_CTL_BURST BIT(15) |
| 15 | #define MT_DMA_CTL_SD_LEN0 GENMASK(29, 16) |
| 16 | #define MT_DMA_CTL_LAST_SEC0 BIT(30) |
| 17 | #define MT_DMA_CTL_DMA_DONE BIT(31) |
| 18 | |
| 19 | #define MT_DMA_HDR_LEN 4 |
| 20 | #define MT_RX_INFO_LEN 4 |
| 21 | #define MT_FCE_INFO_LEN 4 |
| 22 | #define MT_RX_RXWI_LEN 32 |
| 23 | |
| 24 | struct mt76_desc { |
| 25 | __le32 buf0; |
| 26 | __le32 ctrl; |
| 27 | __le32 buf1; |
| 28 | __le32 info; |
| 29 | } __packed __aligned(4); |
| 30 | |
| 31 | enum mt76_qsel { |
| 32 | MT_QSEL_MGMT, |
| 33 | MT_QSEL_HCCA, |
| 34 | MT_QSEL_EDCA, |
| 35 | MT_QSEL_EDCA_2, |
| 36 | }; |
| 37 | |
| 38 | enum mt76_mcu_evt_type { |
| 39 | EVT_CMD_DONE, |
| 40 | EVT_CMD_ERROR, |
| 41 | EVT_CMD_RETRY, |
| 42 | EVT_EVENT_PWR_RSP, |
| 43 | EVT_EVENT_WOW_RSP, |
| 44 | EVT_EVENT_CARRIER_DETECT_RSP, |
| 45 | EVT_EVENT_DFS_DETECT_RSP, |
| 46 | }; |
| 47 | |
| 48 | int mt76_dma_rx_poll(struct napi_struct *napi, int budget); |
| 49 | void mt76_dma_attach(struct mt76_dev *dev); |
| 50 | void mt76_dma_cleanup(struct mt76_dev *dev); |
| 51 | |
| 52 | #endif |