blob: f63bc9e26743baedaf23cfd265ae30ed86e6b6c9 [file] [log] [blame]
developer3abe1ad2022-01-24 11:13:32 +08001#define _GNU_SOURCE
2#include <fcntl.h>
3#include <sys/mman.h>
4#include <sys/stat.h>
5#include <sys/wait.h>
6
7#include "atenl.h"
8
developer11f4a0b2023-03-31 17:43:25 +08009#define EEPROM_PART_SIZE 0xFF000
developera6267142022-01-26 20:50:22 +080010char *eeprom_file;
developer3abe1ad2022-01-24 11:13:32 +080011
developer82af5012022-11-01 11:15:32 +080012static int
13atenl_create_file(struct atenl *an, bool flash_mode)
developer3abe1ad2022-01-24 11:13:32 +080014{
developer82af5012022-11-01 11:15:32 +080015 char fname[64], buf[1024];
16 ssize_t w, len, max_len, total_len = 0;
17 int fd_ori, fd, ret;
developer3abe1ad2022-01-24 11:13:32 +080018
developer82af5012022-11-01 11:15:32 +080019 /* reserve space for pre-cal data in flash mode */
20 if (flash_mode) {
21 atenl_dbg("%s: init eeprom with flash mode\n", __func__);
22 max_len = EEPROM_PART_SIZE;
23 } else {
24 atenl_dbg("%s: init eeprom with efuse mode\n", __func__);
developerf90c9af2022-12-28 22:40:23 +080025 max_len = 0x1e00;
developer3abe1ad2022-01-24 11:13:32 +080026 }
developer3abe1ad2022-01-24 11:13:32 +080027
developer82af5012022-11-01 11:15:32 +080028 snprintf(fname, sizeof(fname),
29 "/sys/kernel/debug/ieee80211/phy%d/mt76/eeprom",
30 get_band_val(an, 0, phy_idx));
31 fd_ori = open(fname, O_RDONLY);
32 if (fd_ori < 0)
developer3abe1ad2022-01-24 11:13:32 +080033 return -1;
developer3abe1ad2022-01-24 11:13:32 +080034
developera6267142022-01-26 20:50:22 +080035 fd = open(eeprom_file, O_RDWR | O_CREAT | O_EXCL, 00644);
developer3abe1ad2022-01-24 11:13:32 +080036 if (fd < 0)
37 goto out;
38
developer82af5012022-11-01 11:15:32 +080039 while ((len = read(fd_ori, buf, sizeof(buf))) > 0) {
developer3abe1ad2022-01-24 11:13:32 +080040retry:
41 w = write(fd, buf, len);
developer5698c9c2022-05-30 16:40:23 +080042 if (w > 0) {
developer82af5012022-11-01 11:15:32 +080043 total_len += len;
developer3abe1ad2022-01-24 11:13:32 +080044 continue;
developer5698c9c2022-05-30 16:40:23 +080045 }
developer3abe1ad2022-01-24 11:13:32 +080046
47 if (errno == EINTR)
48 goto retry;
49
50 perror("write");
developera6267142022-01-26 20:50:22 +080051 unlink(eeprom_file);
developer3abe1ad2022-01-24 11:13:32 +080052 close(fd);
53 fd = -1;
54 goto out;
55 }
56
developer82af5012022-11-01 11:15:32 +080057 /* reserve space for pre-cal data in flash mode */
58 len = sizeof(buf);
59 memset(buf, 0, len);
60 while (total_len < max_len) {
developer3abe1ad2022-01-24 11:13:32 +080061 w = write(fd, buf, len);
developer3abe1ad2022-01-24 11:13:32 +080062
developer82af5012022-11-01 11:15:32 +080063 if (w > 0) {
64 total_len += len;
65 continue;
66 }
developer3abe1ad2022-01-24 11:13:32 +080067
developer82af5012022-11-01 11:15:32 +080068 if (errno != EINTR) {
69 perror("write");
70 unlink(eeprom_file);
71 close(fd);
72 fd = -1;
73 goto out;
74 }
developer3abe1ad2022-01-24 11:13:32 +080075 }
76
developer82af5012022-11-01 11:15:32 +080077
developer3abe1ad2022-01-24 11:13:32 +080078 ret = lseek(fd, 0, SEEK_SET);
79 if (ret) {
80 close(fd_ori);
81 close(fd);
82 return ret;
83 }
84
85out:
86 close(fd_ori);
87 return fd;
88}
89
90static bool
91atenl_eeprom_file_exists(void)
92{
93 struct stat st;
94
developera6267142022-01-26 20:50:22 +080095 return stat(eeprom_file, &st) == 0;
developer3abe1ad2022-01-24 11:13:32 +080096}
97
98static int
99atenl_eeprom_init_file(struct atenl *an, bool flash_mode)
100{
101 int fd;
102
developer82af5012022-11-01 11:15:32 +0800103 if (!atenl_eeprom_file_exists())
104 return atenl_create_file(an, flash_mode);
developer3abe1ad2022-01-24 11:13:32 +0800105
developera6267142022-01-26 20:50:22 +0800106 fd = open(eeprom_file, O_RDWR);
developer3abe1ad2022-01-24 11:13:32 +0800107 if (fd < 0)
108 perror("open");
109
developer3abe1ad2022-01-24 11:13:32 +0800110 return fd;
111}
112
113static void
developer5698c9c2022-05-30 16:40:23 +0800114atenl_eeprom_init_chip_id(struct atenl *an)
115{
116 an->chip_id = *(u16 *)an->eeprom_data;
117
118 if (is_mt7915(an)) {
119 an->adie_id = 0x7975;
120 } else if (is_mt7916(an)) {
121 an->adie_id = 0x7976;
122 } else if (is_mt7986(an)) {
123 bool is_7975 = false;
124 u32 val;
125 u8 sub_id;
126
127 atenl_reg_read(an, 0x18050000, &val);
128
129 switch (val & 0xf) {
130 case MT7975_ONE_ADIE_SINGLE_BAND:
131 is_7975 = true;
132 /* fallthrough */
133 case MT7976_ONE_ADIE_SINGLE_BAND:
134 sub_id = 0xa;
135 break;
136 case MT7976_ONE_ADIE_DBDC:
137 sub_id = 0x7;
138 break;
139 case MT7975_DUAL_ADIE_DBDC:
140 is_7975 = true;
141 /* fallthrough */
142 case MT7976_DUAL_ADIE_DBDC:
143 default:
144 sub_id = 0xf;
145 break;
146 }
147
148 an->sub_chip_id = sub_id;
149 an->adie_id = is_7975 ? 0x7975 : 0x7976;
developerf90c9af2022-12-28 22:40:23 +0800150 } else if (is_mt7996(an)) {
151 /* TODO: parse info if required */
developer5698c9c2022-05-30 16:40:23 +0800152 }
153}
154
155static void
developer3abe1ad2022-01-24 11:13:32 +0800156atenl_eeprom_init_max_size(struct atenl *an)
157{
158 switch (an->chip_id) {
159 case 0x7915:
160 an->eeprom_size = 3584;
developer071927d2022-08-31 20:39:29 +0800161 an->eeprom_prek_offs = 0x62;
developer3abe1ad2022-01-24 11:13:32 +0800162 break;
163 case 0x7906:
164 case 0x7916:
165 case 0x7986:
166 an->eeprom_size = 4096;
developer071927d2022-08-31 20:39:29 +0800167 an->eeprom_prek_offs = 0x19a;
developer3abe1ad2022-01-24 11:13:32 +0800168 break;
developerf90c9af2022-12-28 22:40:23 +0800169 case 0x7990:
170 an->eeprom_size = 7680;
171 an->eeprom_prek_offs = 0x1a5;
developer3abe1ad2022-01-24 11:13:32 +0800172 default:
173 break;
174 }
175}
176
177static void
178atenl_eeprom_init_band_cap(struct atenl *an)
179{
developerf90c9af2022-12-28 22:40:23 +0800180#define EAGLE_BAND_SEL(index) MT_EE_WIFI_EAGLE_CONF##index##_BAND_SEL
developer3abe1ad2022-01-24 11:13:32 +0800181 u8 *eeprom = an->eeprom_data;
182
183 if (is_mt7915(an)) {
184 u8 val = eeprom[MT_EE_WIFI_CONF];
185 u8 band_sel = FIELD_GET(MT_EE_WIFI_CONF0_BAND_SEL, val);
186 struct atenl_band *anb = &an->anb[0];
187
188 /* MT7915A */
189 if (band_sel == MT_EE_BAND_SEL_DEFAULT) {
190 anb->valid = true;
191 anb->cap = BAND_TYPE_2G_5G;
192 return;
193 }
194
195 /* MT7915D */
196 if (band_sel == MT_EE_BAND_SEL_2GHZ) {
197 anb->valid = true;
198 anb->cap = BAND_TYPE_2G;
199 }
200
201 val = eeprom[MT_EE_WIFI_CONF + 1];
202 band_sel = FIELD_GET(MT_EE_WIFI_CONF0_BAND_SEL, val);
203 anb++;
204
205 if (band_sel == MT_EE_BAND_SEL_5GHZ) {
206 anb->valid = true;
207 anb->cap = BAND_TYPE_5G;
208 }
209 } else if (is_mt7916(an) || is_mt7986(an)) {
210 struct atenl_band *anb;
211 u8 val, band_sel;
212 int i;
213
214 for (i = 0; i < 2; i++) {
215 val = eeprom[MT_EE_WIFI_CONF + i];
216 band_sel = FIELD_GET(MT_EE_WIFI_CONF0_BAND_SEL, val);
217 anb = &an->anb[i];
218
219 anb->valid = true;
220 switch (band_sel) {
221 case MT_EE_BAND_SEL_2G:
222 anb->cap = BAND_TYPE_2G;
223 break;
224 case MT_EE_BAND_SEL_5G:
225 anb->cap = BAND_TYPE_5G;
226 break;
227 case MT_EE_BAND_SEL_6G:
228 anb->cap = BAND_TYPE_6G;
229 break;
230 case MT_EE_BAND_SEL_5G_6G:
231 anb->cap = BAND_TYPE_5G_6G;
232 break;
233 default:
234 break;
235 }
236 }
developerf90c9af2022-12-28 22:40:23 +0800237 } else if (is_mt7996(an)) {
238 struct atenl_band *anb;
239 u8 val, band_sel;
240 u8 band_sel_mask[3] = {EAGLE_BAND_SEL(0), EAGLE_BAND_SEL(1),
241 EAGLE_BAND_SEL(2)};
242 int i;
243
244 for (i = 0; i < 3; i++) {
245 val = eeprom[MT_EE_WIFI_CONF + i];
246 band_sel = FIELD_GET(band_sel_mask[i], val);
247 anb = &an->anb[i];
248
249 anb->valid = true;
250 switch (band_sel) {
251 case MT_EE_EAGLE_BAND_SEL_2GHZ:
252 anb->cap = BAND_TYPE_2G;
253 break;
254 case MT_EE_EAGLE_BAND_SEL_5GHZ:
255 anb->cap = BAND_TYPE_5G;
256 break;
257 case MT_EE_EAGLE_BAND_SEL_6GHZ:
258 anb->cap = BAND_TYPE_6G;
259 break;
260 case MT_EE_EAGLE_BAND_SEL_5GHZ_6GHZ:
261 anb->cap = BAND_TYPE_5G_6G;
262 break;
263 default:
264 break;
265 }
266 }
developer3abe1ad2022-01-24 11:13:32 +0800267 }
268}
269
270static void
271atenl_eeprom_init_antenna_cap(struct atenl *an)
272{
273 if (is_mt7915(an)) {
274 if (an->anb[0].cap == BAND_TYPE_2G_5G)
275 an->anb[0].chainmask = 0xf;
276 else {
277 an->anb[0].chainmask = 0x3;
278 an->anb[1].chainmask = 0xc;
279 }
280 } else if (is_mt7916(an)) {
281 an->anb[0].chainmask = 0x3;
282 an->anb[1].chainmask = 0x3;
283 } else if (is_mt7986(an)) {
284 an->anb[0].chainmask = 0xf;
285 an->anb[1].chainmask = 0xf;
developerf90c9af2022-12-28 22:40:23 +0800286 } else if (is_mt7996(an)) {
287 an->anb[0].chainmask = 0xf;
288 an->anb[1].chainmask = 0xf;
289 an->anb[2].chainmask = 0xf;
developer3abe1ad2022-01-24 11:13:32 +0800290 }
291}
292
293int atenl_eeprom_init(struct atenl *an, u8 phy_idx)
294{
295 bool flash_mode;
296 int eeprom_fd;
developera6267142022-01-26 20:50:22 +0800297 char buf[30];
developer071927d2022-08-31 20:39:29 +0800298 u8 main_phy_idx = phy_idx;
developer3abe1ad2022-01-24 11:13:32 +0800299
300 set_band_val(an, 0, phy_idx, phy_idx);
developer3abe1ad2022-01-24 11:13:32 +0800301 atenl_nl_check_mtd(an);
302 flash_mode = an->mtd_part != NULL;
303
developerf90c9af2022-12-28 22:40:23 +0800304 // Get the first main phy index for this chip
developer071927d2022-08-31 20:39:29 +0800305 if (flash_mode)
developerf90c9af2022-12-28 22:40:23 +0800306 main_phy_idx -= an->band_idx;
developer071927d2022-08-31 20:39:29 +0800307
308 snprintf(buf, sizeof(buf), "/tmp/atenl-eeprom-phy%u", main_phy_idx);
309 eeprom_file = strdup(buf);
310
developer3abe1ad2022-01-24 11:13:32 +0800311 eeprom_fd = atenl_eeprom_init_file(an, flash_mode);
312 if (eeprom_fd < 0)
313 return -1;
314
315 an->eeprom_data = mmap(NULL, EEPROM_PART_SIZE, PROT_READ | PROT_WRITE,
developer071927d2022-08-31 20:39:29 +0800316 MAP_SHARED, eeprom_fd, 0);
developer3abe1ad2022-01-24 11:13:32 +0800317 if (!an->eeprom_data) {
318 perror("mmap");
319 close(eeprom_fd);
320 return -1;
321 }
322
323 an->eeprom_fd = eeprom_fd;
developer5698c9c2022-05-30 16:40:23 +0800324 atenl_eeprom_init_chip_id(an);
developer3abe1ad2022-01-24 11:13:32 +0800325 atenl_eeprom_init_max_size(an);
326 atenl_eeprom_init_band_cap(an);
327 atenl_eeprom_init_antenna_cap(an);
328
329 if (get_band_val(an, 1, valid))
330 set_band_val(an, 1, phy_idx, phy_idx + 1);
331
332 return 0;
333}
334
335void atenl_eeprom_close(struct atenl *an)
336{
337 msync(an->eeprom_data, EEPROM_PART_SIZE, MS_SYNC);
338 munmap(an->eeprom_data, EEPROM_PART_SIZE);
339 close(an->eeprom_fd);
340
developer5698c9c2022-05-30 16:40:23 +0800341 if (!an->cmd_mode) {
developera6267142022-01-26 20:50:22 +0800342 if (remove(eeprom_file))
developer3abe1ad2022-01-24 11:13:32 +0800343 perror("remove");
developera6267142022-01-26 20:50:22 +0800344 }
345
346 free(eeprom_file);
developer3abe1ad2022-01-24 11:13:32 +0800347}
348
developer071927d2022-08-31 20:39:29 +0800349int atenl_eeprom_update_precal(struct atenl *an, int write_offs, int size)
350{
351 u32 offs = an->eeprom_prek_offs;
352 u8 cal_indicator, *eeprom, *pre_cal;
353
354 if (!an->cal && !an->cal_info)
355 return 0;
356
357 eeprom = an->eeprom_data;
358 pre_cal = eeprom + an->eeprom_size;
359 cal_indicator = an->cal_info[4];
360
361 memcpy(eeprom + offs, &cal_indicator, sizeof(u8));
362 memcpy(pre_cal, an->cal_info, PRE_CAL_INFO);
363 pre_cal += (PRE_CAL_INFO + write_offs);
364
365 if (an->cal)
366 memcpy(pre_cal, an->cal, size);
367 else
368 memset(pre_cal, 0, size);
369
370 return 0;
371}
372
developer3abe1ad2022-01-24 11:13:32 +0800373int atenl_eeprom_write_mtd(struct atenl *an)
374{
375 bool flash_mode = an->mtd_part != NULL;
376 pid_t pid;
developer071927d2022-08-31 20:39:29 +0800377 char offset[10];
developer3abe1ad2022-01-24 11:13:32 +0800378
379 if (!flash_mode)
380 return 0;
381
382 pid = fork();
383 if (pid < 0) {
384 perror("Fork");
385 return EXIT_FAILURE;
386 } else if (pid == 0) {
developer3abe1ad2022-01-24 11:13:32 +0800387 int ret;
developer071927d2022-08-31 20:39:29 +0800388 char *part = strdup(an->mtd_part);
389 snprintf(offset, sizeof(offset), "%d", an->mtd_offset);
390 char *cmd[] = {"mtd", "-p", offset, "write", eeprom_file, part, NULL};
developer3abe1ad2022-01-24 11:13:32 +0800391
392 ret = execvp("mtd", cmd);
393 if (ret < 0) {
developer5698c9c2022-05-30 16:40:23 +0800394 atenl_err("%s: exec error\n", __func__);
developer3abe1ad2022-01-24 11:13:32 +0800395 exit(0);
396 }
397 } else {
398 wait(&pid);
399 }
400
401 return 0;
402}
403
developer5698c9c2022-05-30 16:40:23 +0800404/* Directly read values from driver's eeprom.
developer3abe1ad2022-01-24 11:13:32 +0800405 * It's usally used to get calibrated data from driver.
406 */
407int atenl_eeprom_read_from_driver(struct atenl *an, u32 offset, int len)
408{
409 u8 *eeprom_data = an->eeprom_data + offset;
410 char fname[64], buf[1024];
411 int fd_ori, ret;
412 ssize_t rd;
413
414 snprintf(fname, sizeof(fname),
415 "/sys/kernel/debug/ieee80211/phy%d/mt76/eeprom",
416 get_band_val(an, 0, phy_idx));
417 fd_ori = open(fname, O_RDONLY);
418 if (fd_ori < 0)
419 return -1;
420
421 ret = lseek(fd_ori, offset, SEEK_SET);
422 if (ret < 0)
423 goto out;
424
425 while ((rd = read(fd_ori, buf, sizeof(buf))) > 0 && len) {
426 if (len < rd) {
427 memcpy(eeprom_data, buf, len);
428 break;
429 } else {
430 memcpy(eeprom_data, buf, rd);
431 eeprom_data += rd;
432 len -= rd;
433 }
434 }
435
436 ret = 0;
437out:
438 close(fd_ori);
439 return ret;
440}
441
442/* Update all eeprom values to driver before writing efuse */
443static void
444atenl_eeprom_sync_to_driver(struct atenl *an)
445{
446 int i;
447
developera6267142022-01-26 20:50:22 +0800448 for (i = 0; i < an->eeprom_size; i += 16)
developer3abe1ad2022-01-24 11:13:32 +0800449 atenl_nl_write_eeprom(an, i, &an->eeprom_data[i], 16);
450}
451
452void atenl_eeprom_cmd_handler(struct atenl *an, u8 phy_idx, char *cmd)
453{
454 bool flash_mode;
455
456 an->cmd_mode = true;
457
458 atenl_eeprom_init(an, phy_idx);
459 flash_mode = an->mtd_part != NULL;
460
461 if (!strncmp(cmd, "sync eeprom all", 15)) {
462 atenl_eeprom_write_mtd(an);
463 } else if (!strncmp(cmd, "eeprom", 6)) {
464 char *s = strchr(cmd, ' ');
465
466 if (!s) {
developer5698c9c2022-05-30 16:40:23 +0800467 atenl_err("eeprom: please type a correct command\n");
developer3abe1ad2022-01-24 11:13:32 +0800468 return;
469 }
470
471 s++;
472 if (!strncmp(s, "reset", 5)) {
developera6267142022-01-26 20:50:22 +0800473 unlink(eeprom_file);
developer3abe1ad2022-01-24 11:13:32 +0800474 } else if (!strncmp(s, "file", 4)) {
developera6267142022-01-26 20:50:22 +0800475 atenl_info("%s\n", eeprom_file);
developer3abe1ad2022-01-24 11:13:32 +0800476 atenl_info("Flash mode: %d\n", flash_mode);
477 } else if (!strncmp(s, "set", 3)) {
478 u32 offset, val;
479
480 s = strchr(s, ' ');
481 if (!s)
482 return;
483 s++;
484
485 if (!sscanf(s, "%x=%x", &offset, &val) ||
486 offset > EEPROM_PART_SIZE)
487 return;
488
489 an->eeprom_data[offset] = val;
490 atenl_info("set offset 0x%x to 0x%x\n", offset, val);
developer9b7cdad2022-03-10 14:24:55 +0800491 } else if (!strncmp(s, "update buffermode", 17)) {
developera6267142022-01-26 20:50:22 +0800492 atenl_eeprom_sync_to_driver(an);
developer3abe1ad2022-01-24 11:13:32 +0800493 atenl_nl_update_buffer_mode(an);
494 } else if (!strncmp(s, "write", 5)) {
495 s = strchr(s, ' ');
496 if (!s)
497 return;
498 s++;
499
developer9b7cdad2022-03-10 14:24:55 +0800500 if (!strncmp(s, "flash", 5)) {
developer3abe1ad2022-01-24 11:13:32 +0800501 atenl_eeprom_write_mtd(an);
developer9b7cdad2022-03-10 14:24:55 +0800502 } else if (!strncmp(s, "to efuse", 8)) {
503 atenl_eeprom_sync_to_driver(an);
504 atenl_nl_write_efuse_all(an);
505 }
developer3abe1ad2022-01-24 11:13:32 +0800506 } else if (!strncmp(s, "read", 4)) {
507 u32 offset;
508
509 s = strchr(s, ' ');
510 if (!s)
511 return;
512 s++;
513
514 if (!sscanf(s, "%x", &offset) ||
515 offset > EEPROM_PART_SIZE)
516 return;
517
518 atenl_info("val = 0x%x (%u)\n", an->eeprom_data[offset],
519 an->eeprom_data[offset]);
developer071927d2022-08-31 20:39:29 +0800520 } else if (!strncmp(s, "precal", 6)) {
521 s = strchr(s, ' ');
522 if (!s)
523 return;
524 s++;
525
526 if (!strncmp(s, "sync group", 10)) {
527 atenl_nl_precal_sync_from_driver(an, PREK_SYNC_GROUP);
528 } else if (!strncmp(s, "sync dpd 2g", 11)) {
529 atenl_nl_precal_sync_from_driver(an, PREK_SYNC_DPD_2G);
530 } else if (!strncmp(s, "sync dpd 5g", 11)) {
531 atenl_nl_precal_sync_from_driver(an, PREK_SYNC_DPD_5G);
532 } else if (!strncmp(s, "sync dpd 6g", 11)) {
533 atenl_nl_precal_sync_from_driver(an, PREK_SYNC_DPD_6G);
534 } else if (!strncmp(s, "group clean", 11)) {
535 atenl_nl_precal_sync_from_driver(an, PREK_CLEAN_GROUP);
536 } else if (!strncmp(s, "dpd clean", 9)) {
537 atenl_nl_precal_sync_from_driver(an, PREK_CLEAN_DPD);
538 } else if (!strncmp(s, "sync", 4)) {
539 atenl_nl_precal_sync_from_driver(an, PREK_SYNC_ALL);
540 }
developer9b7cdad2022-03-10 14:24:55 +0800541 } else {
542 atenl_err("Unknown eeprom command: %s\n", cmd);
543 }
developer3abe1ad2022-01-24 11:13:32 +0800544 } else {
545 atenl_err("Unknown command: %s\n", cmd);
546 }
547}