blob: 244788d8e9ab2f6a1b0b2584f890442a5634e3ba [file] [log] [blame]
developerf4447452022-07-05 14:02:53 +08001diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
2index 2c54c9c..d3ba9eb 100644
3--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
4+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
5@@ -3814,7 +3814,8 @@ static int mtk_probe(struct platform_device *pdev)
6
7 for (i = 0; i < eth->ppe_num; i++) {
8 eth->ppe[i] = mtk_ppe_init(eth,
9- eth->base + MTK_ETH_PPE_BASE + i * 0x400, 2, i);
10+ eth->base + MTK_ETH_PPE_BASE + i * 0x400,
11+ 2, eth->soc->hash_way, i);
12 if (!eth->ppe[i]) {
13 err = -ENOMEM;
14 goto err_free_dev;
developer0c6c5252022-07-12 11:59:21 +080015@@ -3927,12 +3928,13 @@ static const struct mtk_soc_data mt2701_data = {
developerf4447452022-07-05 14:02:53 +080016 .required_clks = MT7623_CLKS_BITMAP,
17 .required_pctl = true,
18 .has_sram = false,
19+ .hash_way = 2,
20 .offload_version = 2,
developer0c6c5252022-07-12 11:59:21 +080021 .txrx = {
22 .txd_size = sizeof(struct mtk_tx_dma),
23 .rxd_size = sizeof(struct mtk_rx_dma),
24 .dma_max_len = MTK_TX_DMA_BUF_LEN,
25 .dma_len_offset = MTK_TX_DMA_BUF_SHIFT,
26 },
developerf4447452022-07-05 14:02:53 +080027 };
28
developer0c6c5252022-07-12 11:59:21 +080029@@ -3936,12 +3938,13 @@ static const struct mtk_soc_data mt7621_data = {
developerf4447452022-07-05 14:02:53 +080030 .required_clks = MT7621_CLKS_BITMAP,
31 .required_pctl = false,
32 .has_sram = false,
33+ .hash_way = 2,
34 .offload_version = 2,
developer0c6c5252022-07-12 11:59:21 +080035 .txrx = {
36 .txd_size = sizeof(struct mtk_tx_dma),
37 .rxd_size = sizeof(struct mtk_rx_dma),
38 .dma_max_len = MTK_TX_DMA_BUF_LEN,
39 .dma_len_offset = MTK_TX_DMA_BUF_SHIFT,
40 },
developerf4447452022-07-05 14:02:53 +080041 };
42
developer0c6c5252022-07-12 11:59:21 +080043@@ -3946,12 +3949,13 @@ static const struct mtk_soc_data mt7622_data = {
developerf4447452022-07-05 14:02:53 +080044 .required_clks = MT7622_CLKS_BITMAP,
45 .required_pctl = false,
46 .has_sram = false,
47+ .hash_way = 2,
48 .offload_version = 2,
developer0c6c5252022-07-12 11:59:21 +080049 .txrx = {
50 .txd_size = sizeof(struct mtk_tx_dma),
51 .rxd_size = sizeof(struct mtk_rx_dma),
52 .dma_max_len = MTK_TX_DMA_BUF_LEN,
53 .dma_len_offset = MTK_TX_DMA_BUF_SHIFT,
54 },
developerf4447452022-07-05 14:02:53 +080055 };
56
developer0c6c5252022-07-12 11:59:21 +080057@@ -3955,12 +3959,13 @@ static const struct mtk_soc_data mt7623_data = {
developerf4447452022-07-05 14:02:53 +080058 .required_clks = MT7623_CLKS_BITMAP,
59 .required_pctl = true,
60 .has_sram = false,
61+ .hash_way = 2,
62 .offload_version = 2,
developer0c6c5252022-07-12 11:59:21 +080063 .txrx = {
64 .txd_size = sizeof(struct mtk_tx_dma),
65 .rxd_size = sizeof(struct mtk_rx_dma),
66 .dma_max_len = MTK_TX_DMA_BUF_LEN,
67 .dma_len_offset = MTK_TX_DMA_BUF_SHIFT,
68 },
developerf4447452022-07-05 14:02:53 +080069 };
70
developer0c6c5252022-07-12 11:59:21 +080071@@ -3974,12 +3979,13 @@ static const struct mtk_soc_data mt7986_data = {
developerf4447452022-07-05 14:02:53 +080072 .required_clks = MT7986_CLKS_BITMAP,
73 .required_pctl = false,
74 .has_sram = true,
75+ .hash_way = 4,
76 .offload_version = 2,
developer0c6c5252022-07-12 11:59:21 +080077 .txrx = {
78 .txd_size = sizeof(struct mtk_tx_dma_v2),
79 .rxd_size = sizeof(struct mtk_rx_dma_v2),
80 .dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
81 .dma_len_offset = MTK_TX_DMA_BUF_SHIFT_V2,
82 },
developerf4447452022-07-05 14:02:53 +080083 };
84
developer0c6c5252022-07-12 11:59:21 +080085@@ -3984,12 +3990,14 @@ static const struct mtk_soc_data mt7981_data = {
developerf4447452022-07-05 14:02:53 +080086 .required_clks = MT7981_CLKS_BITMAP,
87 .required_pctl = false,
88 .has_sram = true,
89+ .hash_way = 4,
90+ .offload_version = 2,
developer0c6c5252022-07-12 11:59:21 +080091 .txrx = {
92 .txd_size = sizeof(struct mtk_tx_dma_v2),
93 .rxd_size = sizeof(struct mtk_rx_dma_v2),
94 .dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
95 .dma_len_offset = MTK_TX_DMA_BUF_SHIFT_V2,
96 },
developerf4447452022-07-05 14:02:53 +080097 };
98
99 static const struct mtk_soc_data rt5350_data = {
100diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
101index 4a69bd0..35a7543 100644
102--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
103+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
104@@ -1188,6 +1188,7 @@ struct mtk_soc_data {
105 u32 caps;
106 u32 required_clks;
107 bool required_pctl;
108+ u8 hash_way;
109 u8 offload_version;
110 netdev_features_t hw_features;
111 bool has_sram;
112diff --git a/drivers/net/ethernet/mediatek/mtk_ppe.c b/drivers/net/ethernet/mediatek/mtk_ppe.c
113index e4d50eb..918aa22 100755
114--- a/drivers/net/ethernet/mediatek/mtk_ppe.c
115+++ b/drivers/net/ethernet/mediatek/mtk_ppe.c
116@@ -88,7 +88,7 @@ static void mtk_ppe_cache_enable(struct mtk_ppe *ppe, bool enable)
117 enable * MTK_PPE_CACHE_CTL_EN);
118 }
119
120-static u32 mtk_ppe_hash_entry(struct mtk_foe_entry *e)
121+static u32 mtk_ppe_hash_entry(struct mtk_ppe *ppe, struct mtk_foe_entry *e)
122 {
123 u32 hv1, hv2, hv3;
124 u32 hash;
125@@ -122,7 +122,7 @@ static u32 mtk_ppe_hash_entry(struct mtk_foe_entry *e)
126 hash = (hash >> 24) | ((hash & 0xffffff) << 8);
127 hash ^= hv1 ^ hv2 ^ hv3;
128 hash ^= hash >> 16;
129- hash <<= 2;
130+ hash <<= (ffs(ppe->way) - 1);
131 hash &= MTK_PPE_ENTRIES - 1;
132
133 return hash;
134@@ -542,10 +542,10 @@ int mtk_foe_entry_commit(struct mtk_ppe *ppe, struct mtk_flow_entry *entry)
135 if (type == MTK_PPE_PKT_TYPE_BRIDGE)
136 return mtk_foe_entry_commit_l2(ppe, entry);
137
138- hash = mtk_ppe_hash_entry(&entry->data);
139+ hash = mtk_ppe_hash_entry(ppe, &entry->data);
140 entry->hash = 0xffff;
141 spin_lock_bh(&ppe_lock);
142- hlist_add_head(&entry->list, &ppe->foe_flow[hash / 4]);
143+ hlist_add_head(&entry->list, &ppe->foe_flow[hash / ppe->way]);
144 spin_unlock_bh(&ppe_lock);
145
146 return 0;
147@@ -569,7 +569,7 @@ mtk_foe_entry_commit_subflow(struct mtk_ppe *ppe, struct mtk_flow_entry *entry,
148 flow_info->l2_data.base_flow = entry;
149 flow_info->type = MTK_FLOW_TYPE_L2_SUBFLOW;
150 flow_info->hash = hash;
151- hlist_add_head(&flow_info->list, &ppe->foe_flow[hash / 4]);
152+ hlist_add_head(&flow_info->list, &ppe->foe_flow[hash / ppe->way]);
153 hlist_add_head(&flow_info->l2_data.list, &entry->l2_flows);
154
155 hwe = &ppe->foe_table[hash];
156@@ -593,7 +593,7 @@ mtk_foe_entry_commit_subflow(struct mtk_ppe *ppe, struct mtk_flow_entry *entry,
157
158 void __mtk_ppe_check_skb(struct mtk_ppe *ppe, struct sk_buff *skb, u16 hash)
159 {
160- struct hlist_head *head = &ppe->foe_flow[hash / 4];
161+ struct hlist_head *head = &ppe->foe_flow[hash / ppe->way];
162 struct mtk_foe_entry *hwe = &ppe->foe_table[hash];
163 struct mtk_flow_entry *entry;
164 struct mtk_foe_bridge key = {};
165@@ -676,12 +676,12 @@ int mtk_foe_entry_idle_time(struct mtk_ppe *ppe, struct mtk_flow_entry *entry)
166 return __mtk_foe_entry_idle_time(ppe, entry->data.ib1);
167 }
168
169-struct mtk_ppe *mtk_ppe_init(struct mtk_eth *eth, void __iomem *base,
170- int version, int id)
171+struct mtk_ppe *mtk_ppe_init(struct mtk_eth *eth, void __iomem *base, int version, int way, int id)
172 {
173 struct device *dev = eth->dev;
174 struct mtk_foe_entry *foe;
175 struct mtk_ppe *ppe;
176+ struct hlist_head *flow;
177
178 ppe = devm_kzalloc(dev, sizeof(*ppe), GFP_KERNEL);
179 if (!ppe)
180@@ -695,6 +696,7 @@ struct mtk_ppe *mtk_ppe_init(struct mtk_eth *eth, void __iomem *base, int versio
181 ppe->eth = eth;
182 ppe->dev = dev;
183 ppe->version = version;
184+ ppe->way = way;
185 ppe->id = id;
186
187 foe = dmam_alloc_coherent(ppe->dev, MTK_PPE_ENTRIES * sizeof(*foe),
188@@ -704,6 +706,13 @@ struct mtk_ppe *mtk_ppe_init(struct mtk_eth *eth, void __iomem *base, int versio
189
190 ppe->foe_table = foe;
191
192+ flow = devm_kzalloc(dev, (MTK_PPE_ENTRIES / way) * sizeof(*flow),
193+ GFP_KERNEL);
194+ if (!flow)
195+ return NULL;
196+
197+ ppe->foe_flow = flow;
198+
199 return ppe;
200 }
201
202diff --git a/drivers/net/ethernet/mediatek/mtk_ppe.h b/drivers/net/ethernet/mediatek/mtk_ppe.h
203index 21cc551..3d6928c 100644
204--- a/drivers/net/ethernet/mediatek/mtk_ppe.h
205+++ b/drivers/net/ethernet/mediatek/mtk_ppe.h
206@@ -276,19 +276,20 @@ struct mtk_ppe {
207 void __iomem *base;
208 int version;
209 int id;
210+ int way;
211
212 struct mtk_foe_entry *foe_table;
213 dma_addr_t foe_phys;
214
215 u16 foe_check_time[MTK_PPE_ENTRIES];
216- struct hlist_head foe_flow[MTK_PPE_ENTRIES / 2];
217+ struct hlist_head *foe_flow;
218
219 struct rhashtable l2_flows;
220
221 void *acct_table;
222 };
223
224-struct mtk_ppe *mtk_ppe_init(struct mtk_eth *eth, void __iomem *base, int version, int id);
225+struct mtk_ppe *mtk_ppe_init(struct mtk_eth *eth, void __iomem *base, int version, int way, int id);
226 int mtk_ppe_start(struct mtk_ppe *ppe);
227 int mtk_ppe_stop(struct mtk_ppe *ppe);
228