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developer3abe1ad2022-01-24 11:13:32 +08001/* Copyright (C) 2021-2022 Mediatek Inc. */
2#ifndef __ATENL_H
3#define __ATENL_H
4
5#include <arpa/inet.h>
6#include <errno.h>
7#include <fcntl.h>
8#include <limits.h>
9#include <linux/nl80211.h>
10#include <net/if.h>
11#include <stdbool.h>
12#include <stdio.h>
13#include <stdlib.h>
14#include <unistd.h>
15
16#include "nl.h"
17#include "util.h"
developer5698c9c2022-05-30 16:40:23 +080018#include "debug.h"
developer3abe1ad2022-01-24 11:13:32 +080019
developer22227f42022-10-07 15:54:07 +080020#define BRIDGE_NAME_OPENWRT "br-lan"
21#define BRIDGE_NAME_RDKB "brlan0"
developerf90c9af2022-12-28 22:40:23 +080022#define ETH_P_RACFG 0x2880
developer3abe1ad2022-01-24 11:13:32 +080023#define RACFG_PKT_MAX_SIZE 1600
developerf90c9af2022-12-28 22:40:23 +080024#define RACFG_HLEN 12
25#define RACFG_MAGIC_NO 0x18142880
26#define PRE_CAL_INFO 16
developer11f4a0b2023-03-31 17:43:25 +080027#define DPD_INFO_CH_SHIFT 30
28#define DPD_INFO_2G_SHIFT 20
29#define DPD_INFO_5G_SHIFT 10
developer071927d2022-08-31 20:39:29 +080030#define DPD_INFO_6G_SHIFT 0
developer11f4a0b2023-03-31 17:43:25 +080031#define DPD_INFO_MASK GENMASK(9, 0)
developer071927d2022-08-31 20:39:29 +080032#define MT_EE_CAL_UNIT 1024
developer3abe1ad2022-01-24 11:13:32 +080033
34#define RACFG_CMD_TYPE_MASK GENMASK(14, 0)
35#define RACFG_CMD_TYPE_ETHREQ BIT(3)
36#define RACFG_CMD_TYPE_PLATFORM_MODULE GENMASK(4, 3)
37
developer3abe1ad2022-01-24 11:13:32 +080038#define set_band_val(_an, _band, _field, _val) \
39 _an->anb[_band]._field = (_val)
40#define get_band_val(_an, _band, _field) \
41 (_an->anb[_band]._field)
42
43enum atenl_rf_mode {
44 ATENL_RF_MODE_NORMAL,
45 ATENL_RF_MODE_TEST,
46 ATENL_RF_MODE_ICAP,
47 ATENL_RF_MODE_ICAP_OVERLAP,
48
49 __ATENL_RF_MODE_MAX,
50};
51
52struct atenl_rx_stat {
53 u64 total;
54 u64 ok_cnt;
55 u64 err_cnt;
56 u64 len_mismatch;
57};
58
59struct atenl_band {
60 bool valid;
61 u8 phy_idx;
62 u8 cap;
63 u8 chainmask;
64
65 enum mt76_testmode_state cur_state;
66 s8 tx_power;
67 enum atenl_rf_mode rf_mode;
68
69 bool use_tx_time;
developer5698c9c2022-05-30 16:40:23 +080070 u32 tx_time;
71 u32 tx_mpdu_len;
developer3abe1ad2022-01-24 11:13:32 +080072
73 bool reset_tx_cnt;
74 bool reset_rx_cnt;
75
76 /* history */
77 struct atenl_rx_stat rx_stat;
78};
79
developer5698c9c2022-05-30 16:40:23 +080080#define MAX_BAND_NUM 3
developer3abe1ad2022-01-24 11:13:32 +080081
82struct atenl {
83 struct atenl_band anb[MAX_BAND_NUM];
84 u16 chip_id;
developer5698c9c2022-05-30 16:40:23 +080085 u16 adie_id;
86 u8 sub_chip_id;
developer3abe1ad2022-01-24 11:13:32 +080087 u8 cur_band;
88
89 u8 mac_addr[ETH_ALEN];
developer22227f42022-10-07 15:54:07 +080090 char *bridge_name;
developer3abe1ad2022-01-24 11:13:32 +080091 bool unicast;
92 int sock_eth;
developer3abe1ad2022-01-24 11:13:32 +080093
94 const char *mtd_part;
95 u32 mtd_offset;
developerf90c9af2022-12-28 22:40:23 +080096 u8 band_idx;
developer3abe1ad2022-01-24 11:13:32 +080097 u8 *eeprom_data;
98 int eeprom_fd;
99 u16 eeprom_size;
developer071927d2022-08-31 20:39:29 +0800100 u32 eeprom_prek_offs;
101
102 u8 *cal;
103 u32 cal_info[5];
developer3abe1ad2022-01-24 11:13:32 +0800104
105 bool cmd_mode;
developer5698c9c2022-05-30 16:40:23 +0800106
107 /* intermediate data */
108 u8 ibf_mcs;
109 u8 ibf_ant;
developer3abe1ad2022-01-24 11:13:32 +0800110};
111
112struct atenl_cmd_hdr {
113 __be32 magic_no;
114 __be16 cmd_type;
115 __be16 cmd_id;
116 __be16 len;
117 __be16 seq;
118 u8 data[2048];
119} __attribute__((packed));
120
121enum atenl_cmd {
122 HQA_CMD_UNKNOWN,
123 HQA_CMD_LEGACY, /* legacy or deprecated */
124
125 HQA_CMD_OPEN_ADAPTER,
126 HQA_CMD_CLOSE_ADAPTER,
127 HQA_CMD_GET_CHIP_ID,
128 HQA_CMD_GET_SUB_CHIP_ID,
129 HQA_CMD_SET_TX_BW,
130 HQA_CMD_SET_TX_PKT_BW,
131 HQA_CMD_SET_TX_PRI_BW,
132 HQA_CMD_GET_TX_INFO,
133 HQA_CMD_SET_TX_PATH,
134 HQA_CMD_SET_TX_POWER,
135 HQA_CMD_SET_TX_POWER_MANUAL,
136 HQA_CMD_SET_RF_MODE,
137 HQA_CMD_SET_RX_PATH,
138 HQA_CMD_SET_RX_PKT_LEN,
139 HQA_CMD_SET_FREQ_OFFSET,
140 HQA_CMD_SET_TSSI,
141 HQA_CMD_SET_CFG,
142 HQA_CMD_SET_RU,
143 HQA_CMD_SET_BAND,
developer5698c9c2022-05-30 16:40:23 +0800144 HQA_CMD_SET_EEPROM_TO_FW,
developer3abe1ad2022-01-24 11:13:32 +0800145 HQA_CMD_READ_MAC_BBP_REG,
developer5698c9c2022-05-30 16:40:23 +0800146 HQA_CMD_READ_MAC_BBP_REG_QA,
developer3abe1ad2022-01-24 11:13:32 +0800147 HQA_CMD_READ_RF_REG,
148 HQA_CMD_READ_EEPROM_BULK,
149 HQA_CMD_READ_TEMPERATURE,
150 HQA_CMD_WRITE_MAC_BBP_REG,
151 HQA_CMD_WRITE_RF_REG,
152 HQA_CMD_WRITE_EEPROM_BULK,
153 HQA_CMD_WRITE_BUFFER_DONE,
154 HQA_CMD_GET_BAND,
155 HQA_CMD_GET_CFG,
156 HQA_CMD_GET_TX_POWER,
157 HQA_CMD_GET_TX_TONE_POWER,
158 HQA_CMD_GET_EFUSE_FREE_BLOCK,
159 HQA_CMD_GET_FREQ_OFFSET,
160 HQA_CMD_GET_FW_INFO,
161 HQA_CMD_GET_RX_INFO,
162 HQA_CMD_GET_RF_CAP,
163 HQA_CMD_CHECK_EFUSE_MODE,
164 HQA_CMD_CHECK_EFUSE_MODE_TYPE,
165 HQA_CMD_CHECK_EFUSE_MODE_NATIVE,
166 HQA_CMD_ANT_SWAP_CAP,
167 HQA_CMD_RESET_TX_RX_COUNTER,
168 HQA_CMD_CONTINUOUS_TX,
169
170 HQA_CMD_EXT,
171 HQA_CMD_ERR,
172
173 __HQA_CMD_MAX_NUM,
174};
175
176enum atenl_ext_cmd {
177 HQA_EXT_CMD_UNSPEC,
178
179 HQA_EXT_CMD_SET_CHANNEL,
180 HQA_EXT_CMD_SET_TX,
181 HQA_EXT_CMD_START_TX,
182 HQA_EXT_CMD_START_RX,
183 HQA_EXT_CMD_STOP_TX,
184 HQA_EXT_CMD_STOP_RX,
185 HQA_EXT_CMD_SET_TX_TIME_OPT,
186
187 HQA_EXT_CMD_OFF_CH_SCAN,
188
189 HQA_EXT_CMD_IBF_SET_VAL,
190 HQA_EXT_CMD_IBF_GET_STATUS,
191 HQA_EXT_CMD_IBF_PROF_UPDATE_ALL,
192
193 HQA_EXT_CMD_ERR,
194
195 __HQA_EXT_CMD_MAX_NUM,
196};
197
198struct atenl_data {
199 u8 buf[RACFG_PKT_MAX_SIZE];
200 int len;
developer5698c9c2022-05-30 16:40:23 +0800201 u16 cmd_id;
202 u8 ext_id;
developer3abe1ad2022-01-24 11:13:32 +0800203 enum atenl_cmd cmd;
developer3abe1ad2022-01-24 11:13:32 +0800204 enum atenl_ext_cmd ext_cmd;
205};
206
developer5698c9c2022-05-30 16:40:23 +0800207struct atenl_ops {
developer3abe1ad2022-01-24 11:13:32 +0800208 int (*ops)(struct atenl *an, struct atenl_data *data);
developer5698c9c2022-05-30 16:40:23 +0800209 u8 cmd;
210 u8 flags;
211 u16 cmd_id;
212 u16 resp_len;
developer3abe1ad2022-01-24 11:13:32 +0800213};
214
developer5698c9c2022-05-30 16:40:23 +0800215#define ATENL_OPS_FLAG_EXT_CMD BIT(0)
216#define ATENL_OPS_FLAG_LEGACY BIT(1)
217#define ATENL_OPS_FLAG_SKIP BIT(2)
218
developer3abe1ad2022-01-24 11:13:32 +0800219static inline struct atenl_cmd_hdr * atenl_hdr(struct atenl_data *data)
220{
221 u8 *hqa_data = (u8 *)data->buf + ETH_HLEN;
222
223 return (struct atenl_cmd_hdr *)hqa_data;
224}
225
developer3abe1ad2022-01-24 11:13:32 +0800226enum atenl_phy_type {
227 ATENL_PHY_TYPE_CCK,
228 ATENL_PHY_TYPE_OFDM,
229 ATENL_PHY_TYPE_HT,
230 ATENL_PHY_TYPE_HT_GF,
231 ATENL_PHY_TYPE_VHT,
232 ATENL_PHY_TYPE_HE_SU = 8,
233 ATENL_PHY_TYPE_HE_EXT_SU,
234 ATENL_PHY_TYPE_HE_TB,
235 ATENL_PHY_TYPE_HE_MU,
developer77215642023-05-15 13:52:35 +0800236 ATENL_PHY_TYPE_EHT_SU = 13,
237 ATENL_PHY_TYPE_EHT_TRIG,
238 ATENL_PHY_TYPE_EHT_MU,
developer3abe1ad2022-01-24 11:13:32 +0800239};
240
241enum atenl_e2p_mode {
242 E2P_EFUSE_MODE = 1,
243 E2P_FLASH_MODE,
244 E2P_EEPROM_MODE,
245 E2P_BIN_MODE,
246};
247
248enum atenl_band_type {
249 BAND_TYPE_UNUSE,
250 BAND_TYPE_2G,
251 BAND_TYPE_5G,
252 BAND_TYPE_2G_5G,
253 BAND_TYPE_6G,
254 BAND_TYPE_2G_6G,
255 BAND_TYPE_5G_6G,
256 BAND_TYPE_2G_5G_6G,
257};
258
259enum atenl_ch_band {
260 CH_BAND_2GHZ,
261 CH_BAND_5GHZ,
262 CH_BAND_6GHZ,
263};
264
265/* for mt7915 */
266enum {
267 MT_EE_BAND_SEL_DEFAULT,
268 MT_EE_BAND_SEL_5GHZ,
269 MT_EE_BAND_SEL_2GHZ,
270 MT_EE_BAND_SEL_DUAL,
271};
272
273/* for mt7916/mt7986 */
274enum {
275 MT_EE_BAND_SEL_2G,
276 MT_EE_BAND_SEL_5G,
277 MT_EE_BAND_SEL_6G,
278 MT_EE_BAND_SEL_5G_6G,
279};
280
developerf90c9af2022-12-28 22:40:23 +0800281/* for mt7996 */
282enum {
283 MT_EE_EAGLE_BAND_SEL_DEFAULT,
284 MT_EE_EAGLE_BAND_SEL_2GHZ,
285 MT_EE_EAGLE_BAND_SEL_5GHZ,
286 MT_EE_EAGLE_BAND_SEL_6GHZ,
287 MT_EE_EAGLE_BAND_SEL_5GHZ_6GHZ,
288};
289
developer3abe1ad2022-01-24 11:13:32 +0800290#define MT_EE_WIFI_CONF 0x190
291#define MT_EE_WIFI_CONF0_BAND_SEL GENMASK(7, 6)
developerf90c9af2022-12-28 22:40:23 +0800292#define MT_EE_WIFI_EAGLE_CONF0_BAND_SEL GENMASK(2, 0)
293#define MT_EE_WIFI_EAGLE_CONF1_BAND_SEL GENMASK(5, 3)
294#define MT_EE_WIFI_EAGLE_CONF2_BAND_SEL GENMASK(2, 0)
developer3abe1ad2022-01-24 11:13:32 +0800295
296enum {
297 MT7976_ONE_ADIE_DBDC = 0x7,
298 MT7975_ONE_ADIE_SINGLE_BAND = 0x8, /* AX7800 */
299 MT7976_ONE_ADIE_SINGLE_BAND = 0xa, /* AX7800 */
300 MT7975_DUAL_ADIE_DBDC = 0xd, /* AX6000 */
301 MT7976_DUAL_ADIE_DBDC = 0xf, /* AX6000 */
302};
303
304enum {
305 TEST_CBW_20MHZ,
306 TEST_CBW_40MHZ,
307 TEST_CBW_80MHZ,
308 TEST_CBW_10MHZ,
309 TEST_CBW_5MHZ,
310 TEST_CBW_160MHZ,
311 TEST_CBW_8080MHZ,
developer77215642023-05-15 13:52:35 +0800312 TEST_CBW_320MHZ = 12,
developer3abe1ad2022-01-24 11:13:32 +0800313
developer77215642023-05-15 13:52:35 +0800314 TEST_CBW_MAX = TEST_CBW_320MHZ,
developer3abe1ad2022-01-24 11:13:32 +0800315};
316
317struct atenl_rx_info_hdr {
318 __be32 type;
319 __be32 ver;
320 __be32 val;
321 __be32 len;
322} __attribute__((packed));
323
324struct atenl_rx_info_band {
325 __be32 mac_rx_fcs_err_cnt;
326 __be32 mac_rx_mdrdy_cnt;
327 __be32 mac_rx_len_mismatch;
328 __be32 mac_rx_fcs_ok_cnt;
329 __be32 phy_rx_fcs_err_cnt_cck;
330 __be32 phy_rx_fcs_err_cnt_ofdm;
331 __be32 phy_rx_pd_cck;
332 __be32 phy_rx_pd_ofdm;
333 __be32 phy_rx_sig_err_cck;
334 __be32 phy_rx_sfd_err_cck;
335 __be32 phy_rx_sig_err_ofdm;
336 __be32 phy_rx_tag_err_ofdm;
337 __be32 phy_rx_mdrdy_cnt_cck;
338 __be32 phy_rx_mdrdy_cnt_ofdm;
339} __attribute__((packed));
340
341struct atenl_rx_info_path {
342 __be32 rcpi;
343 __be32 rssi;
344 __be32 fagc_ib_rssi;
345 __be32 fagc_wb_rssi;
346 __be32 inst_ib_rssi;
347 __be32 inst_wb_rssi;
348} __attribute__((packed));
349
350struct atenl_rx_info_user {
351 __be32 freq_offset;
352 __be32 snr;
353 __be32 fcs_error_cnt;
354} __attribute__((packed));
355
356struct atenl_rx_info_comm {
357 __be32 rx_fifo_full;
358 __be32 aci_hit_low;
359 __be32 aci_hit_high;
360 __be32 mu_pkt_count;
361 __be32 sig_mcs;
362 __be32 sinr;
363 __be32 driver_rx_count;
364} __attribute__((packed));
365
366enum atenl_ibf_action {
367 TXBF_ACT_INIT = 1,
368 TXBF_ACT_CHANNEL,
369 TXBF_ACT_MCS,
370 TXBF_ACT_POWER,
371 TXBF_ACT_TX_ANT,
372 TXBF_ACT_RX_START,
373 TXBF_ACT_RX_ANT,
374 TXBF_ACT_LNA_GAIN,
375 TXBF_ACT_IBF_PHASE_COMP,
376 TXBF_ACT_TX_PKT,
377 TXBF_ACT_IBF_PROF_UPDATE,
378 TXBF_ACT_EBF_PROF_UPDATE,
379 TXBF_ACT_IBF_PHASE_CAL,
380 TXBF_ACT_IBF_PHASE_E2P_UPDATE = 16,
381};
382
developer071927d2022-08-31 20:39:29 +0800383enum prek_ops {
384 PREK_SYNC_ALL = 1,
385 PREK_SYNC_GROUP,
386 PREK_SYNC_DPD_2G,
387 PREK_SYNC_DPD_5G,
388 PREK_SYNC_DPD_6G,
389 PREK_CLEAN_GROUP,
390 PREK_CLEAN_DPD,
391};
392
developer3abe1ad2022-01-24 11:13:32 +0800393static inline bool is_mt7915(struct atenl *an)
394{
395 return an->chip_id == 0x7915;
396}
397
398static inline bool is_mt7916(struct atenl *an)
399{
400 return (an->chip_id == 0x7916) || (an->chip_id == 0x7906);
401}
402
403static inline bool is_mt7986(struct atenl *an)
404{
405 return an->chip_id == 0x7986;
406}
407
developerf90c9af2022-12-28 22:40:23 +0800408static inline bool is_mt7996(struct atenl *an)
409{
410 return an->chip_id == 0x7990;
411}
412
developer3abe1ad2022-01-24 11:13:32 +0800413int atenl_eth_init(struct atenl *an);
414int atenl_eth_recv(struct atenl *an, struct atenl_data *data);
415int atenl_eth_send(struct atenl *an, struct atenl_data *data);
developer5698c9c2022-05-30 16:40:23 +0800416int atenl_hqa_proc_cmd(struct atenl *an);
developer3abe1ad2022-01-24 11:13:32 +0800417int atenl_nl_process(struct atenl *an, struct atenl_data *data);
418int atenl_nl_process_many(struct atenl *an, struct atenl_data *data);
419int atenl_nl_check_mtd(struct atenl *an);
420int atenl_nl_write_eeprom(struct atenl *an, u32 offset, u8 *val, int len);
developer9b7cdad2022-03-10 14:24:55 +0800421int atenl_nl_write_efuse_all(struct atenl *an);
developer3abe1ad2022-01-24 11:13:32 +0800422int atenl_nl_update_buffer_mode(struct atenl *an);
423int atenl_nl_set_state(struct atenl *an, u8 band,
424 enum mt76_testmode_state state);
developer5698c9c2022-05-30 16:40:23 +0800425int atenl_nl_set_aid(struct atenl *an, u8 band, u8 aid);
developer071927d2022-08-31 20:39:29 +0800426int atenl_nl_precal_sync_from_driver(struct atenl *an, enum prek_ops ops);
developer44ae8e92023-07-21 13:42:14 +0800427void atenl_get_ibf_cal_result(struct atenl *an);
developer3abe1ad2022-01-24 11:13:32 +0800428int atenl_eeprom_init(struct atenl *an, u8 phy_idx);
429void atenl_eeprom_close(struct atenl *an);
430int atenl_eeprom_write_mtd(struct atenl *an);
developer071927d2022-08-31 20:39:29 +0800431int atenl_eeprom_update_precal(struct atenl *an, int write_offs, int size);
developer3abe1ad2022-01-24 11:13:32 +0800432int atenl_eeprom_read_from_driver(struct atenl *an, u32 offset, int len);
433void atenl_eeprom_cmd_handler(struct atenl *an, u8 phy_idx, char *cmd);
434u16 atenl_get_center_channel(u8 bw, u8 ch_band, u16 ctrl_ch);
435int atenl_reg_read(struct atenl *an, u32 offset, u32 *res);
436int atenl_reg_write(struct atenl *an, u32 offset, u32 val);
developer5698c9c2022-05-30 16:40:23 +0800437int atenl_rf_read(struct atenl *an, u32 wf_sel, u32 offset, u32 *res);
438int atenl_rf_write(struct atenl *an, u32 wf_sel, u32 offset, u32 val);
developer3abe1ad2022-01-24 11:13:32 +0800439
440#endif