developer | c2cfe0f | 2023-09-22 04:11:09 +0800 | [diff] [blame] | 1 | From e13a81689d5df310915182b8b7f2858ac65a0472 Mon Sep 17 00:00:00 2001 |
developer | 064da3c | 2023-06-13 15:57:26 +0800 | [diff] [blame] | 2 | From: mtk27745 <rex.lu@mediatek.com> |
| 3 | Date: Tue, 23 May 2023 12:06:29 +0800 |
developer | c2cfe0f | 2023-09-22 04:11:09 +0800 | [diff] [blame] | 4 | Subject: [PATCH 2008/2012] wifi: mt76: add SER support for wed3.0 |
developer | 064da3c | 2023-06-13 15:57:26 +0800 | [diff] [blame] | 5 | |
| 6 | Change-Id: I2711b9dc336fca9a1ae32a8fbf27810a7e27b1e3 |
| 7 | --- |
| 8 | dma.c | 7 +++++-- |
developer | c2cfe0f | 2023-09-22 04:11:09 +0800 | [diff] [blame] | 9 | mt7996/dma.c | 42 +++++++++++++++++++++++++++++++++++++++--- |
developer | 064da3c | 2023-06-13 15:57:26 +0800 | [diff] [blame] | 10 | mt7996/mac.c | 49 ++++++++++++++++++++++++++++++++++++++++++++++++- |
| 11 | mt7996/mmio.c | 47 +++++++++++++++++++++++++++++++++++++++++++++++ |
developer | c2cfe0f | 2023-09-22 04:11:09 +0800 | [diff] [blame] | 12 | 4 files changed, 139 insertions(+), 6 deletions(-) |
developer | 064da3c | 2023-06-13 15:57:26 +0800 | [diff] [blame] | 13 | |
| 14 | diff --git a/dma.c b/dma.c |
developer | c2cfe0f | 2023-09-22 04:11:09 +0800 | [diff] [blame] | 15 | index 8097a3121..bfe188134 100644 |
developer | 064da3c | 2023-06-13 15:57:26 +0800 | [diff] [blame] | 16 | --- a/dma.c |
| 17 | +++ b/dma.c |
developer | c2cfe0f | 2023-09-22 04:11:09 +0800 | [diff] [blame] | 18 | @@ -772,8 +772,9 @@ int mt76_dma_wed_setup(struct mt76_dev *dev, struct mt76_queue *q, bool reset) |
developer | 064da3c | 2023-06-13 15:57:26 +0800 | [diff] [blame] | 19 | q->head = q->ndesc - 1; |
| 20 | q->queued = q->ndesc - 1; |
| 21 | } |
| 22 | + q->flags = flags; |
| 23 | } else { |
| 24 | - ret = mtk_wed_device_rx_ring_setup(wed, ring, q->regs, 0); |
| 25 | + ret = mtk_wed_device_rx_ring_setup(wed, ring, q->regs, reset); |
| 26 | if (!ret) |
| 27 | q->wed_regs = wed->rx_ring[ring].reg_base; |
| 28 | } |
developer | c2cfe0f | 2023-09-22 04:11:09 +0800 | [diff] [blame] | 29 | @@ -904,7 +905,9 @@ done: |
developer | 064da3c | 2023-06-13 15:57:26 +0800 | [diff] [blame] | 30 | |
| 31 | /* reset WED rx queues */ |
| 32 | mt76_dma_wed_setup(dev, q, true); |
| 33 | - if (q->flags != MT_WED_Q_TXFREE) { |
| 34 | + if (q->flags != MT_WED_Q_TXFREE && |
| 35 | + !((q->flags & MT_QFLAG_RRO) && |
| 36 | + mtk_wed_device_active(&dev->mmio.wed))) { |
| 37 | mt76_dma_sync_idx(dev, q); |
| 38 | mt76_dma_rx_fill(dev, q); |
| 39 | } |
| 40 | diff --git a/mt7996/dma.c b/mt7996/dma.c |
developer | c2cfe0f | 2023-09-22 04:11:09 +0800 | [diff] [blame] | 41 | index 309cc242e..9416d7947 100644 |
developer | 064da3c | 2023-06-13 15:57:26 +0800 | [diff] [blame] | 42 | --- a/mt7996/dma.c |
| 43 | +++ b/mt7996/dma.c |
developer | c2cfe0f | 2023-09-22 04:11:09 +0800 | [diff] [blame] | 44 | @@ -611,11 +611,35 @@ int mt7996_dma_init(struct mt7996_dev *dev) |
developer | 064da3c | 2023-06-13 15:57:26 +0800 | [diff] [blame] | 45 | return 0; |
| 46 | } |
| 47 | |
| 48 | +static void mt7996_dma_wed_reset(struct mt7996_dev *dev) |
| 49 | +{ |
| 50 | + struct mt76_dev *mdev = &dev->mt76; |
| 51 | + |
| 52 | + if (!test_bit(MT76_STATE_WED_RESET, &dev->mphy.state)) |
| 53 | + return; |
| 54 | + |
| 55 | + complete(&mdev->mmio.wed_reset); |
| 56 | + |
| 57 | + if (!wait_for_completion_timeout(&dev->mt76.mmio.wed_reset_complete, |
| 58 | + 3 * HZ)) |
| 59 | + dev_err(dev->mt76.dev, "wed reset complete timeout\n"); |
| 60 | +} |
| 61 | + |
| 62 | +static void |
| 63 | +mt7996_dma_reset_tx_queue(struct mt7996_dev *dev, struct mt76_queue *q) |
| 64 | +{ |
| 65 | + mt76_queue_reset(dev, q, false); |
| 66 | + if (mtk_wed_device_active(&dev->mt76.mmio.wed)) |
| 67 | + mt76_dma_wed_setup(&dev->mt76, q, true); |
| 68 | +} |
| 69 | + |
| 70 | void mt7996_dma_reset(struct mt7996_dev *dev, bool force) |
| 71 | { |
| 72 | struct mt76_phy *phy2 = dev->mt76.phys[MT_BAND1]; |
| 73 | struct mt76_phy *phy3 = dev->mt76.phys[MT_BAND2]; |
| 74 | u32 hif1_ofs = MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0); |
| 75 | + struct mtk_wed_device *wed = &dev->mt76.mmio.wed; |
| 76 | + struct mtk_wed_device *wed_ext = &dev->mt76.mmio.wed_ext; |
| 77 | int i; |
| 78 | |
| 79 | mt76_clear(dev, MT_WFDMA0_GLO_CFG, |
developer | c2cfe0f | 2023-09-22 04:11:09 +0800 | [diff] [blame] | 80 | @@ -649,21 +673,33 @@ void mt7996_dma_reset(struct mt7996_dev *dev, bool force) |
developer | 064da3c | 2023-06-13 15:57:26 +0800 | [diff] [blame] | 81 | if (force) |
| 82 | mt7996_wfsys_reset(dev); |
| 83 | |
| 84 | + if (dev->hif2 && mtk_wed_device_active(wed_ext)) |
| 85 | + mtk_wed_device_dma_reset(wed_ext); |
| 86 | + |
| 87 | + if (mtk_wed_device_active(wed)) |
| 88 | + mtk_wed_device_dma_reset(wed); |
| 89 | + |
| 90 | mt7996_dma_disable(dev, force); |
| 91 | + mt7996_dma_wed_reset(dev); |
| 92 | |
| 93 | /* reset hw queues */ |
| 94 | for (i = 0; i < __MT_TXQ_MAX; i++) { |
| 95 | - mt76_queue_reset(dev, dev->mphy.q_tx[i], false); |
| 96 | + mt7996_dma_reset_tx_queue(dev, dev->mphy.q_tx[i]); |
| 97 | if (phy2) |
| 98 | - mt76_queue_reset(dev, phy2->q_tx[i], false); |
| 99 | + mt7996_dma_reset_tx_queue(dev, phy2->q_tx[i]); |
| 100 | if (phy3) |
| 101 | - mt76_queue_reset(dev, phy3->q_tx[i], false); |
| 102 | + mt7996_dma_reset_tx_queue(dev, phy3->q_tx[i]); |
| 103 | } |
| 104 | |
| 105 | for (i = 0; i < __MT_MCUQ_MAX; i++) |
| 106 | mt76_queue_reset(dev, dev->mt76.q_mcu[i], false); |
| 107 | |
| 108 | mt76_for_each_q_rx(&dev->mt76, i) { |
| 109 | + if (mtk_wed_device_active(wed) && |
| 110 | + ((dev->mt76.q_rx[i].flags & MT_QFLAG_RRO) || |
| 111 | + dev->mt76.q_rx[i].flags == MT_WED_Q_TXFREE)) |
| 112 | + continue; |
| 113 | + |
| 114 | mt76_queue_reset(dev, &dev->mt76.q_rx[i], false); |
| 115 | } |
| 116 | |
| 117 | diff --git a/mt7996/mac.c b/mt7996/mac.c |
developer | c2cfe0f | 2023-09-22 04:11:09 +0800 | [diff] [blame] | 118 | index e331594d3..f994203aa 100644 |
developer | 064da3c | 2023-06-13 15:57:26 +0800 | [diff] [blame] | 119 | --- a/mt7996/mac.c |
| 120 | +++ b/mt7996/mac.c |
developer | c2cfe0f | 2023-09-22 04:11:09 +0800 | [diff] [blame] | 121 | @@ -1804,6 +1804,10 @@ mt7996_mac_restart(struct mt7996_dev *dev) |
developer | 064da3c | 2023-06-13 15:57:26 +0800 | [diff] [blame] | 122 | /* disable all tx/rx napi */ |
| 123 | mt76_worker_disable(&dev->mt76.tx_worker); |
| 124 | mt76_for_each_q_rx(mdev, i) { |
| 125 | + if (mtk_wed_device_active(&dev->mt76.mmio.wed) && |
| 126 | + (mdev->q_rx[i].flags & MT_QFLAG_RRO)) |
| 127 | + continue; |
| 128 | + |
| 129 | if (mdev->q_rx[i].ndesc) |
| 130 | napi_disable(&dev->mt76.napi[i]); |
| 131 | } |
developer | c2cfe0f | 2023-09-22 04:11:09 +0800 | [diff] [blame] | 132 | @@ -1817,6 +1821,10 @@ mt7996_mac_restart(struct mt7996_dev *dev) |
developer | 064da3c | 2023-06-13 15:57:26 +0800 | [diff] [blame] | 133 | |
| 134 | local_bh_disable(); |
| 135 | mt76_for_each_q_rx(mdev, i) { |
| 136 | + if (mtk_wed_device_active(&dev->mt76.mmio.wed) && |
| 137 | + (mdev->q_rx[i].flags & MT_QFLAG_RRO)) |
| 138 | + continue; |
| 139 | + |
| 140 | if (mdev->q_rx[i].ndesc) { |
| 141 | napi_enable(&dev->mt76.napi[i]); |
| 142 | napi_schedule(&dev->mt76.napi[i]); |
developer | c2cfe0f | 2023-09-22 04:11:09 +0800 | [diff] [blame] | 143 | @@ -1991,6 +1999,13 @@ void mt7996_mac_reset_work(struct work_struct *work) |
developer | 064da3c | 2023-06-13 15:57:26 +0800 | [diff] [blame] | 144 | |
| 145 | dev_info(dev->mt76.dev,"\n%s L1 SER recovery start.", |
| 146 | wiphy_name(dev->mt76.hw->wiphy)); |
| 147 | + |
| 148 | + if (mtk_wed_device_active(&dev->mt76.mmio.wed_ext)) |
| 149 | + mtk_wed_device_stop(&dev->mt76.mmio.wed_ext); |
| 150 | + |
| 151 | + if (mtk_wed_device_active(&dev->mt76.mmio.wed)) |
| 152 | + mtk_wed_device_stop(&dev->mt76.mmio.wed); |
| 153 | + |
| 154 | ieee80211_stop_queues(mt76_hw(dev)); |
| 155 | if (phy2) |
| 156 | ieee80211_stop_queues(phy2->mt76->hw); |
developer | c2cfe0f | 2023-09-22 04:11:09 +0800 | [diff] [blame] | 157 | @@ -2014,8 +2029,13 @@ void mt7996_mac_reset_work(struct work_struct *work) |
developer | 064da3c | 2023-06-13 15:57:26 +0800 | [diff] [blame] | 158 | cancel_delayed_work_sync(&phy3->mt76->mac_work); |
| 159 | } |
| 160 | mt76_worker_disable(&dev->mt76.tx_worker); |
| 161 | - mt76_for_each_q_rx(&dev->mt76, i) |
| 162 | + mt76_for_each_q_rx(&dev->mt76, i) { |
| 163 | + if (mtk_wed_device_active(&dev->mt76.mmio.wed) && |
| 164 | + (dev->mt76.q_rx[i].flags & MT_QFLAG_RRO)) |
| 165 | + continue; |
| 166 | + |
| 167 | napi_disable(&dev->mt76.napi[i]); |
| 168 | + } |
| 169 | napi_disable(&dev->mt76.tx_napi); |
| 170 | |
| 171 | mutex_lock(&dev->mt76.mutex); |
developer | c2cfe0f | 2023-09-22 04:11:09 +0800 | [diff] [blame] | 172 | @@ -2038,6 +2058,29 @@ void mt7996_mac_reset_work(struct work_struct *work) |
| 173 | /* enable DMA Tx/Tx and interrupt */ |
| 174 | mt7996_dma_start(dev, false, false); |
developer | 064da3c | 2023-06-13 15:57:26 +0800 | [diff] [blame] | 175 | |
| 176 | + |
| 177 | + if (mtk_wed_device_active(&dev->mt76.mmio.wed)) { |
| 178 | + u32 wed_irq_mask = dev->mt76.mmio.irqmask | |
| 179 | + MT_INT_RRO_RX_DONE | |
| 180 | + MT_INT_TX_DONE_BAND2; |
| 181 | + |
| 182 | + if (mtk_wed_get_rx_capa(&dev->mt76.mmio.wed)) |
| 183 | + wed_irq_mask &= ~MT_INT_RX_DONE_RRO_IND; |
| 184 | + |
| 185 | + mt76_wr(dev, MT_INT_MASK_CSR, wed_irq_mask); |
| 186 | + |
| 187 | + mtk_wed_device_start_hwrro(&dev->mt76.mmio.wed, wed_irq_mask, true); |
| 188 | + mt7996_irq_enable(dev, wed_irq_mask); |
| 189 | + mt7996_irq_disable(dev, 0); |
| 190 | + } |
| 191 | + |
| 192 | + if (mtk_wed_device_active(&dev->mt76.mmio.wed_ext)) { |
| 193 | + mt76_wr(dev, MT_INT1_MASK_CSR, |
| 194 | + dev->mt76.mmio.irqmask | MT_INT_TX_DONE_BAND2); |
| 195 | + mtk_wed_device_start(&dev->mt76.mmio.wed_ext, |
| 196 | + dev->mt76.mmio.irqmask | MT_INT_TX_DONE_BAND2); |
| 197 | + } |
| 198 | + |
| 199 | clear_bit(MT76_MCU_RESET, &dev->mphy.state); |
| 200 | clear_bit(MT76_RESET, &dev->mphy.state); |
| 201 | if (phy2) |
developer | c2cfe0f | 2023-09-22 04:11:09 +0800 | [diff] [blame] | 202 | @@ -2047,6 +2090,10 @@ void mt7996_mac_reset_work(struct work_struct *work) |
developer | 064da3c | 2023-06-13 15:57:26 +0800 | [diff] [blame] | 203 | |
| 204 | local_bh_disable(); |
| 205 | mt76_for_each_q_rx(&dev->mt76, i) { |
| 206 | + if (mtk_wed_device_active(&dev->mt76.mmio.wed) && |
| 207 | + ((dev->mt76.q_rx[i].flags & MT_QFLAG_RRO))) |
| 208 | + continue; |
| 209 | + |
| 210 | napi_enable(&dev->mt76.napi[i]); |
| 211 | napi_schedule(&dev->mt76.napi[i]); |
| 212 | } |
| 213 | diff --git a/mt7996/mmio.c b/mt7996/mmio.c |
developer | c2cfe0f | 2023-09-22 04:11:09 +0800 | [diff] [blame] | 214 | index 1805d892f..940f94998 100644 |
developer | 064da3c | 2023-06-13 15:57:26 +0800 | [diff] [blame] | 215 | --- a/mt7996/mmio.c |
| 216 | +++ b/mt7996/mmio.c |
| 217 | @@ -6,9 +6,11 @@ |
| 218 | #include <linux/kernel.h> |
| 219 | #include <linux/module.h> |
| 220 | #include <linux/pci.h> |
| 221 | +#include <linux/rtnetlink.h> |
| 222 | |
| 223 | #include "mt7996.h" |
| 224 | #include "mac.h" |
| 225 | +#include "mcu.h" |
| 226 | #include "../trace.h" |
| 227 | #include "../dma.h" |
| 228 | |
developer | c2cfe0f | 2023-09-22 04:11:09 +0800 | [diff] [blame] | 229 | @@ -320,6 +322,43 @@ unmap: |
developer | 064da3c | 2023-06-13 15:57:26 +0800 | [diff] [blame] | 230 | mt7996_mmio_wed_release_rx_buf(wed); |
| 231 | return -ENOMEM; |
| 232 | } |
| 233 | + |
| 234 | +static int mt7996_mmio_wed_reset(struct mtk_wed_device *wed) |
| 235 | +{ |
| 236 | + struct mt76_dev *mdev = container_of(wed, struct mt76_dev, mmio.wed); |
| 237 | + struct mt7996_dev *dev = container_of(mdev, struct mt7996_dev, mt76); |
| 238 | + struct mt76_phy *mphy = &dev->mphy; |
| 239 | + int ret; |
| 240 | + |
| 241 | + ASSERT_RTNL(); |
| 242 | + |
| 243 | + if (test_and_set_bit(MT76_STATE_WED_RESET, &mphy->state)) |
| 244 | + return -EBUSY; |
| 245 | + |
| 246 | + ret = mt7996_mcu_set_ser(dev, UNI_CMD_SER_TRIGGER, UNI_CMD_SER_SET_RECOVER_L1, |
| 247 | + mphy->band_idx); |
| 248 | + if (ret) |
| 249 | + goto out; |
| 250 | + |
| 251 | + rtnl_unlock(); |
| 252 | + if (!wait_for_completion_timeout(&mdev->mmio.wed_reset, 20 * HZ)) { |
| 253 | + dev_err(mdev->dev, "wed reset timeout\n"); |
| 254 | + ret = -ETIMEDOUT; |
| 255 | + } |
| 256 | + rtnl_lock(); |
| 257 | +out: |
| 258 | + clear_bit(MT76_STATE_WED_RESET, &mphy->state); |
| 259 | + |
| 260 | + return ret; |
| 261 | +} |
| 262 | + |
| 263 | +static void mt7996_mmio_wed_reset_complete(struct mtk_wed_device *wed) |
| 264 | +{ |
| 265 | + struct mt76_dev *dev = container_of(wed, struct mt76_dev, mmio.wed); |
| 266 | + |
| 267 | + complete(&dev->mmio.wed_reset_complete); |
| 268 | +} |
| 269 | + |
| 270 | #endif |
| 271 | |
| 272 | int mt7996_mmio_wed_init(struct mt7996_dev *dev, void *pdev_ptr, |
developer | c2cfe0f | 2023-09-22 04:11:09 +0800 | [diff] [blame] | 273 | @@ -445,6 +484,14 @@ int mt7996_mmio_wed_init(struct mt7996_dev *dev, void *pdev_ptr, |
developer | 064da3c | 2023-06-13 15:57:26 +0800 | [diff] [blame] | 274 | wed->wlan.init_rx_buf = mt7996_mmio_wed_init_rx_buf; |
| 275 | wed->wlan.release_rx_buf = mt7996_mmio_wed_release_rx_buf; |
| 276 | wed->wlan.update_wo_rx_stats = NULL; |
| 277 | + if (hif2) { |
| 278 | + wed->wlan.reset = NULL; |
| 279 | + wed->wlan.reset_complete = NULL; |
| 280 | + } else { |
| 281 | + wed->wlan.reset = mt7996_mmio_wed_reset; |
| 282 | + wed->wlan.reset_complete = mt7996_mmio_wed_reset_complete; |
| 283 | + } |
| 284 | + |
| 285 | |
| 286 | if (mtk_wed_device_attach(wed)) |
| 287 | return 0; |
| 288 | -- |
| 289 | 2.39.2 |
| 290 | |