developer | c2cfe0f | 2023-09-22 04:11:09 +0800 | [diff] [blame] | 1 | From 7faad00dd85cec867c133a7d48ccb3b500719f94 Mon Sep 17 00:00:00 2001 |
developer | 1bc2ce2 | 2023-03-25 00:47:41 +0800 | [diff] [blame] | 2 | From: StanleyYP Wang <StanleyYP.Wang@mediatek.com> |
| 3 | Date: Wed, 1 Mar 2023 11:59:16 +0800 |
developer | c2cfe0f | 2023-09-22 04:11:09 +0800 | [diff] [blame] | 4 | Subject: [PATCH 1003/1024] wifi: mt76: testmode: add basic testmode support |
developer | 1bc2ce2 | 2023-03-25 00:47:41 +0800 | [diff] [blame] | 5 | |
| 6 | Signed-off-by: StanleyYP Wang <StanleyYP.Wang@mediatek.com> |
| 7 | --- |
| 8 | eeprom.c | 6 +- |
| 9 | mac80211.c | 3 +- |
developer | c2cfe0f | 2023-09-22 04:11:09 +0800 | [diff] [blame] | 10 | mt76.h | 35 +++ |
developer | 1bc2ce2 | 2023-03-25 00:47:41 +0800 | [diff] [blame] | 11 | mt76_connac_mcu.h | 2 + |
developer | c2cfe0f | 2023-09-22 04:11:09 +0800 | [diff] [blame] | 12 | mt7996/Makefile | 1 + |
developer | 1bc2ce2 | 2023-03-25 00:47:41 +0800 | [diff] [blame] | 13 | mt7996/eeprom.c | 35 ++- |
| 14 | mt7996/eeprom.h | 1 + |
| 15 | mt7996/init.c | 7 + |
developer | c2cfe0f | 2023-09-22 04:11:09 +0800 | [diff] [blame] | 16 | mt7996/mac.c | 3 +- |
developer | 064da3c | 2023-06-13 15:57:26 +0800 | [diff] [blame] | 17 | mt7996/main.c | 16 ++ |
| 18 | mt7996/mcu.c | 42 ++- |
developer | 1bc2ce2 | 2023-03-25 00:47:41 +0800 | [diff] [blame] | 19 | mt7996/mcu.h | 27 ++ |
developer | c2cfe0f | 2023-09-22 04:11:09 +0800 | [diff] [blame] | 20 | mt7996/mt7996.h | 23 ++ |
| 21 | mt7996/testmode.c | 674 ++++++++++++++++++++++++++++++++++++++++++++++ |
| 22 | mt7996/testmode.h | 297 ++++++++++++++++++++ |
| 23 | testmode.c | 78 ++++-- |
| 24 | testmode.h | 64 +++++ |
| 25 | tools/fields.c | 102 ++++++- |
| 26 | 18 files changed, 1382 insertions(+), 34 deletions(-) |
developer | 1bc2ce2 | 2023-03-25 00:47:41 +0800 | [diff] [blame] | 27 | create mode 100644 mt7996/testmode.c |
| 28 | create mode 100644 mt7996/testmode.h |
| 29 | |
| 30 | diff --git a/eeprom.c b/eeprom.c |
developer | c2cfe0f | 2023-09-22 04:11:09 +0800 | [diff] [blame] | 31 | index a07ca8440..437d8ca24 100644 |
developer | 1bc2ce2 | 2023-03-25 00:47:41 +0800 | [diff] [blame] | 32 | --- a/eeprom.c |
| 33 | +++ b/eeprom.c |
developer | c2cfe0f | 2023-09-22 04:11:09 +0800 | [diff] [blame] | 34 | @@ -94,8 +94,10 @@ static int mt76_get_of_epprom_from_mtd(struct mt76_dev *dev, void *eep, int offs |
developer | 1bc2ce2 | 2023-03-25 00:47:41 +0800 | [diff] [blame] | 35 | } |
| 36 | |
| 37 | #ifdef CONFIG_NL80211_TESTMODE |
| 38 | - dev->test_mtd.name = devm_kstrdup(dev->dev, part, GFP_KERNEL); |
| 39 | - dev->test_mtd.offset = offset; |
| 40 | + if (len == dev->eeprom.size) { |
| 41 | + dev->test_mtd.name = devm_kstrdup(dev->dev, part, GFP_KERNEL); |
| 42 | + dev->test_mtd.offset = offset; |
| 43 | + } |
| 44 | #endif |
| 45 | |
| 46 | out_put_node: |
| 47 | diff --git a/mac80211.c b/mac80211.c |
developer | c2cfe0f | 2023-09-22 04:11:09 +0800 | [diff] [blame] | 48 | index 12fcb2b01..5740ba061 100644 |
developer | 1bc2ce2 | 2023-03-25 00:47:41 +0800 | [diff] [blame] | 49 | --- a/mac80211.c |
| 50 | +++ b/mac80211.c |
developer | c2cfe0f | 2023-09-22 04:11:09 +0800 | [diff] [blame] | 51 | @@ -835,7 +835,8 @@ void mt76_rx(struct mt76_dev *dev, enum mt76_rxq_id q, struct sk_buff *skb) |
developer | 1bc2ce2 | 2023-03-25 00:47:41 +0800 | [diff] [blame] | 52 | } |
| 53 | |
| 54 | #ifdef CONFIG_NL80211_TESTMODE |
| 55 | - if (phy->test.state == MT76_TM_STATE_RX_FRAMES) { |
| 56 | + if (!(phy->test.flag & MT_TM_FW_RX_COUNT) && |
| 57 | + phy->test.state == MT76_TM_STATE_RX_FRAMES) { |
| 58 | phy->test.rx_stats.packets[q]++; |
| 59 | if (status->flag & RX_FLAG_FAILED_FCS_CRC) |
| 60 | phy->test.rx_stats.fcs_error[q]++; |
| 61 | diff --git a/mt76.h b/mt76.h |
developer | c2cfe0f | 2023-09-22 04:11:09 +0800 | [diff] [blame] | 62 | index a2382160d..ad1123c4a 100644 |
developer | 1bc2ce2 | 2023-03-25 00:47:41 +0800 | [diff] [blame] | 63 | --- a/mt76.h |
| 64 | +++ b/mt76.h |
developer | c2cfe0f | 2023-09-22 04:11:09 +0800 | [diff] [blame] | 65 | @@ -658,14 +658,20 @@ struct mt76_testmode_ops { |
developer | 1bc2ce2 | 2023-03-25 00:47:41 +0800 | [diff] [blame] | 66 | int (*set_params)(struct mt76_phy *phy, struct nlattr **tb, |
| 67 | enum mt76_testmode_state new_state); |
| 68 | int (*dump_stats)(struct mt76_phy *phy, struct sk_buff *msg); |
| 69 | + void (*reset_rx_stats)(struct mt76_phy *phy); |
| 70 | + void (*tx_stop)(struct mt76_phy *phy); |
| 71 | }; |
| 72 | |
| 73 | +#define MT_TM_FW_RX_COUNT BIT(0) |
| 74 | + |
| 75 | struct mt76_testmode_data { |
| 76 | enum mt76_testmode_state state; |
| 77 | |
developer | c2cfe0f | 2023-09-22 04:11:09 +0800 | [diff] [blame] | 78 | u32 param_set[DIV_ROUND_UP(NUM_MT76_TM_ATTRS, 32)]; |
| 79 | struct sk_buff *tx_skb; |
| 80 | |
| 81 | + u8 sku_en; |
| 82 | + |
| 83 | u32 tx_count; |
| 84 | u16 tx_mpdu_len; |
| 85 | |
| 86 | @@ -675,6 +681,7 @@ struct mt76_testmode_data { |
developer | 1bc2ce2 | 2023-03-25 00:47:41 +0800 | [diff] [blame] | 87 | u8 tx_rate_sgi; |
| 88 | u8 tx_rate_ldpc; |
| 89 | u8 tx_rate_stbc; |
| 90 | + u16 tx_preamble_puncture; |
| 91 | u8 tx_ltf; |
| 92 | |
| 93 | u8 tx_antenna_mask; |
developer | c2cfe0f | 2023-09-22 04:11:09 +0800 | [diff] [blame] | 94 | @@ -684,6 +691,9 @@ struct mt76_testmode_data { |
developer | 1bc2ce2 | 2023-03-25 00:47:41 +0800 | [diff] [blame] | 95 | u32 tx_time; |
| 96 | u32 tx_ipg; |
| 97 | |
| 98 | + bool ibf; |
| 99 | + bool ebf; |
| 100 | + |
| 101 | u32 freq_offset; |
| 102 | |
| 103 | u8 tx_power[4]; |
developer | c2cfe0f | 2023-09-22 04:11:09 +0800 | [diff] [blame] | 104 | @@ -698,7 +708,16 @@ struct mt76_testmode_data { |
developer | 1bc2ce2 | 2023-03-25 00:47:41 +0800 | [diff] [blame] | 105 | struct { |
| 106 | u64 packets[__MT_RXQ_MAX]; |
| 107 | u64 fcs_error[__MT_RXQ_MAX]; |
| 108 | + u64 len_mismatch; |
| 109 | } rx_stats; |
| 110 | + u8 flag; |
developer | de9ecce | 2023-05-22 11:17:16 +0800 | [diff] [blame] | 111 | + |
| 112 | + struct { |
| 113 | + u8 type; |
| 114 | + u8 enable; |
| 115 | + } cfg; |
| 116 | + |
developer | 1bc2ce2 | 2023-03-25 00:47:41 +0800 | [diff] [blame] | 117 | + u8 aid; |
| 118 | }; |
| 119 | |
| 120 | struct mt76_vif { |
developer | c2cfe0f | 2023-09-22 04:11:09 +0800 | [diff] [blame] | 121 | @@ -1370,6 +1389,22 @@ int mt76_testmode_dump(struct ieee80211_hw *hw, struct sk_buff *skb, |
developer | de9ecce | 2023-05-22 11:17:16 +0800 | [diff] [blame] | 122 | int mt76_testmode_set_state(struct mt76_phy *phy, enum mt76_testmode_state state); |
| 123 | int mt76_testmode_alloc_skb(struct mt76_phy *phy, u32 len); |
| 124 | |
| 125 | +static inline void |
| 126 | +mt76_testmode_param_set(struct mt76_testmode_data *td, u16 idx) |
| 127 | +{ |
| 128 | +#ifdef CONFIG_NL80211_TESTMODE |
| 129 | + td->param_set[idx / 32] |= BIT(idx % 32); |
| 130 | +#endif |
| 131 | +} |
| 132 | + |
| 133 | +static inline bool |
| 134 | +mt76_testmode_param_present(struct mt76_testmode_data *td, u16 idx) |
| 135 | +{ |
| 136 | +#ifdef CONFIG_NL80211_TESTMODE |
| 137 | + return td->param_set[idx / 32] & BIT(idx % 32); |
| 138 | +#endif |
| 139 | +} |
| 140 | + |
| 141 | static inline void mt76_testmode_reset(struct mt76_phy *phy, bool disable) |
| 142 | { |
| 143 | #ifdef CONFIG_NL80211_TESTMODE |
developer | 1bc2ce2 | 2023-03-25 00:47:41 +0800 | [diff] [blame] | 144 | diff --git a/mt76_connac_mcu.h b/mt76_connac_mcu.h |
developer | c2cfe0f | 2023-09-22 04:11:09 +0800 | [diff] [blame] | 145 | index 8562ca42a..7e859da65 100644 |
developer | 1bc2ce2 | 2023-03-25 00:47:41 +0800 | [diff] [blame] | 146 | --- a/mt76_connac_mcu.h |
| 147 | +++ b/mt76_connac_mcu.h |
developer | c2cfe0f | 2023-09-22 04:11:09 +0800 | [diff] [blame] | 148 | @@ -1237,11 +1237,13 @@ enum { |
developer | 1bc2ce2 | 2023-03-25 00:47:41 +0800 | [diff] [blame] | 149 | MCU_UNI_CMD_EFUSE_CTRL = 0x2d, |
| 150 | MCU_UNI_CMD_RA = 0x2f, |
| 151 | MCU_UNI_CMD_MURU = 0x31, |
| 152 | + MCU_UNI_CMD_TESTMODE_RX_STAT = 0x32, |
| 153 | MCU_UNI_CMD_BF = 0x33, |
| 154 | MCU_UNI_CMD_CHANNEL_SWITCH = 0x34, |
| 155 | MCU_UNI_CMD_THERMAL = 0x35, |
| 156 | MCU_UNI_CMD_VOW = 0x37, |
developer | c2cfe0f | 2023-09-22 04:11:09 +0800 | [diff] [blame] | 157 | MCU_UNI_CMD_FIXED_RATE_TABLE = 0x40, |
developer | 1bc2ce2 | 2023-03-25 00:47:41 +0800 | [diff] [blame] | 158 | + MCU_UNI_CMD_TESTMODE_CTRL = 0x46, |
| 159 | MCU_UNI_CMD_RRO = 0x57, |
| 160 | MCU_UNI_CMD_OFFCH_SCAN_CTRL = 0x58, |
developer | c2cfe0f | 2023-09-22 04:11:09 +0800 | [diff] [blame] | 161 | MCU_UNI_CMD_PER_STA_INFO = 0x6d, |
developer | 1bc2ce2 | 2023-03-25 00:47:41 +0800 | [diff] [blame] | 162 | diff --git a/mt7996/Makefile b/mt7996/Makefile |
developer | c2cfe0f | 2023-09-22 04:11:09 +0800 | [diff] [blame] | 163 | index a056b40e0..7bb17f440 100644 |
developer | 1bc2ce2 | 2023-03-25 00:47:41 +0800 | [diff] [blame] | 164 | --- a/mt7996/Makefile |
| 165 | +++ b/mt7996/Makefile |
developer | c2cfe0f | 2023-09-22 04:11:09 +0800 | [diff] [blame] | 166 | @@ -8,5 +8,6 @@ mt7996e-y := pci.o init.o dma.o eeprom.o main.o mcu.o mac.o \ |
developer | 1bc2ce2 | 2023-03-25 00:47:41 +0800 | [diff] [blame] | 167 | debugfs.o mmio.o |
developer | de9ecce | 2023-05-22 11:17:16 +0800 | [diff] [blame] | 168 | |
| 169 | mt7996e-$(CONFIG_DEV_COREDUMP) += coredump.o |
developer | 1bc2ce2 | 2023-03-25 00:47:41 +0800 | [diff] [blame] | 170 | +mt7996e-$(CONFIG_NL80211_TESTMODE) += testmode.o |
developer | c2cfe0f | 2023-09-22 04:11:09 +0800 | [diff] [blame] | 171 | |
| 172 | mt7996e-y += mtk_debugfs.o mtk_mcu.o |
developer | 1bc2ce2 | 2023-03-25 00:47:41 +0800 | [diff] [blame] | 173 | diff --git a/mt7996/eeprom.c b/mt7996/eeprom.c |
developer | c2cfe0f | 2023-09-22 04:11:09 +0800 | [diff] [blame] | 174 | index 1d98d99eb..b81ed64ce 100644 |
developer | 1bc2ce2 | 2023-03-25 00:47:41 +0800 | [diff] [blame] | 175 | --- a/mt7996/eeprom.c |
| 176 | +++ b/mt7996/eeprom.c |
| 177 | @@ -6,6 +6,11 @@ |
| 178 | #include <linux/firmware.h> |
| 179 | #include "mt7996.h" |
| 180 | #include "eeprom.h" |
| 181 | +#include <linux/moduleparam.h> |
| 182 | + |
| 183 | +static bool testmode_enable; |
| 184 | +module_param(testmode_enable, bool, 0644); |
| 185 | +MODULE_PARM_DESC(testmode_enable, "Enable testmode"); |
| 186 | |
| 187 | static int mt7996_check_eeprom(struct mt7996_dev *dev) |
| 188 | { |
| 189 | @@ -23,7 +28,10 @@ static int mt7996_check_eeprom(struct mt7996_dev *dev) |
| 190 | static char *mt7996_eeprom_name(struct mt7996_dev *dev) |
| 191 | { |
| 192 | /* reserve for future variants */ |
| 193 | - return MT7996_EEPROM_DEFAULT; |
| 194 | + if (dev->testmode_enable) |
| 195 | + return MT7996_EEPROM_DEFAULT_TM; |
| 196 | + else |
| 197 | + return MT7996_EEPROM_DEFAULT; |
| 198 | } |
| 199 | |
| 200 | static int |
| 201 | @@ -52,21 +60,36 @@ out: |
| 202 | return ret; |
| 203 | } |
| 204 | |
| 205 | -static int mt7996_eeprom_load(struct mt7996_dev *dev) |
| 206 | +int mt7996_eeprom_check_fw_mode(struct mt7996_dev *dev) |
| 207 | { |
| 208 | + u8 *eeprom; |
| 209 | int ret; |
| 210 | |
| 211 | + /* load eeprom in flash or bin file mode to determine fw mode */ |
| 212 | ret = mt76_eeprom_init(&dev->mt76, MT7996_EEPROM_SIZE); |
| 213 | if (ret < 0) |
| 214 | return ret; |
| 215 | |
| 216 | if (ret) { |
| 217 | dev->flash_mode = true; |
| 218 | - } else { |
| 219 | - u8 free_block_num; |
| 220 | - u32 block_num, i; |
| 221 | - u32 eeprom_blk_size = MT7996_EEPROM_BLOCK_SIZE; |
| 222 | + eeprom = dev->mt76.eeprom.data; |
| 223 | + /* testmode enable priority: eeprom field > module parameter */ |
| 224 | + dev->testmode_enable = !mt7996_check_eeprom(dev) ? eeprom[MT_EE_TESTMODE_EN] : |
| 225 | + testmode_enable; |
| 226 | + } |
| 227 | + |
| 228 | + return ret; |
| 229 | +} |
| 230 | + |
| 231 | +static int mt7996_eeprom_load(struct mt7996_dev *dev) |
| 232 | +{ |
| 233 | + int ret; |
| 234 | + u8 free_block_num; |
| 235 | + u32 block_num, i; |
| 236 | + u32 eeprom_blk_size = MT7996_EEPROM_BLOCK_SIZE; |
| 237 | |
| 238 | + /* flash or bin file mode eeprom is loaded before mcu init */ |
| 239 | + if (!dev->flash_mode) { |
| 240 | ret = mt7996_mcu_get_eeprom_free_block(dev, &free_block_num); |
| 241 | if (ret < 0) |
| 242 | return ret; |
| 243 | diff --git a/mt7996/eeprom.h b/mt7996/eeprom.h |
developer | c2cfe0f | 2023-09-22 04:11:09 +0800 | [diff] [blame] | 244 | index 412d6e2f8..9ea3667f1 100644 |
developer | 1bc2ce2 | 2023-03-25 00:47:41 +0800 | [diff] [blame] | 245 | --- a/mt7996/eeprom.h |
| 246 | +++ b/mt7996/eeprom.h |
| 247 | @@ -14,6 +14,7 @@ enum mt7996_eeprom_field { |
| 248 | MT_EE_MAC_ADDR = 0x004, |
| 249 | MT_EE_MAC_ADDR2 = 0x00a, |
| 250 | MT_EE_WIFI_CONF = 0x190, |
| 251 | + MT_EE_TESTMODE_EN = 0x1af, |
| 252 | MT_EE_MAC_ADDR3 = 0x2c0, |
| 253 | MT_EE_RATE_DELTA_2G = 0x1400, |
| 254 | MT_EE_RATE_DELTA_5G = 0x147d, |
| 255 | diff --git a/mt7996/init.c b/mt7996/init.c |
developer | c2cfe0f | 2023-09-22 04:11:09 +0800 | [diff] [blame] | 256 | index 2fe3da475..f41e4e5eb 100644 |
developer | 1bc2ce2 | 2023-03-25 00:47:41 +0800 | [diff] [blame] | 257 | --- a/mt7996/init.c |
| 258 | +++ b/mt7996/init.c |
developer | c2cfe0f | 2023-09-22 04:11:09 +0800 | [diff] [blame] | 259 | @@ -663,6 +663,10 @@ static int mt7996_init_hardware(struct mt7996_dev *dev) |
developer | 1bc2ce2 | 2023-03-25 00:47:41 +0800 | [diff] [blame] | 260 | |
| 261 | set_bit(MT76_STATE_INITIALIZED, &dev->mphy.state); |
| 262 | |
| 263 | + ret = mt7996_eeprom_check_fw_mode(dev); |
| 264 | + if (ret < 0) |
| 265 | + return ret; |
| 266 | + |
| 267 | ret = mt7996_mcu_init(dev); |
| 268 | if (ret) |
| 269 | return ret; |
developer | c2cfe0f | 2023-09-22 04:11:09 +0800 | [diff] [blame] | 270 | @@ -1076,6 +1080,9 @@ int mt7996_register_device(struct mt7996_dev *dev) |
developer | 1bc2ce2 | 2023-03-25 00:47:41 +0800 | [diff] [blame] | 271 | |
| 272 | mt7996_init_wiphy(hw); |
| 273 | |
| 274 | +#ifdef CONFIG_NL80211_TESTMODE |
| 275 | + dev->mt76.test_ops = &mt7996_testmode_ops; |
| 276 | +#endif |
developer | c2cfe0f | 2023-09-22 04:11:09 +0800 | [diff] [blame] | 277 | ret = mt76_register_device(&dev->mt76, true, mt76_rates, |
| 278 | ARRAY_SIZE(mt76_rates)); |
| 279 | if (ret) |
| 280 | diff --git a/mt7996/mac.c b/mt7996/mac.c |
| 281 | index d7751cf55..f00133489 100644 |
| 282 | --- a/mt7996/mac.c |
| 283 | +++ b/mt7996/mac.c |
| 284 | @@ -654,7 +654,8 @@ mt7996_mac_fill_rx(struct mt7996_dev *dev, struct sk_buff *skb) |
| 285 | status->flag |= RX_FLAG_8023; |
| 286 | } |
| 287 | |
| 288 | - if (rxv && mode >= MT_PHY_TYPE_HE_SU && !(status->flag & RX_FLAG_8023)) |
| 289 | + if (rxv && mode >= MT_PHY_TYPE_HE_SU && mode < MT_PHY_TYPE_EHT_SU && |
| 290 | + !(status->flag & RX_FLAG_8023)) |
| 291 | mt76_connac3_mac_decode_he_radiotap(skb, rxv, mode); |
| 292 | |
| 293 | if (!status->wcid || !ieee80211_is_data_qos(fc)) |
developer | 1bc2ce2 | 2023-03-25 00:47:41 +0800 | [diff] [blame] | 294 | diff --git a/mt7996/main.c b/mt7996/main.c |
developer | c2cfe0f | 2023-09-22 04:11:09 +0800 | [diff] [blame] | 295 | index 04a2d07a8..3336602f1 100644 |
developer | 1bc2ce2 | 2023-03-25 00:47:41 +0800 | [diff] [blame] | 296 | --- a/mt7996/main.c |
| 297 | +++ b/mt7996/main.c |
developer | 064da3c | 2023-06-13 15:57:26 +0800 | [diff] [blame] | 298 | @@ -23,6 +23,18 @@ static bool mt7996_dev_running(struct mt7996_dev *dev) |
developer | 1bc2ce2 | 2023-03-25 00:47:41 +0800 | [diff] [blame] | 299 | return phy && test_bit(MT76_STATE_RUNNING, &phy->mt76->state); |
| 300 | } |
| 301 | |
| 302 | +static void mt7996_testmode_disable_all(struct mt7996_dev *dev) |
| 303 | +{ |
| 304 | + struct mt7996_phy *phy; |
| 305 | + int i; |
| 306 | + |
| 307 | + for (i = 0; i < __MT_MAX_BAND; i++) { |
| 308 | + phy = __mt7996_phy(dev, i); |
developer | 064da3c | 2023-06-13 15:57:26 +0800 | [diff] [blame] | 309 | + if (phy) |
| 310 | + mt76_testmode_set_state(phy->mt76, MT76_TM_STATE_OFF); |
developer | 1bc2ce2 | 2023-03-25 00:47:41 +0800 | [diff] [blame] | 311 | + } |
| 312 | +} |
| 313 | + |
| 314 | int mt7996_run(struct ieee80211_hw *hw) |
| 315 | { |
| 316 | struct mt7996_dev *dev = mt7996_hw_dev(hw); |
developer | 064da3c | 2023-06-13 15:57:26 +0800 | [diff] [blame] | 317 | @@ -37,6 +49,8 @@ int mt7996_run(struct ieee80211_hw *hw) |
developer | 1bc2ce2 | 2023-03-25 00:47:41 +0800 | [diff] [blame] | 318 | goto out; |
| 319 | } |
| 320 | |
| 321 | + mt7996_testmode_disable_all(dev); |
| 322 | + |
| 323 | mt7996_mac_enable_nf(dev, phy->mt76->band_idx); |
| 324 | |
| 325 | ret = mt7996_mcu_set_rts_thresh(phy, 0x92b); |
developer | c2cfe0f | 2023-09-22 04:11:09 +0800 | [diff] [blame] | 326 | @@ -1437,6 +1451,8 @@ const struct ieee80211_ops mt7996_ops = { |
developer | 1bc2ce2 | 2023-03-25 00:47:41 +0800 | [diff] [blame] | 327 | .sta_set_decap_offload = mt7996_sta_set_decap_offload, |
| 328 | .add_twt_setup = mt7996_mac_add_twt_setup, |
| 329 | .twt_teardown_request = mt7996_twt_teardown_request, |
| 330 | + CFG80211_TESTMODE_CMD(mt76_testmode_cmd) |
| 331 | + CFG80211_TESTMODE_DUMP(mt76_testmode_dump) |
| 332 | #ifdef CONFIG_MAC80211_DEBUGFS |
| 333 | .sta_add_debugfs = mt7996_sta_add_debugfs, |
| 334 | #endif |
| 335 | diff --git a/mt7996/mcu.c b/mt7996/mcu.c |
developer | c2cfe0f | 2023-09-22 04:11:09 +0800 | [diff] [blame] | 336 | index 867818825..837cf1b30 100644 |
developer | 1bc2ce2 | 2023-03-25 00:47:41 +0800 | [diff] [blame] | 337 | --- a/mt7996/mcu.c |
| 338 | +++ b/mt7996/mcu.c |
developer | c2cfe0f | 2023-09-22 04:11:09 +0800 | [diff] [blame] | 339 | @@ -2718,8 +2718,12 @@ static int mt7996_load_ram(struct mt7996_dev *dev) |
developer | 064da3c | 2023-06-13 15:57:26 +0800 | [diff] [blame] | 340 | { |
| 341 | int ret; |
developer | 1bc2ce2 | 2023-03-25 00:47:41 +0800 | [diff] [blame] | 342 | |
developer | 064da3c | 2023-06-13 15:57:26 +0800 | [diff] [blame] | 343 | - ret = __mt7996_load_ram(dev, "WM", MT7996_FIRMWARE_WM, |
| 344 | - MT7996_RAM_TYPE_WM); |
developer | 1bc2ce2 | 2023-03-25 00:47:41 +0800 | [diff] [blame] | 345 | + if (dev->testmode_enable) |
developer | 064da3c | 2023-06-13 15:57:26 +0800 | [diff] [blame] | 346 | + ret = __mt7996_load_ram(dev, "WM_TM", MT7996_FIRMWARE_WM_TM, |
| 347 | + MT7996_RAM_TYPE_WM_TM); |
developer | 1bc2ce2 | 2023-03-25 00:47:41 +0800 | [diff] [blame] | 348 | + else |
developer | 064da3c | 2023-06-13 15:57:26 +0800 | [diff] [blame] | 349 | + ret = __mt7996_load_ram(dev, "WM", MT7996_FIRMWARE_WM, |
| 350 | + MT7996_RAM_TYPE_WM); |
| 351 | if (ret) |
| 352 | return ret; |
| 353 | |
developer | c2cfe0f | 2023-09-22 04:11:09 +0800 | [diff] [blame] | 354 | @@ -4316,3 +4320,37 @@ int mt7996_mcu_get_all_sta_info(struct mt7996_phy *phy, u16 tag) |
| 355 | return mt76_mcu_send_msg(&dev->mt76, MCU_WM_UNI_CMD(ALL_STA_INFO), |
| 356 | &req, sizeof(req), false); |
developer | 1bc2ce2 | 2023-03-25 00:47:41 +0800 | [diff] [blame] | 357 | } |
| 358 | + |
| 359 | +int mt7996_mcu_set_tx_power_ctrl(struct mt7996_phy *phy, u8 power_ctrl_id, u8 data) |
| 360 | +{ |
| 361 | + struct mt7996_dev *dev = phy->dev; |
| 362 | + struct tx_power_ctrl req = { |
| 363 | + .tag = cpu_to_le16(power_ctrl_id), |
| 364 | + .len = cpu_to_le16(sizeof(req) - 4), |
| 365 | + .power_ctrl_id = power_ctrl_id, |
| 366 | + .band_idx = phy->mt76->band_idx, |
| 367 | + }; |
| 368 | + |
| 369 | + switch (power_ctrl_id) { |
| 370 | + case UNI_TXPOWER_SKU_POWER_LIMIT_CTRL: |
| 371 | + req.sku_enable = !!data; |
| 372 | + break; |
| 373 | + case UNI_TXPOWER_PERCENTAGE_CTRL: |
| 374 | + req.percentage_ctrl_enable = !!data; |
| 375 | + break; |
| 376 | + case UNI_TXPOWER_PERCENTAGE_DROP_CTRL: |
| 377 | + req.power_drop_level = data; |
| 378 | + break; |
| 379 | + case UNI_TXPOWER_BACKOFF_POWER_LIMIT_CTRL: |
| 380 | + req.bf_backoff_enable = !!data; |
| 381 | + break; |
| 382 | + case UNI_TXPOWER_ATE_MODE_CTRL: |
| 383 | + req.ate_mode_enable = !!data; |
| 384 | + break; |
| 385 | + default: |
| 386 | + req.sku_enable = !!data; |
| 387 | + } |
| 388 | + |
| 389 | + return mt76_mcu_send_msg(&dev->mt76, MCU_WM_UNI_CMD(TXPOWER), |
| 390 | + &req, sizeof(req), false); |
| 391 | +} |
| 392 | diff --git a/mt7996/mcu.h b/mt7996/mcu.h |
developer | c2cfe0f | 2023-09-22 04:11:09 +0800 | [diff] [blame] | 393 | index ccc260c83..86701c3f6 100644 |
developer | 1bc2ce2 | 2023-03-25 00:47:41 +0800 | [diff] [blame] | 394 | --- a/mt7996/mcu.h |
| 395 | +++ b/mt7996/mcu.h |
developer | c2cfe0f | 2023-09-22 04:11:09 +0800 | [diff] [blame] | 396 | @@ -818,6 +818,33 @@ enum { |
developer | 1bc2ce2 | 2023-03-25 00:47:41 +0800 | [diff] [blame] | 397 | UNI_CMD_THERMAL_PROTECT_DUTY_CONFIG, |
| 398 | }; |
| 399 | |
| 400 | +struct tx_power_ctrl { |
| 401 | + u8 _rsv[4]; |
| 402 | + |
| 403 | + __le16 tag; |
| 404 | + __le16 len; |
| 405 | + |
| 406 | + u8 power_ctrl_id; |
| 407 | + union { |
| 408 | + bool sku_enable; |
| 409 | + bool ate_mode_enable; |
| 410 | + bool percentage_ctrl_enable; |
| 411 | + bool bf_backoff_enable; |
| 412 | + u8 power_drop_level; |
| 413 | + }; |
| 414 | + u8 band_idx; |
| 415 | + u8 rsv[1]; |
| 416 | +} __packed; |
| 417 | + |
| 418 | +enum { |
| 419 | + UNI_TXPOWER_SKU_POWER_LIMIT_CTRL = 0, |
| 420 | + UNI_TXPOWER_PERCENTAGE_CTRL = 1, |
| 421 | + UNI_TXPOWER_PERCENTAGE_DROP_CTRL = 2, |
| 422 | + UNI_TXPOWER_BACKOFF_POWER_LIMIT_CTRL = 3, |
| 423 | + UNI_TXPOWER_POWER_LIMIT_TABLE_CTRL = 4, |
| 424 | + UNI_TXPOWER_ATE_MODE_CTRL = 6, |
| 425 | +}; |
| 426 | + |
| 427 | enum { |
| 428 | UNI_CMD_ACCESS_REG_BASIC = 0x0, |
| 429 | UNI_CMD_ACCESS_RF_REG_BASIC, |
| 430 | diff --git a/mt7996/mt7996.h b/mt7996/mt7996.h |
developer | c2cfe0f | 2023-09-22 04:11:09 +0800 | [diff] [blame] | 431 | index 8aa124a0c..18208388b 100644 |
developer | 1bc2ce2 | 2023-03-25 00:47:41 +0800 | [diff] [blame] | 432 | --- a/mt7996/mt7996.h |
| 433 | +++ b/mt7996/mt7996.h |
developer | 064da3c | 2023-06-13 15:57:26 +0800 | [diff] [blame] | 434 | @@ -31,9 +31,11 @@ |
developer | 1bc2ce2 | 2023-03-25 00:47:41 +0800 | [diff] [blame] | 435 | #define MT7996_FIRMWARE_WA "mediatek/mt7996/mt7996_wa.bin" |
| 436 | #define MT7996_FIRMWARE_WM "mediatek/mt7996/mt7996_wm.bin" |
| 437 | #define MT7996_FIRMWARE_DSP "mediatek/mt7996/mt7996_dsp.bin" |
| 438 | +#define MT7996_FIRMWARE_WM_TM "mediatek/mt7996/mt7996_wm_tm.bin" |
| 439 | #define MT7996_ROM_PATCH "mediatek/mt7996/mt7996_rom_patch.bin" |
| 440 | |
| 441 | #define MT7996_EEPROM_DEFAULT "mediatek/mt7996/mt7996_eeprom.bin" |
| 442 | +#define MT7996_EEPROM_DEFAULT_TM "mediatek/mt7996/mt7996_eeprom_tm.bin" |
| 443 | #define MT7996_EEPROM_SIZE 7680 |
| 444 | #define MT7996_EEPROM_BLOCK_SIZE 16 |
developer | 064da3c | 2023-06-13 15:57:26 +0800 | [diff] [blame] | 445 | #define MT7996_TOKEN_SIZE 16384 |
developer | c2cfe0f | 2023-09-22 04:11:09 +0800 | [diff] [blame] | 446 | @@ -65,6 +67,7 @@ struct mt7996_dfs_pattern; |
developer | 1bc2ce2 | 2023-03-25 00:47:41 +0800 | [diff] [blame] | 447 | |
| 448 | enum mt7996_ram_type { |
developer | 064da3c | 2023-06-13 15:57:26 +0800 | [diff] [blame] | 449 | MT7996_RAM_TYPE_WM, |
developer | 1bc2ce2 | 2023-03-25 00:47:41 +0800 | [diff] [blame] | 450 | + MT7996_RAM_TYPE_WM_TM = MT7996_RAM_TYPE_WM, |
| 451 | MT7996_RAM_TYPE_WA, |
| 452 | MT7996_RAM_TYPE_DSP, |
developer | c2cfe0f | 2023-09-22 04:11:09 +0800 | [diff] [blame] | 453 | __MT7996_RAM_TYPE_MAX, |
| 454 | @@ -188,6 +191,21 @@ struct mt7996_phy { |
developer | 1bc2ce2 | 2023-03-25 00:47:41 +0800 | [diff] [blame] | 455 | struct mt76_channel_state state_ts; |
developer | c2cfe0f | 2023-09-22 04:11:09 +0800 | [diff] [blame] | 456 | |
| 457 | bool has_aux_rx; |
developer | 1bc2ce2 | 2023-03-25 00:47:41 +0800 | [diff] [blame] | 458 | + |
| 459 | +#ifdef CONFIG_NL80211_TESTMODE |
| 460 | + struct { |
| 461 | + u32 *reg_backup; |
| 462 | + |
| 463 | + s32 last_freq_offset; |
| 464 | + u8 last_rcpi[4]; |
developer | c2cfe0f | 2023-09-22 04:11:09 +0800 | [diff] [blame] | 465 | + s8 last_rssi[4]; |
developer | 1bc2ce2 | 2023-03-25 00:47:41 +0800 | [diff] [blame] | 466 | + s8 last_ib_rssi[4]; |
| 467 | + s8 last_wb_rssi[4]; |
| 468 | + u8 last_snr; |
| 469 | + |
| 470 | + u8 spe_idx; |
| 471 | + } test; |
| 472 | +#endif |
| 473 | }; |
| 474 | |
| 475 | struct mt7996_dev { |
developer | c2cfe0f | 2023-09-22 04:11:09 +0800 | [diff] [blame] | 476 | @@ -247,6 +265,8 @@ struct mt7996_dev { |
developer | 1bc2ce2 | 2023-03-25 00:47:41 +0800 | [diff] [blame] | 477 | bool flash_mode:1; |
| 478 | bool has_eht:1; |
| 479 | |
| 480 | + bool testmode_enable; |
| 481 | + |
| 482 | bool ibf; |
| 483 | u8 fw_debug_wm; |
| 484 | u8 fw_debug_wa; |
developer | c2cfe0f | 2023-09-22 04:11:09 +0800 | [diff] [blame] | 485 | @@ -358,6 +378,7 @@ mt7996_band_valid(struct mt7996_dev *dev, u8 band) |
developer | 1bc2ce2 | 2023-03-25 00:47:41 +0800 | [diff] [blame] | 486 | extern const struct ieee80211_ops mt7996_ops; |
| 487 | extern struct pci_driver mt7996_pci_driver; |
| 488 | extern struct pci_driver mt7996_hif_driver; |
| 489 | +extern const struct mt76_testmode_ops mt7996_testmode_ops; |
| 490 | |
| 491 | struct mt7996_dev *mt7996_mmio_probe(struct device *pdev, |
| 492 | void __iomem *mem_base, u32 device_id); |
developer | c2cfe0f | 2023-09-22 04:11:09 +0800 | [diff] [blame] | 493 | @@ -367,6 +388,7 @@ u64 __mt7996_get_tsf(struct ieee80211_hw *hw, struct mt7996_vif *mvif); |
developer | 1bc2ce2 | 2023-03-25 00:47:41 +0800 | [diff] [blame] | 494 | int mt7996_register_device(struct mt7996_dev *dev); |
| 495 | void mt7996_unregister_device(struct mt7996_dev *dev); |
| 496 | int mt7996_eeprom_init(struct mt7996_dev *dev); |
| 497 | +int mt7996_eeprom_check_fw_mode(struct mt7996_dev *dev); |
| 498 | int mt7996_eeprom_parse_hw_cap(struct mt7996_dev *dev, struct mt7996_phy *phy); |
| 499 | int mt7996_eeprom_get_target_power(struct mt7996_dev *dev, |
| 500 | struct ieee80211_channel *chan); |
developer | c2cfe0f | 2023-09-22 04:11:09 +0800 | [diff] [blame] | 501 | @@ -450,6 +472,7 @@ int mt7996_mcu_fw_dbg_ctrl(struct mt7996_dev *dev, u32 module, u8 level); |
developer | de9ecce | 2023-05-22 11:17:16 +0800 | [diff] [blame] | 502 | int mt7996_mcu_trigger_assert(struct mt7996_dev *dev); |
developer | 1bc2ce2 | 2023-03-25 00:47:41 +0800 | [diff] [blame] | 503 | void mt7996_mcu_rx_event(struct mt7996_dev *dev, struct sk_buff *skb); |
| 504 | void mt7996_mcu_exit(struct mt7996_dev *dev); |
| 505 | +int mt7996_mcu_set_tx_power_ctrl(struct mt7996_phy *phy, u8 power_ctrl_id, u8 data); |
| 506 | |
| 507 | static inline u8 mt7996_max_interface_num(struct mt7996_dev *dev) |
| 508 | { |
| 509 | diff --git a/mt7996/testmode.c b/mt7996/testmode.c |
| 510 | new file mode 100644 |
developer | c2cfe0f | 2023-09-22 04:11:09 +0800 | [diff] [blame] | 511 | index 000000000..fb041c336 |
developer | 1bc2ce2 | 2023-03-25 00:47:41 +0800 | [diff] [blame] | 512 | --- /dev/null |
| 513 | +++ b/mt7996/testmode.c |
developer | c2cfe0f | 2023-09-22 04:11:09 +0800 | [diff] [blame] | 514 | @@ -0,0 +1,674 @@ |
developer | 1bc2ce2 | 2023-03-25 00:47:41 +0800 | [diff] [blame] | 515 | +// SPDX-License-Identifier: ISC |
| 516 | +/* |
| 517 | + * Copyright (C) 2022 MediaTek Inc. |
| 518 | + */ |
| 519 | + |
| 520 | +#include "mt7996.h" |
| 521 | +#include "mac.h" |
| 522 | +#include "mcu.h" |
| 523 | +#include "testmode.h" |
| 524 | + |
| 525 | +enum { |
| 526 | + TM_CHANGED_TXPOWER, |
| 527 | + TM_CHANGED_FREQ_OFFSET, |
developer | c2cfe0f | 2023-09-22 04:11:09 +0800 | [diff] [blame] | 528 | + TM_CHANGED_SKU_EN, |
developer | 1bc2ce2 | 2023-03-25 00:47:41 +0800 | [diff] [blame] | 529 | + TM_CHANGED_TX_LENGTH, |
| 530 | + TM_CHANGED_TX_TIME, |
developer | de9ecce | 2023-05-22 11:17:16 +0800 | [diff] [blame] | 531 | + TM_CHANGED_CFG, |
developer | 1bc2ce2 | 2023-03-25 00:47:41 +0800 | [diff] [blame] | 532 | + |
| 533 | + /* must be last */ |
| 534 | + NUM_TM_CHANGED |
| 535 | +}; |
| 536 | + |
| 537 | +static const u8 tm_change_map[] = { |
| 538 | + [TM_CHANGED_TXPOWER] = MT76_TM_ATTR_TX_POWER, |
| 539 | + [TM_CHANGED_FREQ_OFFSET] = MT76_TM_ATTR_FREQ_OFFSET, |
developer | c2cfe0f | 2023-09-22 04:11:09 +0800 | [diff] [blame] | 540 | + [TM_CHANGED_SKU_EN] = MT76_TM_ATTR_SKU_EN, |
developer | 1bc2ce2 | 2023-03-25 00:47:41 +0800 | [diff] [blame] | 541 | + [TM_CHANGED_TX_LENGTH] = MT76_TM_ATTR_TX_LENGTH, |
| 542 | + [TM_CHANGED_TX_TIME] = MT76_TM_ATTR_TX_TIME, |
developer | de9ecce | 2023-05-22 11:17:16 +0800 | [diff] [blame] | 543 | + [TM_CHANGED_CFG] = MT76_TM_ATTR_CFG, |
developer | 1bc2ce2 | 2023-03-25 00:47:41 +0800 | [diff] [blame] | 544 | +}; |
| 545 | + |
| 546 | +static u8 mt7996_tm_bw_mapping(enum nl80211_chan_width width, enum bw_mapping_method method) |
| 547 | +{ |
| 548 | + static const u8 width_to_bw[][NUM_BW_MAP] = { |
| 549 | + [NL80211_CHAN_WIDTH_40] = {FW_CDBW_40MHZ, TM_CBW_40MHZ}, |
| 550 | + [NL80211_CHAN_WIDTH_80] = {FW_CDBW_80MHZ, TM_CBW_80MHZ}, |
| 551 | + [NL80211_CHAN_WIDTH_80P80] = {FW_CDBW_8080MHZ, TM_CBW_8080MHZ}, |
| 552 | + [NL80211_CHAN_WIDTH_160] = {FW_CDBW_160MHZ, TM_CBW_160MHZ}, |
| 553 | + [NL80211_CHAN_WIDTH_5] = {FW_CDBW_5MHZ, TM_CBW_5MHZ}, |
| 554 | + [NL80211_CHAN_WIDTH_10] = {FW_CDBW_10MHZ, TM_CBW_10MHZ}, |
| 555 | + [NL80211_CHAN_WIDTH_20] = {FW_CDBW_20MHZ, TM_CBW_20MHZ}, |
| 556 | + [NL80211_CHAN_WIDTH_20_NOHT] = {FW_CDBW_20MHZ, TM_CBW_20MHZ}, |
| 557 | + [NL80211_CHAN_WIDTH_320] = {FW_CDBW_320MHZ, TM_CBW_320MHZ}, |
| 558 | + }; |
| 559 | + |
| 560 | + if (width >= ARRAY_SIZE(width_to_bw)) |
| 561 | + return 0; |
| 562 | + |
| 563 | + return width_to_bw[width][method]; |
| 564 | +} |
| 565 | + |
| 566 | +static u8 mt7996_tm_rate_to_phy(u8 tx_rate_mode) |
| 567 | +{ |
| 568 | + static const u8 rate_to_phy[] = { |
| 569 | + [MT76_TM_TX_MODE_CCK] = MT_PHY_TYPE_CCK, |
| 570 | + [MT76_TM_TX_MODE_OFDM] = MT_PHY_TYPE_OFDM, |
| 571 | + [MT76_TM_TX_MODE_HT] = MT_PHY_TYPE_HT, |
| 572 | + [MT76_TM_TX_MODE_VHT] = MT_PHY_TYPE_VHT, |
| 573 | + [MT76_TM_TX_MODE_HE_SU] = MT_PHY_TYPE_HE_SU, |
| 574 | + [MT76_TM_TX_MODE_HE_EXT_SU] = MT_PHY_TYPE_HE_EXT_SU, |
| 575 | + [MT76_TM_TX_MODE_HE_TB] = MT_PHY_TYPE_HE_TB, |
| 576 | + [MT76_TM_TX_MODE_HE_MU] = MT_PHY_TYPE_HE_MU, |
| 577 | + [MT76_TM_TX_MODE_EHT_SU] = MT_PHY_TYPE_EHT_SU, |
| 578 | + [MT76_TM_TX_MODE_EHT_TRIG] = MT_PHY_TYPE_EHT_TRIG, |
| 579 | + [MT76_TM_TX_MODE_EHT_MU] = MT_PHY_TYPE_EHT_MU, |
| 580 | + }; |
| 581 | + |
| 582 | + if (tx_rate_mode > MT76_TM_TX_MODE_MAX) |
| 583 | + return -EINVAL; |
| 584 | + |
| 585 | + return rate_to_phy[tx_rate_mode]; |
| 586 | +} |
| 587 | + |
| 588 | +static int |
developer | 064da3c | 2023-06-13 15:57:26 +0800 | [diff] [blame] | 589 | +mt7996_tm_check_antenna(struct mt7996_phy *phy) |
| 590 | +{ |
| 591 | + struct mt76_testmode_data *td = &phy->mt76->test; |
| 592 | + struct mt7996_dev *dev = phy->dev; |
| 593 | + u8 band_idx = phy->mt76->band_idx; |
| 594 | + u32 chainmask = phy->mt76->chainmask; |
| 595 | + u32 aux_rx_mask; |
| 596 | + |
| 597 | + chainmask = chainmask >> dev->chainshift[band_idx]; |
| 598 | + aux_rx_mask = BIT(fls(chainmask)) * phy->has_aux_rx; |
| 599 | + if (td->tx_antenna_mask & ~(chainmask | aux_rx_mask)) { |
| 600 | + dev_err(dev->mt76.dev, |
| 601 | + "tx antenna mask 0x%x exceeds hw limit (chainmask 0x%x, has aux rx: %s)\n", |
| 602 | + td->tx_antenna_mask, chainmask, phy->has_aux_rx ? "yes" : "no"); |
| 603 | + return -EINVAL; |
| 604 | + } |
| 605 | + |
| 606 | + return 0; |
| 607 | +} |
| 608 | + |
| 609 | +static int |
developer | 1bc2ce2 | 2023-03-25 00:47:41 +0800 | [diff] [blame] | 610 | +mt7996_tm_set(struct mt7996_dev *dev, u32 func_idx, u32 data) |
| 611 | +{ |
| 612 | + struct mt7996_tm_req req = { |
| 613 | + .rf_test = { |
| 614 | + .tag = cpu_to_le16(UNI_RF_TEST_CTRL), |
| 615 | + .len = cpu_to_le16(sizeof(req.rf_test)), |
| 616 | + .action = RF_ACTION_SET, |
| 617 | + .op.rf.func_idx = func_idx, |
| 618 | + .op.rf.param.func_data = cpu_to_le32(data), |
| 619 | + }, |
| 620 | + }; |
| 621 | + |
| 622 | + return mt76_mcu_send_msg(&dev->mt76, MCU_WM_UNI_CMD(TESTMODE_CTRL), &req, |
| 623 | + sizeof(req), false); |
| 624 | +} |
| 625 | + |
| 626 | +static int |
| 627 | +mt7996_tm_get(struct mt7996_dev *dev, u32 func_idx, u32 data, u32 *result) |
| 628 | +{ |
| 629 | + struct mt7996_tm_req req = { |
| 630 | + .rf_test = { |
| 631 | + .tag = cpu_to_le16(UNI_RF_TEST_CTRL), |
| 632 | + .len = cpu_to_le16(sizeof(req.rf_test)), |
| 633 | + .action = RF_ACTION_GET, |
| 634 | + .op.rf.func_idx = func_idx, |
| 635 | + .op.rf.param.func_data = cpu_to_le32(data), |
| 636 | + }, |
| 637 | + }; |
| 638 | + struct mt7996_tm_event *event; |
| 639 | + struct sk_buff *skb; |
| 640 | + int ret; |
| 641 | + |
| 642 | + ret = mt76_mcu_send_and_get_msg(&dev->mt76, MCU_WM_UNI_CMD_QUERY(TESTMODE_CTRL), |
| 643 | + &req, sizeof(req), true, &skb); |
| 644 | + if (ret) |
| 645 | + return ret; |
| 646 | + |
| 647 | + event = (struct mt7996_tm_event *)skb->data; |
| 648 | + *result = event->result.payload_length; |
| 649 | + |
| 650 | + dev_kfree_skb(skb); |
| 651 | + |
| 652 | + return ret; |
| 653 | +} |
| 654 | + |
| 655 | +static void |
| 656 | +mt7996_tm_set_antenna(struct mt7996_phy *phy, u32 func_idx) |
| 657 | +{ |
| 658 | +#define SPE_INDEX_MASK BIT(31) |
developer | 064da3c | 2023-06-13 15:57:26 +0800 | [diff] [blame] | 659 | +#define TX_ANTENNA_MASK GENMASK(3, 0) |
developer | 1bc2ce2 | 2023-03-25 00:47:41 +0800 | [diff] [blame] | 660 | +#define RX_ANTENNA_MASK GENMASK(20, 16) /* RX antenna mask at most 5 bit */ |
| 661 | + struct mt7996_dev *dev = phy->dev; |
| 662 | + struct mt76_testmode_data *td = &phy->mt76->test; |
developer | de9ecce | 2023-05-22 11:17:16 +0800 | [diff] [blame] | 663 | + u32 antenna_mask; |
developer | 1bc2ce2 | 2023-03-25 00:47:41 +0800 | [diff] [blame] | 664 | + |
developer | de9ecce | 2023-05-22 11:17:16 +0800 | [diff] [blame] | 665 | + if (!mt76_testmode_param_present(td, MT76_TM_ATTR_TX_ANTENNA)) |
developer | 1bc2ce2 | 2023-03-25 00:47:41 +0800 | [diff] [blame] | 666 | + return; |
| 667 | + |
| 668 | + if (func_idx == SET_ID(TX_PATH)) |
| 669 | + antenna_mask = td->tx_spe_idx ? (SPE_INDEX_MASK | td->tx_spe_idx) : |
developer | 064da3c | 2023-06-13 15:57:26 +0800 | [diff] [blame] | 670 | + td->tx_antenna_mask & TX_ANTENNA_MASK; |
developer | 1bc2ce2 | 2023-03-25 00:47:41 +0800 | [diff] [blame] | 671 | + else if (func_idx == SET_ID(RX_PATH)) |
| 672 | + antenna_mask = u32_encode_bits(td->tx_antenna_mask, RX_ANTENNA_MASK); |
| 673 | + else |
| 674 | + return; |
| 675 | + |
| 676 | + mt7996_tm_set(dev, func_idx, antenna_mask); |
| 677 | +} |
| 678 | + |
| 679 | +static void |
| 680 | +mt7996_tm_set_mac_addr(struct mt7996_dev *dev, u8 *addr, u32 func_idx) |
| 681 | +{ |
| 682 | +#define REMAIN_PART_TAG BIT(18) |
| 683 | + u32 own_mac_first = 0, own_mac_remain = 0; |
| 684 | + int len = sizeof(u32); |
| 685 | + |
| 686 | + memcpy(&own_mac_first, addr, len); |
| 687 | + mt7996_tm_set(dev, func_idx, own_mac_first); |
| 688 | + /* Set the remain part of mac address */ |
| 689 | + memcpy(&own_mac_remain, addr + len, ETH_ALEN - len); |
| 690 | + mt7996_tm_set(dev, func_idx | REMAIN_PART_TAG, own_mac_remain); |
| 691 | +} |
| 692 | + |
| 693 | +static int |
| 694 | +mt7996_tm_rf_switch_mode(struct mt7996_dev *dev, u32 op_mode) |
| 695 | +{ |
| 696 | + struct mt7996_tm_req req = { |
| 697 | + .rf_test = { |
| 698 | + .tag = cpu_to_le16(UNI_RF_TEST_CTRL), |
| 699 | + .len = cpu_to_le16(sizeof(req.rf_test)), |
| 700 | + .action = RF_ACTION_SWITCH_TO_RF_TEST, |
| 701 | + .op.op_mode = cpu_to_le32(op_mode), |
| 702 | + }, |
| 703 | + }; |
| 704 | + |
| 705 | + return mt76_mcu_send_msg(&dev->mt76, MCU_WM_UNI_CMD(TESTMODE_CTRL), &req, |
| 706 | + sizeof(req), false); |
| 707 | +} |
| 708 | + |
| 709 | +static void |
| 710 | +mt7996_tm_init(struct mt7996_phy *phy, bool en) |
| 711 | +{ |
developer | 1bc2ce2 | 2023-03-25 00:47:41 +0800 | [diff] [blame] | 712 | + struct mt7996_dev *dev = phy->dev; |
| 713 | + u8 rf_test_mode = en ? RF_OPER_RF_TEST : RF_OPER_NORMAL; |
| 714 | + |
| 715 | + if (!test_bit(MT76_STATE_RUNNING, &phy->mt76->state)) |
| 716 | + return; |
| 717 | + |
| 718 | + mt7996_mcu_set_tx_power_ctrl(phy, POWER_CTRL(ATE_MODE), en); |
| 719 | + mt7996_mcu_set_tx_power_ctrl(phy, POWER_CTRL(SKU_POWER_LIMIT), !en); |
developer | 1bc2ce2 | 2023-03-25 00:47:41 +0800 | [diff] [blame] | 720 | + mt7996_mcu_set_tx_power_ctrl(phy, POWER_CTRL(BACKOFF_POWER_LIMIT), !en); |
| 721 | + |
| 722 | + mt7996_tm_rf_switch_mode(dev, rf_test_mode); |
| 723 | + |
| 724 | + mt7996_mcu_add_bss_info(phy, phy->monitor_vif, en); |
| 725 | + mt7996_mcu_add_sta(dev, phy->monitor_vif, NULL, en); |
| 726 | + |
| 727 | + mt7996_tm_set(dev, SET_ID(BAND_IDX), phy->mt76->band_idx); |
| 728 | + |
| 729 | + /* use firmware counter for RX stats */ |
| 730 | + phy->mt76->test.flag |= MT_TM_FW_RX_COUNT; |
| 731 | +} |
| 732 | + |
| 733 | +static void |
| 734 | +mt7996_tm_update_channel(struct mt7996_phy *phy) |
| 735 | +{ |
| 736 | +#define CHAN_FREQ_BW_80P80_TAG (SET_ID(CHAN_FREQ) | BIT(16)) |
| 737 | + struct mt7996_dev *dev = phy->dev; |
| 738 | + struct cfg80211_chan_def *chandef = &phy->mt76->chandef; |
| 739 | + struct ieee80211_channel *chan = chandef->chan; |
| 740 | + u8 width = chandef->width; |
| 741 | + static const u8 ch_band[] = { |
| 742 | + [NL80211_BAND_2GHZ] = 0, |
| 743 | + [NL80211_BAND_5GHZ] = 1, |
| 744 | + [NL80211_BAND_6GHZ] = 2, |
| 745 | + }; |
| 746 | + |
| 747 | + if (!chan || !chandef) { |
| 748 | + dev_info(dev->mt76.dev, "chandef not found, channel update failed!\n"); |
| 749 | + return; |
| 750 | + } |
| 751 | + |
| 752 | + /* system bw */ |
| 753 | + mt7996_tm_set(dev, SET_ID(CBW), mt7996_tm_bw_mapping(width, BW_MAP_NL_TO_FW)); |
| 754 | + |
| 755 | + if (width == NL80211_CHAN_WIDTH_80P80) { |
| 756 | + width = NL80211_CHAN_WIDTH_160; |
| 757 | + mt7996_tm_set(dev, CHAN_FREQ_BW_80P80_TAG, chandef->center_freq2 * 1000); |
| 758 | + } |
| 759 | + |
| 760 | + /* TODO: define per-packet bw */ |
| 761 | + /* per-packet bw */ |
| 762 | + mt7996_tm_set(dev, SET_ID(DBW), mt7996_tm_bw_mapping(width, BW_MAP_NL_TO_FW)); |
| 763 | + |
| 764 | + /* control channel selection index */ |
| 765 | + mt7996_tm_set(dev, SET_ID(PRIMARY_CH), 0); |
| 766 | + mt7996_tm_set(dev, SET_ID(BAND), ch_band[chan->band]); |
| 767 | + |
| 768 | + /* trigger switch channel calibration */ |
| 769 | + mt7996_tm_set(dev, SET_ID(CHAN_FREQ), chandef->center_freq1 * 1000); |
| 770 | + |
| 771 | + // TODO: update power limit table |
| 772 | +} |
| 773 | + |
| 774 | +static void |
| 775 | +mt7996_tm_tx_stop(struct mt76_phy *mphy) |
| 776 | +{ |
| 777 | + struct mt76_testmode_data *td = &mphy->test; |
| 778 | + struct mt7996_phy *phy = mphy->priv; |
| 779 | + struct mt7996_dev *dev = phy->dev; |
| 780 | + |
| 781 | + mt7996_tm_set(dev, SET_ID(COMMAND), RF_CMD(STOP_TEST)); |
| 782 | + td->tx_pending = 0; |
| 783 | +} |
| 784 | + |
| 785 | +static void |
| 786 | +mt7996_tm_set_tx_frames(struct mt7996_phy *phy, bool en) |
| 787 | +{ |
| 788 | +#define FRAME_CONTROL 0x88 |
| 789 | + struct mt76_testmode_data *td = &phy->mt76->test; |
| 790 | + struct mt7996_dev *dev = phy->dev; |
| 791 | + |
| 792 | + //TODO: RU operation, replace mcs, nss, and ldpc |
| 793 | + if (en) { |
| 794 | + mt7996_tm_set(dev, SET_ID(MAC_HEADER), FRAME_CONTROL); |
| 795 | + mt7996_tm_set(dev, SET_ID(SEQ_CTRL), 0); |
| 796 | + mt7996_tm_set(dev, SET_ID(TX_COUNT), td->tx_count); |
| 797 | + mt7996_tm_set(dev, SET_ID(TX_MODE), mt7996_tm_rate_to_phy(td->tx_rate_mode)); |
| 798 | + mt7996_tm_set(dev, SET_ID(TX_RATE), td->tx_rate_idx); |
developer | de9ecce | 2023-05-22 11:17:16 +0800 | [diff] [blame] | 799 | + |
| 800 | + if (mt76_testmode_param_present(td, MT76_TM_ATTR_TX_POWER)) |
| 801 | + mt7996_tm_set(dev, SET_ID(POWER), td->tx_power[0]); |
| 802 | + |
| 803 | + if (mt76_testmode_param_present(td, MT76_TM_ATTR_TX_TIME)) { |
| 804 | + mt7996_tm_set(dev, SET_ID(TX_LEN), 0); |
| 805 | + mt7996_tm_set(dev, SET_ID(TX_TIME), td->tx_time); |
| 806 | + } else { |
| 807 | + mt7996_tm_set(dev, SET_ID(TX_LEN), td->tx_mpdu_len); |
| 808 | + mt7996_tm_set(dev, SET_ID(TX_TIME), 0); |
| 809 | + } |
| 810 | + |
developer | 1bc2ce2 | 2023-03-25 00:47:41 +0800 | [diff] [blame] | 811 | + mt7996_tm_set_antenna(phy, SET_ID(TX_PATH)); |
developer | 064da3c | 2023-06-13 15:57:26 +0800 | [diff] [blame] | 812 | + mt7996_tm_set_antenna(phy, SET_ID(RX_PATH)); |
developer | 1bc2ce2 | 2023-03-25 00:47:41 +0800 | [diff] [blame] | 813 | + mt7996_tm_set(dev, SET_ID(STBC), td->tx_rate_stbc); |
| 814 | + mt7996_tm_set(dev, SET_ID(ENCODE_MODE), td->tx_rate_ldpc); |
| 815 | + mt7996_tm_set(dev, SET_ID(IBF_ENABLE), td->ibf); |
| 816 | + mt7996_tm_set(dev, SET_ID(EBF_ENABLE), td->ebf); |
| 817 | + mt7996_tm_set(dev, SET_ID(IPG), td->tx_ipg); |
| 818 | + mt7996_tm_set(dev, SET_ID(GI), td->tx_rate_sgi); |
| 819 | + mt7996_tm_set(dev, SET_ID(NSS), td->tx_rate_nss); |
| 820 | + mt7996_tm_set(dev, SET_ID(AID_OFFSET), 0); |
| 821 | + mt7996_tm_set(dev, SET_ID(PUNCTURE), td->tx_preamble_puncture); |
| 822 | + |
| 823 | + mt7996_tm_set(dev, SET_ID(MAX_PE), 2); |
| 824 | + mt7996_tm_set(dev, SET_ID(HW_TX_MODE), 0); |
| 825 | + mt7996_tm_update_channel(phy); |
| 826 | + |
| 827 | + /* trigger firmware to start TX */ |
| 828 | + mt7996_tm_set(dev, SET_ID(COMMAND), RF_CMD(START_TX)); |
| 829 | + } else { |
| 830 | + mt7996_tm_tx_stop(phy->mt76); |
| 831 | + } |
| 832 | +} |
| 833 | + |
| 834 | +static int |
| 835 | +mt7996_tm_rx_stats_user_ctrl(struct mt7996_phy *phy, u16 user_idx) |
| 836 | +{ |
| 837 | + struct mt7996_dev *dev = phy->dev; |
| 838 | + struct mt7996_tm_rx_req req = { |
| 839 | + .band = phy->mt76->band_idx, |
| 840 | + .user_ctrl = { |
| 841 | + .tag = cpu_to_le16(UNI_TM_RX_STAT_SET_USER_CTRL), |
| 842 | + .len = cpu_to_le16(sizeof(req.user_ctrl)), |
| 843 | + .band_idx = phy->mt76->band_idx, |
| 844 | + .user_idx = cpu_to_le16(user_idx), |
| 845 | + }, |
| 846 | + }; |
| 847 | + |
| 848 | + return mt76_mcu_send_msg(&dev->mt76, MCU_WM_UNI_CMD(TESTMODE_RX_STAT), &req, |
| 849 | + sizeof(req), false); |
| 850 | +} |
| 851 | + |
| 852 | +static void |
| 853 | +mt7996_tm_set_rx_frames(struct mt7996_phy *phy, bool en) |
| 854 | +{ |
| 855 | +#define RX_MU_DISABLE 0xf800 |
| 856 | + struct mt76_testmode_data *td = &phy->mt76->test; |
| 857 | + struct mt7996_dev *dev = phy->dev; |
| 858 | + int ret; |
| 859 | + |
| 860 | + if (en) { |
| 861 | + ret = mt7996_tm_rx_stats_user_ctrl(phy, td->aid); |
| 862 | + if (ret) { |
| 863 | + dev_info(dev->mt76.dev, "Set RX stats user control failed!\n"); |
| 864 | + return; |
| 865 | + } |
| 866 | + |
| 867 | + mt7996_tm_update_channel(phy); |
| 868 | + |
| 869 | + if (td->tx_rate_mode >= MT76_TM_TX_MODE_HE_MU) { |
| 870 | + if (td->aid) |
| 871 | + ret = mt7996_tm_set(dev, SET_ID(RX_MU_AID), td->aid); |
| 872 | + else |
| 873 | + ret = mt7996_tm_set(dev, SET_ID(RX_MU_AID), RX_MU_DISABLE); |
| 874 | + } |
| 875 | + mt7996_tm_set(dev, SET_ID(TX_MODE), mt7996_tm_rate_to_phy(td->tx_rate_mode)); |
| 876 | + mt7996_tm_set(dev, SET_ID(GI), td->tx_rate_sgi); |
| 877 | + mt7996_tm_set_antenna(phy, SET_ID(RX_PATH)); |
| 878 | + mt7996_tm_set(dev, SET_ID(MAX_PE), 2); |
| 879 | + |
| 880 | + mt7996_tm_set_mac_addr(dev, td->addr[1], SET_ID(SA)); |
| 881 | + |
| 882 | + /* trigger firmware to start RX */ |
| 883 | + mt7996_tm_set(dev, SET_ID(COMMAND), RF_CMD(START_RX)); |
| 884 | + } else { |
| 885 | + /* trigger firmware to stop RX */ |
| 886 | + mt7996_tm_set(dev, SET_ID(COMMAND), RF_CMD(STOP_TEST)); |
| 887 | + } |
| 888 | +} |
| 889 | + |
| 890 | +static void |
| 891 | +mt7996_tm_set_tx_cont(struct mt7996_phy *phy, bool en) |
| 892 | +{ |
| 893 | +#define CONT_WAVE_MODE_OFDM 3 |
| 894 | + struct mt76_testmode_data *td = &phy->mt76->test; |
| 895 | + struct mt7996_dev *dev = phy->dev; |
| 896 | + |
| 897 | + if (en) { |
| 898 | + mt7996_tm_update_channel(phy); |
| 899 | + mt7996_tm_set(dev, SET_ID(TX_MODE), mt7996_tm_rate_to_phy(td->tx_rate_mode)); |
| 900 | + mt7996_tm_set(dev, SET_ID(TX_RATE), td->tx_rate_idx); |
| 901 | + /* fix payload is OFDM */ |
| 902 | + mt7996_tm_set(dev, SET_ID(CONT_WAVE_MODE), CONT_WAVE_MODE_OFDM); |
| 903 | + mt7996_tm_set(dev, SET_ID(ANT_MASK), td->tx_antenna_mask); |
| 904 | + |
| 905 | + /* trigger firmware to start CONT TX */ |
| 906 | + mt7996_tm_set(dev, SET_ID(COMMAND), RF_CMD(CONT_WAVE)); |
| 907 | + } else { |
| 908 | + /* trigger firmware to stop CONT TX */ |
| 909 | + mt7996_tm_set(dev, SET_ID(COMMAND), RF_CMD(STOP_TEST)); |
| 910 | + } |
| 911 | +} |
| 912 | + |
| 913 | +static void |
| 914 | +mt7996_tm_update_params(struct mt7996_phy *phy, u32 changed) |
| 915 | +{ |
| 916 | + struct mt76_testmode_data *td = &phy->mt76->test; |
| 917 | + struct mt7996_dev *dev = phy->dev; |
| 918 | + bool en = td->state != MT76_TM_STATE_OFF; |
| 919 | + |
| 920 | + if (changed & BIT(TM_CHANGED_FREQ_OFFSET)) |
| 921 | + mt7996_tm_set(dev, SET_ID(FREQ_OFFSET), en ? td->freq_offset : 0); |
| 922 | + if (changed & BIT(TM_CHANGED_TXPOWER)) |
| 923 | + mt7996_tm_set(dev, SET_ID(POWER), td->tx_power[0]); |
developer | c2cfe0f | 2023-09-22 04:11:09 +0800 | [diff] [blame] | 924 | + if (changed & BIT(TM_CHANGED_SKU_EN)) { |
| 925 | + mt7996_tm_update_channel(phy); |
| 926 | + mt7996_mcu_set_tx_power_ctrl(phy, POWER_CTRL(SKU_POWER_LIMIT), td->sku_en); |
| 927 | + mt7996_mcu_set_tx_power_ctrl(phy, POWER_CTRL(BACKOFF_POWER_LIMIT), td->sku_en); |
| 928 | + mt7996_mcu_set_txpower_sku(phy); |
| 929 | + } |
developer | 1bc2ce2 | 2023-03-25 00:47:41 +0800 | [diff] [blame] | 930 | + if (changed & BIT(TM_CHANGED_TX_LENGTH)) { |
| 931 | + mt7996_tm_set(dev, SET_ID(TX_LEN), td->tx_mpdu_len); |
| 932 | + mt7996_tm_set(dev, SET_ID(TX_TIME), 0); |
| 933 | + } |
| 934 | + if (changed & BIT(TM_CHANGED_TX_TIME)) { |
| 935 | + mt7996_tm_set(dev, SET_ID(TX_LEN), 0); |
| 936 | + mt7996_tm_set(dev, SET_ID(TX_TIME), td->tx_time); |
| 937 | + } |
developer | de9ecce | 2023-05-22 11:17:16 +0800 | [diff] [blame] | 938 | + if (changed & BIT(TM_CHANGED_CFG)) { |
| 939 | + u32 func_idx = td->cfg.enable ? SET_ID(CFG_ON) : SET_ID(CFG_OFF); |
| 940 | + |
| 941 | + mt7996_tm_set(dev, func_idx, td->cfg.type); |
| 942 | + } |
developer | 1bc2ce2 | 2023-03-25 00:47:41 +0800 | [diff] [blame] | 943 | +} |
| 944 | + |
| 945 | +static int |
| 946 | +mt7996_tm_set_state(struct mt76_phy *mphy, enum mt76_testmode_state state) |
| 947 | +{ |
| 948 | + struct mt76_testmode_data *td = &mphy->test; |
| 949 | + struct mt7996_phy *phy = mphy->priv; |
| 950 | + enum mt76_testmode_state prev_state = td->state; |
| 951 | + |
| 952 | + mphy->test.state = state; |
| 953 | + |
| 954 | + if (prev_state != MT76_TM_STATE_OFF) |
| 955 | + mt7996_tm_set(phy->dev, SET_ID(BAND_IDX), mphy->band_idx); |
| 956 | + |
| 957 | + if (prev_state == MT76_TM_STATE_TX_FRAMES || |
| 958 | + state == MT76_TM_STATE_TX_FRAMES) |
| 959 | + mt7996_tm_set_tx_frames(phy, state == MT76_TM_STATE_TX_FRAMES); |
| 960 | + else if (prev_state == MT76_TM_STATE_RX_FRAMES || |
| 961 | + state == MT76_TM_STATE_RX_FRAMES) |
| 962 | + mt7996_tm_set_rx_frames(phy, state == MT76_TM_STATE_RX_FRAMES); |
| 963 | + else if (prev_state == MT76_TM_STATE_TX_CONT || |
| 964 | + state == MT76_TM_STATE_TX_CONT) |
| 965 | + mt7996_tm_set_tx_cont(phy, state == MT76_TM_STATE_TX_CONT); |
| 966 | + else if (prev_state == MT76_TM_STATE_OFF || |
| 967 | + state == MT76_TM_STATE_OFF) |
| 968 | + mt7996_tm_init(phy, !(state == MT76_TM_STATE_OFF)); |
| 969 | + |
| 970 | + if ((state == MT76_TM_STATE_IDLE && |
| 971 | + prev_state == MT76_TM_STATE_OFF) || |
| 972 | + (state == MT76_TM_STATE_OFF && |
| 973 | + prev_state == MT76_TM_STATE_IDLE)) { |
| 974 | + u32 changed = 0; |
developer | 064da3c | 2023-06-13 15:57:26 +0800 | [diff] [blame] | 975 | + int i, ret; |
developer | 1bc2ce2 | 2023-03-25 00:47:41 +0800 | [diff] [blame] | 976 | + |
| 977 | + for (i = 0; i < ARRAY_SIZE(tm_change_map); i++) { |
| 978 | + u16 cur = tm_change_map[i]; |
| 979 | + |
developer | de9ecce | 2023-05-22 11:17:16 +0800 | [diff] [blame] | 980 | + if (mt76_testmode_param_present(td, cur)) |
developer | 1bc2ce2 | 2023-03-25 00:47:41 +0800 | [diff] [blame] | 981 | + changed |= BIT(i); |
| 982 | + } |
| 983 | + |
developer | 064da3c | 2023-06-13 15:57:26 +0800 | [diff] [blame] | 984 | + ret = mt7996_tm_check_antenna(phy); |
| 985 | + if (ret) |
| 986 | + return ret; |
| 987 | + |
developer | 1bc2ce2 | 2023-03-25 00:47:41 +0800 | [diff] [blame] | 988 | + mt7996_tm_update_params(phy, changed); |
| 989 | + } |
| 990 | + |
| 991 | + return 0; |
| 992 | +} |
| 993 | + |
| 994 | +static int |
| 995 | +mt7996_tm_set_params(struct mt76_phy *mphy, struct nlattr **tb, |
| 996 | + enum mt76_testmode_state new_state) |
| 997 | +{ |
| 998 | + struct mt76_testmode_data *td = &mphy->test; |
| 999 | + struct mt7996_phy *phy = mphy->priv; |
| 1000 | + struct mt7996_dev *dev = phy->dev; |
developer | 064da3c | 2023-06-13 15:57:26 +0800 | [diff] [blame] | 1001 | + u32 changed = 0; |
| 1002 | + int i, ret; |
developer | 1bc2ce2 | 2023-03-25 00:47:41 +0800 | [diff] [blame] | 1003 | + |
| 1004 | + BUILD_BUG_ON(NUM_TM_CHANGED >= 32); |
| 1005 | + |
| 1006 | + if (new_state == MT76_TM_STATE_OFF || |
| 1007 | + td->state == MT76_TM_STATE_OFF) |
| 1008 | + return 0; |
| 1009 | + |
developer | 064da3c | 2023-06-13 15:57:26 +0800 | [diff] [blame] | 1010 | + ret = mt7996_tm_check_antenna(phy); |
| 1011 | + if (ret) |
| 1012 | + return ret; |
developer | 1bc2ce2 | 2023-03-25 00:47:41 +0800 | [diff] [blame] | 1013 | + |
| 1014 | + for (i = 0; i < ARRAY_SIZE(tm_change_map); i++) { |
| 1015 | + if (tb[tm_change_map[i]]) |
| 1016 | + changed |= BIT(i); |
| 1017 | + } |
| 1018 | + |
| 1019 | + mt7996_tm_set(dev, SET_ID(BAND_IDX), mphy->band_idx); |
| 1020 | + mt7996_tm_update_params(phy, changed); |
| 1021 | + |
| 1022 | + return 0; |
| 1023 | +} |
| 1024 | + |
| 1025 | +static int |
| 1026 | +mt7996_tm_get_rx_stats(struct mt7996_phy *phy) |
| 1027 | +{ |
| 1028 | + struct mt7996_dev *dev = phy->dev; |
| 1029 | + struct mt7996_tm_rx_req req = { |
| 1030 | + .band = phy->mt76->band_idx, |
| 1031 | + .rx_stat_all = { |
| 1032 | + .tag = cpu_to_le16(UNI_TM_RX_STAT_GET_ALL_V2), |
| 1033 | + .len = cpu_to_le16(sizeof(req.rx_stat_all)), |
| 1034 | + .band_idx = phy->mt76->band_idx, |
| 1035 | + }, |
| 1036 | + }; |
| 1037 | + struct mt76_testmode_data *td = &phy->mt76->test; |
| 1038 | + struct mt7996_tm_rx_event *rx_stats; |
| 1039 | + struct mt7996_tm_rx_event_stat_all *rx_stats_all; |
| 1040 | + struct sk_buff *skb; |
| 1041 | + enum mt76_rxq_id qid; |
| 1042 | + int i, ret = 0; |
| 1043 | + u32 mac_rx_mdrdy_cnt; |
| 1044 | + u16 mac_rx_len_mismatch, fcs_err_count; |
| 1045 | + |
| 1046 | + if (td->state != MT76_TM_STATE_RX_FRAMES) |
| 1047 | + return 0; |
| 1048 | + |
| 1049 | + ret = mt76_mcu_send_and_get_msg(&dev->mt76, MCU_WM_UNI_CMD_QUERY(TESTMODE_RX_STAT), |
| 1050 | + &req, sizeof(req), true, &skb); |
| 1051 | + |
| 1052 | + if (ret) |
| 1053 | + return ret; |
| 1054 | + |
| 1055 | + rx_stats = (struct mt7996_tm_rx_event *)skb->data; |
| 1056 | + rx_stats_all = &rx_stats->rx_stat_all; |
| 1057 | + |
| 1058 | + phy->test.last_freq_offset = le32_to_cpu(rx_stats_all->user_info[0].freq_offset); |
| 1059 | + phy->test.last_snr = le32_to_cpu(rx_stats_all->user_info[0].snr); |
| 1060 | + for (i = 0; i < ARRAY_SIZE(phy->test.last_rcpi); i++) { |
| 1061 | + phy->test.last_rcpi[i] = le16_to_cpu(rx_stats_all->rxv_info[i].rcpi); |
developer | c2cfe0f | 2023-09-22 04:11:09 +0800 | [diff] [blame] | 1062 | + phy->test.last_rssi[i] = le16_to_cpu(rx_stats_all->rxv_info[i].rssi); |
developer | 1bc2ce2 | 2023-03-25 00:47:41 +0800 | [diff] [blame] | 1063 | + phy->test.last_ib_rssi[i] = rx_stats_all->fagc[i].ib_rssi; |
| 1064 | + phy->test.last_wb_rssi[i] = rx_stats_all->fagc[i].wb_rssi; |
| 1065 | + } |
| 1066 | + |
| 1067 | + if (phy->mt76->band_idx == 2) |
| 1068 | + qid = MT_RXQ_BAND2; |
| 1069 | + else if (phy->mt76->band_idx == 1) |
| 1070 | + qid = MT_RXQ_BAND1; |
| 1071 | + else |
| 1072 | + qid = MT_RXQ_MAIN; |
| 1073 | + |
| 1074 | + fcs_err_count = le16_to_cpu(rx_stats_all->band_info.mac_rx_fcs_err_cnt); |
| 1075 | + mac_rx_len_mismatch = le16_to_cpu(rx_stats_all->band_info.mac_rx_len_mismatch); |
| 1076 | + mac_rx_mdrdy_cnt = le32_to_cpu(rx_stats_all->band_info.mac_rx_mdrdy_cnt); |
| 1077 | + td->rx_stats.packets[qid] += mac_rx_mdrdy_cnt; |
| 1078 | + td->rx_stats.packets[qid] += fcs_err_count; |
| 1079 | + td->rx_stats.fcs_error[qid] += fcs_err_count; |
| 1080 | + td->rx_stats.len_mismatch += mac_rx_len_mismatch; |
| 1081 | + |
| 1082 | + dev_kfree_skb(skb); |
| 1083 | + |
| 1084 | + return ret; |
| 1085 | +} |
| 1086 | + |
| 1087 | +static void |
developer | de9ecce | 2023-05-22 11:17:16 +0800 | [diff] [blame] | 1088 | +mt7996_tm_reset_trx_stats(struct mt76_phy *mphy) |
developer | 1bc2ce2 | 2023-03-25 00:47:41 +0800 | [diff] [blame] | 1089 | +{ |
| 1090 | + struct mt7996_phy *phy = mphy->priv; |
| 1091 | + struct mt7996_dev *dev = phy->dev; |
| 1092 | + |
| 1093 | + memset(&mphy->test.rx_stats, 0, sizeof(mphy->test.rx_stats)); |
| 1094 | + mt7996_tm_set(dev, SET_ID(TRX_COUNTER_RESET), 0); |
| 1095 | +} |
| 1096 | + |
| 1097 | +static int |
| 1098 | +mt7996_tm_get_tx_stats(struct mt7996_phy *phy) |
| 1099 | +{ |
| 1100 | + struct mt7996_dev *dev = phy->dev; |
| 1101 | + struct mt76_testmode_data *td = &phy->mt76->test; |
| 1102 | + int ret; |
| 1103 | + |
| 1104 | + if (td->state != MT76_TM_STATE_TX_FRAMES) |
| 1105 | + return 0; |
| 1106 | + |
| 1107 | + ret = mt7996_tm_get(dev, GET_ID(TXED_COUNT), 0, &td->tx_done); |
| 1108 | + if (ret) |
| 1109 | + return ret; |
| 1110 | + |
| 1111 | + td->tx_pending = td->tx_count - td->tx_done; |
| 1112 | + |
| 1113 | + return ret; |
| 1114 | +} |
| 1115 | + |
| 1116 | +static int |
| 1117 | +mt7996_tm_dump_stats(struct mt76_phy *mphy, struct sk_buff *msg) |
| 1118 | +{ |
| 1119 | + struct mt7996_phy *phy = mphy->priv; |
| 1120 | + void *rx, *rssi; |
| 1121 | + int i; |
| 1122 | + |
| 1123 | + mt7996_tm_set(phy->dev, SET_ID(BAND_IDX), mphy->band_idx); |
| 1124 | + mt7996_tm_get_rx_stats(phy); |
| 1125 | + mt7996_tm_get_tx_stats(phy); |
| 1126 | + |
| 1127 | + rx = nla_nest_start(msg, MT76_TM_STATS_ATTR_LAST_RX); |
| 1128 | + if (!rx) |
| 1129 | + return -ENOMEM; |
| 1130 | + |
| 1131 | + if (nla_put_s32(msg, MT76_TM_RX_ATTR_FREQ_OFFSET, phy->test.last_freq_offset)) |
| 1132 | + return -ENOMEM; |
| 1133 | + |
| 1134 | + rssi = nla_nest_start(msg, MT76_TM_RX_ATTR_RCPI); |
| 1135 | + if (!rssi) |
| 1136 | + return -ENOMEM; |
| 1137 | + |
| 1138 | + for (i = 0; i < ARRAY_SIZE(phy->test.last_rcpi); i++) |
| 1139 | + if (nla_put_u8(msg, i, phy->test.last_rcpi[i])) |
| 1140 | + return -ENOMEM; |
| 1141 | + |
| 1142 | + nla_nest_end(msg, rssi); |
| 1143 | + |
developer | c2cfe0f | 2023-09-22 04:11:09 +0800 | [diff] [blame] | 1144 | + rssi = nla_nest_start(msg, MT76_TM_RX_ATTR_RSSI); |
| 1145 | + if (!rssi) |
| 1146 | + return -ENOMEM; |
| 1147 | + |
| 1148 | + for (i = 0; i < ARRAY_SIZE(phy->test.last_rssi); i++) |
| 1149 | + if (nla_put_s8(msg, i, phy->test.last_rssi[i])) |
| 1150 | + return -ENOMEM; |
| 1151 | + |
| 1152 | + nla_nest_end(msg, rssi); |
| 1153 | + |
developer | 1bc2ce2 | 2023-03-25 00:47:41 +0800 | [diff] [blame] | 1154 | + rssi = nla_nest_start(msg, MT76_TM_RX_ATTR_IB_RSSI); |
| 1155 | + if (!rssi) |
| 1156 | + return -ENOMEM; |
| 1157 | + |
| 1158 | + for (i = 0; i < ARRAY_SIZE(phy->test.last_ib_rssi); i++) |
| 1159 | + if (nla_put_s8(msg, i, phy->test.last_ib_rssi[i])) |
| 1160 | + return -ENOMEM; |
| 1161 | + |
| 1162 | + nla_nest_end(msg, rssi); |
| 1163 | + |
| 1164 | + rssi = nla_nest_start(msg, MT76_TM_RX_ATTR_WB_RSSI); |
| 1165 | + if (!rssi) |
| 1166 | + return -ENOMEM; |
| 1167 | + |
| 1168 | + for (i = 0; i < ARRAY_SIZE(phy->test.last_wb_rssi); i++) |
| 1169 | + if (nla_put_s8(msg, i, phy->test.last_wb_rssi[i])) |
| 1170 | + return -ENOMEM; |
| 1171 | + |
| 1172 | + nla_nest_end(msg, rssi); |
| 1173 | + |
| 1174 | + if (nla_put_u8(msg, MT76_TM_RX_ATTR_SNR, phy->test.last_snr)) |
| 1175 | + return -ENOMEM; |
| 1176 | + |
| 1177 | + nla_nest_end(msg, rx); |
| 1178 | + |
| 1179 | + return 0; |
| 1180 | +} |
| 1181 | + |
| 1182 | +const struct mt76_testmode_ops mt7996_testmode_ops = { |
| 1183 | + .set_state = mt7996_tm_set_state, |
| 1184 | + .set_params = mt7996_tm_set_params, |
| 1185 | + .dump_stats = mt7996_tm_dump_stats, |
developer | de9ecce | 2023-05-22 11:17:16 +0800 | [diff] [blame] | 1186 | + .reset_rx_stats = mt7996_tm_reset_trx_stats, |
developer | 1bc2ce2 | 2023-03-25 00:47:41 +0800 | [diff] [blame] | 1187 | + .tx_stop = mt7996_tm_tx_stop, |
| 1188 | +}; |
| 1189 | diff --git a/mt7996/testmode.h b/mt7996/testmode.h |
| 1190 | new file mode 100644 |
developer | c2cfe0f | 2023-09-22 04:11:09 +0800 | [diff] [blame] | 1191 | index 000000000..e4d55a61a |
developer | 1bc2ce2 | 2023-03-25 00:47:41 +0800 | [diff] [blame] | 1192 | --- /dev/null |
| 1193 | +++ b/mt7996/testmode.h |
developer | c2cfe0f | 2023-09-22 04:11:09 +0800 | [diff] [blame] | 1194 | @@ -0,0 +1,297 @@ |
developer | 1bc2ce2 | 2023-03-25 00:47:41 +0800 | [diff] [blame] | 1195 | +/* SPDX-License-Identifier: ISC */ |
| 1196 | +/* Copyright (C) 2020 MediaTek Inc. */ |
| 1197 | + |
| 1198 | +#ifndef __MT7996_TESTMODE_H |
| 1199 | +#define __MT7996_TESTMODE_H |
| 1200 | + |
| 1201 | +enum { |
| 1202 | + TM_CBW_20MHZ, |
| 1203 | + TM_CBW_40MHZ, |
| 1204 | + TM_CBW_80MHZ, |
| 1205 | + TM_CBW_10MHZ, |
| 1206 | + TM_CBW_5MHZ, |
| 1207 | + TM_CBW_160MHZ, |
| 1208 | + TM_CBW_8080MHZ, |
| 1209 | + TM_CBW_320MHZ = 12, |
| 1210 | +}; |
| 1211 | + |
| 1212 | +/* BW defined in FW hal_cal_flow_rom.h */ |
| 1213 | +enum { |
| 1214 | + FW_CDBW_20MHZ, |
| 1215 | + FW_CDBW_40MHZ, |
| 1216 | + FW_CDBW_80MHZ, |
| 1217 | + FW_CDBW_160MHZ, |
| 1218 | + FW_CDBW_320MHZ, |
| 1219 | + FW_CDBW_5MHZ, |
| 1220 | + FW_CDBW_10MHZ, |
| 1221 | + FW_CDBW_8080MHZ, |
| 1222 | +}; |
| 1223 | + |
| 1224 | +enum bw_mapping_method { |
| 1225 | + BW_MAP_NL_TO_FW, |
| 1226 | + BW_MAP_NL_TO_TM, |
| 1227 | + |
| 1228 | + NUM_BW_MAP, |
| 1229 | +}; |
| 1230 | + |
| 1231 | +struct mt7996_tm_rf_test { |
| 1232 | + __le16 tag; |
| 1233 | + __le16 len; |
| 1234 | + |
| 1235 | + u8 action; |
| 1236 | + u8 icap_len; |
| 1237 | + u8 _rsv[2]; |
| 1238 | + union { |
| 1239 | + __le32 op_mode; |
| 1240 | + __le32 freq; |
| 1241 | + |
| 1242 | + struct { |
| 1243 | + __le32 func_idx; |
| 1244 | + union { |
| 1245 | + __le32 func_data; |
| 1246 | + __le32 cal_dump; |
| 1247 | + |
| 1248 | + u8 _pad[80]; |
| 1249 | + } param; |
| 1250 | + } rf; |
| 1251 | + } op; |
| 1252 | +} __packed; |
| 1253 | + |
| 1254 | +struct mt7996_tm_req { |
| 1255 | + u8 _rsv[4]; |
| 1256 | + |
| 1257 | + struct mt7996_tm_rf_test rf_test; |
| 1258 | +} __packed; |
| 1259 | + |
| 1260 | +struct mt7996_tm_rf_test_result { |
| 1261 | + __le32 func_idx; |
| 1262 | + __le32 payload_length; |
| 1263 | + u8 event[0]; |
| 1264 | +}; |
| 1265 | + |
| 1266 | +struct mt7996_tm_event { |
| 1267 | + u8 _rsv[4]; |
| 1268 | + |
| 1269 | + __le16 tag; |
| 1270 | + __le16 len; |
| 1271 | + struct mt7996_tm_rf_test_result result; |
| 1272 | +} __packed; |
| 1273 | + |
| 1274 | +enum { |
| 1275 | + RF_ACTION_SWITCH_TO_RF_TEST, |
| 1276 | + RF_ACTION_IN_RF_TEST, |
| 1277 | + RF_ACTION_SET = 3, |
| 1278 | + RF_ACTION_GET, |
| 1279 | +}; |
| 1280 | + |
| 1281 | +enum { |
| 1282 | + RF_OPER_NORMAL, |
| 1283 | + RF_OPER_RF_TEST, |
| 1284 | + RF_OPER_ICAP, |
| 1285 | + RF_OPER_ICAP_OVERLAP, |
| 1286 | + RF_OPER_WIFI_SPECTRUM, |
| 1287 | +}; |
| 1288 | + |
| 1289 | +enum { |
| 1290 | + UNI_RF_TEST_CTRL, |
| 1291 | +}; |
| 1292 | + |
| 1293 | +#define RF_CMD(cmd) RF_TEST_CMD_##cmd |
| 1294 | + |
| 1295 | +enum { |
| 1296 | + RF_TEST_CMD_STOP_TEST = 0, |
| 1297 | + RF_TEST_CMD_START_TX = 1, |
| 1298 | + RF_TEST_CMD_START_RX = 2, |
| 1299 | + RF_TEST_CMD_CONT_WAVE = 10, |
| 1300 | + RF_TEST_CMD_TX_COMMIT = 18, |
| 1301 | + RF_TEST_CMD_RX_COMMIT = 19, |
| 1302 | +}; |
| 1303 | + |
| 1304 | +#define SET_ID(id) RF_TEST_ID_SET_##id |
| 1305 | +#define GET_ID(id) RF_TEST_ID_GET_##id |
| 1306 | + |
| 1307 | +enum { |
| 1308 | + RF_TEST_ID_SET_COMMAND = 1, |
| 1309 | + RF_TEST_ID_SET_POWER = 2, |
| 1310 | + RF_TEST_ID_SET_TX_RATE = 3, |
| 1311 | + RF_TEST_ID_SET_TX_MODE = 4, |
| 1312 | + RF_TEST_ID_SET_TX_LEN = 6, |
| 1313 | + RF_TEST_ID_SET_TX_COUNT = 7, |
| 1314 | + RF_TEST_ID_SET_IPG = 8, |
| 1315 | + RF_TEST_ID_SET_GI = 16, |
| 1316 | + RF_TEST_ID_SET_STBC = 17, |
| 1317 | + RF_TEST_ID_SET_CHAN_FREQ = 18, |
| 1318 | + RF_TEST_ID_GET_TXED_COUNT = 32, |
| 1319 | + RF_TEST_ID_SET_CONT_WAVE_MODE = 65, |
| 1320 | + RF_TEST_ID_SET_DA = 68, |
| 1321 | + RF_TEST_ID_SET_SA = 69, |
| 1322 | + RF_TEST_ID_SET_CBW = 71, |
| 1323 | + RF_TEST_ID_SET_DBW = 72, |
| 1324 | + RF_TEST_ID_SET_PRIMARY_CH = 73, |
| 1325 | + RF_TEST_ID_SET_ENCODE_MODE = 74, |
| 1326 | + RF_TEST_ID_SET_BAND = 90, |
| 1327 | + RF_TEST_ID_SET_TRX_COUNTER_RESET = 91, |
| 1328 | + RF_TEST_ID_SET_MAC_HEADER = 101, |
| 1329 | + RF_TEST_ID_SET_SEQ_CTRL = 102, |
developer | de9ecce | 2023-05-22 11:17:16 +0800 | [diff] [blame] | 1330 | + RF_TEST_ID_SET_PAYLOAD = 103, |
developer | 1bc2ce2 | 2023-03-25 00:47:41 +0800 | [diff] [blame] | 1331 | + RF_TEST_ID_SET_BAND_IDX = 104, |
| 1332 | + RF_TEST_ID_SET_RX_PATH = 106, |
| 1333 | + RF_TEST_ID_SET_FREQ_OFFSET = 107, |
| 1334 | + RF_TEST_ID_GET_FREQ_OFFSET = 108, |
| 1335 | + RF_TEST_ID_SET_TX_PATH = 113, |
| 1336 | + RF_TEST_ID_SET_NSS = 114, |
| 1337 | + RF_TEST_ID_SET_ANT_MASK = 115, |
| 1338 | + RF_TEST_ID_SET_IBF_ENABLE = 126, |
| 1339 | + RF_TEST_ID_SET_EBF_ENABLE = 127, |
| 1340 | + RF_TEST_ID_GET_TX_POWER = 136, |
| 1341 | + RF_TEST_ID_SET_RX_MU_AID = 157, |
| 1342 | + RF_TEST_ID_SET_HW_TX_MODE = 167, |
| 1343 | + RF_TEST_ID_SET_PUNCTURE = 168, |
developer | de9ecce | 2023-05-22 11:17:16 +0800 | [diff] [blame] | 1344 | + RF_TEST_ID_SET_CFG_ON = 176, |
| 1345 | + RF_TEST_ID_SET_CFG_OFF = 177, |
developer | 1bc2ce2 | 2023-03-25 00:47:41 +0800 | [diff] [blame] | 1346 | + RF_TEST_ID_SET_BSSID = 189, |
| 1347 | + RF_TEST_ID_SET_TX_TIME = 190, |
| 1348 | + RF_TEST_ID_SET_MAX_PE = 191, |
| 1349 | + RF_TEST_ID_SET_AID_OFFSET = 204, |
| 1350 | +}; |
| 1351 | + |
developer | c2cfe0f | 2023-09-22 04:11:09 +0800 | [diff] [blame] | 1352 | +#define POWER_CTRL(type) UNI_TXPOWER_##type##_CTRL |
| 1353 | + |
developer | 1bc2ce2 | 2023-03-25 00:47:41 +0800 | [diff] [blame] | 1354 | +struct mt7996_tm_rx_stat_user_ctrl { |
| 1355 | + __le16 tag; |
| 1356 | + __le16 len; |
| 1357 | + |
| 1358 | + u8 band_idx; |
| 1359 | + u8 rsv; |
| 1360 | + __le16 user_idx; |
| 1361 | +} __packed; |
| 1362 | + |
| 1363 | +struct mt7996_tm_rx_stat_all { |
| 1364 | + __le16 tag; |
| 1365 | + __le16 len; |
| 1366 | + |
| 1367 | + u8 band_idx; |
| 1368 | + u8 rsv[3]; |
| 1369 | +} __packed; |
| 1370 | + |
| 1371 | +struct mt7996_tm_rx_req { |
| 1372 | + u8 band; |
| 1373 | + u8 _rsv[3]; |
| 1374 | + |
| 1375 | + union { |
| 1376 | + struct mt7996_tm_rx_stat_user_ctrl user_ctrl; |
| 1377 | + struct mt7996_tm_rx_stat_all rx_stat_all; |
| 1378 | + }; |
| 1379 | +} __packed; |
| 1380 | + |
| 1381 | +enum { |
| 1382 | + UNI_TM_RX_STAT_SET_USER_CTRL = 7, |
| 1383 | + UNI_TM_RX_STAT_GET_ALL_V2 = 9, |
| 1384 | +}; |
| 1385 | + |
| 1386 | +struct rx_band_info { |
| 1387 | + /* mac part */ |
| 1388 | + __le16 mac_rx_fcs_err_cnt; |
| 1389 | + __le16 mac_rx_len_mismatch; |
| 1390 | + __le16 mac_rx_fcs_ok_cnt; |
| 1391 | + u8 rsv1[2]; |
| 1392 | + __le32 mac_rx_mdrdy_cnt; |
| 1393 | + |
| 1394 | + /* phy part */ |
| 1395 | + __le16 phy_rx_fcs_err_cnt_cck; |
| 1396 | + __le16 phy_rx_fcs_err_cnt_ofdm; |
| 1397 | + __le16 phy_rx_pd_cck; |
| 1398 | + __le16 phy_rx_pd_ofdm; |
| 1399 | + __le16 phy_rx_sig_err_cck; |
| 1400 | + __le16 phy_rx_sfd_err_cck; |
| 1401 | + __le16 phy_rx_sig_err_ofdm; |
| 1402 | + __le16 phy_rx_tag_err_ofdm; |
| 1403 | + __le16 phy_rx_mdrdy_cnt_cck; |
| 1404 | + __le16 phy_rx_mdrdy_cnt_ofdm; |
| 1405 | +} __packed; |
| 1406 | + |
| 1407 | +struct rx_band_info_ext { |
| 1408 | + /* mac part */ |
| 1409 | + __le32 mac_rx_mpdu_cnt; |
| 1410 | + |
| 1411 | + /* phy part */ |
| 1412 | + u8 rsv[4]; |
| 1413 | +} __packed; |
| 1414 | + |
| 1415 | +struct rx_common_info { |
| 1416 | + __le16 rx_fifo_full; |
| 1417 | + u8 rsv[2]; |
| 1418 | + __le32 aci_hit_low; |
| 1419 | + __le32 aci_hit_high; |
| 1420 | +} __packed; |
| 1421 | + |
| 1422 | +struct rx_common_info_ext { |
| 1423 | + __le32 driver_rx_count; |
| 1424 | + __le32 sinr; |
| 1425 | + __le32 mu_pkt_count; |
| 1426 | + |
| 1427 | + /* mac part */ |
| 1428 | + u8 _rsv[4]; |
| 1429 | + |
| 1430 | + /* phy part */ |
| 1431 | + u8 sig_mcs; |
| 1432 | + u8 rsv[3]; |
| 1433 | +} __packed; |
| 1434 | + |
| 1435 | +struct rx_rxv_info { |
| 1436 | + __le16 rcpi; |
| 1437 | + s16 rssi; |
| 1438 | + s16 snr; |
| 1439 | + s16 adc_rssi; |
| 1440 | +} __packed; |
| 1441 | + |
| 1442 | +struct rx_rssi_info { |
| 1443 | + s8 ib_rssi; |
| 1444 | + s8 wb_rssi; |
| 1445 | + u8 rsv[2]; |
| 1446 | +} __packed; |
| 1447 | + |
| 1448 | +struct rx_user_info { |
| 1449 | + s32 freq_offset; |
| 1450 | + s32 snr; |
| 1451 | + __le32 fcs_err_count; |
| 1452 | +} __packed; |
| 1453 | + |
| 1454 | +struct rx_user_info_ext { |
| 1455 | + s8 ne_var_db_all_user; |
| 1456 | + u8 rsv[3]; |
| 1457 | +} __packed; |
| 1458 | + |
| 1459 | +#define MAX_ANTENNA_NUM 8 |
| 1460 | +#define MAX_USER_NUM 16 |
| 1461 | + |
| 1462 | +struct mt7996_tm_rx_event_stat_all { |
| 1463 | + __le16 tag; |
| 1464 | + __le16 len; |
| 1465 | + |
| 1466 | + struct rx_band_info band_info; |
| 1467 | + struct rx_band_info_ext band_info_ext; |
| 1468 | + struct rx_common_info common_info; |
| 1469 | + struct rx_common_info_ext common_info_ext; |
| 1470 | + |
| 1471 | + /* RXV info */ |
| 1472 | + struct rx_rxv_info rxv_info[MAX_ANTENNA_NUM]; |
| 1473 | + |
| 1474 | + /* RSSI info */ |
| 1475 | + struct rx_rssi_info fagc[MAX_ANTENNA_NUM]; |
| 1476 | + struct rx_rssi_info inst[MAX_ANTENNA_NUM]; |
| 1477 | + |
| 1478 | + /* User info */ |
| 1479 | + struct rx_user_info user_info[MAX_USER_NUM]; |
| 1480 | + struct rx_user_info_ext user_info_ext[MAX_USER_NUM]; |
| 1481 | +} __packed; |
| 1482 | + |
| 1483 | +struct mt7996_tm_rx_event { |
| 1484 | + u8 _rsv[4]; |
| 1485 | + |
| 1486 | + union { |
| 1487 | + struct mt7996_tm_rx_event_stat_all rx_stat_all; |
| 1488 | + }; |
| 1489 | +} __packed; |
| 1490 | + |
| 1491 | +#endif |
| 1492 | diff --git a/testmode.c b/testmode.c |
developer | c2cfe0f | 2023-09-22 04:11:09 +0800 | [diff] [blame] | 1493 | index 5c93aa6a8..bbe8230fd 100644 |
developer | 1bc2ce2 | 2023-03-25 00:47:41 +0800 | [diff] [blame] | 1494 | --- a/testmode.c |
| 1495 | +++ b/testmode.c |
developer | c2cfe0f | 2023-09-22 04:11:09 +0800 | [diff] [blame] | 1496 | @@ -2,11 +2,13 @@ |
developer | 1bc2ce2 | 2023-03-25 00:47:41 +0800 | [diff] [blame] | 1497 | /* Copyright (C) 2020 Felix Fietkau <nbd@nbd.name> */ |
| 1498 | |
| 1499 | #include <linux/random.h> |
| 1500 | +#include "mt76_connac.h" |
| 1501 | #include "mt76.h" |
| 1502 | |
| 1503 | const struct nla_policy mt76_tm_policy[NUM_MT76_TM_ATTRS] = { |
developer | c2cfe0f | 2023-09-22 04:11:09 +0800 | [diff] [blame] | 1504 | [MT76_TM_ATTR_RESET] = { .type = NLA_FLAG }, |
| 1505 | [MT76_TM_ATTR_STATE] = { .type = NLA_U8 }, |
| 1506 | + [MT76_TM_ATTR_SKU_EN] = { .type = NLA_U8 }, |
| 1507 | [MT76_TM_ATTR_TX_COUNT] = { .type = NLA_U32 }, |
| 1508 | [MT76_TM_ATTR_TX_LENGTH] = { .type = NLA_U32 }, |
| 1509 | [MT76_TM_ATTR_TX_RATE_MODE] = { .type = NLA_U8 }, |
| 1510 | @@ -82,6 +84,11 @@ mt76_testmode_max_mpdu_len(struct mt76_phy *phy, u8 tx_rate_mode) |
developer | 1bc2ce2 | 2023-03-25 00:47:41 +0800 | [diff] [blame] | 1511 | IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_7991) |
| 1512 | return IEEE80211_MAX_MPDU_LEN_VHT_7991; |
| 1513 | return IEEE80211_MAX_MPDU_LEN_VHT_11454; |
| 1514 | + case MT76_TM_TX_MODE_EHT_SU: |
| 1515 | + case MT76_TM_TX_MODE_EHT_TRIG: |
| 1516 | + case MT76_TM_TX_MODE_EHT_MU: |
| 1517 | + /* TODO: check the limit */ |
| 1518 | + return UINT_MAX; |
| 1519 | case MT76_TM_TX_MODE_CCK: |
| 1520 | case MT76_TM_TX_MODE_OFDM: |
| 1521 | default: |
developer | c2cfe0f | 2023-09-22 04:11:09 +0800 | [diff] [blame] | 1522 | @@ -183,6 +190,9 @@ mt76_testmode_tx_init(struct mt76_phy *phy) |
developer | 1bc2ce2 | 2023-03-25 00:47:41 +0800 | [diff] [blame] | 1523 | u8 max_nss = hweight8(phy->antenna_mask); |
| 1524 | int ret; |
| 1525 | |
| 1526 | + if (is_mt7996(phy->dev)) |
| 1527 | + return 0; |
| 1528 | + |
| 1529 | ret = mt76_testmode_alloc_skb(phy, td->tx_mpdu_len); |
| 1530 | if (ret) |
| 1531 | return ret; |
developer | c2cfe0f | 2023-09-22 04:11:09 +0800 | [diff] [blame] | 1532 | @@ -275,7 +285,9 @@ mt76_testmode_tx_start(struct mt76_phy *phy) |
developer | 1bc2ce2 | 2023-03-25 00:47:41 +0800 | [diff] [blame] | 1533 | td->tx_queued = 0; |
| 1534 | td->tx_done = 0; |
| 1535 | td->tx_pending = td->tx_count; |
| 1536 | - mt76_worker_schedule(&dev->tx_worker); |
| 1537 | + |
| 1538 | + if (!is_mt7996(dev)) |
| 1539 | + mt76_worker_schedule(&dev->tx_worker); |
| 1540 | } |
| 1541 | |
| 1542 | static void |
developer | c2cfe0f | 2023-09-22 04:11:09 +0800 | [diff] [blame] | 1543 | @@ -284,6 +296,11 @@ mt76_testmode_tx_stop(struct mt76_phy *phy) |
developer | 1bc2ce2 | 2023-03-25 00:47:41 +0800 | [diff] [blame] | 1544 | struct mt76_testmode_data *td = &phy->test; |
| 1545 | struct mt76_dev *dev = phy->dev; |
| 1546 | |
| 1547 | + if (is_mt7996(dev) && dev->test_ops->tx_stop) { |
| 1548 | + dev->test_ops->tx_stop(phy); |
| 1549 | + return; |
| 1550 | + } |
| 1551 | + |
| 1552 | mt76_worker_disable(&dev->tx_worker); |
| 1553 | |
| 1554 | td->tx_pending = 0; |
developer | c2cfe0f | 2023-09-22 04:11:09 +0800 | [diff] [blame] | 1555 | @@ -296,22 +313,11 @@ mt76_testmode_tx_stop(struct mt76_phy *phy) |
developer | de9ecce | 2023-05-22 11:17:16 +0800 | [diff] [blame] | 1556 | mt76_testmode_free_skb(phy); |
| 1557 | } |
| 1558 | |
| 1559 | -static inline void |
| 1560 | -mt76_testmode_param_set(struct mt76_testmode_data *td, u16 idx) |
| 1561 | -{ |
| 1562 | - td->param_set[idx / 32] |= BIT(idx % 32); |
| 1563 | -} |
| 1564 | - |
| 1565 | -static inline bool |
| 1566 | -mt76_testmode_param_present(struct mt76_testmode_data *td, u16 idx) |
| 1567 | -{ |
| 1568 | - return td->param_set[idx / 32] & BIT(idx % 32); |
| 1569 | -} |
| 1570 | - |
| 1571 | static void |
developer | 1bc2ce2 | 2023-03-25 00:47:41 +0800 | [diff] [blame] | 1572 | mt76_testmode_init_defaults(struct mt76_phy *phy) |
| 1573 | { |
| 1574 | struct mt76_testmode_data *td = &phy->test; |
| 1575 | + u8 addr[ETH_ALEN] = {phy->band_idx, 0x11, 0x22, 0xaa, 0xbb, 0xcc}; |
| 1576 | |
| 1577 | if (td->tx_mpdu_len > 0) |
| 1578 | return; |
developer | c2cfe0f | 2023-09-22 04:11:09 +0800 | [diff] [blame] | 1579 | @@ -319,11 +325,18 @@ mt76_testmode_init_defaults(struct mt76_phy *phy) |
developer | 1bc2ce2 | 2023-03-25 00:47:41 +0800 | [diff] [blame] | 1580 | td->tx_mpdu_len = 1024; |
| 1581 | td->tx_count = 1; |
| 1582 | td->tx_rate_mode = MT76_TM_TX_MODE_OFDM; |
| 1583 | + td->tx_rate_idx = 7; |
| 1584 | td->tx_rate_nss = 1; |
| 1585 | + /* 0xffff for OFDMA no puncture */ |
| 1586 | + td->tx_preamble_puncture = ~(td->tx_preamble_puncture & 0); |
| 1587 | + td->tx_ipg = 50; |
| 1588 | |
| 1589 | - memcpy(td->addr[0], phy->macaddr, ETH_ALEN); |
| 1590 | - memcpy(td->addr[1], phy->macaddr, ETH_ALEN); |
| 1591 | - memcpy(td->addr[2], phy->macaddr, ETH_ALEN); |
developer | c2cfe0f | 2023-09-22 04:11:09 +0800 | [diff] [blame] | 1592 | + /* rx stat user config */ |
| 1593 | + td->aid = 1; |
| 1594 | + |
developer | 1bc2ce2 | 2023-03-25 00:47:41 +0800 | [diff] [blame] | 1595 | + memcpy(td->addr[0], addr, ETH_ALEN); |
| 1596 | + memcpy(td->addr[1], addr, ETH_ALEN); |
| 1597 | + memcpy(td->addr[2], addr, ETH_ALEN); |
| 1598 | } |
| 1599 | |
| 1600 | static int |
developer | c2cfe0f | 2023-09-22 04:11:09 +0800 | [diff] [blame] | 1601 | @@ -353,7 +366,7 @@ __mt76_testmode_set_state(struct mt76_phy *phy, enum mt76_testmode_state state) |
developer | 1bc2ce2 | 2023-03-25 00:47:41 +0800 | [diff] [blame] | 1602 | if (state == MT76_TM_STATE_TX_FRAMES) |
| 1603 | mt76_testmode_tx_start(phy); |
| 1604 | else if (state == MT76_TM_STATE_RX_FRAMES) { |
| 1605 | - memset(&phy->test.rx_stats, 0, sizeof(phy->test.rx_stats)); |
| 1606 | + dev->test_ops->reset_rx_stats(phy); |
| 1607 | } |
| 1608 | |
| 1609 | phy->test.state = state; |
developer | c2cfe0f | 2023-09-22 04:11:09 +0800 | [diff] [blame] | 1610 | @@ -434,6 +447,9 @@ int mt76_testmode_cmd(struct ieee80211_hw *hw, struct ieee80211_vif *vif, |
| 1611 | |
| 1612 | mt76_testmode_init_defaults(phy); |
| 1613 | |
| 1614 | + if (tb[MT76_TM_ATTR_SKU_EN]) |
| 1615 | + td->sku_en = nla_get_u8(tb[MT76_TM_ATTR_SKU_EN]); |
| 1616 | + |
| 1617 | if (tb[MT76_TM_ATTR_TX_COUNT]) |
| 1618 | td->tx_count = nla_get_u32(tb[MT76_TM_ATTR_TX_COUNT]); |
| 1619 | |
| 1620 | @@ -454,7 +470,8 @@ int mt76_testmode_cmd(struct ieee80211_hw *hw, struct ieee80211_vif *vif, |
developer | 1bc2ce2 | 2023-03-25 00:47:41 +0800 | [diff] [blame] | 1621 | mt76_tm_get_u8(tb[MT76_TM_ATTR_TX_DUTY_CYCLE], |
| 1622 | &td->tx_duty_cycle, 0, 99) || |
| 1623 | mt76_tm_get_u8(tb[MT76_TM_ATTR_TX_POWER_CONTROL], |
| 1624 | - &td->tx_power_control, 0, 1)) |
| 1625 | + &td->tx_power_control, 0, 1) || |
| 1626 | + mt76_tm_get_u8(tb[MT76_TM_ATTR_AID], &td->aid, 0, 16)) |
| 1627 | goto out; |
| 1628 | |
| 1629 | if (tb[MT76_TM_ATTR_TX_LENGTH]) { |
developer | c2cfe0f | 2023-09-22 04:11:09 +0800 | [diff] [blame] | 1630 | @@ -494,7 +511,9 @@ int mt76_testmode_cmd(struct ieee80211_hw *hw, struct ieee80211_vif *vif, |
developer | 1bc2ce2 | 2023-03-25 00:47:41 +0800 | [diff] [blame] | 1631 | idx >= ARRAY_SIZE(td->tx_power)) |
| 1632 | goto out; |
| 1633 | |
| 1634 | - td->tx_power[idx++] = nla_get_u8(cur); |
| 1635 | + err = mt76_tm_get_u8(cur, &td->tx_power[idx++], 0, 63); |
| 1636 | + if (err) |
| 1637 | + return err; |
| 1638 | } |
| 1639 | } |
| 1640 | |
developer | c2cfe0f | 2023-09-22 04:11:09 +0800 | [diff] [blame] | 1641 | @@ -512,6 +531,22 @@ int mt76_testmode_cmd(struct ieee80211_hw *hw, struct ieee80211_vif *vif, |
developer | de9ecce | 2023-05-22 11:17:16 +0800 | [diff] [blame] | 1642 | } |
| 1643 | } |
| 1644 | |
| 1645 | + if (tb[MT76_TM_ATTR_CFG]) { |
| 1646 | + struct nlattr *cur; |
| 1647 | + int rem, idx = 0; |
| 1648 | + |
| 1649 | + nla_for_each_nested(cur, tb[MT76_TM_ATTR_CFG], rem) { |
| 1650 | + if (nla_len(cur) != 1 || idx >= 2) |
| 1651 | + goto out; |
| 1652 | + |
| 1653 | + if (idx == 0) |
| 1654 | + td->cfg.type = nla_get_u8(cur); |
| 1655 | + else |
| 1656 | + td->cfg.enable = nla_get_u8(cur); |
| 1657 | + idx++; |
| 1658 | + } |
| 1659 | + } |
| 1660 | + |
| 1661 | if (dev->test_ops->set_params) { |
| 1662 | err = dev->test_ops->set_params(phy, tb, state); |
| 1663 | if (err) |
developer | c2cfe0f | 2023-09-22 04:11:09 +0800 | [diff] [blame] | 1664 | @@ -561,6 +596,9 @@ mt76_testmode_dump_stats(struct mt76_phy *phy, struct sk_buff *msg) |
developer | 1bc2ce2 | 2023-03-25 00:47:41 +0800 | [diff] [blame] | 1665 | nla_put_u64_64bit(msg, MT76_TM_STATS_ATTR_RX_PACKETS, rx_packets, |
| 1666 | MT76_TM_STATS_ATTR_PAD) || |
| 1667 | nla_put_u64_64bit(msg, MT76_TM_STATS_ATTR_RX_FCS_ERROR, rx_fcs_error, |
| 1668 | + MT76_TM_STATS_ATTR_PAD) || |
| 1669 | + nla_put_u64_64bit(msg, MT76_TM_STATS_ATTR_RX_LEN_MISMATCH, |
| 1670 | + td->rx_stats.len_mismatch, |
| 1671 | MT76_TM_STATS_ATTR_PAD)) |
| 1672 | return -EMSGSIZE; |
| 1673 | |
developer | c2cfe0f | 2023-09-22 04:11:09 +0800 | [diff] [blame] | 1674 | @@ -625,6 +663,8 @@ int mt76_testmode_dump(struct ieee80211_hw *hw, struct sk_buff *msg, |
developer | 1bc2ce2 | 2023-03-25 00:47:41 +0800 | [diff] [blame] | 1675 | nla_put_u8(msg, MT76_TM_ATTR_TX_RATE_SGI, td->tx_rate_sgi) || |
| 1676 | nla_put_u8(msg, MT76_TM_ATTR_TX_RATE_LDPC, td->tx_rate_ldpc) || |
| 1677 | nla_put_u8(msg, MT76_TM_ATTR_TX_RATE_STBC, td->tx_rate_stbc) || |
developer | c2cfe0f | 2023-09-22 04:11:09 +0800 | [diff] [blame] | 1678 | + nla_put_u8(msg, MT76_TM_ATTR_SKU_EN, td->sku_en) || |
developer | 1bc2ce2 | 2023-03-25 00:47:41 +0800 | [diff] [blame] | 1679 | + nla_put_u8(msg, MT76_TM_ATTR_AID, td->aid) || |
| 1680 | (mt76_testmode_param_present(td, MT76_TM_ATTR_TX_LTF) && |
| 1681 | nla_put_u8(msg, MT76_TM_ATTR_TX_LTF, td->tx_ltf)) || |
| 1682 | (mt76_testmode_param_present(td, MT76_TM_ATTR_TX_ANTENNA) && |
| 1683 | diff --git a/testmode.h b/testmode.h |
developer | c2cfe0f | 2023-09-22 04:11:09 +0800 | [diff] [blame] | 1684 | index a40cd74b4..141bb8625 100644 |
developer | 1bc2ce2 | 2023-03-25 00:47:41 +0800 | [diff] [blame] | 1685 | --- a/testmode.h |
| 1686 | +++ b/testmode.h |
developer | c2cfe0f | 2023-09-22 04:11:09 +0800 | [diff] [blame] | 1687 | @@ -19,6 +19,7 @@ |
| 1688 | * @MT76_TM_ATTR_MTD_OFFSET: offset of eeprom data within the partition (u32) |
| 1689 | * @MT76_TM_ATTR_BAND_IDX: band idx of the chip (u8) |
| 1690 | * |
| 1691 | + * @MT76_TM_ATTR_SKU_EN: config txpower sku is enabled or disabled in testmode (u8) |
| 1692 | * @MT76_TM_ATTR_TX_COUNT: configured number of frames to send when setting |
| 1693 | * state to MT76_TM_STATE_TX_FRAMES (u32) |
| 1694 | * @MT76_TM_ATTR_TX_PENDING: pending frames during MT76_TM_STATE_TX_FRAMES (u32) |
| 1695 | @@ -39,6 +40,11 @@ |
developer | 1bc2ce2 | 2023-03-25 00:47:41 +0800 | [diff] [blame] | 1696 | * |
| 1697 | * @MT76_TM_ATTR_STATS: statistics (nested, see &enum mt76_testmode_stats_attr) |
| 1698 | * |
| 1699 | + * @MT76_TM_ATTR_PRECAL: Pre-cal data (u8) |
| 1700 | + * @MT76_TM_ATTR_PRECAL_INFO: group size, dpd size, dpd_info, transmit size, |
| 1701 | + * eeprom cal indicator (u32), |
| 1702 | + * dpd_info = [dpd_per_chan_size, chan_num_2g, |
| 1703 | + * chan_num_5g, chan_num_6g] |
| 1704 | * @MT76_TM_ATTR_TX_SPE_IDX: tx spatial extension index (u8) |
| 1705 | * |
| 1706 | * @MT76_TM_ATTR_TX_DUTY_CYCLE: packet tx duty cycle (u8) |
developer | c2cfe0f | 2023-09-22 04:11:09 +0800 | [diff] [blame] | 1707 | @@ -48,6 +54,29 @@ |
developer | 1bc2ce2 | 2023-03-25 00:47:41 +0800 | [diff] [blame] | 1708 | * @MT76_TM_ATTR_DRV_DATA: driver specific netlink attrs (nested) |
| 1709 | * |
| 1710 | * @MT76_TM_ATTR_MAC_ADDRS: array of nested MAC addresses (nested) |
| 1711 | + * |
| 1712 | + * @MT76_TM_ATTR_EEPROM_ACTION: eeprom setting actions |
| 1713 | + * (u8, see &enum mt76_testmode_eeprom_action) |
| 1714 | + * @MT76_TM_ATTR_EEPROM_OFFSET: offset of eeprom data block for writing (u32) |
| 1715 | + * @MT76_TM_ATTR_EEPROM_VAL: values for writing into a 16-byte data block |
| 1716 | + * (nested, u8 attrs) |
| 1717 | + * |
| 1718 | + * @MT76_TM_ATTR_CFG: config testmode rf feature (nested, see &mt76_testmode_cfg) |
| 1719 | + * @MT76_TM_ATTR_TXBF_ACT: txbf setting actions (u8) |
| 1720 | + * @MT76_TM_ATTR_TXBF_PARAM: txbf parameters (nested) |
| 1721 | + * |
| 1722 | + * @MT76_TM_ATTR_OFF_CH_SCAN_CH: config the channel of background chain (ZWDFS) (u8) |
| 1723 | + * @MT76_TM_ATTR_OFF_CH_SCAN_CENTER_CH: config the center channel of background chain (ZWDFS) (u8) |
| 1724 | + * @MT76_TM_ATTR_OFF_CH_SCAN_BW: config the bandwidth of background chain (ZWDFS) (u8) |
| 1725 | + * @MT76_TM_ATTR_OFF_CH_SCAN_PATH: config the tx path of background chain (ZWDFS) (u8) |
| 1726 | + * |
| 1727 | + * @MT76_TM_ATTR_IPI_THRESHOLD: config the IPI index you want to read (u8) |
| 1728 | + * @MT76_TM_ATTR_IPI_PERIOD: config the time period for reading |
| 1729 | + * the histogram of specific IPI index (u8) |
| 1730 | + * @MT76_TM_ATTR_IPI_ANTENNA_INDEX: config the antenna index for reading |
| 1731 | + * the histogram of specific IPI index (u8) |
| 1732 | + * @MT76_TM_ATTR_IPI_RESET: Reset the IPI counter |
| 1733 | + * |
| 1734 | */ |
| 1735 | enum mt76_testmode_attr { |
| 1736 | MT76_TM_ATTR_UNSPEC, |
developer | c2cfe0f | 2023-09-22 04:11:09 +0800 | [diff] [blame] | 1737 | @@ -59,6 +88,7 @@ enum mt76_testmode_attr { |
| 1738 | MT76_TM_ATTR_MTD_OFFSET, |
| 1739 | MT76_TM_ATTR_BAND_IDX, |
| 1740 | |
| 1741 | + MT76_TM_ATTR_SKU_EN, |
| 1742 | MT76_TM_ATTR_TX_COUNT, |
| 1743 | MT76_TM_ATTR_TX_LENGTH, |
| 1744 | MT76_TM_ATTR_TX_RATE_MODE, |
| 1745 | @@ -76,6 +106,8 @@ enum mt76_testmode_attr { |
developer | 1bc2ce2 | 2023-03-25 00:47:41 +0800 | [diff] [blame] | 1746 | MT76_TM_ATTR_FREQ_OFFSET, |
| 1747 | |
| 1748 | MT76_TM_ATTR_STATS, |
| 1749 | + MT76_TM_ATTR_PRECAL, |
| 1750 | + MT76_TM_ATTR_PRECAL_INFO, |
| 1751 | |
| 1752 | MT76_TM_ATTR_TX_SPE_IDX, |
| 1753 | |
developer | c2cfe0f | 2023-09-22 04:11:09 +0800 | [diff] [blame] | 1754 | @@ -86,6 +118,27 @@ enum mt76_testmode_attr { |
developer | 1bc2ce2 | 2023-03-25 00:47:41 +0800 | [diff] [blame] | 1755 | MT76_TM_ATTR_DRV_DATA, |
| 1756 | |
| 1757 | MT76_TM_ATTR_MAC_ADDRS, |
| 1758 | + MT76_TM_ATTR_AID, |
| 1759 | + MT76_TM_ATTR_RU_ALLOC, |
| 1760 | + MT76_TM_ATTR_RU_IDX, |
| 1761 | + |
| 1762 | + MT76_TM_ATTR_EEPROM_ACTION, |
| 1763 | + MT76_TM_ATTR_EEPROM_OFFSET, |
| 1764 | + MT76_TM_ATTR_EEPROM_VAL, |
| 1765 | + |
| 1766 | + MT76_TM_ATTR_CFG, |
| 1767 | + MT76_TM_ATTR_TXBF_ACT, |
| 1768 | + MT76_TM_ATTR_TXBF_PARAM, |
| 1769 | + |
| 1770 | + MT76_TM_ATTR_OFF_CH_SCAN_CH, |
| 1771 | + MT76_TM_ATTR_OFF_CH_SCAN_CENTER_CH, |
| 1772 | + MT76_TM_ATTR_OFF_CH_SCAN_BW, |
| 1773 | + MT76_TM_ATTR_OFF_CH_SCAN_PATH, |
| 1774 | + |
| 1775 | + MT76_TM_ATTR_IPI_THRESHOLD, |
| 1776 | + MT76_TM_ATTR_IPI_PERIOD, |
| 1777 | + MT76_TM_ATTR_IPI_ANTENNA_INDEX, |
| 1778 | + MT76_TM_ATTR_IPI_RESET, |
| 1779 | |
| 1780 | /* keep last */ |
| 1781 | NUM_MT76_TM_ATTRS, |
developer | c2cfe0f | 2023-09-22 04:11:09 +0800 | [diff] [blame] | 1782 | @@ -103,6 +156,8 @@ enum mt76_testmode_attr { |
developer | 1bc2ce2 | 2023-03-25 00:47:41 +0800 | [diff] [blame] | 1783 | * @MT76_TM_STATS_ATTR_RX_FCS_ERROR: number of rx packets with FCS error (u64) |
| 1784 | * @MT76_TM_STATS_ATTR_LAST_RX: information about the last received packet |
| 1785 | * see &enum mt76_testmode_rx_attr |
| 1786 | + * @MT76_TM_STATS_ATTR_RX_LEN_MISMATCH: number of rx packets with length |
| 1787 | + * mismatch error (u64) |
| 1788 | */ |
| 1789 | enum mt76_testmode_stats_attr { |
| 1790 | MT76_TM_STATS_ATTR_UNSPEC, |
developer | c2cfe0f | 2023-09-22 04:11:09 +0800 | [diff] [blame] | 1791 | @@ -115,6 +170,7 @@ enum mt76_testmode_stats_attr { |
developer | 1bc2ce2 | 2023-03-25 00:47:41 +0800 | [diff] [blame] | 1792 | MT76_TM_STATS_ATTR_RX_PACKETS, |
| 1793 | MT76_TM_STATS_ATTR_RX_FCS_ERROR, |
| 1794 | MT76_TM_STATS_ATTR_LAST_RX, |
| 1795 | + MT76_TM_STATS_ATTR_RX_LEN_MISMATCH, |
| 1796 | |
| 1797 | /* keep last */ |
| 1798 | NUM_MT76_TM_STATS_ATTRS, |
developer | c2cfe0f | 2023-09-22 04:11:09 +0800 | [diff] [blame] | 1799 | @@ -127,6 +183,7 @@ enum mt76_testmode_stats_attr { |
| 1800 | * |
| 1801 | * @MT76_TM_RX_ATTR_FREQ_OFFSET: frequency offset (s32) |
| 1802 | * @MT76_TM_RX_ATTR_RCPI: received channel power indicator (array, u8) |
| 1803 | + * @MT76_TM_RX_ATTR_RSSI: received signal strength indicator (array, s8) |
| 1804 | * @MT76_TM_RX_ATTR_IB_RSSI: internal inband RSSI (array, s8) |
| 1805 | * @MT76_TM_RX_ATTR_WB_RSSI: internal wideband RSSI (array, s8) |
| 1806 | * @MT76_TM_RX_ATTR_SNR: signal-to-noise ratio (u8) |
| 1807 | @@ -136,6 +193,7 @@ enum mt76_testmode_rx_attr { |
| 1808 | |
| 1809 | MT76_TM_RX_ATTR_FREQ_OFFSET, |
| 1810 | MT76_TM_RX_ATTR_RCPI, |
| 1811 | + MT76_TM_RX_ATTR_RSSI, |
| 1812 | MT76_TM_RX_ATTR_IB_RSSI, |
| 1813 | MT76_TM_RX_ATTR_WB_RSSI, |
| 1814 | MT76_TM_RX_ATTR_SNR, |
| 1815 | @@ -179,6 +237,9 @@ enum mt76_testmode_state { |
developer | 1bc2ce2 | 2023-03-25 00:47:41 +0800 | [diff] [blame] | 1816 | * @MT76_TM_TX_MODE_HE_EXT_SU: 802.11ax extended-range SU |
| 1817 | * @MT76_TM_TX_MODE_HE_TB: 802.11ax trigger-based |
| 1818 | * @MT76_TM_TX_MODE_HE_MU: 802.11ax multi-user MIMO |
| 1819 | + * @MT76_TM_TX_MODE_EHT_SU: 802.11be single-user MIMO |
| 1820 | + * @MT76_TM_TX_MODE_EHT_TRIG: 802.11be trigger-based |
| 1821 | + * @MT76_TM_TX_MODE_EHT_MU: 802.11be multi-user MIMO |
| 1822 | */ |
| 1823 | enum mt76_testmode_tx_mode { |
| 1824 | MT76_TM_TX_MODE_CCK, |
developer | c2cfe0f | 2023-09-22 04:11:09 +0800 | [diff] [blame] | 1825 | @@ -189,6 +250,9 @@ enum mt76_testmode_tx_mode { |
developer | 1bc2ce2 | 2023-03-25 00:47:41 +0800 | [diff] [blame] | 1826 | MT76_TM_TX_MODE_HE_EXT_SU, |
| 1827 | MT76_TM_TX_MODE_HE_TB, |
| 1828 | MT76_TM_TX_MODE_HE_MU, |
| 1829 | + MT76_TM_TX_MODE_EHT_SU, |
| 1830 | + MT76_TM_TX_MODE_EHT_TRIG, |
| 1831 | + MT76_TM_TX_MODE_EHT_MU, |
| 1832 | |
| 1833 | /* keep last */ |
| 1834 | NUM_MT76_TM_TX_MODES, |
| 1835 | diff --git a/tools/fields.c b/tools/fields.c |
developer | c2cfe0f | 2023-09-22 04:11:09 +0800 | [diff] [blame] | 1836 | index e3f690896..055f90f3c 100644 |
developer | 1bc2ce2 | 2023-03-25 00:47:41 +0800 | [diff] [blame] | 1837 | --- a/tools/fields.c |
| 1838 | +++ b/tools/fields.c |
| 1839 | @@ -10,6 +10,7 @@ static const char * const testmode_state[] = { |
| 1840 | [MT76_TM_STATE_IDLE] = "idle", |
| 1841 | [MT76_TM_STATE_TX_FRAMES] = "tx_frames", |
| 1842 | [MT76_TM_STATE_RX_FRAMES] = "rx_frames", |
| 1843 | + [MT76_TM_STATE_TX_CONT] = "tx_cont", |
| 1844 | }; |
| 1845 | |
| 1846 | static const char * const testmode_tx_mode[] = { |
| 1847 | @@ -21,6 +22,9 @@ static const char * const testmode_tx_mode[] = { |
| 1848 | [MT76_TM_TX_MODE_HE_EXT_SU] = "he_ext_su", |
| 1849 | [MT76_TM_TX_MODE_HE_TB] = "he_tb", |
| 1850 | [MT76_TM_TX_MODE_HE_MU] = "he_mu", |
| 1851 | + [MT76_TM_TX_MODE_EHT_SU] = "eht_su", |
| 1852 | + [MT76_TM_TX_MODE_EHT_TRIG] = "eht_tb", |
| 1853 | + [MT76_TM_TX_MODE_EHT_MU] = "eht_mu", |
| 1854 | }; |
| 1855 | |
| 1856 | static void print_enum(const struct tm_field *field, struct nlattr *attr) |
developer | c2cfe0f | 2023-09-22 04:11:09 +0800 | [diff] [blame] | 1857 | @@ -65,7 +69,7 @@ static bool parse_u8(const struct tm_field *field, int idx, |
| 1858 | |
| 1859 | static void print_u8(const struct tm_field *field, struct nlattr *attr) |
| 1860 | { |
| 1861 | - printf("%d", nla_get_u8(attr)); |
| 1862 | + printf("%u", nla_get_u8(attr)); |
| 1863 | } |
| 1864 | |
| 1865 | static void print_s8(const struct tm_field *field, struct nlattr *attr) |
| 1866 | @@ -86,12 +90,12 @@ static void print_s32(const struct tm_field *field, struct nlattr *attr) |
| 1867 | |
| 1868 | static void print_u32(const struct tm_field *field, struct nlattr *attr) |
| 1869 | { |
| 1870 | - printf("%d", nla_get_u32(attr)); |
| 1871 | + printf("%u", nla_get_u32(attr)); |
| 1872 | } |
| 1873 | |
| 1874 | static void print_u64(const struct tm_field *field, struct nlattr *attr) |
| 1875 | { |
| 1876 | - printf("%lld", (unsigned long long)nla_get_u64(attr)); |
| 1877 | + printf("%llu", (unsigned long long)nla_get_u64(attr)); |
| 1878 | } |
| 1879 | |
| 1880 | static bool parse_flag(const struct tm_field *field, int idx, |
developer | 1bc2ce2 | 2023-03-25 00:47:41 +0800 | [diff] [blame] | 1881 | @@ -201,6 +205,62 @@ static void print_extra_stats(const struct tm_field *field, struct nlattr **tb) |
| 1882 | printf("%srx_per=%.02f%%\n", prefix, 100 * failed / total); |
| 1883 | } |
| 1884 | |
| 1885 | +static bool parse_mac(const struct tm_field *field, int idx, |
| 1886 | + struct nl_msg *msg, const char *val) |
| 1887 | +{ |
| 1888 | +#define ETH_ALEN 6 |
| 1889 | + bool ret = true; |
| 1890 | + char *str, *cur, *ap; |
| 1891 | + void *a; |
| 1892 | + |
| 1893 | + str = strdup(val); |
| 1894 | + ap = str; |
| 1895 | + |
| 1896 | + a = nla_nest_start(msg, idx); |
| 1897 | + |
| 1898 | + idx = 0; |
| 1899 | + while ((cur = strsep(&ap, ",")) != NULL) { |
| 1900 | + unsigned char addr[ETH_ALEN]; |
| 1901 | + char *val, *tmp = cur; |
| 1902 | + int i = 0; |
| 1903 | + |
| 1904 | + while ((val = strsep(&tmp, ":")) != NULL) { |
| 1905 | + if (i >= ETH_ALEN) |
| 1906 | + break; |
| 1907 | + |
| 1908 | + addr[i++] = strtoul(val, NULL, 16); |
| 1909 | + } |
| 1910 | + |
| 1911 | + nla_put(msg, idx, ETH_ALEN, addr); |
| 1912 | + |
| 1913 | + idx++; |
| 1914 | + } |
| 1915 | + |
| 1916 | + nla_nest_end(msg, a); |
| 1917 | + |
| 1918 | + free(str); |
| 1919 | + |
| 1920 | + return ret; |
| 1921 | +} |
| 1922 | + |
| 1923 | +static void print_mac(const struct tm_field *field, struct nlattr *attr) |
| 1924 | +{ |
| 1925 | +#define MAC2STR(a) (a)[0], (a)[1], (a)[2], (a)[3], (a)[4], (a)[5] |
| 1926 | +#define MACSTR "%02x:%02x:%02x:%02x:%02x:%02x" |
| 1927 | + unsigned char addr[3][6]; |
| 1928 | + struct nlattr *cur; |
| 1929 | + int idx = 0; |
| 1930 | + int rem; |
| 1931 | + |
| 1932 | + nla_for_each_nested(cur, attr, rem) { |
| 1933 | + if (nla_len(cur) != 6) |
| 1934 | + continue; |
| 1935 | + memcpy(addr[idx++], nla_data(cur), 6); |
| 1936 | + } |
| 1937 | + |
| 1938 | + printf("" MACSTR "," MACSTR "," MACSTR "", |
| 1939 | + MAC2STR(addr[0]), MAC2STR(addr[1]), MAC2STR(addr[2])); |
| 1940 | +} |
| 1941 | |
| 1942 | #define FIELD_GENERIC(_field, _name, ...) \ |
| 1943 | [FIELD_NAME(_field)] = { \ |
developer | c2cfe0f | 2023-09-22 04:11:09 +0800 | [diff] [blame] | 1944 | @@ -250,10 +310,18 @@ static void print_extra_stats(const struct tm_field *field, struct nlattr **tb) |
developer | 1bc2ce2 | 2023-03-25 00:47:41 +0800 | [diff] [blame] | 1945 | ##__VA_ARGS__ \ |
| 1946 | ) |
| 1947 | |
| 1948 | +#define FIELD_MAC(_field, _name) \ |
| 1949 | + [FIELD_NAME(_field)] = { \ |
| 1950 | + .name = _name, \ |
| 1951 | + .parse = parse_mac, \ |
| 1952 | + .print = print_mac \ |
| 1953 | + } |
| 1954 | + |
| 1955 | #define FIELD_NAME(_field) MT76_TM_RX_ATTR_##_field |
| 1956 | static const struct tm_field rx_fields[NUM_MT76_TM_RX_ATTRS] = { |
| 1957 | FIELD_RO(s32, FREQ_OFFSET, "freq_offset"), |
developer | c2cfe0f | 2023-09-22 04:11:09 +0800 | [diff] [blame] | 1958 | FIELD_ARRAY_RO(u8, RCPI, "rcpi"), |
| 1959 | + FIELD_ARRAY_RO(s8, RSSI, "rssi"), |
| 1960 | FIELD_ARRAY_RO(s8, IB_RSSI, "ib_rssi"), |
| 1961 | FIELD_ARRAY_RO(s8, WB_RSSI, "wb_rssi"), |
| 1962 | FIELD_RO(s8, SNR, "snr"), |
| 1963 | @@ -261,6 +329,7 @@ static const struct tm_field rx_fields[NUM_MT76_TM_RX_ATTRS] = { |
| 1964 | static struct nla_policy rx_policy[NUM_MT76_TM_RX_ATTRS] = { |
| 1965 | [MT76_TM_RX_ATTR_FREQ_OFFSET] = { .type = NLA_U32 }, |
| 1966 | [MT76_TM_RX_ATTR_RCPI] = { .type = NLA_NESTED }, |
| 1967 | + [MT76_TM_RX_ATTR_RSSI] = { .type = NLA_NESTED }, |
| 1968 | [MT76_TM_RX_ATTR_IB_RSSI] = { .type = NLA_NESTED }, |
| 1969 | [MT76_TM_RX_ATTR_WB_RSSI] = { .type = NLA_NESTED }, |
| 1970 | [MT76_TM_RX_ATTR_SNR] = { .type = NLA_U8 }, |
| 1971 | @@ -274,6 +343,7 @@ static const struct tm_field stats_fields[NUM_MT76_TM_STATS_ATTRS] = { |
developer | 1bc2ce2 | 2023-03-25 00:47:41 +0800 | [diff] [blame] | 1972 | FIELD_RO(u32, TX_DONE, "tx_done"), |
| 1973 | FIELD_RO(u64, RX_PACKETS, "rx_packets"), |
| 1974 | FIELD_RO(u64, RX_FCS_ERROR, "rx_fcs_error"), |
| 1975 | + FIELD_RO(u64, RX_LEN_MISMATCH, "rx_len_mismatch"), |
| 1976 | FIELD_NESTED_RO(LAST_RX, rx, "last_"), |
| 1977 | }; |
| 1978 | static struct nla_policy stats_policy[NUM_MT76_TM_STATS_ATTRS] = { |
developer | c2cfe0f | 2023-09-22 04:11:09 +0800 | [diff] [blame] | 1979 | @@ -282,6 +352,7 @@ static struct nla_policy stats_policy[NUM_MT76_TM_STATS_ATTRS] = { |
developer | 1bc2ce2 | 2023-03-25 00:47:41 +0800 | [diff] [blame] | 1980 | [MT76_TM_STATS_ATTR_TX_DONE] = { .type = NLA_U32 }, |
| 1981 | [MT76_TM_STATS_ATTR_RX_PACKETS] = { .type = NLA_U64 }, |
| 1982 | [MT76_TM_STATS_ATTR_RX_FCS_ERROR] = { .type = NLA_U64 }, |
| 1983 | + [MT76_TM_STATS_ATTR_RX_LEN_MISMATCH] = { .type = NLA_U64 }, |
| 1984 | }; |
| 1985 | #undef FIELD_NAME |
| 1986 | |
developer | c2cfe0f | 2023-09-22 04:11:09 +0800 | [diff] [blame] | 1987 | @@ -291,6 +362,7 @@ static const struct tm_field testdata_fields[NUM_MT76_TM_ATTRS] = { |
| 1988 | FIELD_ENUM(STATE, "state", testmode_state), |
| 1989 | FIELD_RO(string, MTD_PART, "mtd_part"), |
| 1990 | FIELD_RO(u32, MTD_OFFSET, "mtd_offset"), |
| 1991 | + FIELD(u8, SKU_EN, "sku_en"), |
| 1992 | FIELD(u32, TX_COUNT, "tx_count"), |
| 1993 | FIELD(u32, TX_LENGTH, "tx_length"), |
| 1994 | FIELD_ENUM(TX_RATE_MODE, "tx_rate_mode", testmode_tx_mode), |
| 1995 | @@ -300,12 +372,20 @@ static const struct tm_field testdata_fields[NUM_MT76_TM_ATTRS] = { |
developer | 1bc2ce2 | 2023-03-25 00:47:41 +0800 | [diff] [blame] | 1996 | FIELD(u8, TX_RATE_LDPC, "tx_rate_ldpc"), |
| 1997 | FIELD(u8, TX_RATE_STBC, "tx_rate_stbc"), |
| 1998 | FIELD(u8, TX_LTF, "tx_ltf"), |
| 1999 | + FIELD(u8, TX_DUTY_CYCLE, "tx_duty_cycle"), |
| 2000 | + FIELD(u32, TX_IPG, "tx_ipg"), |
| 2001 | + FIELD(u32, TX_TIME, "tx_time"), |
| 2002 | FIELD(u8, TX_POWER_CONTROL, "tx_power_control"), |
| 2003 | FIELD_ARRAY(u8, TX_POWER, "tx_power"), |
| 2004 | FIELD(u8, TX_ANTENNA, "tx_antenna"), |
| 2005 | FIELD(u32, FREQ_OFFSET, "freq_offset"), |
| 2006 | + FIELD(u8, AID, "aid"), |
| 2007 | + FIELD(u8, RU_ALLOC, "ru_alloc"), |
| 2008 | + FIELD(u8, RU_IDX, "ru_idx"), |
| 2009 | + FIELD_MAC(MAC_ADDRS, "mac_addrs"), |
| 2010 | FIELD_NESTED_RO(STATS, stats, "", |
| 2011 | .print_extra = print_extra_stats), |
| 2012 | + |
| 2013 | }; |
| 2014 | #undef FIELD_NAME |
| 2015 | |
developer | c2cfe0f | 2023-09-22 04:11:09 +0800 | [diff] [blame] | 2016 | @@ -313,6 +393,7 @@ static struct nla_policy testdata_policy[NUM_MT76_TM_ATTRS] = { |
| 2017 | [MT76_TM_ATTR_STATE] = { .type = NLA_U8 }, |
| 2018 | [MT76_TM_ATTR_MTD_PART] = { .type = NLA_STRING }, |
| 2019 | [MT76_TM_ATTR_MTD_OFFSET] = { .type = NLA_U32 }, |
| 2020 | + [MT76_TM_ATTR_SKU_EN] = { .type = NLA_U8 }, |
| 2021 | [MT76_TM_ATTR_TX_COUNT] = { .type = NLA_U32 }, |
| 2022 | [MT76_TM_ATTR_TX_LENGTH] = { .type = NLA_U32 }, |
| 2023 | [MT76_TM_ATTR_TX_RATE_MODE] = { .type = NLA_U8 }, |
| 2024 | @@ -322,10 +403,25 @@ static struct nla_policy testdata_policy[NUM_MT76_TM_ATTRS] = { |
developer | 1bc2ce2 | 2023-03-25 00:47:41 +0800 | [diff] [blame] | 2025 | [MT76_TM_ATTR_TX_RATE_LDPC] = { .type = NLA_U8 }, |
| 2026 | [MT76_TM_ATTR_TX_RATE_STBC] = { .type = NLA_U8 }, |
| 2027 | [MT76_TM_ATTR_TX_LTF] = { .type = NLA_U8 }, |
| 2028 | + [MT76_TM_ATTR_TX_DUTY_CYCLE] = { .type = NLA_U8 }, |
| 2029 | + [MT76_TM_ATTR_TX_IPG] = { .type = NLA_U32 }, |
| 2030 | + [MT76_TM_ATTR_TX_TIME] = { .type = NLA_U32 }, |
| 2031 | [MT76_TM_ATTR_TX_POWER_CONTROL] = { .type = NLA_U8 }, |
| 2032 | [MT76_TM_ATTR_TX_ANTENNA] = { .type = NLA_U8 }, |
| 2033 | + [MT76_TM_ATTR_TX_SPE_IDX] = { .type = NLA_U8 }, |
| 2034 | [MT76_TM_ATTR_FREQ_OFFSET] = { .type = NLA_U32 }, |
| 2035 | + [MT76_TM_ATTR_AID] = { .type = NLA_U8 }, |
| 2036 | + [MT76_TM_ATTR_RU_ALLOC] = { .type = NLA_U8 }, |
| 2037 | + [MT76_TM_ATTR_RU_IDX] = { .type = NLA_U8 }, |
| 2038 | [MT76_TM_ATTR_STATS] = { .type = NLA_NESTED }, |
| 2039 | + [MT76_TM_ATTR_TXBF_ACT] = { .type = NLA_U8 }, |
| 2040 | + [MT76_TM_ATTR_OFF_CH_SCAN_CH] = { .type = NLA_U8 }, |
| 2041 | + [MT76_TM_ATTR_OFF_CH_SCAN_CENTER_CH] = { .type = NLA_U8 }, |
| 2042 | + [MT76_TM_ATTR_OFF_CH_SCAN_BW] = { .type = NLA_U8 }, |
| 2043 | + [MT76_TM_ATTR_IPI_THRESHOLD] = { .type = NLA_U8 }, |
| 2044 | + [MT76_TM_ATTR_IPI_PERIOD] = { .type = NLA_U32 }, |
| 2045 | + [MT76_TM_ATTR_IPI_ANTENNA_INDEX] = { .type = NLA_U8 }, |
| 2046 | + [MT76_TM_ATTR_IPI_RESET] = { .type = NLA_U8 }, |
| 2047 | }; |
| 2048 | |
| 2049 | const struct tm_field msg_field = { |
| 2050 | -- |
developer | c2cfe0f | 2023-09-22 04:11:09 +0800 | [diff] [blame] | 2051 | 2.39.2 |
developer | 1bc2ce2 | 2023-03-25 00:47:41 +0800 | [diff] [blame] | 2052 | |