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git01.mediatek.com / openwrt / feeds / mtk-openwrt-feeds / 02fd57b6733a970e06d2d5787d26f3cbfaa5a80a / . / autobuild_mac80211_release / mt7988_mt7996_mac80211 / package / kernel / mt76 / patches / 1000-wifi-mt76-mt7996-add-debug-tool.patch
blob: 11599c0e8adcb7b4bfbd1cab38951ee48e5adf19 [file] [log] [blame]
developerc2cfe0f2023-09-22 04:11:09 +0800[diff] [blame]1From 36a71ed07925573d2eff73f7be91c86763151470 Mon Sep 17 00:00:00 2001
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]2From: Shayne Chen <shayne.chen@mediatek.com>
3Date: Fri, 24 Mar 2023 14:02:32 +0800
developerc2cfe0f2023-09-22 04:11:09 +0800[diff] [blame]4Subject: [PATCH 1000/1024] wifi: mt76: mt7996: add debug tool
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]5
6Change-Id: Ie10390b01f17db893dbfbf3221bf63a4bd1fe38f
developerc2cfe0f2023-09-22 04:11:09 +0800[diff] [blame]7Signed-off-by: StanleyYP Wang <StanleyYP.Wang@mediatek.com>
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]8---
developerc2cfe0f2023-09-22 04:11:09 +0800[diff] [blame]9 mt7996/Makefile | 4 +
developer064da3c2023-06-13 15:57:26 +0800[diff] [blame]10 mt7996/coredump.c | 10 +-
11 mt7996/coredump.h | 7 +
developerc2cfe0f2023-09-22 04:11:09 +0800[diff] [blame]12 mt7996/debugfs.c | 34 +-
developer064da3c2023-06-13 15:57:26 +0800[diff] [blame]13 mt7996/mt7996.h | 14 +
developerc2cfe0f2023-09-22 04:11:09 +0800[diff] [blame]14 mt7996/mtk_debug.h | 2147 ++++++++++++++++++++++++++++++++++++++
15 mt7996/mtk_debugfs.c | 2379 ++++++++++++++++++++++++++++++++++++++++++
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]16 mt7996/mtk_mcu.c | 18 +
17 mt7996/mtk_mcu.h | 16 +
18 tools/fwlog.c | 25 +-
developerc2cfe0f2023-09-22 04:11:09 +0800[diff] [blame]19 10 files changed, 4634 insertions(+), 20 deletions(-)
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]20 create mode 100644 mt7996/mtk_debug.h
21 create mode 100644 mt7996/mtk_debugfs.c
22 create mode 100644 mt7996/mtk_mcu.c
23 create mode 100644 mt7996/mtk_mcu.h
24
25diff --git a/mt7996/Makefile b/mt7996/Makefile
developerc2cfe0f2023-09-22 04:11:09 +0800[diff] [blame]26index 07c8b555c..a056b40e0 100644
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]27--- a/mt7996/Makefile
28+++ b/mt7996/Makefile
developerc2cfe0f2023-09-22 04:11:09 +0800[diff] [blame]29@@ -1,4 +1,6 @@
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]30 # SPDX-License-Identifier: ISC
developerc2cfe0f2023-09-22 04:11:09 +0800[diff] [blame]31+EXTRA_CFLAGS += -DCONFIG_MT76_LEDS
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]32+EXTRA_CFLAGS += -DCONFIG_MTK_DEBUG
33
34 obj-$(CONFIG_MT7996E) += mt7996e.o
35
developerc2cfe0f2023-09-22 04:11:09 +0800[diff] [blame]36@@ -6,3 +8,5 @@ mt7996e-y := pci.o init.o dma.o eeprom.o main.o mcu.o mac.o \
37 debugfs.o mmio.o
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]38
developerc2cfe0f2023-09-22 04:11:09 +0800[diff] [blame]39 mt7996e-$(CONFIG_DEV_COREDUMP) += coredump.o
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]40+
41+mt7996e-y += mtk_debugfs.o mtk_mcu.o
developer064da3c2023-06-13 15:57:26 +0800[diff] [blame]42diff --git a/mt7996/coredump.c b/mt7996/coredump.c
developerc2cfe0f2023-09-22 04:11:09 +0800[diff] [blame]43index 60b88085c..a7f91b56d 100644
developer064da3c2023-06-13 15:57:26 +0800[diff] [blame]44--- a/mt7996/coredump.c
45+++ b/mt7996/coredump.c
46@@ -195,7 +195,7 @@ mt7996_coredump_fw_stack(struct mt7996_dev *dev, u8 type, struct mt7996_coredump
47 }
48 }
49
50-static struct mt7996_coredump *mt7996_coredump_build(struct mt7996_dev *dev, u8 type)
51+struct mt7996_coredump *mt7996_coredump_build(struct mt7996_dev *dev, u8 type, bool full_dump)
52 {
53 struct mt7996_crash_data *crash_data = dev->coredump.crash_data[type];
54 struct mt7996_coredump *dump;
55@@ -206,7 +206,7 @@ static struct mt7996_coredump *mt7996_coredump_build(struct mt7996_dev *dev, u8
56
57 len = hdr_len;
58
59- if (coredump_memdump && crash_data->memdump_buf_len)
60+ if (full_dump && coredump_memdump && crash_data->memdump_buf_len)
61 len += sizeof(*dump_mem) + crash_data->memdump_buf_len;
62
63 sofar += hdr_len;
64@@ -248,6 +248,9 @@ static struct mt7996_coredump *mt7996_coredump_build(struct mt7996_dev *dev, u8
65 mt7996_coredump_fw_state(dev, type, dump, &exception);
66 mt7996_coredump_fw_stack(dev, type, dump, exception);
67
68+ if (!full_dump)
69+ goto skip_dump_mem;
70+
71 /* gather memory content */
72 dump_mem = (struct mt7996_coredump_mem *)(buf + sofar);
73 dump_mem->len = crash_data->memdump_buf_len;
74@@ -255,6 +258,7 @@ static struct mt7996_coredump *mt7996_coredump_build(struct mt7996_dev *dev, u8
75 memcpy(dump_mem->data, crash_data->memdump_buf,
76 crash_data->memdump_buf_len);
77
78+skip_dump_mem:
79 mutex_unlock(&dev->dump_mutex);
80
81 return dump;
82@@ -264,7 +268,7 @@ int mt7996_coredump_submit(struct mt7996_dev *dev, u8 type)
83 {
84 struct mt7996_coredump *dump;
85
86- dump = mt7996_coredump_build(dev, type);
87+ dump = mt7996_coredump_build(dev, type, true);
88 if (!dump) {
89 dev_warn(dev->mt76.dev, "no crash dump data found\n");
90 return -ENODATA;
91diff --git a/mt7996/coredump.h b/mt7996/coredump.h
developerc2cfe0f2023-09-22 04:11:09 +0800[diff] [blame]92index 01ed3731c..93cd84a03 100644
developer064da3c2023-06-13 15:57:26 +0800[diff] [blame]93--- a/mt7996/coredump.h
94+++ b/mt7996/coredump.h
95@@ -75,6 +75,7 @@ struct mt7996_mem_region {
96 const struct mt7996_mem_region *
97 mt7996_coredump_get_mem_layout(struct mt7996_dev *dev, u8 type, u32 *num);
98 struct mt7996_crash_data *mt7996_coredump_new(struct mt7996_dev *dev, u8 type);
99+struct mt7996_coredump *mt7996_coredump_build(struct mt7996_dev *dev, u8 type, bool full_dump);
100 int mt7996_coredump_submit(struct mt7996_dev *dev, u8 type);
101 int mt7996_coredump_register(struct mt7996_dev *dev);
102 void mt7996_coredump_unregister(struct mt7996_dev *dev);
103@@ -92,6 +93,12 @@ static inline int mt7996_coredump_submit(struct mt7996_dev *dev, u8 type)
104 return 0;
105 }
106
107+static inline struct
108+mt7996_coredump *mt7996_coredump_build(struct mt7996_dev *dev, u8 type, bool full_dump)
109+{
110+ return NULL;
111+}
112+
113 static inline struct
114 mt7996_crash_data *mt7996_coredump_new(struct mt7996_dev *dev, u8 type)
115 {
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]116diff --git a/mt7996/debugfs.c b/mt7996/debugfs.c
developerc2cfe0f2023-09-22 04:11:09 +0800[diff] [blame]117index 9bd953586..92aa1644f 100644
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]118--- a/mt7996/debugfs.c
119+++ b/mt7996/debugfs.c
developerc2cfe0f2023-09-22 04:11:09 +0800[diff] [blame]120@@ -290,11 +290,20 @@ mt7996_fw_debug_wm_set(void *data, u64 val)
121 DEBUG_SPL,
122 DEBUG_RPT_RX,
123 DEBUG_RPT_RA = 68,
124+ DEBUG_IDS_PP = 93,
125+ DEBUG_IDS_RA = 94,
126+ DEBUG_IDS_BF = 95,
127+ DEBUG_IDS_SR = 96,
128+ DEBUG_IDS_RU = 97,
129+ DEBUG_IDS_MUMIMO = 98,
130 } debug;
131 bool tx, rx, en;
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]132 int ret;
133
134 dev->fw_debug_wm = val ? MCU_FW_LOG_TO_HOST : 0;
135+#ifdef CONFIG_MTK_DEBUG
136+ dev->fw_debug_wm = val;
137+#endif
138
139 if (dev->fw_debug_bin)
140 val = MCU_FW_LOG_RELAY;
developerc2cfe0f2023-09-22 04:11:09 +0800[diff] [blame]141@@ -309,8 +318,8 @@ mt7996_fw_debug_wm_set(void *data, u64 val)
142 if (ret)
143 return ret;
144
145- for (debug = DEBUG_TXCMD; debug <= DEBUG_RPT_RA; debug++) {
146- if (debug == 67)
147+ for (debug = DEBUG_TXCMD; debug <= DEBUG_IDS_MUMIMO; debug++) {
148+ if (debug == 67 || (debug > DEBUG_RPT_RA && debug < DEBUG_IDS_PP))
149 continue;
150
151 if (debug == DEBUG_RPT_RX)
152@@ -401,11 +410,12 @@ mt7996_fw_debug_bin_set(void *data, u64 val)
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]153 };
154 struct mt7996_dev *dev = data;
155
156- if (!dev->relay_fwlog)
157+ if (!dev->relay_fwlog) {
158 dev->relay_fwlog = relay_open("fwlog_data", dev->debugfs_dir,
159 1500, 512, &relay_cb, NULL);
160- if (!dev->relay_fwlog)
161- return -ENOMEM;
162+ if (!dev->relay_fwlog)
163+ return -ENOMEM;
164+ }
165
166 dev->fw_debug_bin = val;
167
developerc2cfe0f2023-09-22 04:11:09 +0800[diff] [blame]168@@ -819,6 +829,11 @@ int mt7996_init_debugfs(struct mt7996_phy *phy)
developer064da3c2023-06-13 15:57:26 +0800[diff] [blame]169 if (phy == &dev->phy)
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]170 dev->debugfs_dir = dir;
developer064da3c2023-06-13 15:57:26 +0800[diff] [blame]171
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]172+#ifdef CONFIG_MTK_DEBUG
developer064da3c2023-06-13 15:57:26 +0800[diff] [blame]173+ debugfs_create_u16("wlan_idx", 0600, dir, &dev->wlan_idx);
174+ mt7996_mtk_init_debugfs(phy, dir);
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]175+#endif
developer064da3c2023-06-13 15:57:26 +0800[diff] [blame]176+
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]177 return 0;
178 }
developer064da3c2023-06-13 15:57:26 +0800[diff] [blame]179
developerc2cfe0f2023-09-22 04:11:09 +0800[diff] [blame]180@@ -831,6 +846,12 @@ mt7996_debugfs_write_fwlog(struct mt7996_dev *dev, const void *hdr, int hdrlen,
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]181 void *dest;
182
183 spin_lock_irqsave(&lock, flags);
184+
185+ if (!dev->relay_fwlog) {
186+ spin_unlock_irqrestore(&lock, flags);
187+ return;
188+ }
189+
190 dest = relay_reserve(dev->relay_fwlog, hdrlen + len + 4);
191 if (dest) {
192 *(u32 *)dest = hdrlen + len;
developerc2cfe0f2023-09-22 04:11:09 +0800[diff] [blame]193@@ -863,9 +884,6 @@ void mt7996_debugfs_rx_fw_monitor(struct mt7996_dev *dev, const void *data, int
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]194 .msg_type = cpu_to_le16(PKT_TYPE_RX_FW_MONITOR),
195 };
196
197- if (!dev->relay_fwlog)
198- return;
199-
200 hdr.serial_id = cpu_to_le16(dev->fw_debug_seq++);
201 hdr.timestamp = cpu_to_le32(mt76_rr(dev, MT_LPON_FRCR(0)));
202 hdr.len = *(__le16 *)data;
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]203diff --git a/mt7996/mt7996.h b/mt7996/mt7996.h
developerc2cfe0f2023-09-22 04:11:09 +0800[diff] [blame]204index 4477b95d6..8aa124a0c 100644
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]205--- a/mt7996/mt7996.h
206+++ b/mt7996/mt7996.h
developerc2cfe0f2023-09-22 04:11:09 +0800[diff] [blame]207@@ -264,6 +264,16 @@ struct mt7996_dev {
208 spinlock_t reg_lock;
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]209
210 u8 wtbl_size_group;
211+
212+#ifdef CONFIG_MTK_DEBUG
213+ u16 wlan_idx;
214+ struct {
developer064da3c2023-06-13 15:57:26 +0800[diff] [blame]215+ u8 sku_disable;
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]216+ u32 fw_dbg_module;
217+ u8 fw_dbg_lv;
218+ u32 bcn_total_cnt[__MT_MAX_BAND];
219+ } dbg;
220+#endif
221 };
222
223 enum {
developerc2cfe0f2023-09-22 04:11:09 +0800[diff] [blame]224@@ -544,4 +554,8 @@ void mt7996_sta_add_debugfs(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]225 struct ieee80211_sta *sta, struct dentry *dir);
226 #endif
227
228+#ifdef CONFIG_MTK_DEBUG
229+int mt7996_mtk_init_debugfs(struct mt7996_phy *phy, struct dentry *dir);
230+#endif
231+
232 #endif
233diff --git a/mt7996/mtk_debug.h b/mt7996/mtk_debug.h
234new file mode 100644
developerc2cfe0f2023-09-22 04:11:09 +0800[diff] [blame]235index 000000000..368f0bcf0
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]236--- /dev/null
237+++ b/mt7996/mtk_debug.h
developerc2cfe0f2023-09-22 04:11:09 +0800[diff] [blame]238@@ -0,0 +1,2147 @@
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]239+#ifndef __MTK_DEBUG_H
240+#define __MTK_DEBUG_H
241+
242+#ifdef CONFIG_MTK_DEBUG
243+#define NO_SHIFT_DEFINE 0xFFFFFFFF
244+#define BITS(m, n) (~(BIT(m)-1) & ((BIT(n) - 1) | BIT(n)))
245+
246+#define GET_FIELD(_field, _reg) \
247+ ({ \
248+ (((_reg) & (_field##_MASK)) >> (_field##_SHIFT)); \
249+ })
250+
251+/* AGG */
252+#define BN0_WF_AGG_TOP_BASE 0x820e2000
253+#define BN1_WF_AGG_TOP_BASE 0x820f2000
254+#define IP1_BN0_WF_AGG_TOP_BASE 0x830e2000
255+
256+#define BN0_WF_AGG_TOP_SCR_ADDR (BN0_WF_AGG_TOP_BASE + 0x0) // 2000
257+#define BN0_WF_AGG_TOP_SCR0_ADDR (BN0_WF_AGG_TOP_BASE + 0x4) // 2004
258+#define BN0_WF_AGG_TOP_SCR1_ADDR (BN0_WF_AGG_TOP_BASE + 0x8) // 2008
259+#define BN0_WF_AGG_TOP_BCR_ADDR (BN0_WF_AGG_TOP_BASE + 0xc) // 200C
260+#define BN0_WF_AGG_TOP_BWCR_ADDR (BN0_WF_AGG_TOP_BASE + 0x10) // 2010
261+#define BN0_WF_AGG_TOP_ARCR0_ADDR (BN0_WF_AGG_TOP_BASE + 0x14) // 2014
262+#define BN0_WF_AGG_TOP_ARUCR_ADDR (BN0_WF_AGG_TOP_BASE + 0x18) // 2018
263+#define BN0_WF_AGG_TOP_ARDCR_ADDR (BN0_WF_AGG_TOP_BASE + 0x1c) // 201C
264+#define BN0_WF_AGG_TOP_AALCR0_ADDR (BN0_WF_AGG_TOP_BASE + 0x20) // 2020
265+#define BN0_WF_AGG_TOP_AALCR1_ADDR (BN0_WF_AGG_TOP_BASE + 0x24) // 2024
266+#define BN0_WF_AGG_TOP_PCR0_ADDR (BN0_WF_AGG_TOP_BASE + 0x28) // 2028
267+#define BN0_WF_AGG_TOP_PCR1_ADDR (BN0_WF_AGG_TOP_BASE + 0x2c) // 202C
268+#define BN0_WF_AGG_TOP_TTCR0_ADDR (BN0_WF_AGG_TOP_BASE + 0x30) // 2030
269+#define BN0_WF_AGG_TOP_TTCR1_ADDR (BN0_WF_AGG_TOP_BASE + 0x34) // 2034
270+#define BN0_WF_AGG_TOP_ACR1_ADDR (BN0_WF_AGG_TOP_BASE + 0x38) // 2038
271+#define BN0_WF_AGG_TOP_ACR4_ADDR (BN0_WF_AGG_TOP_BASE + 0x3c) // 203C
272+#define BN0_WF_AGG_TOP_ACR5_ADDR (BN0_WF_AGG_TOP_BASE + 0x40) // 2040
273+#define BN0_WF_AGG_TOP_ACR6_ADDR (BN0_WF_AGG_TOP_BASE + 0x44) // 2044
274+#define BN0_WF_AGG_TOP_ACR8_ADDR (BN0_WF_AGG_TOP_BASE + 0x4c) // 204C
275+#define BN0_WF_AGG_TOP_MRCR_ADDR (BN0_WF_AGG_TOP_BASE + 0x50) // 2050
276+#define BN0_WF_AGG_TOP_MMPDR_ADDR (BN0_WF_AGG_TOP_BASE + 0x54) // 2054
277+#define BN0_WF_AGG_TOP_GFPDR_ADDR (BN0_WF_AGG_TOP_BASE + 0x58) // 2058
278+#define BN0_WF_AGG_TOP_VHTPDR_ADDR (BN0_WF_AGG_TOP_BASE + 0x5c) // 205C
279+#define BN0_WF_AGG_TOP_HEPDR_ADDR (BN0_WF_AGG_TOP_BASE + 0x60) // 2060
280+#define BN0_WF_AGG_TOP_CTCR_ADDR (BN0_WF_AGG_TOP_BASE + 0x64) // 2064
281+#define BN0_WF_AGG_TOP_ATCR3_ADDR (BN0_WF_AGG_TOP_BASE + 0x68) // 2068
282+#define BN0_WF_AGG_TOP_SRCR_ADDR (BN0_WF_AGG_TOP_BASE + 0x6c) // 206C
283+#define BN0_WF_AGG_TOP_VBCR_ADDR (BN0_WF_AGG_TOP_BASE + 0x70) // 2070
284+#define BN0_WF_AGG_TOP_TCR_ADDR (BN0_WF_AGG_TOP_BASE + 0x74) // 2074
285+#define BN0_WF_AGG_TOP_SRHS_ADDR (BN0_WF_AGG_TOP_BASE + 0x78) // 2078
286+#define BN0_WF_AGG_TOP_DBRCR0_ADDR (BN0_WF_AGG_TOP_BASE + 0x7c) // 207C
287+#define BN0_WF_AGG_TOP_DBRCR1_ADDR (BN0_WF_AGG_TOP_BASE + 0x80) // 2080
288+#define BN0_WF_AGG_TOP_CTETCR_ADDR (BN0_WF_AGG_TOP_BASE + 0x84) // 2084
289+#define BN0_WF_AGG_TOP_WPDR_ADDR (BN0_WF_AGG_TOP_BASE + 0x88) // 2088
290+#define BN0_WF_AGG_TOP_PLRPDR_ADDR (BN0_WF_AGG_TOP_BASE + 0x8c) // 208C
291+#define BN0_WF_AGG_TOP_CECR_ADDR (BN0_WF_AGG_TOP_BASE + 0x90) // 2090
292+#define BN0_WF_AGG_TOP_OMRCR0_ADDR (BN0_WF_AGG_TOP_BASE + 0x94) // 2094
293+#define BN0_WF_AGG_TOP_OMRCR1_ADDR (BN0_WF_AGG_TOP_BASE + 0x98) // 2098
294+#define BN0_WF_AGG_TOP_OMRCR2_ADDR (BN0_WF_AGG_TOP_BASE + 0x9c) // 209C
295+#define BN0_WF_AGG_TOP_OMRCR3_ADDR (BN0_WF_AGG_TOP_BASE + 0xa0) // 20A0
296+#define BN0_WF_AGG_TOP_TMCR_ADDR (BN0_WF_AGG_TOP_BASE + 0xa4) // 20A4
297+#define BN0_WF_AGG_TOP_TWTCR_ADDR (BN0_WF_AGG_TOP_BASE + 0xa8) // 20A8
298+#define BN0_WF_AGG_TOP_TWTSTACR_ADDR (BN0_WF_AGG_TOP_BASE + 0xac) // 20AC
299+#define BN0_WF_AGG_TOP_TWTE0TB_ADDR (BN0_WF_AGG_TOP_BASE + 0xb0) // 20B0
300+#define BN0_WF_AGG_TOP_TWTE1TB_ADDR (BN0_WF_AGG_TOP_BASE + 0xb4) // 20B4
301+#define BN0_WF_AGG_TOP_TWTE2TB_ADDR (BN0_WF_AGG_TOP_BASE + 0xb8) // 20B8
302+#define BN0_WF_AGG_TOP_TWTE3TB_ADDR (BN0_WF_AGG_TOP_BASE + 0xbc) // 20BC
303+#define BN0_WF_AGG_TOP_TWTE4TB_ADDR (BN0_WF_AGG_TOP_BASE + 0xc0) // 20C0
304+#define BN0_WF_AGG_TOP_TWTE5TB_ADDR (BN0_WF_AGG_TOP_BASE + 0xc4) // 20C4
305+#define BN0_WF_AGG_TOP_TWTE6TB_ADDR (BN0_WF_AGG_TOP_BASE + 0xc8) // 20C8
306+#define BN0_WF_AGG_TOP_TWTE7TB_ADDR (BN0_WF_AGG_TOP_BASE + 0xcc) // 20CC
307+#define BN0_WF_AGG_TOP_TWTE8TB_ADDR (BN0_WF_AGG_TOP_BASE + 0xd0) // 20D0
308+#define BN0_WF_AGG_TOP_TWTE9TB_ADDR (BN0_WF_AGG_TOP_BASE + 0xd4) // 20D4
309+#define BN0_WF_AGG_TOP_TWTEATB_ADDR (BN0_WF_AGG_TOP_BASE + 0xd8) // 20D8
310+#define BN0_WF_AGG_TOP_TWTEBTB_ADDR (BN0_WF_AGG_TOP_BASE + 0xdc) // 20DC
311+#define BN0_WF_AGG_TOP_TWTECTB_ADDR (BN0_WF_AGG_TOP_BASE + 0xe0) // 20E0
312+#define BN0_WF_AGG_TOP_TWTEDTB_ADDR (BN0_WF_AGG_TOP_BASE + 0xe4) // 20E4
313+#define BN0_WF_AGG_TOP_TWTEETB_ADDR (BN0_WF_AGG_TOP_BASE + 0xe8) // 20E8
314+#define BN0_WF_AGG_TOP_TWTEFTB_ADDR (BN0_WF_AGG_TOP_BASE + 0xec) // 20EC
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]315+#define BN0_WF_AGG_TOP_ATCR0_ADDR (BN0_WF_AGG_TOP_BASE + 0x108) // 2108
316+#define BN0_WF_AGG_TOP_ATCR1_ADDR (BN0_WF_AGG_TOP_BASE + 0x10c) // 210C
317+#define BN0_WF_AGG_TOP_TCCR_ADDR (BN0_WF_AGG_TOP_BASE + 0x110) // 2110
318+#define BN0_WF_AGG_TOP_TFCR_ADDR (BN0_WF_AGG_TOP_BASE + 0x114) // 2114
319+#define BN0_WF_AGG_TOP_MUCR0_ADDR (BN0_WF_AGG_TOP_BASE + 0x118) // 2118
320+#define BN0_WF_AGG_TOP_MUCR1_ADDR (BN0_WF_AGG_TOP_BASE + 0x11c) // 211C
developerc2cfe0f2023-09-22 04:11:09 +0800[diff] [blame]321+#define BN0_WF_AGG_TOP_AALCR2_ADDR (BN0_WF_AGG_TOP_BASE + 0x128) // 2128
322+#define BN0_WF_AGG_TOP_AALCR3_ADDR (BN0_WF_AGG_TOP_BASE + 0x12c) // 212C
323+#define BN0_WF_AGG_TOP_AALCR4_ADDR (BN0_WF_AGG_TOP_BASE + 0x130) // 2130
324+#define BN0_WF_AGG_TOP_AALCR5_ADDR (BN0_WF_AGG_TOP_BASE + 0x134) // 2134
325+#define BN0_WF_AGG_TOP_AALCR6_ADDR (BN0_WF_AGG_TOP_BASE + 0x138) // 2138
326+#define BN0_WF_AGG_TOP_AALCR7_ADDR (BN0_WF_AGG_TOP_BASE + 0x13c) // 213C
327+#define BN0_WF_AGG_TOP_CSDCR0_ADDR (BN0_WF_AGG_TOP_BASE + 0x150) // 2150
328+#define BN0_WF_AGG_TOP_CSDCR1_ADDR (BN0_WF_AGG_TOP_BASE + 0x154) // 2154
329+#define BN0_WF_AGG_TOP_CSDCR2_ADDR (BN0_WF_AGG_TOP_BASE + 0x158) // 2158
330+#define BN0_WF_AGG_TOP_CSDCR3_ADDR (BN0_WF_AGG_TOP_BASE + 0x15c) // 215C
331+#define BN0_WF_AGG_TOP_CSDCR4_ADDR (BN0_WF_AGG_TOP_BASE + 0x160) // 2160
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]332+#define BN0_WF_AGG_TOP_DYNSCR_ADDR (BN0_WF_AGG_TOP_BASE + 0x178) // 2178
333+#define BN0_WF_AGG_TOP_DYNSSCR_ADDR (BN0_WF_AGG_TOP_BASE + 0x198) // 2198
334+#define BN0_WF_AGG_TOP_TCDCNT0_ADDR (BN0_WF_AGG_TOP_BASE + 0x2c8) // 22C8
335+#define BN0_WF_AGG_TOP_TCDCNT1_ADDR (BN0_WF_AGG_TOP_BASE + 0x2cc) // 22CC
336+#define BN0_WF_AGG_TOP_TCSR0_ADDR (BN0_WF_AGG_TOP_BASE + 0x2d0) // 22D0
337+#define BN0_WF_AGG_TOP_TCSR1_ADDR (BN0_WF_AGG_TOP_BASE + 0x2d4) // 22D4
338+#define BN0_WF_AGG_TOP_TCSR2_ADDR (BN0_WF_AGG_TOP_BASE + 0x2d8) // 22D8
339+#define BN0_WF_AGG_TOP_DCR_ADDR (BN0_WF_AGG_TOP_BASE + 0x2e4) // 22E4
340+#define BN0_WF_AGG_TOP_SMDCR_ADDR (BN0_WF_AGG_TOP_BASE + 0x2e8) // 22E8
341+#define BN0_WF_AGG_TOP_TXCMDSMCR_ADDR (BN0_WF_AGG_TOP_BASE + 0x2ec) // 22EC
342+#define BN0_WF_AGG_TOP_SMCR0_ADDR (BN0_WF_AGG_TOP_BASE + 0x2f0) // 22F0
343+#define BN0_WF_AGG_TOP_SMCR1_ADDR (BN0_WF_AGG_TOP_BASE + 0x2f4) // 22F4
344+#define BN0_WF_AGG_TOP_SMCR2_ADDR (BN0_WF_AGG_TOP_BASE + 0x2f8) // 22F8
345+#define BN0_WF_AGG_TOP_SMCR3_ADDR (BN0_WF_AGG_TOP_BASE + 0x2fc) // 22FC
346+
347+#define BN0_WF_AGG_TOP_AALCR0_AC01_AGG_LIMIT_ADDR BN0_WF_AGG_TOP_AALCR0_ADDR
348+#define BN0_WF_AGG_TOP_AALCR0_AC01_AGG_LIMIT_MASK 0x03FF0000 // AC01_AGG_LIMIT[25..16]
349+#define BN0_WF_AGG_TOP_AALCR0_AC01_AGG_LIMIT_SHFT 16
350+#define BN0_WF_AGG_TOP_AALCR0_AC00_AGG_LIMIT_ADDR BN0_WF_AGG_TOP_AALCR0_ADDR
351+#define BN0_WF_AGG_TOP_AALCR0_AC00_AGG_LIMIT_MASK 0x000003FF // AC00_AGG_LIMIT[9..0]
352+#define BN0_WF_AGG_TOP_AALCR0_AC00_AGG_LIMIT_SHFT 0
353+
354+#define BN0_WF_AGG_TOP_AALCR1_AC03_AGG_LIMIT_ADDR BN0_WF_AGG_TOP_AALCR1_ADDR
355+#define BN0_WF_AGG_TOP_AALCR1_AC03_AGG_LIMIT_MASK 0x03FF0000 // AC03_AGG_LIMIT[25..16]
356+#define BN0_WF_AGG_TOP_AALCR1_AC03_AGG_LIMIT_SHFT 16
357+#define BN0_WF_AGG_TOP_AALCR1_AC02_AGG_LIMIT_ADDR BN0_WF_AGG_TOP_AALCR1_ADDR
358+#define BN0_WF_AGG_TOP_AALCR1_AC02_AGG_LIMIT_MASK 0x000003FF // AC02_AGG_LIMIT[9..0]
359+#define BN0_WF_AGG_TOP_AALCR1_AC02_AGG_LIMIT_SHFT 0
360+
361+#define BN0_WF_AGG_TOP_AALCR2_AC11_AGG_LIMIT_ADDR BN0_WF_AGG_TOP_AALCR2_ADDR
362+#define BN0_WF_AGG_TOP_AALCR2_AC11_AGG_LIMIT_MASK 0x03FF0000 // AC11_AGG_LIMIT[25..16]
363+#define BN0_WF_AGG_TOP_AALCR2_AC11_AGG_LIMIT_SHFT 16
364+#define BN0_WF_AGG_TOP_AALCR2_AC10_AGG_LIMIT_ADDR BN0_WF_AGG_TOP_AALCR2_ADDR
365+#define BN0_WF_AGG_TOP_AALCR2_AC10_AGG_LIMIT_MASK 0x000003FF // AC10_AGG_LIMIT[9..0]
366+#define BN0_WF_AGG_TOP_AALCR2_AC10_AGG_LIMIT_SHFT 0
367+
368+#define BN0_WF_AGG_TOP_AALCR3_AC13_AGG_LIMIT_ADDR BN0_WF_AGG_TOP_AALCR3_ADDR
369+#define BN0_WF_AGG_TOP_AALCR3_AC13_AGG_LIMIT_MASK 0x03FF0000 // AC13_AGG_LIMIT[25..16]
370+#define BN0_WF_AGG_TOP_AALCR3_AC13_AGG_LIMIT_SHFT 16
371+#define BN0_WF_AGG_TOP_AALCR3_AC12_AGG_LIMIT_ADDR BN0_WF_AGG_TOP_AALCR3_ADDR
372+#define BN0_WF_AGG_TOP_AALCR3_AC12_AGG_LIMIT_MASK 0x000003FF // AC12_AGG_LIMIT[9..0]
373+#define BN0_WF_AGG_TOP_AALCR3_AC12_AGG_LIMIT_SHFT 0
374+
375+#define BN0_WF_AGG_TOP_AALCR4_AC21_AGG_LIMIT_ADDR BN0_WF_AGG_TOP_AALCR4_ADDR
376+#define BN0_WF_AGG_TOP_AALCR4_AC21_AGG_LIMIT_MASK 0x03FF0000 // AC21_AGG_LIMIT[25..16]
377+#define BN0_WF_AGG_TOP_AALCR4_AC21_AGG_LIMIT_SHFT 16
378+#define BN0_WF_AGG_TOP_AALCR4_AC20_AGG_LIMIT_ADDR BN0_WF_AGG_TOP_AALCR4_ADDR
379+#define BN0_WF_AGG_TOP_AALCR4_AC20_AGG_LIMIT_MASK 0x000003FF // AC20_AGG_LIMIT[9..0]
380+#define BN0_WF_AGG_TOP_AALCR4_AC20_AGG_LIMIT_SHFT 0
381+
382+#define BN0_WF_AGG_TOP_AALCR5_AC23_AGG_LIMIT_ADDR BN0_WF_AGG_TOP_AALCR5_ADDR
383+#define BN0_WF_AGG_TOP_AALCR5_AC23_AGG_LIMIT_MASK 0x03FF0000 // AC23_AGG_LIMIT[25..16]
384+#define BN0_WF_AGG_TOP_AALCR5_AC23_AGG_LIMIT_SHFT 16
385+#define BN0_WF_AGG_TOP_AALCR5_AC22_AGG_LIMIT_ADDR BN0_WF_AGG_TOP_AALCR5_ADDR
386+#define BN0_WF_AGG_TOP_AALCR5_AC22_AGG_LIMIT_MASK 0x000003FF // AC22_AGG_LIMIT[9..0]
387+#define BN0_WF_AGG_TOP_AALCR5_AC22_AGG_LIMIT_SHFT 0
388+
389+#define BN0_WF_AGG_TOP_AALCR6_AC31_AGG_LIMIT_ADDR BN0_WF_AGG_TOP_AALCR6_ADDR
390+#define BN0_WF_AGG_TOP_AALCR6_AC31_AGG_LIMIT_MASK 0x03FF0000 // AC31_AGG_LIMIT[25..16]
391+#define BN0_WF_AGG_TOP_AALCR6_AC31_AGG_LIMIT_SHFT 16
392+#define BN0_WF_AGG_TOP_AALCR6_AC30_AGG_LIMIT_ADDR BN0_WF_AGG_TOP_AALCR6_ADDR
393+#define BN0_WF_AGG_TOP_AALCR6_AC30_AGG_LIMIT_MASK 0x000003FF // AC30_AGG_LIMIT[9..0]
394+#define BN0_WF_AGG_TOP_AALCR6_AC30_AGG_LIMIT_SHFT 0
395+#define BN0_WF_AGG_TOP_AALCR7_AC33_AGG_LIMIT_ADDR BN0_WF_AGG_TOP_AALCR7_ADDR
396+#define BN0_WF_AGG_TOP_AALCR7_AC33_AGG_LIMIT_MASK 0x03FF0000 // AC33_AGG_LIMIT[25..16]
397+#define BN0_WF_AGG_TOP_AALCR7_AC33_AGG_LIMIT_SHFT 16
398+#define BN0_WF_AGG_TOP_AALCR7_AC32_AGG_LIMIT_ADDR BN0_WF_AGG_TOP_AALCR7_ADDR
399+#define BN0_WF_AGG_TOP_AALCR7_AC32_AGG_LIMIT_MASK 0x000003FF // AC32_AGG_LIMIT[9..0]
400+#define BN0_WF_AGG_TOP_AALCR7_AC32_AGG_LIMIT_SHFT 0
401+
402+/* DMA */
403+struct queue_desc {
404+ u32 hw_desc_base;
405+ u16 ring_size;
406+ char *const ring_info;
407+};
developer064da3c2023-06-13 15:57:26 +0800[diff] [blame]408+
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]409+// HOST DMA
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]410+#define WF_WFDMA_HOST_DMA0_BASE 0xd4000
411+
412+#define WF_WFDMA_HOST_DMA0_HOST_INT_STA_ADDR \
413+ (WF_WFDMA_HOST_DMA0_BASE + 0x200) /* 4200 */
414+#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_ADDR \
415+ (WF_WFDMA_HOST_DMA0_BASE + 0X204) /* 4204 */
416+#define WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_ADDR \
417+ (WF_WFDMA_HOST_DMA0_BASE + 0x208) /* 4208 */
418+
419+#define WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_RX_DMA_BUSY_ADDR \
420+ WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_ADDR
421+#define WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK \
422+ 0x00000008 /* RX_DMA_BUSY[3] */
423+#define WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT 3
424+#define WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_RX_DMA_EN_ADDR \
425+ WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_ADDR
426+#define WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_RX_DMA_EN_MASK \
427+ 0x00000004 /* RX_DMA_EN[2] */
428+#define WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_RX_DMA_EN_SHFT 2
429+#define WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_TX_DMA_BUSY_ADDR \
430+ WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_ADDR
431+#define WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK \
432+ 0x00000002 /* TX_DMA_BUSY[1] */
433+#define WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT 1
434+#define WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_TX_DMA_EN_ADDR \
435+ WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_ADDR
436+#define WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_TX_DMA_EN_MASK \
437+ 0x00000001 /* TX_DMA_EN[0] */
438+#define WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_TX_DMA_EN_SHFT 0
439+
440+
441+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING0_CTRL0_ADDR \
442+ (WF_WFDMA_HOST_DMA0_BASE + 0x300) /* 4300 */
443+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING0_CTRL1_ADDR \
444+ (WF_WFDMA_HOST_DMA0_BASE + 0x304) /* 4304 */
445+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING0_CTRL2_ADDR \
446+ (WF_WFDMA_HOST_DMA0_BASE + 0x308) /* 4308 */
447+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING0_CTRL3_ADDR \
448+ (WF_WFDMA_HOST_DMA0_BASE + 0x30c) /* 430C */
449+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING1_CTRL0_ADDR \
450+ (WF_WFDMA_HOST_DMA0_BASE + 0x310) /* 4310 */
451+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING1_CTRL1_ADDR \
452+ (WF_WFDMA_HOST_DMA0_BASE + 0x314) /* 4314 */
453+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING1_CTRL2_ADDR \
454+ (WF_WFDMA_HOST_DMA0_BASE + 0x318) /* 4318 */
455+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING1_CTRL3_ADDR \
456+ (WF_WFDMA_HOST_DMA0_BASE + 0x31c) /* 431C */
457+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING2_CTRL0_ADDR \
458+ (WF_WFDMA_HOST_DMA0_BASE + 0x320) /* 4320 */
459+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING2_CTRL1_ADDR \
460+ (WF_WFDMA_HOST_DMA0_BASE + 0x324) /* 4324 */
461+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING2_CTRL2_ADDR \
462+ (WF_WFDMA_HOST_DMA0_BASE + 0x328) /* 4328 */
463+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING2_CTRL3_ADDR \
464+ (WF_WFDMA_HOST_DMA0_BASE + 0x32c) /* 432C */
465+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING3_CTRL0_ADDR \
466+ (WF_WFDMA_HOST_DMA0_BASE + 0x330) /* 4330 */
467+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING3_CTRL1_ADDR \
468+ (WF_WFDMA_HOST_DMA0_BASE + 0x334) /* 4334 */
469+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING3_CTRL2_ADDR \
470+ (WF_WFDMA_HOST_DMA0_BASE + 0x338) /* 4338 */
471+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING3_CTRL3_ADDR \
472+ (WF_WFDMA_HOST_DMA0_BASE + 0x33c) /* 433C */
473+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING4_CTRL0_ADDR \
474+ (WF_WFDMA_HOST_DMA0_BASE + 0x340) /* 4340 */
475+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING4_CTRL1_ADDR \
476+ (WF_WFDMA_HOST_DMA0_BASE + 0x344) /* 4344 */
477+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING4_CTRL2_ADDR \
478+ (WF_WFDMA_HOST_DMA0_BASE + 0x348) /* 4348 */
479+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING4_CTRL3_ADDR \
480+ (WF_WFDMA_HOST_DMA0_BASE + 0x34c) /* 434C */
481+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING5_CTRL0_ADDR \
482+ (WF_WFDMA_HOST_DMA0_BASE + 0x350) /* 4350 */
483+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING5_CTRL1_ADDR \
484+ (WF_WFDMA_HOST_DMA0_BASE + 0x354) /* 4354 */
485+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING5_CTRL2_ADDR \
486+ (WF_WFDMA_HOST_DMA0_BASE + 0x358) /* 4358 */
487+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING5_CTRL3_ADDR \
488+ (WF_WFDMA_HOST_DMA0_BASE + 0x35c) /* 435C */
489+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING6_CTRL0_ADDR \
490+ (WF_WFDMA_HOST_DMA0_BASE + 0x360) /* 4360 */
491+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING6_CTRL1_ADDR \
492+ (WF_WFDMA_HOST_DMA0_BASE + 0x364) /* 4364 */
493+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING6_CTRL2_ADDR \
494+ (WF_WFDMA_HOST_DMA0_BASE + 0x368) /* 4368 */
495+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING6_CTRL3_ADDR \
496+ (WF_WFDMA_HOST_DMA0_BASE + 0x36c) /* 436C */
497+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING16_CTRL0_ADDR \
498+ (WF_WFDMA_HOST_DMA0_BASE + 0x400) /* 4400 */
499+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING16_CTRL1_ADDR \
500+ (WF_WFDMA_HOST_DMA0_BASE + 0x404) /* 4404 */
501+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING16_CTRL2_ADDR \
502+ (WF_WFDMA_HOST_DMA0_BASE + 0x408) /* 4408 */
503+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING16_CTRL3_ADDR \
504+ (WF_WFDMA_HOST_DMA0_BASE + 0x40c) /* 440C */
505+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING17_CTRL0_ADDR \
506+ (WF_WFDMA_HOST_DMA0_BASE + 0x410) /* 4410 */
507+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING17_CTRL1_ADDR \
508+ (WF_WFDMA_HOST_DMA0_BASE + 0x414) /* 4414 */
509+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING17_CTRL2_ADDR \
510+ (WF_WFDMA_HOST_DMA0_BASE + 0x418) /* 4418 */
511+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING17_CTRL3_ADDR \
512+ (WF_WFDMA_HOST_DMA0_BASE + 0x41c) /* 441C */
513+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING18_CTRL0_ADDR \
514+ (WF_WFDMA_HOST_DMA0_BASE + 0x420) /* 4420 */
515+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING18_CTRL1_ADDR \
516+ (WF_WFDMA_HOST_DMA0_BASE + 0x424) /* 4424 */
517+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING18_CTRL2_ADDR \
518+ (WF_WFDMA_HOST_DMA0_BASE + 0x428) /* 4428 */
519+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING18_CTRL3_ADDR \
520+ (WF_WFDMA_HOST_DMA0_BASE + 0x42c) /* 442C */
521+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING19_CTRL0_ADDR \
522+ (WF_WFDMA_HOST_DMA0_BASE + 0x430) /* 4430 */
523+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING19_CTRL1_ADDR \
524+ (WF_WFDMA_HOST_DMA0_BASE + 0x434) /* 4434 */
525+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING19_CTRL2_ADDR \
526+ (WF_WFDMA_HOST_DMA0_BASE + 0x438) /* 4438 */
527+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING19_CTRL3_ADDR \
528+ (WF_WFDMA_HOST_DMA0_BASE + 0x43c) /* 443C */
529+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING20_CTRL0_ADDR \
530+ (WF_WFDMA_HOST_DMA0_BASE + 0x440) /* 4440 */
531+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING20_CTRL1_ADDR \
532+ (WF_WFDMA_HOST_DMA0_BASE + 0x444) /* 4444 */
533+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING20_CTRL2_ADDR \
534+ (WF_WFDMA_HOST_DMA0_BASE + 0x448) /* 4448 */
535+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING20_CTRL3_ADDR \
536+ (WF_WFDMA_HOST_DMA0_BASE + 0x44c) /* 444C */
537+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING21_CTRL0_ADDR \
538+ (WF_WFDMA_HOST_DMA0_BASE + 0x450) /* 4450 */
539+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING21_CTRL1_ADDR \
540+ (WF_WFDMA_HOST_DMA0_BASE + 0x454) /* 4454 */
541+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING21_CTRL2_ADDR \
542+ (WF_WFDMA_HOST_DMA0_BASE + 0x458) /* 4458 */
543+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING21_CTRL3_ADDR \
544+ (WF_WFDMA_HOST_DMA0_BASE + 0x45c) /* 445c */
545+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING22_CTRL0_ADDR (WF_WFDMA_HOST_DMA0_BASE + 0x460) // 4460
546+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING22_CTRL1_ADDR (WF_WFDMA_HOST_DMA0_BASE + 0x464) // 4464
547+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING22_CTRL2_ADDR (WF_WFDMA_HOST_DMA0_BASE + 0x468) // 4468
548+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING22_CTRL3_ADDR (WF_WFDMA_HOST_DMA0_BASE + 0x46c) // 446C
549+
550+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING0_CTRL0_ADDR \
551+ (WF_WFDMA_HOST_DMA0_BASE + 0x500) /* 4500 */
552+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING0_CTRL1_ADDR \
553+ (WF_WFDMA_HOST_DMA0_BASE + 0x504) /* 4504 */
554+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING0_CTRL2_ADDR \
555+ (WF_WFDMA_HOST_DMA0_BASE + 0x508) /* 4508 */
556+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING0_CTRL3_ADDR \
557+ (WF_WFDMA_HOST_DMA0_BASE + 0x50c) /* 450C */
558+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING1_CTRL0_ADDR \
559+ (WF_WFDMA_HOST_DMA0_BASE + 0x510) /* 4510 */
560+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING1_CTRL1_ADDR \
561+ (WF_WFDMA_HOST_DMA0_BASE + 0x514) /* 4514 */
562+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING1_CTRL2_ADDR \
563+ (WF_WFDMA_HOST_DMA0_BASE + 0x518) /* 4518 */
564+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING1_CTRL3_ADDR \
565+ (WF_WFDMA_HOST_DMA0_BASE + 0x51c) /* 451C */
566+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING2_CTRL0_ADDR \
567+ (WF_WFDMA_HOST_DMA0_BASE + 0x520) /* 4520 */
568+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING2_CTRL1_ADDR \
569+ (WF_WFDMA_HOST_DMA0_BASE + 0x524) /* 4524 */
570+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING2_CTRL2_ADDR \
571+ (WF_WFDMA_HOST_DMA0_BASE + 0x528) /* 4528 */
572+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING2_CTRL3_ADDR \
573+ (WF_WFDMA_HOST_DMA0_BASE + 0x52C) /* 452C */
574+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING3_CTRL0_ADDR \
575+ (WF_WFDMA_HOST_DMA0_BASE + 0x530) /* 4530 */
576+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING3_CTRL1_ADDR \
577+ (WF_WFDMA_HOST_DMA0_BASE + 0x534) /* 4534 */
578+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING3_CTRL2_ADDR \
579+ (WF_WFDMA_HOST_DMA0_BASE + 0x538) /* 4538 */
580+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING3_CTRL3_ADDR \
581+ (WF_WFDMA_HOST_DMA0_BASE + 0x53C) /* 453C */
582+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING4_CTRL0_ADDR \
583+ (WF_WFDMA_HOST_DMA0_BASE + 0x540) /* 4540 */
584+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING4_CTRL1_ADDR \
585+ (WF_WFDMA_HOST_DMA0_BASE + 0x544) /* 4544 */
586+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING4_CTRL2_ADDR \
587+ (WF_WFDMA_HOST_DMA0_BASE + 0x548) /* 4548 */
588+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING4_CTRL3_ADDR \
589+ (WF_WFDMA_HOST_DMA0_BASE + 0x54c) /* 454C */
590+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING5_CTRL0_ADDR \
591+ (WF_WFDMA_HOST_DMA0_BASE + 0x550) /* 4550 */
592+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING5_CTRL1_ADDR \
593+ (WF_WFDMA_HOST_DMA0_BASE + 0x554) /* 4554 */
594+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING5_CTRL2_ADDR \
595+ (WF_WFDMA_HOST_DMA0_BASE + 0x558) /* 4558 */
596+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING5_CTRL3_ADDR \
597+ (WF_WFDMA_HOST_DMA0_BASE + 0x55c) /* 455C */
598+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING6_CTRL0_ADDR \
599+ (WF_WFDMA_HOST_DMA0_BASE + 0x560) /* 4560 */
600+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING6_CTRL1_ADDR \
601+ (WF_WFDMA_HOST_DMA0_BASE + 0x564) /* 4564 */
602+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING6_CTRL2_ADDR \
603+ (WF_WFDMA_HOST_DMA0_BASE + 0x568) /* 4568 */
604+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING6_CTRL3_ADDR \
605+ (WF_WFDMA_HOST_DMA0_BASE + 0x56c) /* 456C */
606+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING7_CTRL0_ADDR \
607+ (WF_WFDMA_HOST_DMA0_BASE + 0x570) /* 4570 */
608+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING7_CTRL1_ADDR \
609+ (WF_WFDMA_HOST_DMA0_BASE + 0x574) /* 4574 */
610+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING7_CTRL2_ADDR \
611+ (WF_WFDMA_HOST_DMA0_BASE + 0x578) /* 4578 */
612+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING7_CTRL3_ADDR \
613+ (WF_WFDMA_HOST_DMA0_BASE + 0x57c) /* 457C */
614+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING8_CTRL0_ADDR \
615+ (WF_WFDMA_HOST_DMA0_BASE + 0x580) /* 4580 */
616+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING8_CTRL1_ADDR \
617+ (WF_WFDMA_HOST_DMA0_BASE + 0x584) /* 4584 */
618+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING8_CTRL2_ADDR \
619+ (WF_WFDMA_HOST_DMA0_BASE + 0x588) /* 4588 */
620+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING8_CTRL3_ADDR \
621+ (WF_WFDMA_HOST_DMA0_BASE + 0x58c) /* 458C */
622+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING9_CTRL0_ADDR \
623+ (WF_WFDMA_HOST_DMA0_BASE + 0x590) /* 4590 */
624+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING9_CTRL1_ADDR \
625+ (WF_WFDMA_HOST_DMA0_BASE + 0x594) /* 4594 */
626+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING9_CTRL2_ADDR \
627+ (WF_WFDMA_HOST_DMA0_BASE + 0x598) /* 4598 */
628+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING9_CTRL3_ADDR \
629+ (WF_WFDMA_HOST_DMA0_BASE + 0x59c) /* 459C */
630+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING10_CTRL0_ADDR (WF_WFDMA_HOST_DMA0_BASE + 0x5a0) // 45A0
631+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING10_CTRL1_ADDR (WF_WFDMA_HOST_DMA0_BASE + 0x5a4) // 45A4
632+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING10_CTRL2_ADDR (WF_WFDMA_HOST_DMA0_BASE + 0x5a8) // 45A8
633+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING10_CTRL3_ADDR (WF_WFDMA_HOST_DMA0_BASE + 0x5ac) // 45AC
634+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING11_CTRL0_ADDR (WF_WFDMA_HOST_DMA0_BASE + 0x5b0) // 45B0
635+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING11_CTRL1_ADDR (WF_WFDMA_HOST_DMA0_BASE + 0x5b4) // 45B4
636+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING11_CTRL2_ADDR (WF_WFDMA_HOST_DMA0_BASE + 0x5b8) // 45B8
637+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING11_CTRL3_ADDR (WF_WFDMA_HOST_DMA0_BASE + 0x5bc) // 45BC
638+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING12_CTRL0_ADDR (WF_WFDMA_HOST_DMA0_BASE + 0x5C0) // 45C0
639+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING12_CTRL1_ADDR (WF_WFDMA_HOST_DMA0_BASE + 0x5C4) // 45C4
640+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING12_CTRL2_ADDR (WF_WFDMA_HOST_DMA0_BASE + 0x5C8) // 45C8
641+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING12_CTRL3_ADDR (WF_WFDMA_HOST_DMA0_BASE + 0x5CC) // 45CC
642+
643+// HOST PCIE1 DMA
644+#define WF_WFDMA_HOST_DMA0_PCIE1_BASE 0xd8000
645+
646+#define WF_WFDMA_HOST_DMA0_PCIE1_HOST_INT_STA_ADDR (WF_WFDMA_HOST_DMA0_PCIE1_BASE + 0x200) // 8200
647+#define WF_WFDMA_HOST_DMA0_PCIE1_HOST_INT_ENA_ADDR (WF_WFDMA_HOST_DMA0_PCIE1_BASE + 0X204) // 8204
648+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_GLO_CFG_ADDR (WF_WFDMA_HOST_DMA0_PCIE1_BASE + 0x208) // 8208
649+
650+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_GLO_CFG_PDMA_BT_SIZE_SHFT 4
651+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK 0x00000008
652+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT 3
653+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_GLO_CFG_RX_DMA_EN_MASK 0x00000004
654+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_GLO_CFG_RX_DMA_EN_SHFT 2
655+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK 0x00000002
656+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT 1
657+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_GLO_CFG_TX_DMA_EN_MASK 0x00000001
658+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_GLO_CFG_TX_DMA_EN_SHFT 0
659+
660+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_TX_RING21_CTRL0_ADDR (WF_WFDMA_HOST_DMA0_PCIE1_BASE + 0x450) // 8450
661+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_TX_RING21_CTRL1_ADDR (WF_WFDMA_HOST_DMA0_PCIE1_BASE + 0x454) // 8454
662+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_TX_RING21_CTRL2_ADDR (WF_WFDMA_HOST_DMA0_PCIE1_BASE + 0x458) // 8458
663+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_TX_RING21_CTRL3_ADDR (WF_WFDMA_HOST_DMA0_PCIE1_BASE + 0x45c) // 845C
664+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_TX_RING22_CTRL0_ADDR (WF_WFDMA_HOST_DMA0_PCIE1_BASE + 0x460) // 8460
665+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_TX_RING22_CTRL1_ADDR (WF_WFDMA_HOST_DMA0_PCIE1_BASE + 0x464) // 8464
666+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_TX_RING22_CTRL2_ADDR (WF_WFDMA_HOST_DMA0_PCIE1_BASE + 0x468) // 8468
667+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_TX_RING22_CTRL3_ADDR (WF_WFDMA_HOST_DMA0_PCIE1_BASE + 0x46c) // 846C
668+
669+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_RX_RING3_CTRL0_ADDR (WF_WFDMA_HOST_DMA0_PCIE1_BASE + 0x530) // 8530
670+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_RX_RING3_CTRL1_ADDR (WF_WFDMA_HOST_DMA0_PCIE1_BASE + 0x534) // 8534
671+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_RX_RING3_CTRL2_ADDR (WF_WFDMA_HOST_DMA0_PCIE1_BASE + 0x538) // 8538
672+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_RX_RING3_CTRL3_ADDR (WF_WFDMA_HOST_DMA0_PCIE1_BASE + 0x53C) // 853C
673+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_RX_RING5_CTRL0_ADDR (WF_WFDMA_HOST_DMA0_PCIE1_BASE + 0x550) // 8550
674+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_RX_RING5_CTRL1_ADDR (WF_WFDMA_HOST_DMA0_PCIE1_BASE + 0x554) // 8554
675+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_RX_RING5_CTRL2_ADDR (WF_WFDMA_HOST_DMA0_PCIE1_BASE + 0x558) // 8558
676+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_RX_RING5_CTRL3_ADDR (WF_WFDMA_HOST_DMA0_PCIE1_BASE + 0x55c) // 855C
677+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_RX_RING6_CTRL0_ADDR (WF_WFDMA_HOST_DMA0_PCIE1_BASE + 0x560) // 8560
678+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_RX_RING6_CTRL1_ADDR (WF_WFDMA_HOST_DMA0_PCIE1_BASE + 0x564) // 8564
679+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_RX_RING6_CTRL2_ADDR (WF_WFDMA_HOST_DMA0_PCIE1_BASE + 0x568) // 8568
680+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_RX_RING6_CTRL3_ADDR (WF_WFDMA_HOST_DMA0_PCIE1_BASE + 0x56c) // 856C
681+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_RX_RING7_CTRL0_ADDR (WF_WFDMA_HOST_DMA0_PCIE1_BASE + 0x570) // 8570
682+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_RX_RING7_CTRL1_ADDR (WF_WFDMA_HOST_DMA0_PCIE1_BASE + 0x574) // 8574
683+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_RX_RING7_CTRL2_ADDR (WF_WFDMA_HOST_DMA0_PCIE1_BASE + 0x578) // 8578
684+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_RX_RING7_CTRL3_ADDR (WF_WFDMA_HOST_DMA0_PCIE1_BASE + 0x57c) // 857C
685+//MCU DMA
686+//#define WF_WFDMA_MCU_DMA0_BASE 0x02000
687+#define WF_WFDMA_MCU_DMA0_BASE 0x54000000
688+
689+#define WF_WFDMA_MCU_DMA0_HOST_INT_STA_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x200) // 0200
690+#define WF_WFDMA_MCU_DMA0_HOST_INT_ENA_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0X204) // 0204
691+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x208) // 0208
692+
693+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_BUSY_ADDR WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_ADDR
694+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK 0x00000008 // RX_DMA_BUSY[3]
695+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT 3
696+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_EN_ADDR WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_ADDR
697+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_EN_MASK 0x00000004 // RX_DMA_EN[2]
698+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_EN_SHFT 2
699+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_BUSY_ADDR WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_ADDR
700+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK 0x00000002 // TX_DMA_BUSY[1]
701+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT 1
702+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_EN_ADDR WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_ADDR
703+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_EN_MASK 0x00000001 // TX_DMA_EN[0]
704+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_EN_SHFT 0
705+
706+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING0_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x300) // 0300
707+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING0_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x304) // 0304
708+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING0_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x308) // 0308
709+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING0_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x30c) // 030C
710+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING1_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x310) // 0310
711+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING1_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x314) // 0314
712+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING1_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x318) // 0318
713+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING1_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x31c) // 031C
714+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING2_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x320) // 0320
715+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING2_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x324) // 0324
716+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING2_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x328) // 0328
717+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING2_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x32c) // 032C
718+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING3_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x330) // 0330
719+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING3_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x334) // 0334
720+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING3_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x338) // 0338
721+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING3_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x33c) // 033C
722+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING4_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x340) // 0340
723+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING4_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x344) // 0344
724+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING4_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x348) // 0348
725+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING4_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x34c) // 034C
726+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING5_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x350) // 0350
727+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING5_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x354) // 0354
728+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING5_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x358) // 0358
729+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING5_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x35c) // 035C
730+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING6_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x360) // 0360
731+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING6_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x364) // 0364
732+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING6_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x368) // 0368
733+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING6_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x36c) // 036C
734+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING7_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x370) // 0370
735+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING7_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x374) // 0374
736+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING7_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x378) // 0378
737+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING7_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x37c) // 037C
738+
739+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING0_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x500) // 0500
740+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING0_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x504) // 0504
741+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING0_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x508) // 0508
742+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING0_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x50c) // 050C
743+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING1_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x510) // 0510
744+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING1_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x514) // 0514
745+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING1_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x518) // 0518
746+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING1_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x51c) // 051C
747+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING2_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x520) // 0520
748+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING2_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x524) // 0524
749+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING2_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x528) // 0528
750+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING2_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x52C) // 052C
751+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING3_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x530) // 0530
752+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING3_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x534) // 0534
753+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING3_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x538) // 0538
754+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING3_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x53C) // 053C
755+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING4_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x540) // 0540
756+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING4_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x544) // 0544
757+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING4_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x548) // 0548
758+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING4_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x54C) // 054C
759+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING5_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x550) // 0550
760+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING5_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x554) // 0554
761+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING5_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x558) // 0558
762+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING5_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x55C) // 055C
763+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING6_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x560) // 0560
764+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING6_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x564) // 0564
765+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING6_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x568) // 0568
766+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING6_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x56c) // 056C
767+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING7_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x570) // 0570
768+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING7_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x574) // 0574
769+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING7_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x578) // 0578
770+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING7_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x57c) // 057C
771+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING8_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x580) // 0580
772+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING8_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x584) // 0584
773+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING8_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x588) // 0588
774+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING8_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x58c) // 058C
775+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING9_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x590) // 0590
776+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING9_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x594) // 0594
777+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING9_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x598) // 0598
778+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING9_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x59c) // 059C
779+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING10_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x5A0) // 05A0
780+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING10_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x5A4) // 05A4
781+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING10_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x5A8) // 05A8
782+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING10_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x5Ac) // 05AC
783+
784+// MEM DMA
785+#define WF_WFDMA_MEM_DMA_BASE 0x58000000
786+
787+#define WF_WFDMA_MEM_DMA_HOST_INT_STA_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x200) // 0200
788+#define WF_WFDMA_MEM_DMA_HOST_INT_ENA_ADDR (WF_WFDMA_MEM_DMA_BASE + 0X204) // 0204
789+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x208) // 0208
790+
791+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_BUSY_ADDR WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_ADDR
792+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK 0x00000008 // RX_DMA_BUSY[3]
793+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT 3
794+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_EN_ADDR WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_ADDR
795+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_EN_MASK 0x00000004 // RX_DMA_EN[2]
796+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_EN_SHFT 2
797+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_BUSY_ADDR WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_ADDR
798+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK 0x00000002 // TX_DMA_BUSY[1]
799+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT 1
800+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_EN_ADDR WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_ADDR
801+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_EN_MASK 0x00000001 // TX_DMA_EN[0]
802+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_EN_SHFT 0
803+
804+#define WF_WFDMA_MEM_DMA_WPDMA_TX_RING0_CTRL0_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x300) // 0300
805+#define WF_WFDMA_MEM_DMA_WPDMA_TX_RING0_CTRL1_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x304) // 0304
806+#define WF_WFDMA_MEM_DMA_WPDMA_TX_RING0_CTRL2_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x308) // 0308
807+#define WF_WFDMA_MEM_DMA_WPDMA_TX_RING0_CTRL3_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x30c) // 030C
808+#define WF_WFDMA_MEM_DMA_WPDMA_TX_RING1_CTRL0_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x310) // 0310
809+#define WF_WFDMA_MEM_DMA_WPDMA_TX_RING1_CTRL1_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x314) // 0314
810+#define WF_WFDMA_MEM_DMA_WPDMA_TX_RING1_CTRL2_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x318) // 0318
811+#define WF_WFDMA_MEM_DMA_WPDMA_TX_RING1_CTRL3_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x31c) // 031C
812+#define WF_WFDMA_MEM_DMA_WPDMA_TX_RING2_CTRL0_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x320) // 0320
813+#define WF_WFDMA_MEM_DMA_WPDMA_TX_RING2_CTRL1_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x324) // 0324
814+#define WF_WFDMA_MEM_DMA_WPDMA_TX_RING2_CTRL2_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x328) // 0328
815+#define WF_WFDMA_MEM_DMA_WPDMA_TX_RING2_CTRL3_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x32c) // 032C
816+
817+#define WF_WFDMA_MEM_DMA_WPDMA_RX_RING0_CTRL0_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x500) // 0500
818+#define WF_WFDMA_MEM_DMA_WPDMA_RX_RING0_CTRL1_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x504) // 0504
819+#define WF_WFDMA_MEM_DMA_WPDMA_RX_RING0_CTRL2_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x508) // 0508
820+#define WF_WFDMA_MEM_DMA_WPDMA_RX_RING0_CTRL3_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x50c) // 050C
821+#define WF_WFDMA_MEM_DMA_WPDMA_RX_RING1_CTRL0_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x510) // 0510
822+#define WF_WFDMA_MEM_DMA_WPDMA_RX_RING1_CTRL1_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x514) // 0514
823+#define WF_WFDMA_MEM_DMA_WPDMA_RX_RING1_CTRL2_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x518) // 0518
824+#define WF_WFDMA_MEM_DMA_WPDMA_RX_RING1_CTRL3_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x51c) // 051C
825+#define WF_WFDMA_MEM_DMA_WPDMA_RX_RING2_CTRL0_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x520) // 0520
826+#define WF_WFDMA_MEM_DMA_WPDMA_RX_RING2_CTRL1_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x524) // 0524
827+#define WF_WFDMA_MEM_DMA_WPDMA_RX_RING2_CTRL2_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x528) // 0528
828+#define WF_WFDMA_MEM_DMA_WPDMA_RX_RING2_CTRL3_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x52C) // 052C
829+
830+/* MIB */
831+#define WF_UMIB_TOP_BASE 0x820cd000
832+#define BN0_WF_MIB_TOP_BASE 0x820ed000
833+#define BN1_WF_MIB_TOP_BASE 0x820fd000
834+#define IP1_BN0_WF_MIB_TOP_BASE 0x830ed000
835+
836+#define WF_UMIB_TOP_B0BROCR_ADDR (WF_UMIB_TOP_BASE + 0x484) // D484
837+#define WF_UMIB_TOP_B0BRBCR_ADDR (WF_UMIB_TOP_BASE + 0x4D4) // D4D4
838+#define WF_UMIB_TOP_B0BRDCR_ADDR (WF_UMIB_TOP_BASE + 0x524) // D524
839+#define WF_UMIB_TOP_B1BROCR_ADDR (WF_UMIB_TOP_BASE + 0x5E8) // D5E8
840+#define WF_UMIB_TOP_B2BROCR_ADDR (WF_UMIB_TOP_BASE + 0x74C) // D74C
841+
842+#define BN0_WF_MIB_TOP_M0SCR0_ADDR (BN0_WF_MIB_TOP_BASE + 0x000) // D000
843+#define BN0_WF_MIB_TOP_M0SDR6_ADDR (BN0_WF_MIB_TOP_BASE + 0x020) // D020
844+#define BN0_WF_MIB_TOP_M0SDR9_ADDR (BN0_WF_MIB_TOP_BASE + 0x024) // D024
845+#define BN0_WF_MIB_TOP_M0SDR18_ADDR (BN0_WF_MIB_TOP_BASE + 0x030) // D030
846+#define BN0_WF_MIB_TOP_BTOCR_ADDR (BN0_WF_MIB_TOP_BASE + 0x400) // D400
847+#define BN0_WF_MIB_TOP_BTBCR_ADDR (BN0_WF_MIB_TOP_BASE + 0x450) // D450
848+#define BN0_WF_MIB_TOP_BTDCR_ADDR (BN0_WF_MIB_TOP_BASE + 0x590) // D590
849+#define BN0_WF_MIB_TOP_BTCR_ADDR (BN0_WF_MIB_TOP_BASE + 0x5A0) // D5A0
850+#define BN0_WF_MIB_TOP_RVSR0_ADDR (BN0_WF_MIB_TOP_BASE + 0x720) // D720
851+
852+#define BN0_WF_MIB_TOP_TSCR0_ADDR (BN0_WF_MIB_TOP_BASE + 0x6B0) // D6B0
853+#define BN0_WF_MIB_TOP_TSCR3_ADDR (BN0_WF_MIB_TOP_BASE + 0x6BC) // D6BC
854+#define BN0_WF_MIB_TOP_TSCR4_ADDR (BN0_WF_MIB_TOP_BASE + 0x6C0) // D6C0
855+#define BN0_WF_MIB_TOP_TSCR5_ADDR (BN0_WF_MIB_TOP_BASE + 0x6C4) // D6C4
856+#define BN0_WF_MIB_TOP_TSCR6_ADDR (BN0_WF_MIB_TOP_BASE + 0x6C8) // D6C8
857+#define BN0_WF_MIB_TOP_TSCR7_ADDR (BN0_WF_MIB_TOP_BASE + 0x6D0) // D6D0
858+#define BN0_WF_MIB_TOP_TSCR8_ADDR (BN0_WF_MIB_TOP_BASE + 0x6CC) // D6CC
859+
860+#define BN0_WF_MIB_TOP_TBCR0_ADDR (BN0_WF_MIB_TOP_BASE + 0x6EC) // D6EC
861+#define BN0_WF_MIB_TOP_TBCR1_ADDR (BN0_WF_MIB_TOP_BASE + 0x6F0) // D6F0
862+#define BN0_WF_MIB_TOP_TBCR2_ADDR (BN0_WF_MIB_TOP_BASE + 0x6F4) // D6F4
863+#define BN0_WF_MIB_TOP_TBCR3_ADDR (BN0_WF_MIB_TOP_BASE + 0x6F8) // D6F8
864+#define BN0_WF_MIB_TOP_TBCR4_ADDR (BN0_WF_MIB_TOP_BASE + 0x6FC) // D6FC
865+
866+#define BN0_WF_MIB_TOP_TDRCR0_ADDR (BN0_WF_MIB_TOP_BASE + 0x728) // D728
867+#define BN0_WF_MIB_TOP_TDRCR1_ADDR (BN0_WF_MIB_TOP_BASE + 0x72C) // D72C
868+#define BN0_WF_MIB_TOP_TDRCR2_ADDR (BN0_WF_MIB_TOP_BASE + 0x730) // D730
869+#define BN0_WF_MIB_TOP_TDRCR3_ADDR (BN0_WF_MIB_TOP_BASE + 0x734) // D734
870+#define BN0_WF_MIB_TOP_TDRCR4_ADDR (BN0_WF_MIB_TOP_BASE + 0x738) // D738
871+
872+#define BN0_WF_MIB_TOP_BTSCR0_ADDR (BN0_WF_MIB_TOP_BASE + 0x5E0) // D5E0
873+#define BN0_WF_MIB_TOP_BTSCR1_ADDR (BN0_WF_MIB_TOP_BASE + 0x5F0) // D5F0
874+#define BN0_WF_MIB_TOP_BTSCR2_ADDR (BN0_WF_MIB_TOP_BASE + 0x600) // D600
875+#define BN0_WF_MIB_TOP_BTSCR3_ADDR (BN0_WF_MIB_TOP_BASE + 0x610) // D610
876+#define BN0_WF_MIB_TOP_BTSCR4_ADDR (BN0_WF_MIB_TOP_BASE + 0x620) // D620
877+#define BN0_WF_MIB_TOP_BTSCR5_ADDR (BN0_WF_MIB_TOP_BASE + 0x788) // D788
878+#define BN0_WF_MIB_TOP_BTSCR6_ADDR (BN0_WF_MIB_TOP_BASE + 0x798) // D798
879+
880+#define BN0_WF_MIB_TOP_RSCR1_ADDR (BN0_WF_MIB_TOP_BASE + 0x7AC) // D7AC
881+#define BN0_WF_MIB_TOP_BSCR2_ADDR (BN0_WF_MIB_TOP_BASE + 0x9D4) // D9D4
882+#define BN0_WF_MIB_TOP_TSCR18_ADDR (BN0_WF_MIB_TOP_BASE + 0xA1C) // DA1C
883+
884+#define BN0_WF_MIB_TOP_MSR0_ADDR (BN0_WF_MIB_TOP_BASE + 0xA64) // DA64
885+#define BN0_WF_MIB_TOP_MSR1_ADDR (BN0_WF_MIB_TOP_BASE + 0xA68) // DA68
886+#define BN0_WF_MIB_TOP_MSR2_ADDR (BN0_WF_MIB_TOP_BASE + 0xA6C) // DA6C
887+#define BN0_WF_MIB_TOP_MCTR5_ADDR (BN0_WF_MIB_TOP_BASE + 0xA70) // DA70
888+#define BN0_WF_MIB_TOP_MCTR6_ADDR (BN0_WF_MIB_TOP_BASE + 0xA74) // DA74
889+
890+#define BN0_WF_MIB_TOP_RSCR26_ADDR (BN0_WF_MIB_TOP_BASE + 0x950) // D950
891+#define BN0_WF_MIB_TOP_RSCR27_ADDR (BN0_WF_MIB_TOP_BASE + 0x954) // D954
892+#define BN0_WF_MIB_TOP_RSCR28_ADDR (BN0_WF_MIB_TOP_BASE + 0x958) // D958
893+#define BN0_WF_MIB_TOP_RSCR31_ADDR (BN0_WF_MIB_TOP_BASE + 0x964) // D964
894+#define BN0_WF_MIB_TOP_RSCR33_ADDR (BN0_WF_MIB_TOP_BASE + 0x96C) // D96C
895+#define BN0_WF_MIB_TOP_RSCR35_ADDR (BN0_WF_MIB_TOP_BASE + 0x974) // D974
896+#define BN0_WF_MIB_TOP_RSCR36_ADDR (BN0_WF_MIB_TOP_BASE + 0x978) // D978
897+
898+#define BN0_WF_MIB_TOP_TSCR3_AMPDU_MPDU_COUNT_MASK 0xFFFFFFFF // AMPDU_MPDU_COUNT[31..0]
899+#define BN0_WF_MIB_TOP_TSCR4_AMPDU_ACKED_COUNT_MASK 0xFFFFFFFF // AMPDU_ACKED_COUNT[31..0]
900+#define BN0_WF_MIB_TOP_M0SDR6_CHANNEL_IDLE_COUNT_MASK 0x0000FFFF // CHANNEL_IDLE_COUNT[15..0]
901+#define BN0_WF_MIB_TOP_M0SDR9_CCA_NAV_TX_TIME_MASK 0x00FFFFFF // CCA_NAV_TX_TIME[23..0]
902+#define BN0_WF_MIB_TOP_RSCR26_RX_MDRDY_COUNT_MASK 0xFFFFFFFF // RX_MDRDY_COUNT[31..0]
903+#define BN0_WF_MIB_TOP_MSR0_CCK_MDRDY_TIME_MASK 0xFFFFFFFF // CCK_MDRDY_TIME[31..0]
904+#define BN0_WF_MIB_TOP_MSR1_OFDM_LG_MIXED_VHT_MDRDY_TIME_MASK 0xFFFFFFFF // OFDM_LG_MIXED_VHT_MDRDY_TIME[31..0]
905+#define BN0_WF_MIB_TOP_MSR2_OFDM_GREEN_MDRDY_TIME_MASK 0xFFFFFFFF // OFDM_GREEN_MDRDY_TIME[31..0]
906+#define BN0_WF_MIB_TOP_MCTR5_P_CCA_TIME_MASK 0xFFFFFFFF // P_CCA_TIME[31..0]
907+#define BN0_WF_MIB_TOP_MCTR6_S_CCA_TIME_MASK 0xFFFFFFFF // S_CCA_TIME[31..0]
908+#define BN0_WF_MIB_TOP_M0SDR18_P_ED_TIME_MASK 0x00FFFFFF // P_ED_TIME[23..0]
909+#define BN0_WF_MIB_TOP_TSCR18_BEACONTXCOUNT_MASK 0xFFFFFFFF // BEACONTXCOUNT[31..0]
910+#define BN0_WF_MIB_TOP_TBCR0_TX_20MHZ_CNT_MASK 0xFFFFFFFF // TX_20MHZ_CNT[31..0]
911+#define BN0_WF_MIB_TOP_TBCR1_TX_40MHZ_CNT_MASK 0xFFFFFFFF // TX_40MHZ_CNT[31..0]
912+#define BN0_WF_MIB_TOP_TBCR2_TX_80MHZ_CNT_MASK 0xFFFFFFFF // TX_80MHZ_CNT[31..0]
913+#define BN0_WF_MIB_TOP_TBCR3_TX_160MHZ_CNT_MASK 0xFFFFFFFF // TX_160MHZ_CNT[31..0]
914+#define BN0_WF_MIB_TOP_TBCR4_TX_320MHZ_CNT_MASK 0xFFFFFFFF // TX_320MHZ_CNT[31..0]
915+#define BN0_WF_MIB_TOP_BSCR2_MUBF_TX_COUNT_MASK 0xFFFFFFFF // MUBF_TX_COUNT[31..0]
916+#define BN0_WF_MIB_TOP_RVSR0_VEC_MISS_COUNT_MASK 0xFFFFFFFF // VEC_MISS_COUNT[31..0]
917+#define BN0_WF_MIB_TOP_RSCR35_DELIMITER_FAIL_COUNT_MASK 0xFFFFFFFF // DELIMITER_FAIL_COUNT[31..0]
918+#define BN0_WF_MIB_TOP_RSCR1_RX_FCS_ERROR_COUNT_MASK 0xFFFFFFFF // RX_FCS_ERROR_COUNT[31..0]
919+#define BN0_WF_MIB_TOP_RSCR33_RX_FIFO_FULL_COUNT_MASK 0xFFFFFFFF // RX_FIFO_FULL_COUNT[31..0]
920+#define BN0_WF_MIB_TOP_RSCR36_RX_LEN_MISMATCH_MASK 0xFFFFFFFF // RX_LEN_MISMATCH[31..0]
921+#define BN0_WF_MIB_TOP_RSCR31_RX_MPDU_COUNT_MASK 0xFFFFFFFF // RX_MPDU_COUNT[31..0]
922+#define BN0_WF_MIB_TOP_BTSCR5_RTSTXCOUNTn_MASK 0xFFFFFFFF // RTSTXCOUNTn[31..0]
923+#define BN0_WF_MIB_TOP_BTSCR6_RTSRETRYCOUNTn_MASK 0xFFFFFFFF // RTSRETRYCOUNTn[31..0]
924+#define BN0_WF_MIB_TOP_BTSCR0_BAMISSCOUNTn_MASK 0xFFFFFFFF // BAMISSCOUNTn[31..0]
925+#define BN0_WF_MIB_TOP_BTSCR1_ACKFAILCOUNTn_MASK 0xFFFFFFFF // ACKFAILCOUNTn[31..0]
926+#define BN0_WF_MIB_TOP_BTSCR2_FRAMERETRYCOUNTn_MASK 0xFFFFFFFF // FRAMERETRYCOUNTn[31..0]
927+#define BN0_WF_MIB_TOP_BTSCR3_FRAMERETRY2COUNTn_MASK 0xFFFFFFFF // FRAMERETRY2COUNTn[31..0]
928+#define BN0_WF_MIB_TOP_BTSCR4_FRAMERETRY3COUNTn_MASK 0xFFFFFFFF // FRAMERETRY3COUNTn[31..0]
929+#define BN0_WF_MIB_TOP_TRARC0_ADDR (BN0_WF_MIB_TOP_BASE + 0x0B0) // D0B0
930+#define BN0_WF_MIB_TOP_TRARC1_ADDR (BN0_WF_MIB_TOP_BASE + 0x0B4) // D0B4
931+#define BN0_WF_MIB_TOP_TRARC2_ADDR (BN0_WF_MIB_TOP_BASE + 0x0B8) // D0B8
932+#define BN0_WF_MIB_TOP_TRARC3_ADDR (BN0_WF_MIB_TOP_BASE + 0x0BC) // D0BC
933+#define BN0_WF_MIB_TOP_TRARC4_ADDR (BN0_WF_MIB_TOP_BASE + 0x0C0) // D0C0
934+#define BN0_WF_MIB_TOP_TRARC5_ADDR (BN0_WF_MIB_TOP_BASE + 0x0C4) // D0C4
935+#define BN0_WF_MIB_TOP_TRARC6_ADDR (BN0_WF_MIB_TOP_BASE + 0x0C8) // D0C8
936+#define BN0_WF_MIB_TOP_TRARC7_ADDR (BN0_WF_MIB_TOP_BASE + 0x0CC) // D0CC
937+
developerc2cfe0f2023-09-22 04:11:09 +0800[diff] [blame]938+#define BN0_WF_MIB_TOP_TRDR0_ADDR (BN0_WF_MIB_TOP_BASE + 0xA24) // DA24
939+#define BN0_WF_MIB_TOP_TRDR1_ADDR (BN0_WF_MIB_TOP_BASE + 0xA28) // DA28
940+#define BN0_WF_MIB_TOP_TRDR2_ADDR (BN0_WF_MIB_TOP_BASE + 0xA2C) // DA2C
941+#define BN0_WF_MIB_TOP_TRDR3_ADDR (BN0_WF_MIB_TOP_BASE + 0xA30) // DA30
942+#define BN0_WF_MIB_TOP_TRDR4_ADDR (BN0_WF_MIB_TOP_BASE + 0xA34) // DA34
943+#define BN0_WF_MIB_TOP_TRDR5_ADDR (BN0_WF_MIB_TOP_BASE + 0xA38) // DA38
944+#define BN0_WF_MIB_TOP_TRDR6_ADDR (BN0_WF_MIB_TOP_BASE + 0xA3C) // DA3C
945+#define BN0_WF_MIB_TOP_TRDR7_ADDR (BN0_WF_MIB_TOP_BASE + 0xA40) // DA40
946+#define BN0_WF_MIB_TOP_TRDR8_ADDR (BN0_WF_MIB_TOP_BASE + 0xA44) // DA44
947+#define BN0_WF_MIB_TOP_TRDR9_ADDR (BN0_WF_MIB_TOP_BASE + 0xA48) // DA48
948+#define BN0_WF_MIB_TOP_TRDR10_ADDR (BN0_WF_MIB_TOP_BASE + 0xA4C) // DA4C
949+#define BN0_WF_MIB_TOP_TRDR11_ADDR (BN0_WF_MIB_TOP_BASE + 0xA50) // DA50
950+#define BN0_WF_MIB_TOP_TRDR12_ADDR (BN0_WF_MIB_TOP_BASE + 0xA54) // DA54
951+#define BN0_WF_MIB_TOP_TRDR13_ADDR (BN0_WF_MIB_TOP_BASE + 0xA58) // DA58
952+#define BN0_WF_MIB_TOP_TRDR14_ADDR (BN0_WF_MIB_TOP_BASE + 0xA5C) // DA5C
953+#define BN0_WF_MIB_TOP_TRDR15_ADDR (BN0_WF_MIB_TOP_BASE + 0xA60) // DA60
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]954+
955+#define BN0_WF_MIB_TOP_TRARC0_AGG_RANG_SEL_1_ADDR BN0_WF_MIB_TOP_TRARC0_ADDR
956+#define BN0_WF_MIB_TOP_TRARC0_AGG_RANG_SEL_1_MASK 0x03FF0000 // AGG_RANG_SEL_1[25..16]
957+#define BN0_WF_MIB_TOP_TRARC0_AGG_RANG_SEL_1_SHFT 16
958+#define BN0_WF_MIB_TOP_TRARC0_AGG_RANG_SEL_0_ADDR BN0_WF_MIB_TOP_TRARC0_ADDR
959+#define BN0_WF_MIB_TOP_TRARC0_AGG_RANG_SEL_0_MASK 0x000003FF // AGG_RANG_SEL_0[9..0]
960+#define BN0_WF_MIB_TOP_TRARC0_AGG_RANG_SEL_0_SHFT 0
961+
962+#define BN0_WF_MIB_TOP_TRARC1_AGG_RANG_SEL_3_ADDR BN0_WF_MIB_TOP_TRARC1_ADDR
963+#define BN0_WF_MIB_TOP_TRARC1_AGG_RANG_SEL_3_MASK 0x03FF0000 // AGG_RANG_SEL_3[25..16]
964+#define BN0_WF_MIB_TOP_TRARC1_AGG_RANG_SEL_3_SHFT 16
965+#define BN0_WF_MIB_TOP_TRARC1_AGG_RANG_SEL_2_ADDR BN0_WF_MIB_TOP_TRARC1_ADDR
966+#define BN0_WF_MIB_TOP_TRARC1_AGG_RANG_SEL_2_MASK 0x000003FF // AGG_RANG_SEL_2[9..0]
967+#define BN0_WF_MIB_TOP_TRARC1_AGG_RANG_SEL_2_SHFT 0
968+
969+#define BN0_WF_MIB_TOP_TRARC2_AGG_RANG_SEL_5_ADDR BN0_WF_MIB_TOP_TRARC2_ADDR
970+#define BN0_WF_MIB_TOP_TRARC2_AGG_RANG_SEL_5_MASK 0x03FF0000 // AGG_RANG_SEL_5[25..16]
971+#define BN0_WF_MIB_TOP_TRARC2_AGG_RANG_SEL_5_SHFT 16
972+#define BN0_WF_MIB_TOP_TRARC2_AGG_RANG_SEL_4_ADDR BN0_WF_MIB_TOP_TRARC2_ADDR
973+#define BN0_WF_MIB_TOP_TRARC2_AGG_RANG_SEL_4_MASK 0x000003FF // AGG_RANG_SEL_4[9..0]
974+#define BN0_WF_MIB_TOP_TRARC2_AGG_RANG_SEL_4_SHFT 0
975+
976+#define BN0_WF_MIB_TOP_TRARC3_AGG_RANG_SEL_7_ADDR BN0_WF_MIB_TOP_TRARC3_ADDR
977+#define BN0_WF_MIB_TOP_TRARC3_AGG_RANG_SEL_7_MASK 0x03FF0000 // AGG_RANG_SEL_7[25..16]
978+#define BN0_WF_MIB_TOP_TRARC3_AGG_RANG_SEL_7_SHFT 16
979+#define BN0_WF_MIB_TOP_TRARC3_AGG_RANG_SEL_6_ADDR BN0_WF_MIB_TOP_TRARC3_ADDR
980+#define BN0_WF_MIB_TOP_TRARC3_AGG_RANG_SEL_6_MASK 0x000003FF // AGG_RANG_SEL_6[9..0]
981+#define BN0_WF_MIB_TOP_TRARC3_AGG_RANG_SEL_6_SHFT 0
982+
983+#define BN0_WF_MIB_TOP_TRARC4_AGG_RANG_SEL_9_ADDR BN0_WF_MIB_TOP_TRARC4_ADDR
984+#define BN0_WF_MIB_TOP_TRARC4_AGG_RANG_SEL_9_MASK 0x03FF0000 // AGG_RANG_SEL_9[25..16]
985+#define BN0_WF_MIB_TOP_TRARC4_AGG_RANG_SEL_9_SHFT 16
986+#define BN0_WF_MIB_TOP_TRARC4_AGG_RANG_SEL_8_ADDR BN0_WF_MIB_TOP_TRARC4_ADDR
987+#define BN0_WF_MIB_TOP_TRARC4_AGG_RANG_SEL_8_MASK 0x000003FF // AGG_RANG_SEL_8[9..0]
988+#define BN0_WF_MIB_TOP_TRARC4_AGG_RANG_SEL_8_SHFT 0
989+
990+#define BN0_WF_MIB_TOP_TRARC5_AGG_RANG_SEL_11_ADDR BN0_WF_MIB_TOP_TRARC5_ADDR
991+#define BN0_WF_MIB_TOP_TRARC5_AGG_RANG_SEL_11_MASK 0x03FF0000 // AGG_RANG_SEL_11[25..16]
992+#define BN0_WF_MIB_TOP_TRARC5_AGG_RANG_SEL_11_SHFT 16
993+#define BN0_WF_MIB_TOP_TRARC5_AGG_RANG_SEL_10_ADDR BN0_WF_MIB_TOP_TRARC5_ADDR
994+#define BN0_WF_MIB_TOP_TRARC5_AGG_RANG_SEL_10_MASK 0x000003FF // AGG_RANG_SEL_10[9..0]
995+#define BN0_WF_MIB_TOP_TRARC5_AGG_RANG_SEL_10_SHFT 0
996+
997+#define BN0_WF_MIB_TOP_TRARC6_AGG_RANG_SEL_13_ADDR BN0_WF_MIB_TOP_TRARC6_ADDR
998+#define BN0_WF_MIB_TOP_TRARC6_AGG_RANG_SEL_13_MASK 0x03FF0000 // AGG_RANG_SEL_13[25..16]
999+#define BN0_WF_MIB_TOP_TRARC6_AGG_RANG_SEL_13_SHFT 16
1000+#define BN0_WF_MIB_TOP_TRARC6_AGG_RANG_SEL_12_ADDR BN0_WF_MIB_TOP_TRARC6_ADDR
1001+#define BN0_WF_MIB_TOP_TRARC6_AGG_RANG_SEL_12_MASK 0x000003FF // AGG_RANG_SEL_12[9..0]
1002+#define BN0_WF_MIB_TOP_TRARC6_AGG_RANG_SEL_12_SHFT 0
1003+
1004+#define BN0_WF_MIB_TOP_TRARC7_AGG_RANG_SEL_14_ADDR BN0_WF_MIB_TOP_TRARC7_ADDR
1005+#define BN0_WF_MIB_TOP_TRARC7_AGG_RANG_SEL_14_MASK 0x000003FF // AGG_RANG_SEL_14[9..0]
1006+#define BN0_WF_MIB_TOP_TRARC7_AGG_RANG_SEL_14_SHFT 0
1007+
1008+/* RRO TOP */
1009+#define WF_RRO_TOP_BASE 0xA000 /*0x820C2000 */
1010+#define WF_RRO_TOP_IND_CMD_0_CTRL0_ADDR (WF_RRO_TOP_BASE + 0x40) // 2040
1011+ //
1012+/* WTBL */
1013+enum mt7996_wtbl_type {
1014+ WTBL_TYPE_LMAC, /* WTBL in LMAC */
1015+ WTBL_TYPE_UMAC, /* WTBL in UMAC */
1016+ WTBL_TYPE_KEY, /* Key Table */
1017+ MAX_NUM_WTBL_TYPE
1018+};
1019+
1020+struct berse_wtbl_parse {
1021+ u8 *name;
1022+ u32 mask;
1023+ u32 shift;
1024+ u8 new_line;
1025+};
1026+
1027+enum muar_idx {
1028+ MUAR_INDEX_OWN_MAC_ADDR_0 = 0,
1029+ MUAR_INDEX_OWN_MAC_ADDR_1,
1030+ MUAR_INDEX_OWN_MAC_ADDR_2,
1031+ MUAR_INDEX_OWN_MAC_ADDR_3,
1032+ MUAR_INDEX_OWN_MAC_ADDR_4,
1033+ MUAR_INDEX_OWN_MAC_ADDR_BC_MC = 0xE,
1034+ MUAR_INDEX_UNMATCHED = 0xF,
1035+ MUAR_INDEX_OWN_MAC_ADDR_11 = 0x11,
1036+ MUAR_INDEX_OWN_MAC_ADDR_12,
1037+ MUAR_INDEX_OWN_MAC_ADDR_13,
1038+ MUAR_INDEX_OWN_MAC_ADDR_14,
1039+ MUAR_INDEX_OWN_MAC_ADDR_15,
1040+ MUAR_INDEX_OWN_MAC_ADDR_16,
1041+ MUAR_INDEX_OWN_MAC_ADDR_17,
1042+ MUAR_INDEX_OWN_MAC_ADDR_18,
1043+ MUAR_INDEX_OWN_MAC_ADDR_19,
1044+ MUAR_INDEX_OWN_MAC_ADDR_1A,
1045+ MUAR_INDEX_OWN_MAC_ADDR_1B,
1046+ MUAR_INDEX_OWN_MAC_ADDR_1C,
1047+ MUAR_INDEX_OWN_MAC_ADDR_1D,
1048+ MUAR_INDEX_OWN_MAC_ADDR_1E,
1049+ MUAR_INDEX_OWN_MAC_ADDR_1F,
1050+ MUAR_INDEX_OWN_MAC_ADDR_20,
1051+ MUAR_INDEX_OWN_MAC_ADDR_21,
1052+ MUAR_INDEX_OWN_MAC_ADDR_22,
1053+ MUAR_INDEX_OWN_MAC_ADDR_23,
1054+ MUAR_INDEX_OWN_MAC_ADDR_24,
1055+ MUAR_INDEX_OWN_MAC_ADDR_25,
1056+ MUAR_INDEX_OWN_MAC_ADDR_26,
1057+ MUAR_INDEX_OWN_MAC_ADDR_27,
1058+ MUAR_INDEX_OWN_MAC_ADDR_28,
1059+ MUAR_INDEX_OWN_MAC_ADDR_29,
1060+ MUAR_INDEX_OWN_MAC_ADDR_2A,
1061+ MUAR_INDEX_OWN_MAC_ADDR_2B,
1062+ MUAR_INDEX_OWN_MAC_ADDR_2C,
1063+ MUAR_INDEX_OWN_MAC_ADDR_2D,
1064+ MUAR_INDEX_OWN_MAC_ADDR_2E,
1065+ MUAR_INDEX_OWN_MAC_ADDR_2F
1066+};
1067+
1068+enum cipher_suit {
1069+ IGTK_CIPHER_SUIT_NONE = 0,
1070+ IGTK_CIPHER_SUIT_BIP,
1071+ IGTK_CIPHER_SUIT_BIP_256
1072+};
1073+
1074+#define LWTBL_LEN_IN_DW 36
1075+#define UWTBL_LEN_IN_DW 10
1076+
1077+#define MT_DBG_WTBL_BASE 0x820D8000
1078+
1079+#define MT_DBG_WTBLON_TOP_BASE 0x820d4000
1080+#define MT_DBG_WTBLON_TOP_WDUCR_ADDR (MT_DBG_WTBLON_TOP_BASE + 0x0370) // 4370
1081+#define MT_DBG_WTBLON_TOP_WDUCR_GROUP GENMASK(4, 0)
1082+
1083+#define MT_DBG_UWTBL_TOP_BASE 0x820c4000
1084+#define MT_DBG_UWTBL_TOP_WDUCR_ADDR (MT_DBG_UWTBL_TOP_BASE + 0x0104) // 4104
1085+#define MT_DBG_UWTBL_TOP_WDUCR_GROUP GENMASK(5, 0)
1086+#define MT_DBG_UWTBL_TOP_WDUCR_TARGET BIT(31)
1087+
1088+#define LWTBL_IDX2BASE_ID GENMASK(14, 8)
1089+#define LWTBL_IDX2BASE_DW GENMASK(7, 2)
1090+#define LWTBL_IDX2BASE(_id, _dw) (MT_DBG_WTBL_BASE | \
1091+ FIELD_PREP(LWTBL_IDX2BASE_ID, _id) | \
1092+ FIELD_PREP(LWTBL_IDX2BASE_DW, _dw))
1093+
1094+#define UWTBL_IDX2BASE_ID GENMASK(12, 6)
1095+#define UWTBL_IDX2BASE_DW GENMASK(5, 2)
1096+#define UWTBL_IDX2BASE(_id, _dw) (MT_DBG_UWTBL_TOP_BASE | 0x2000 | \
1097+ FIELD_PREP(UWTBL_IDX2BASE_ID, _id) | \
1098+ FIELD_PREP(UWTBL_IDX2BASE_DW, _dw))
1099+
1100+#define KEYTBL_IDX2BASE_KEY GENMASK(12, 6)
1101+#define KEYTBL_IDX2BASE_DW GENMASK(5, 2)
1102+#define KEYTBL_IDX2BASE(_key, _dw) (MT_DBG_UWTBL_TOP_BASE | 0x2000 | \
1103+ FIELD_PREP(KEYTBL_IDX2BASE_KEY, _key) | \
1104+ FIELD_PREP(KEYTBL_IDX2BASE_DW, _dw))
1105+
1106+// UMAC WTBL
1107+// DW0
1108+#define WF_UWTBL_PEER_MLD_ADDRESS_47_32__DW 0
1109+#define WF_UWTBL_PEER_MLD_ADDRESS_47_32__ADDR 0
1110+#define WF_UWTBL_PEER_MLD_ADDRESS_47_32__MASK 0x0000ffff // 15- 0
1111+#define WF_UWTBL_PEER_MLD_ADDRESS_47_32__SHIFT 0
1112+#define WF_UWTBL_OWN_MLD_ID_DW 0
1113+#define WF_UWTBL_OWN_MLD_ID_ADDR 0
1114+#define WF_UWTBL_OWN_MLD_ID_MASK 0x003f0000 // 21-16
1115+#define WF_UWTBL_OWN_MLD_ID_SHIFT 16
1116+// DW1
1117+#define WF_UWTBL_PEER_MLD_ADDRESS_31_0__DW 1
1118+#define WF_UWTBL_PEER_MLD_ADDRESS_31_0__ADDR 4
1119+#define WF_UWTBL_PEER_MLD_ADDRESS_31_0__MASK 0xffffffff // 31- 0
1120+#define WF_UWTBL_PEER_MLD_ADDRESS_31_0__SHIFT 0
1121+// DW2
1122+#define WF_UWTBL_PN_31_0__DW 2
1123+#define WF_UWTBL_PN_31_0__ADDR 8
1124+#define WF_UWTBL_PN_31_0__MASK 0xffffffff // 31- 0
1125+#define WF_UWTBL_PN_31_0__SHIFT 0
1126+// DW3
1127+#define WF_UWTBL_PN_47_32__DW 3
1128+#define WF_UWTBL_PN_47_32__ADDR 12
1129+#define WF_UWTBL_PN_47_32__MASK 0x0000ffff // 15- 0
1130+#define WF_UWTBL_PN_47_32__SHIFT 0
1131+#define WF_UWTBL_COM_SN_DW 3
1132+#define WF_UWTBL_COM_SN_ADDR 12
1133+#define WF_UWTBL_COM_SN_MASK 0x0fff0000 // 27-16
1134+#define WF_UWTBL_COM_SN_SHIFT 16
1135+// DW4
1136+#define WF_UWTBL_TID0_SN_DW 4
1137+#define WF_UWTBL_TID0_SN_ADDR 16
1138+#define WF_UWTBL_TID0_SN_MASK 0x00000fff // 11- 0
1139+#define WF_UWTBL_TID0_SN_SHIFT 0
1140+#define WF_UWTBL_RX_BIPN_31_0__DW 4
1141+#define WF_UWTBL_RX_BIPN_31_0__ADDR 16
1142+#define WF_UWTBL_RX_BIPN_31_0__MASK 0xffffffff // 31- 0
1143+#define WF_UWTBL_RX_BIPN_31_0__SHIFT 0
1144+#define WF_UWTBL_TID1_SN_DW 4
1145+#define WF_UWTBL_TID1_SN_ADDR 16
1146+#define WF_UWTBL_TID1_SN_MASK 0x00fff000 // 23-12
1147+#define WF_UWTBL_TID1_SN_SHIFT 12
1148+#define WF_UWTBL_TID2_SN_7_0__DW 4
1149+#define WF_UWTBL_TID2_SN_7_0__ADDR 16
1150+#define WF_UWTBL_TID2_SN_7_0__MASK 0xff000000 // 31-24
1151+#define WF_UWTBL_TID2_SN_7_0__SHIFT 24
1152+// DW5
1153+#define WF_UWTBL_TID2_SN_11_8__DW 5
1154+#define WF_UWTBL_TID2_SN_11_8__ADDR 20
1155+#define WF_UWTBL_TID2_SN_11_8__MASK 0x0000000f // 3- 0
1156+#define WF_UWTBL_TID2_SN_11_8__SHIFT 0
1157+#define WF_UWTBL_RX_BIPN_47_32__DW 5
1158+#define WF_UWTBL_RX_BIPN_47_32__ADDR 20
1159+#define WF_UWTBL_RX_BIPN_47_32__MASK 0x0000ffff // 15- 0
1160+#define WF_UWTBL_RX_BIPN_47_32__SHIFT 0
1161+#define WF_UWTBL_TID3_SN_DW 5
1162+#define WF_UWTBL_TID3_SN_ADDR 20
1163+#define WF_UWTBL_TID3_SN_MASK 0x0000fff0 // 15- 4
1164+#define WF_UWTBL_TID3_SN_SHIFT 4
1165+#define WF_UWTBL_TID4_SN_DW 5
1166+#define WF_UWTBL_TID4_SN_ADDR 20
1167+#define WF_UWTBL_TID4_SN_MASK 0x0fff0000 // 27-16
1168+#define WF_UWTBL_TID4_SN_SHIFT 16
1169+#define WF_UWTBL_TID5_SN_3_0__DW 5
1170+#define WF_UWTBL_TID5_SN_3_0__ADDR 20
1171+#define WF_UWTBL_TID5_SN_3_0__MASK 0xf0000000 // 31-28
1172+#define WF_UWTBL_TID5_SN_3_0__SHIFT 28
1173+// DW6
1174+#define WF_UWTBL_TID5_SN_11_4__DW 6
1175+#define WF_UWTBL_TID5_SN_11_4__ADDR 24
1176+#define WF_UWTBL_TID5_SN_11_4__MASK 0x000000ff // 7- 0
1177+#define WF_UWTBL_TID5_SN_11_4__SHIFT 0
1178+#define WF_UWTBL_KEY_LOC2_DW 6
1179+#define WF_UWTBL_KEY_LOC2_ADDR 24
1180+#define WF_UWTBL_KEY_LOC2_MASK 0x00001fff // 12- 0
1181+#define WF_UWTBL_KEY_LOC2_SHIFT 0
1182+#define WF_UWTBL_TID6_SN_DW 6
1183+#define WF_UWTBL_TID6_SN_ADDR 24
1184+#define WF_UWTBL_TID6_SN_MASK 0x000fff00 // 19- 8
1185+#define WF_UWTBL_TID6_SN_SHIFT 8
1186+#define WF_UWTBL_TID7_SN_DW 6
1187+#define WF_UWTBL_TID7_SN_ADDR 24
1188+#define WF_UWTBL_TID7_SN_MASK 0xfff00000 // 31-20
1189+#define WF_UWTBL_TID7_SN_SHIFT 20
1190+// DW7
1191+#define WF_UWTBL_KEY_LOC0_DW 7
1192+#define WF_UWTBL_KEY_LOC0_ADDR 28
1193+#define WF_UWTBL_KEY_LOC0_MASK 0x00001fff // 12- 0
1194+#define WF_UWTBL_KEY_LOC0_SHIFT 0
1195+#define WF_UWTBL_KEY_LOC1_DW 7
1196+#define WF_UWTBL_KEY_LOC1_ADDR 28
1197+#define WF_UWTBL_KEY_LOC1_MASK 0x1fff0000 // 28-16
1198+#define WF_UWTBL_KEY_LOC1_SHIFT 16
1199+// DW8
1200+#define WF_UWTBL_AMSDU_CFG_DW 8
1201+#define WF_UWTBL_AMSDU_CFG_ADDR 32
1202+#define WF_UWTBL_AMSDU_CFG_MASK 0x00000fff // 11- 0
1203+#define WF_UWTBL_AMSDU_CFG_SHIFT 0
developerc2cfe0f2023-09-22 04:11:09 +0800[diff] [blame]1204+#define WF_UWTBL_SEC_ADDR_MODE_DW 8
1205+#define WF_UWTBL_SEC_ADDR_MODE_ADDR 32
1206+#define WF_UWTBL_SEC_ADDR_MODE_MASK 0x00300000 // 21-20
1207+#define WF_UWTBL_SEC_ADDR_MODE_SHIFT 20
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]1208+#define WF_UWTBL_WMM_Q_DW 8
1209+#define WF_UWTBL_WMM_Q_ADDR 32
1210+#define WF_UWTBL_WMM_Q_MASK 0x06000000 // 26-25
1211+#define WF_UWTBL_WMM_Q_SHIFT 25
1212+#define WF_UWTBL_QOS_DW 8
1213+#define WF_UWTBL_QOS_ADDR 32
1214+#define WF_UWTBL_QOS_MASK 0x08000000 // 27-27
1215+#define WF_UWTBL_QOS_SHIFT 27
1216+#define WF_UWTBL_HT_DW 8
1217+#define WF_UWTBL_HT_ADDR 32
1218+#define WF_UWTBL_HT_MASK 0x10000000 // 28-28
1219+#define WF_UWTBL_HT_SHIFT 28
1220+#define WF_UWTBL_HDRT_MODE_DW 8
1221+#define WF_UWTBL_HDRT_MODE_ADDR 32
1222+#define WF_UWTBL_HDRT_MODE_MASK 0x20000000 // 29-29
1223+#define WF_UWTBL_HDRT_MODE_SHIFT 29
1224+// DW9
1225+#define WF_UWTBL_RELATED_IDX0_DW 9
1226+#define WF_UWTBL_RELATED_IDX0_ADDR 36
1227+#define WF_UWTBL_RELATED_IDX0_MASK 0x00000fff // 11- 0
1228+#define WF_UWTBL_RELATED_IDX0_SHIFT 0
1229+#define WF_UWTBL_RELATED_BAND0_DW 9
1230+#define WF_UWTBL_RELATED_BAND0_ADDR 36
1231+#define WF_UWTBL_RELATED_BAND0_MASK 0x00003000 // 13-12
1232+#define WF_UWTBL_RELATED_BAND0_SHIFT 12
1233+#define WF_UWTBL_PRIMARY_MLD_BAND_DW 9
1234+#define WF_UWTBL_PRIMARY_MLD_BAND_ADDR 36
1235+#define WF_UWTBL_PRIMARY_MLD_BAND_MASK 0x0000c000 // 15-14
1236+#define WF_UWTBL_PRIMARY_MLD_BAND_SHIFT 14
1237+#define WF_UWTBL_RELATED_IDX1_DW 9
1238+#define WF_UWTBL_RELATED_IDX1_ADDR 36
1239+#define WF_UWTBL_RELATED_IDX1_MASK 0x0fff0000 // 27-16
1240+#define WF_UWTBL_RELATED_IDX1_SHIFT 16
1241+#define WF_UWTBL_RELATED_BAND1_DW 9
1242+#define WF_UWTBL_RELATED_BAND1_ADDR 36
1243+#define WF_UWTBL_RELATED_BAND1_MASK 0x30000000 // 29-28
1244+#define WF_UWTBL_RELATED_BAND1_SHIFT 28
1245+#define WF_UWTBL_SECONDARY_MLD_BAND_DW 9
1246+#define WF_UWTBL_SECONDARY_MLD_BAND_ADDR 36
1247+#define WF_UWTBL_SECONDARY_MLD_BAND_MASK 0xc0000000 // 31-30
1248+#define WF_UWTBL_SECONDARY_MLD_BAND_SHIFT 30
1249+
1250+/* LMAC WTBL */
1251+// DW0
1252+#define WF_LWTBL_PEER_LINK_ADDRESS_47_32__DW 0
1253+#define WF_LWTBL_PEER_LINK_ADDRESS_47_32__ADDR 0
1254+#define WF_LWTBL_PEER_LINK_ADDRESS_47_32__MASK \
1255+ 0x0000ffff // 15- 0
1256+#define WF_LWTBL_PEER_LINK_ADDRESS_47_32__SHIFT 0
1257+#define WF_LWTBL_MUAR_DW 0
1258+#define WF_LWTBL_MUAR_ADDR 0
1259+#define WF_LWTBL_MUAR_MASK \
1260+ 0x003f0000 // 21-16
1261+#define WF_LWTBL_MUAR_SHIFT 16
1262+#define WF_LWTBL_RCA1_DW 0
1263+#define WF_LWTBL_RCA1_ADDR 0
1264+#define WF_LWTBL_RCA1_MASK \
1265+ 0x00400000 // 22-22
1266+#define WF_LWTBL_RCA1_SHIFT 22
1267+#define WF_LWTBL_KID_DW 0
1268+#define WF_LWTBL_KID_ADDR 0
1269+#define WF_LWTBL_KID_MASK \
1270+ 0x01800000 // 24-23
1271+#define WF_LWTBL_KID_SHIFT 23
1272+#define WF_LWTBL_RCID_DW 0
1273+#define WF_LWTBL_RCID_ADDR 0
1274+#define WF_LWTBL_RCID_MASK \
1275+ 0x02000000 // 25-25
1276+#define WF_LWTBL_RCID_SHIFT 25
1277+#define WF_LWTBL_BAND_DW 0
1278+#define WF_LWTBL_BAND_ADDR 0
1279+#define WF_LWTBL_BAND_MASK \
1280+ 0x0c000000 // 27-26
1281+#define WF_LWTBL_BAND_SHIFT 26
1282+#define WF_LWTBL_RV_DW 0
1283+#define WF_LWTBL_RV_ADDR 0
1284+#define WF_LWTBL_RV_MASK \
1285+ 0x10000000 // 28-28
1286+#define WF_LWTBL_RV_SHIFT 28
1287+#define WF_LWTBL_RCA2_DW 0
1288+#define WF_LWTBL_RCA2_ADDR 0
1289+#define WF_LWTBL_RCA2_MASK \
1290+ 0x20000000 // 29-29
1291+#define WF_LWTBL_RCA2_SHIFT 29
1292+#define WF_LWTBL_WPI_FLAG_DW 0
1293+#define WF_LWTBL_WPI_FLAG_ADDR 0
1294+#define WF_LWTBL_WPI_FLAG_MASK \
1295+ 0x40000000 // 30-30
1296+#define WF_LWTBL_WPI_FLAG_SHIFT 30
1297+// DW1
1298+#define WF_LWTBL_PEER_LINK_ADDRESS_31_0__DW 1
1299+#define WF_LWTBL_PEER_LINK_ADDRESS_31_0__ADDR 4
1300+#define WF_LWTBL_PEER_LINK_ADDRESS_31_0__MASK \
1301+ 0xffffffff // 31- 0
1302+#define WF_LWTBL_PEER_LINK_ADDRESS_31_0__SHIFT 0
1303+// DW2
1304+#define WF_LWTBL_AID_DW 2
1305+#define WF_LWTBL_AID_ADDR 8
1306+#define WF_LWTBL_AID_MASK \
1307+ 0x00000fff // 11- 0
1308+#define WF_LWTBL_AID_SHIFT 0
1309+#define WF_LWTBL_GID_SU_DW 2
1310+#define WF_LWTBL_GID_SU_ADDR 8
1311+#define WF_LWTBL_GID_SU_MASK \
1312+ 0x00001000 // 12-12
1313+#define WF_LWTBL_GID_SU_SHIFT 12
1314+#define WF_LWTBL_SPP_EN_DW 2
1315+#define WF_LWTBL_SPP_EN_ADDR 8
1316+#define WF_LWTBL_SPP_EN_MASK \
1317+ 0x00002000 // 13-13
1318+#define WF_LWTBL_SPP_EN_SHIFT 13
1319+#define WF_LWTBL_WPI_EVEN_DW 2
1320+#define WF_LWTBL_WPI_EVEN_ADDR 8
1321+#define WF_LWTBL_WPI_EVEN_MASK \
1322+ 0x00004000 // 14-14
1323+#define WF_LWTBL_WPI_EVEN_SHIFT 14
1324+#define WF_LWTBL_AAD_OM_DW 2
1325+#define WF_LWTBL_AAD_OM_ADDR 8
1326+#define WF_LWTBL_AAD_OM_MASK \
1327+ 0x00008000 // 15-15
1328+#define WF_LWTBL_AAD_OM_SHIFT 15
1329+#define WF_LWTBL_CIPHER_SUIT_PGTK_DW 2
1330+#define WF_LWTBL_CIPHER_SUIT_PGTK_ADDR 8
1331+#define WF_LWTBL_CIPHER_SUIT_PGTK_MASK \
1332+ 0x001f0000 // 20-16
1333+#define WF_LWTBL_CIPHER_SUIT_PGTK_SHIFT 16
1334+#define WF_LWTBL_FD_DW 2
1335+#define WF_LWTBL_FD_ADDR 8
1336+#define WF_LWTBL_FD_MASK \
1337+ 0x00200000 // 21-21
1338+#define WF_LWTBL_FD_SHIFT 21
1339+#define WF_LWTBL_TD_DW 2
1340+#define WF_LWTBL_TD_ADDR 8
1341+#define WF_LWTBL_TD_MASK \
1342+ 0x00400000 // 22-22
1343+#define WF_LWTBL_TD_SHIFT 22
1344+#define WF_LWTBL_SW_DW 2
1345+#define WF_LWTBL_SW_ADDR 8
1346+#define WF_LWTBL_SW_MASK \
1347+ 0x00800000 // 23-23
1348+#define WF_LWTBL_SW_SHIFT 23
1349+#define WF_LWTBL_UL_DW 2
1350+#define WF_LWTBL_UL_ADDR 8
1351+#define WF_LWTBL_UL_MASK \
1352+ 0x01000000 // 24-24
1353+#define WF_LWTBL_UL_SHIFT 24
1354+#define WF_LWTBL_TX_PS_DW 2
1355+#define WF_LWTBL_TX_PS_ADDR 8
1356+#define WF_LWTBL_TX_PS_MASK \
1357+ 0x02000000 // 25-25
1358+#define WF_LWTBL_TX_PS_SHIFT 25
1359+#define WF_LWTBL_QOS_DW 2
1360+#define WF_LWTBL_QOS_ADDR 8
1361+#define WF_LWTBL_QOS_MASK \
1362+ 0x04000000 // 26-26
1363+#define WF_LWTBL_QOS_SHIFT 26
1364+#define WF_LWTBL_HT_DW 2
1365+#define WF_LWTBL_HT_ADDR 8
1366+#define WF_LWTBL_HT_MASK \
1367+ 0x08000000 // 27-27
1368+#define WF_LWTBL_HT_SHIFT 27
1369+#define WF_LWTBL_VHT_DW 2
1370+#define WF_LWTBL_VHT_ADDR 8
1371+#define WF_LWTBL_VHT_MASK \
1372+ 0x10000000 // 28-28
1373+#define WF_LWTBL_VHT_SHIFT 28
1374+#define WF_LWTBL_HE_DW 2
1375+#define WF_LWTBL_HE_ADDR 8
1376+#define WF_LWTBL_HE_MASK \
1377+ 0x20000000 // 29-29
1378+#define WF_LWTBL_HE_SHIFT 29
1379+#define WF_LWTBL_EHT_DW 2
1380+#define WF_LWTBL_EHT_ADDR 8
1381+#define WF_LWTBL_EHT_MASK \
1382+ 0x40000000 // 30-30
1383+#define WF_LWTBL_EHT_SHIFT 30
1384+#define WF_LWTBL_MESH_DW 2
1385+#define WF_LWTBL_MESH_ADDR 8
1386+#define WF_LWTBL_MESH_MASK \
1387+ 0x80000000 // 31-31
1388+#define WF_LWTBL_MESH_SHIFT 31
1389+// DW3
1390+#define WF_LWTBL_WMM_Q_DW 3
1391+#define WF_LWTBL_WMM_Q_ADDR 12
1392+#define WF_LWTBL_WMM_Q_MASK \
1393+ 0x00000003 // 1- 0
1394+#define WF_LWTBL_WMM_Q_SHIFT 0
1395+#define WF_LWTBL_EHT_SIG_MCS_DW 3
1396+#define WF_LWTBL_EHT_SIG_MCS_ADDR 12
1397+#define WF_LWTBL_EHT_SIG_MCS_MASK \
1398+ 0x0000000c // 3- 2
1399+#define WF_LWTBL_EHT_SIG_MCS_SHIFT 2
1400+#define WF_LWTBL_HDRT_MODE_DW 3
1401+#define WF_LWTBL_HDRT_MODE_ADDR 12
1402+#define WF_LWTBL_HDRT_MODE_MASK \
1403+ 0x00000010 // 4- 4
1404+#define WF_LWTBL_HDRT_MODE_SHIFT 4
1405+#define WF_LWTBL_BEAM_CHG_DW 3
1406+#define WF_LWTBL_BEAM_CHG_ADDR 12
1407+#define WF_LWTBL_BEAM_CHG_MASK \
1408+ 0x00000020 // 5- 5
1409+#define WF_LWTBL_BEAM_CHG_SHIFT 5
1410+#define WF_LWTBL_EHT_LTF_SYM_NUM_OPT_DW 3
1411+#define WF_LWTBL_EHT_LTF_SYM_NUM_OPT_ADDR 12
1412+#define WF_LWTBL_EHT_LTF_SYM_NUM_OPT_MASK \
1413+ 0x000000c0 // 7- 6
1414+#define WF_LWTBL_EHT_LTF_SYM_NUM_OPT_SHIFT 6
1415+#define WF_LWTBL_PFMU_IDX_DW 3
1416+#define WF_LWTBL_PFMU_IDX_ADDR 12
1417+#define WF_LWTBL_PFMU_IDX_MASK \
1418+ 0x0000ff00 // 15- 8
1419+#define WF_LWTBL_PFMU_IDX_SHIFT 8
1420+#define WF_LWTBL_ULPF_IDX_DW 3
1421+#define WF_LWTBL_ULPF_IDX_ADDR 12
1422+#define WF_LWTBL_ULPF_IDX_MASK \
1423+ 0x00ff0000 // 23-16
1424+#define WF_LWTBL_ULPF_IDX_SHIFT 16
1425+#define WF_LWTBL_RIBF_DW 3
1426+#define WF_LWTBL_RIBF_ADDR 12
1427+#define WF_LWTBL_RIBF_MASK \
1428+ 0x01000000 // 24-24
1429+#define WF_LWTBL_RIBF_SHIFT 24
1430+#define WF_LWTBL_ULPF_DW 3
1431+#define WF_LWTBL_ULPF_ADDR 12
1432+#define WF_LWTBL_ULPF_MASK \
1433+ 0x02000000 // 25-25
1434+#define WF_LWTBL_ULPF_SHIFT 25
developerc2cfe0f2023-09-22 04:11:09 +0800[diff] [blame]1435+#define WF_LWTBL_BYPASS_TXSMM_DW 3
1436+#define WF_LWTBL_BYPASS_TXSMM_ADDR 12
1437+#define WF_LWTBL_BYPASS_TXSMM_MASK \
1438+ 0x04000000 // 26-26
1439+#define WF_LWTBL_BYPASS_TXSMM_SHIFT 26
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]1440+#define WF_LWTBL_TBF_HT_DW 3
1441+#define WF_LWTBL_TBF_HT_ADDR 12
1442+#define WF_LWTBL_TBF_HT_MASK \
1443+ 0x08000000 // 27-27
1444+#define WF_LWTBL_TBF_HT_SHIFT 27
1445+#define WF_LWTBL_TBF_VHT_DW 3
1446+#define WF_LWTBL_TBF_VHT_ADDR 12
1447+#define WF_LWTBL_TBF_VHT_MASK \
1448+ 0x10000000 // 28-28
1449+#define WF_LWTBL_TBF_VHT_SHIFT 28
1450+#define WF_LWTBL_TBF_HE_DW 3
1451+#define WF_LWTBL_TBF_HE_ADDR 12
1452+#define WF_LWTBL_TBF_HE_MASK \
1453+ 0x20000000 // 29-29
1454+#define WF_LWTBL_TBF_HE_SHIFT 29
1455+#define WF_LWTBL_TBF_EHT_DW 3
1456+#define WF_LWTBL_TBF_EHT_ADDR 12
1457+#define WF_LWTBL_TBF_EHT_MASK \
1458+ 0x40000000 // 30-30
1459+#define WF_LWTBL_TBF_EHT_SHIFT 30
1460+#define WF_LWTBL_IGN_FBK_DW 3
1461+#define WF_LWTBL_IGN_FBK_ADDR 12
1462+#define WF_LWTBL_IGN_FBK_MASK \
1463+ 0x80000000 // 31-31
1464+#define WF_LWTBL_IGN_FBK_SHIFT 31
1465+// DW4
developerc2cfe0f2023-09-22 04:11:09 +0800[diff] [blame]1466+#define WF_LWTBL_NEGOTIATED_WINSIZE0_DW 4
1467+#define WF_LWTBL_NEGOTIATED_WINSIZE0_ADDR 16
1468+#define WF_LWTBL_NEGOTIATED_WINSIZE0_MASK \
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]1469+ 0x00000007 // 2- 0
developerc2cfe0f2023-09-22 04:11:09 +0800[diff] [blame]1470+#define WF_LWTBL_NEGOTIATED_WINSIZE0_SHIFT 0
1471+#define WF_LWTBL_NEGOTIATED_WINSIZE1_DW 4
1472+#define WF_LWTBL_NEGOTIATED_WINSIZE1_ADDR 16
1473+#define WF_LWTBL_NEGOTIATED_WINSIZE1_MASK \
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]1474+ 0x00000038 // 5- 3
developerc2cfe0f2023-09-22 04:11:09 +0800[diff] [blame]1475+#define WF_LWTBL_NEGOTIATED_WINSIZE1_SHIFT 3
1476+#define WF_LWTBL_NEGOTIATED_WINSIZE2_DW 4
1477+#define WF_LWTBL_NEGOTIATED_WINSIZE2_ADDR 16
1478+#define WF_LWTBL_NEGOTIATED_WINSIZE2_MASK \
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]1479+ 0x000001c0 // 8- 6
developerc2cfe0f2023-09-22 04:11:09 +0800[diff] [blame]1480+#define WF_LWTBL_NEGOTIATED_WINSIZE2_SHIFT 6
1481+#define WF_LWTBL_NEGOTIATED_WINSIZE3_DW 4
1482+#define WF_LWTBL_NEGOTIATED_WINSIZE3_ADDR 16
1483+#define WF_LWTBL_NEGOTIATED_WINSIZE3_MASK \
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]1484+ 0x00000e00 // 11- 9
developerc2cfe0f2023-09-22 04:11:09 +0800[diff] [blame]1485+#define WF_LWTBL_NEGOTIATED_WINSIZE3_SHIFT 9
1486+#define WF_LWTBL_NEGOTIATED_WINSIZE4_DW 4
1487+#define WF_LWTBL_NEGOTIATED_WINSIZE4_ADDR 16
1488+#define WF_LWTBL_NEGOTIATED_WINSIZE4_MASK \
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]1489+ 0x00007000 // 14-12
developerc2cfe0f2023-09-22 04:11:09 +0800[diff] [blame]1490+#define WF_LWTBL_NEGOTIATED_WINSIZE4_SHIFT 12
1491+#define WF_LWTBL_NEGOTIATED_WINSIZE5_DW 4
1492+#define WF_LWTBL_NEGOTIATED_WINSIZE5_ADDR 16
1493+#define WF_LWTBL_NEGOTIATED_WINSIZE5_MASK \
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]1494+ 0x00038000 // 17-15
developerc2cfe0f2023-09-22 04:11:09 +0800[diff] [blame]1495+#define WF_LWTBL_NEGOTIATED_WINSIZE5_SHIFT 15
1496+#define WF_LWTBL_NEGOTIATED_WINSIZE6_DW 4
1497+#define WF_LWTBL_NEGOTIATED_WINSIZE6_ADDR 16
1498+#define WF_LWTBL_NEGOTIATED_WINSIZE6_MASK \
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]1499+ 0x001c0000 // 20-18
developerc2cfe0f2023-09-22 04:11:09 +0800[diff] [blame]1500+#define WF_LWTBL_NEGOTIATED_WINSIZE6_SHIFT 18
1501+#define WF_LWTBL_NEGOTIATED_WINSIZE7_DW 4
1502+#define WF_LWTBL_NEGOTIATED_WINSIZE7_ADDR 16
1503+#define WF_LWTBL_NEGOTIATED_WINSIZE7_MASK \
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]1504+ 0x00e00000 // 23-21
developerc2cfe0f2023-09-22 04:11:09 +0800[diff] [blame]1505+#define WF_LWTBL_NEGOTIATED_WINSIZE7_SHIFT 21
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]1506+#define WF_LWTBL_PE_DW 4
1507+#define WF_LWTBL_PE_ADDR 16
1508+#define WF_LWTBL_PE_MASK \
1509+ 0x03000000 // 25-24
1510+#define WF_LWTBL_PE_SHIFT 24
1511+#define WF_LWTBL_DIS_RHTR_DW 4
1512+#define WF_LWTBL_DIS_RHTR_ADDR 16
1513+#define WF_LWTBL_DIS_RHTR_MASK \
1514+ 0x04000000 // 26-26
1515+#define WF_LWTBL_DIS_RHTR_SHIFT 26
1516+#define WF_LWTBL_LDPC_HT_DW 4
1517+#define WF_LWTBL_LDPC_HT_ADDR 16
1518+#define WF_LWTBL_LDPC_HT_MASK \
1519+ 0x08000000 // 27-27
1520+#define WF_LWTBL_LDPC_HT_SHIFT 27
1521+#define WF_LWTBL_LDPC_VHT_DW 4
1522+#define WF_LWTBL_LDPC_VHT_ADDR 16
1523+#define WF_LWTBL_LDPC_VHT_MASK \
1524+ 0x10000000 // 28-28
1525+#define WF_LWTBL_LDPC_VHT_SHIFT 28
1526+#define WF_LWTBL_LDPC_HE_DW 4
1527+#define WF_LWTBL_LDPC_HE_ADDR 16
1528+#define WF_LWTBL_LDPC_HE_MASK \
1529+ 0x20000000 // 29-29
1530+#define WF_LWTBL_LDPC_HE_SHIFT 29
1531+#define WF_LWTBL_LDPC_EHT_DW 4
1532+#define WF_LWTBL_LDPC_EHT_ADDR 16
1533+#define WF_LWTBL_LDPC_EHT_MASK \
1534+ 0x40000000 // 30-30
1535+#define WF_LWTBL_LDPC_EHT_SHIFT 30
developerc2cfe0f2023-09-22 04:11:09 +0800[diff] [blame]1536+#define WF_LWTBL_BA_MODE_DW 4
1537+#define WF_LWTBL_BA_MODE_ADDR 16
1538+#define WF_LWTBL_BA_MODE_MASK \
1539+ 0x80000000 // 31-31
1540+#define WF_LWTBL_BA_MODE_SHIFT 31
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]1541+// DW5
1542+#define WF_LWTBL_AF_DW 5
1543+#define WF_LWTBL_AF_ADDR 20
1544+#define WF_LWTBL_AF_MASK \
1545+ 0x00000007 // 2- 0
1546+#define WF_LWTBL_AF_SHIFT 0
1547+#define WF_LWTBL_AF_HE_DW 5
1548+#define WF_LWTBL_AF_HE_ADDR 20
1549+#define WF_LWTBL_AF_HE_MASK \
1550+ 0x00000018 // 4- 3
1551+#define WF_LWTBL_AF_HE_SHIFT 3
1552+#define WF_LWTBL_RTS_DW 5
1553+#define WF_LWTBL_RTS_ADDR 20
1554+#define WF_LWTBL_RTS_MASK \
1555+ 0x00000020 // 5- 5
1556+#define WF_LWTBL_RTS_SHIFT 5
1557+#define WF_LWTBL_SMPS_DW 5
1558+#define WF_LWTBL_SMPS_ADDR 20
1559+#define WF_LWTBL_SMPS_MASK \
1560+ 0x00000040 // 6- 6
1561+#define WF_LWTBL_SMPS_SHIFT 6
1562+#define WF_LWTBL_DYN_BW_DW 5
1563+#define WF_LWTBL_DYN_BW_ADDR 20
1564+#define WF_LWTBL_DYN_BW_MASK \
1565+ 0x00000080 // 7- 7
1566+#define WF_LWTBL_DYN_BW_SHIFT 7
1567+#define WF_LWTBL_MMSS_DW 5
1568+#define WF_LWTBL_MMSS_ADDR 20
1569+#define WF_LWTBL_MMSS_MASK \
1570+ 0x00000700 // 10- 8
1571+#define WF_LWTBL_MMSS_SHIFT 8
1572+#define WF_LWTBL_USR_DW 5
1573+#define WF_LWTBL_USR_ADDR 20
1574+#define WF_LWTBL_USR_MASK \
1575+ 0x00000800 // 11-11
1576+#define WF_LWTBL_USR_SHIFT 11
1577+#define WF_LWTBL_SR_R_DW 5
1578+#define WF_LWTBL_SR_R_ADDR 20
1579+#define WF_LWTBL_SR_R_MASK \
1580+ 0x00007000 // 14-12
1581+#define WF_LWTBL_SR_R_SHIFT 12
1582+#define WF_LWTBL_SR_ABORT_DW 5
1583+#define WF_LWTBL_SR_ABORT_ADDR 20
1584+#define WF_LWTBL_SR_ABORT_MASK \
1585+ 0x00008000 // 15-15
1586+#define WF_LWTBL_SR_ABORT_SHIFT 15
1587+#define WF_LWTBL_TX_POWER_OFFSET_DW 5
1588+#define WF_LWTBL_TX_POWER_OFFSET_ADDR 20
1589+#define WF_LWTBL_TX_POWER_OFFSET_MASK \
1590+ 0x003f0000 // 21-16
1591+#define WF_LWTBL_TX_POWER_OFFSET_SHIFT 16
1592+#define WF_LWTBL_LTF_EHT_DW 5
1593+#define WF_LWTBL_LTF_EHT_ADDR 20
1594+#define WF_LWTBL_LTF_EHT_MASK \
1595+ 0x00c00000 // 23-22
1596+#define WF_LWTBL_LTF_EHT_SHIFT 22
1597+#define WF_LWTBL_GI_EHT_DW 5
1598+#define WF_LWTBL_GI_EHT_ADDR 20
1599+#define WF_LWTBL_GI_EHT_MASK \
1600+ 0x03000000 // 25-24
1601+#define WF_LWTBL_GI_EHT_SHIFT 24
1602+#define WF_LWTBL_DOPPL_DW 5
1603+#define WF_LWTBL_DOPPL_ADDR 20
1604+#define WF_LWTBL_DOPPL_MASK \
1605+ 0x04000000 // 26-26
1606+#define WF_LWTBL_DOPPL_SHIFT 26
1607+#define WF_LWTBL_TXOP_PS_CAP_DW 5
1608+#define WF_LWTBL_TXOP_PS_CAP_ADDR 20
1609+#define WF_LWTBL_TXOP_PS_CAP_MASK \
1610+ 0x08000000 // 27-27
1611+#define WF_LWTBL_TXOP_PS_CAP_SHIFT 27
1612+#define WF_LWTBL_DU_I_PSM_DW 5
1613+#define WF_LWTBL_DU_I_PSM_ADDR 20
1614+#define WF_LWTBL_DU_I_PSM_MASK \
1615+ 0x10000000 // 28-28
1616+#define WF_LWTBL_DU_I_PSM_SHIFT 28
1617+#define WF_LWTBL_I_PSM_DW 5
1618+#define WF_LWTBL_I_PSM_ADDR 20
1619+#define WF_LWTBL_I_PSM_MASK \
1620+ 0x20000000 // 29-29
1621+#define WF_LWTBL_I_PSM_SHIFT 29
1622+#define WF_LWTBL_PSM_DW 5
1623+#define WF_LWTBL_PSM_ADDR 20
1624+#define WF_LWTBL_PSM_MASK \
1625+ 0x40000000 // 30-30
1626+#define WF_LWTBL_PSM_SHIFT 30
1627+#define WF_LWTBL_SKIP_TX_DW 5
1628+#define WF_LWTBL_SKIP_TX_ADDR 20
1629+#define WF_LWTBL_SKIP_TX_MASK \
1630+ 0x80000000 // 31-31
1631+#define WF_LWTBL_SKIP_TX_SHIFT 31
1632+// DW6
1633+#define WF_LWTBL_CBRN_DW 6
1634+#define WF_LWTBL_CBRN_ADDR 24
1635+#define WF_LWTBL_CBRN_MASK \
1636+ 0x00000007 // 2- 0
1637+#define WF_LWTBL_CBRN_SHIFT 0
1638+#define WF_LWTBL_DBNSS_EN_DW 6
1639+#define WF_LWTBL_DBNSS_EN_ADDR 24
1640+#define WF_LWTBL_DBNSS_EN_MASK \
1641+ 0x00000008 // 3- 3
1642+#define WF_LWTBL_DBNSS_EN_SHIFT 3
1643+#define WF_LWTBL_BAF_EN_DW 6
1644+#define WF_LWTBL_BAF_EN_ADDR 24
1645+#define WF_LWTBL_BAF_EN_MASK \
1646+ 0x00000010 // 4- 4
1647+#define WF_LWTBL_BAF_EN_SHIFT 4
1648+#define WF_LWTBL_RDGBA_DW 6
1649+#define WF_LWTBL_RDGBA_ADDR 24
1650+#define WF_LWTBL_RDGBA_MASK \
1651+ 0x00000020 // 5- 5
1652+#define WF_LWTBL_RDGBA_SHIFT 5
1653+#define WF_LWTBL_R_DW 6
1654+#define WF_LWTBL_R_ADDR 24
1655+#define WF_LWTBL_R_MASK \
1656+ 0x00000040 // 6- 6
1657+#define WF_LWTBL_R_SHIFT 6
1658+#define WF_LWTBL_SPE_IDX_DW 6
1659+#define WF_LWTBL_SPE_IDX_ADDR 24
1660+#define WF_LWTBL_SPE_IDX_MASK \
1661+ 0x00000f80 // 11- 7
1662+#define WF_LWTBL_SPE_IDX_SHIFT 7
1663+#define WF_LWTBL_G2_DW 6
1664+#define WF_LWTBL_G2_ADDR 24
1665+#define WF_LWTBL_G2_MASK \
1666+ 0x00001000 // 12-12
1667+#define WF_LWTBL_G2_SHIFT 12
1668+#define WF_LWTBL_G4_DW 6
1669+#define WF_LWTBL_G4_ADDR 24
1670+#define WF_LWTBL_G4_MASK \
1671+ 0x00002000 // 13-13
1672+#define WF_LWTBL_G4_SHIFT 13
1673+#define WF_LWTBL_G8_DW 6
1674+#define WF_LWTBL_G8_ADDR 24
1675+#define WF_LWTBL_G8_MASK \
1676+ 0x00004000 // 14-14
1677+#define WF_LWTBL_G8_SHIFT 14
1678+#define WF_LWTBL_G16_DW 6
1679+#define WF_LWTBL_G16_ADDR 24
1680+#define WF_LWTBL_G16_MASK \
1681+ 0x00008000 // 15-15
1682+#define WF_LWTBL_G16_SHIFT 15
1683+#define WF_LWTBL_G2_LTF_DW 6
1684+#define WF_LWTBL_G2_LTF_ADDR 24
1685+#define WF_LWTBL_G2_LTF_MASK \
1686+ 0x00030000 // 17-16
1687+#define WF_LWTBL_G2_LTF_SHIFT 16
1688+#define WF_LWTBL_G4_LTF_DW 6
1689+#define WF_LWTBL_G4_LTF_ADDR 24
1690+#define WF_LWTBL_G4_LTF_MASK \
1691+ 0x000c0000 // 19-18
1692+#define WF_LWTBL_G4_LTF_SHIFT 18
1693+#define WF_LWTBL_G8_LTF_DW 6
1694+#define WF_LWTBL_G8_LTF_ADDR 24
1695+#define WF_LWTBL_G8_LTF_MASK \
1696+ 0x00300000 // 21-20
1697+#define WF_LWTBL_G8_LTF_SHIFT 20
1698+#define WF_LWTBL_G16_LTF_DW 6
1699+#define WF_LWTBL_G16_LTF_ADDR 24
1700+#define WF_LWTBL_G16_LTF_MASK \
1701+ 0x00c00000 // 23-22
1702+#define WF_LWTBL_G16_LTF_SHIFT 22
1703+#define WF_LWTBL_G2_HE_DW 6
1704+#define WF_LWTBL_G2_HE_ADDR 24
1705+#define WF_LWTBL_G2_HE_MASK \
1706+ 0x03000000 // 25-24
1707+#define WF_LWTBL_G2_HE_SHIFT 24
1708+#define WF_LWTBL_G4_HE_DW 6
1709+#define WF_LWTBL_G4_HE_ADDR 24
1710+#define WF_LWTBL_G4_HE_MASK \
1711+ 0x0c000000 // 27-26
1712+#define WF_LWTBL_G4_HE_SHIFT 26
1713+#define WF_LWTBL_G8_HE_DW 6
1714+#define WF_LWTBL_G8_HE_ADDR 24
1715+#define WF_LWTBL_G8_HE_MASK \
1716+ 0x30000000 // 29-28
1717+#define WF_LWTBL_G8_HE_SHIFT 28
1718+#define WF_LWTBL_G16_HE_DW 6
1719+#define WF_LWTBL_G16_HE_ADDR 24
1720+#define WF_LWTBL_G16_HE_MASK \
1721+ 0xc0000000 // 31-30
1722+#define WF_LWTBL_G16_HE_SHIFT 30
1723+// DW7
1724+#define WF_LWTBL_BA_WIN_SIZE0_DW 7
1725+#define WF_LWTBL_BA_WIN_SIZE0_ADDR 28
1726+#define WF_LWTBL_BA_WIN_SIZE0_MASK \
1727+ 0x0000000f // 3- 0
1728+#define WF_LWTBL_BA_WIN_SIZE0_SHIFT 0
1729+#define WF_LWTBL_BA_WIN_SIZE1_DW 7
1730+#define WF_LWTBL_BA_WIN_SIZE1_ADDR 28
1731+#define WF_LWTBL_BA_WIN_SIZE1_MASK \
1732+ 0x000000f0 // 7- 4
1733+#define WF_LWTBL_BA_WIN_SIZE1_SHIFT 4
1734+#define WF_LWTBL_BA_WIN_SIZE2_DW 7
1735+#define WF_LWTBL_BA_WIN_SIZE2_ADDR 28
1736+#define WF_LWTBL_BA_WIN_SIZE2_MASK \
1737+ 0x00000f00 // 11- 8
1738+#define WF_LWTBL_BA_WIN_SIZE2_SHIFT 8
1739+#define WF_LWTBL_BA_WIN_SIZE3_DW 7
1740+#define WF_LWTBL_BA_WIN_SIZE3_ADDR 28
1741+#define WF_LWTBL_BA_WIN_SIZE3_MASK \
1742+ 0x0000f000 // 15-12
1743+#define WF_LWTBL_BA_WIN_SIZE3_SHIFT 12
1744+#define WF_LWTBL_BA_WIN_SIZE4_DW 7
1745+#define WF_LWTBL_BA_WIN_SIZE4_ADDR 28
1746+#define WF_LWTBL_BA_WIN_SIZE4_MASK \
1747+ 0x000f0000 // 19-16
1748+#define WF_LWTBL_BA_WIN_SIZE4_SHIFT 16
1749+#define WF_LWTBL_BA_WIN_SIZE5_DW 7
1750+#define WF_LWTBL_BA_WIN_SIZE5_ADDR 28
1751+#define WF_LWTBL_BA_WIN_SIZE5_MASK \
1752+ 0x00f00000 // 23-20
1753+#define WF_LWTBL_BA_WIN_SIZE5_SHIFT 20
1754+#define WF_LWTBL_BA_WIN_SIZE6_DW 7
1755+#define WF_LWTBL_BA_WIN_SIZE6_ADDR 28
1756+#define WF_LWTBL_BA_WIN_SIZE6_MASK \
1757+ 0x0f000000 // 27-24
1758+#define WF_LWTBL_BA_WIN_SIZE6_SHIFT 24
1759+#define WF_LWTBL_BA_WIN_SIZE7_DW 7
1760+#define WF_LWTBL_BA_WIN_SIZE7_ADDR 28
1761+#define WF_LWTBL_BA_WIN_SIZE7_MASK \
1762+ 0xf0000000 // 31-28
1763+#define WF_LWTBL_BA_WIN_SIZE7_SHIFT 28
1764+// DW8
1765+#define WF_LWTBL_AC0_RTS_FAIL_CNT_DW 8
1766+#define WF_LWTBL_AC0_RTS_FAIL_CNT_ADDR 32
1767+#define WF_LWTBL_AC0_RTS_FAIL_CNT_MASK \
1768+ 0x0000001f // 4- 0
1769+#define WF_LWTBL_AC0_RTS_FAIL_CNT_SHIFT 0
1770+#define WF_LWTBL_AC1_RTS_FAIL_CNT_DW 8
1771+#define WF_LWTBL_AC1_RTS_FAIL_CNT_ADDR 32
1772+#define WF_LWTBL_AC1_RTS_FAIL_CNT_MASK \
1773+ 0x000003e0 // 9- 5
1774+#define WF_LWTBL_AC1_RTS_FAIL_CNT_SHIFT 5
1775+#define WF_LWTBL_AC2_RTS_FAIL_CNT_DW 8
1776+#define WF_LWTBL_AC2_RTS_FAIL_CNT_ADDR 32
1777+#define WF_LWTBL_AC2_RTS_FAIL_CNT_MASK \
1778+ 0x00007c00 // 14-10
1779+#define WF_LWTBL_AC2_RTS_FAIL_CNT_SHIFT 10
1780+#define WF_LWTBL_AC3_RTS_FAIL_CNT_DW 8
1781+#define WF_LWTBL_AC3_RTS_FAIL_CNT_ADDR 32
1782+#define WF_LWTBL_AC3_RTS_FAIL_CNT_MASK \
1783+ 0x000f8000 // 19-15
1784+#define WF_LWTBL_AC3_RTS_FAIL_CNT_SHIFT 15
1785+#define WF_LWTBL_PARTIAL_AID_DW 8
1786+#define WF_LWTBL_PARTIAL_AID_ADDR 32
1787+#define WF_LWTBL_PARTIAL_AID_MASK \
1788+ 0x1ff00000 // 28-20
1789+#define WF_LWTBL_PARTIAL_AID_SHIFT 20
1790+#define WF_LWTBL_CHK_PER_DW 8
1791+#define WF_LWTBL_CHK_PER_ADDR 32
1792+#define WF_LWTBL_CHK_PER_MASK \
1793+ 0x80000000 // 31-31
1794+#define WF_LWTBL_CHK_PER_SHIFT 31
1795+// DW9
1796+#define WF_LWTBL_RX_AVG_MPDU_SIZE_DW 9
1797+#define WF_LWTBL_RX_AVG_MPDU_SIZE_ADDR 36
1798+#define WF_LWTBL_RX_AVG_MPDU_SIZE_MASK \
1799+ 0x00003fff // 13- 0
1800+#define WF_LWTBL_RX_AVG_MPDU_SIZE_SHIFT 0
1801+#define WF_LWTBL_PRITX_SW_MODE_DW 9
1802+#define WF_LWTBL_PRITX_SW_MODE_ADDR 36
1803+#define WF_LWTBL_PRITX_SW_MODE_MASK \
1804+ 0x00008000 // 15-15
1805+#define WF_LWTBL_PRITX_SW_MODE_SHIFT 15
1806+#define WF_LWTBL_PRITX_ERSU_DW 9
1807+#define WF_LWTBL_PRITX_ERSU_ADDR 36
1808+#define WF_LWTBL_PRITX_ERSU_MASK \
1809+ 0x00010000 // 16-16
1810+#define WF_LWTBL_PRITX_ERSU_SHIFT 16
1811+#define WF_LWTBL_PRITX_PLR_DW 9
1812+#define WF_LWTBL_PRITX_PLR_ADDR 36
1813+#define WF_LWTBL_PRITX_PLR_MASK \
1814+ 0x00020000 // 17-17
1815+#define WF_LWTBL_PRITX_PLR_SHIFT 17
1816+#define WF_LWTBL_PRITX_DCM_DW 9
1817+#define WF_LWTBL_PRITX_DCM_ADDR 36
1818+#define WF_LWTBL_PRITX_DCM_MASK \
1819+ 0x00040000 // 18-18
1820+#define WF_LWTBL_PRITX_DCM_SHIFT 18
1821+#define WF_LWTBL_PRITX_ER106T_DW 9
1822+#define WF_LWTBL_PRITX_ER106T_ADDR 36
1823+#define WF_LWTBL_PRITX_ER106T_MASK \
1824+ 0x00080000 // 19-19
1825+#define WF_LWTBL_PRITX_ER106T_SHIFT 19
1826+#define WF_LWTBL_FCAP_DW 9
1827+#define WF_LWTBL_FCAP_ADDR 36
1828+#define WF_LWTBL_FCAP_MASK \
1829+ 0x00700000 // 22-20
1830+#define WF_LWTBL_FCAP_SHIFT 20
1831+#define WF_LWTBL_MPDU_FAIL_CNT_DW 9
1832+#define WF_LWTBL_MPDU_FAIL_CNT_ADDR 36
1833+#define WF_LWTBL_MPDU_FAIL_CNT_MASK \
1834+ 0x03800000 // 25-23
1835+#define WF_LWTBL_MPDU_FAIL_CNT_SHIFT 23
1836+#define WF_LWTBL_MPDU_OK_CNT_DW 9
1837+#define WF_LWTBL_MPDU_OK_CNT_ADDR 36
1838+#define WF_LWTBL_MPDU_OK_CNT_MASK \
1839+ 0x1c000000 // 28-26
1840+#define WF_LWTBL_MPDU_OK_CNT_SHIFT 26
1841+#define WF_LWTBL_RATE_IDX_DW 9
1842+#define WF_LWTBL_RATE_IDX_ADDR 36
1843+#define WF_LWTBL_RATE_IDX_MASK \
1844+ 0xe0000000 // 31-29
1845+#define WF_LWTBL_RATE_IDX_SHIFT 29
1846+// DW10
1847+#define WF_LWTBL_RATE1_DW 10
1848+#define WF_LWTBL_RATE1_ADDR 40
1849+#define WF_LWTBL_RATE1_MASK \
1850+ 0x00007fff // 14- 0
1851+#define WF_LWTBL_RATE1_SHIFT 0
1852+#define WF_LWTBL_RATE2_DW 10
1853+#define WF_LWTBL_RATE2_ADDR 40
1854+#define WF_LWTBL_RATE2_MASK \
1855+ 0x7fff0000 // 30-16
1856+#define WF_LWTBL_RATE2_SHIFT 16
1857+// DW11
1858+#define WF_LWTBL_RATE3_DW 11
1859+#define WF_LWTBL_RATE3_ADDR 44
1860+#define WF_LWTBL_RATE3_MASK \
1861+ 0x00007fff // 14- 0
1862+#define WF_LWTBL_RATE3_SHIFT 0
1863+#define WF_LWTBL_RATE4_DW 11
1864+#define WF_LWTBL_RATE4_ADDR 44
1865+#define WF_LWTBL_RATE4_MASK \
1866+ 0x7fff0000 // 30-16
1867+#define WF_LWTBL_RATE4_SHIFT 16
1868+// DW12
1869+#define WF_LWTBL_RATE5_DW 12
1870+#define WF_LWTBL_RATE5_ADDR 48
1871+#define WF_LWTBL_RATE5_MASK \
1872+ 0x00007fff // 14- 0
1873+#define WF_LWTBL_RATE5_SHIFT 0
1874+#define WF_LWTBL_RATE6_DW 12
1875+#define WF_LWTBL_RATE6_ADDR 48
1876+#define WF_LWTBL_RATE6_MASK \
1877+ 0x7fff0000 // 30-16
1878+#define WF_LWTBL_RATE6_SHIFT 16
1879+// DW13
1880+#define WF_LWTBL_RATE7_DW 13
1881+#define WF_LWTBL_RATE7_ADDR 52
1882+#define WF_LWTBL_RATE7_MASK \
1883+ 0x00007fff // 14- 0
1884+#define WF_LWTBL_RATE7_SHIFT 0
1885+#define WF_LWTBL_RATE8_DW 13
1886+#define WF_LWTBL_RATE8_ADDR 52
1887+#define WF_LWTBL_RATE8_MASK \
1888+ 0x7fff0000 // 30-16
1889+#define WF_LWTBL_RATE8_SHIFT 16
1890+// DW14
1891+#define WF_LWTBL_RATE1_TX_CNT_DW 14
1892+#define WF_LWTBL_RATE1_TX_CNT_ADDR 56
1893+#define WF_LWTBL_RATE1_TX_CNT_MASK \
1894+ 0x0000ffff // 15- 0
1895+#define WF_LWTBL_RATE1_TX_CNT_SHIFT 0
1896+#define WF_LWTBL_CIPHER_SUIT_IGTK_DW 14
1897+#define WF_LWTBL_CIPHER_SUIT_IGTK_ADDR 56
1898+#define WF_LWTBL_CIPHER_SUIT_IGTK_MASK \
1899+ 0x00003000 // 13-12
1900+#define WF_LWTBL_CIPHER_SUIT_IGTK_SHIFT 12
1901+#define WF_LWTBL_CIPHER_SUIT_BIGTK_DW 14
1902+#define WF_LWTBL_CIPHER_SUIT_BIGTK_ADDR 56
1903+#define WF_LWTBL_CIPHER_SUIT_BIGTK_MASK \
1904+ 0x0000c000 // 15-14
1905+#define WF_LWTBL_CIPHER_SUIT_BIGTK_SHIFT 14
1906+#define WF_LWTBL_RATE1_FAIL_CNT_DW 14
1907+#define WF_LWTBL_RATE1_FAIL_CNT_ADDR 56
1908+#define WF_LWTBL_RATE1_FAIL_CNT_MASK \
1909+ 0xffff0000 // 31-16
1910+#define WF_LWTBL_RATE1_FAIL_CNT_SHIFT 16
1911+// DW15
1912+#define WF_LWTBL_RATE2_OK_CNT_DW 15
1913+#define WF_LWTBL_RATE2_OK_CNT_ADDR 60
1914+#define WF_LWTBL_RATE2_OK_CNT_MASK \
1915+ 0x0000ffff // 15- 0
1916+#define WF_LWTBL_RATE2_OK_CNT_SHIFT 0
1917+#define WF_LWTBL_RATE3_OK_CNT_DW 15
1918+#define WF_LWTBL_RATE3_OK_CNT_ADDR 60
1919+#define WF_LWTBL_RATE3_OK_CNT_MASK \
1920+ 0xffff0000 // 31-16
1921+#define WF_LWTBL_RATE3_OK_CNT_SHIFT 16
1922+// DW16
1923+#define WF_LWTBL_CURRENT_BW_TX_CNT_DW 16
1924+#define WF_LWTBL_CURRENT_BW_TX_CNT_ADDR 64
1925+#define WF_LWTBL_CURRENT_BW_TX_CNT_MASK \
1926+ 0x0000ffff // 15- 0
1927+#define WF_LWTBL_CURRENT_BW_TX_CNT_SHIFT 0
1928+#define WF_LWTBL_CURRENT_BW_FAIL_CNT_DW 16
1929+#define WF_LWTBL_CURRENT_BW_FAIL_CNT_ADDR 64
1930+#define WF_LWTBL_CURRENT_BW_FAIL_CNT_MASK \
1931+ 0xffff0000 // 31-16
1932+#define WF_LWTBL_CURRENT_BW_FAIL_CNT_SHIFT 16
1933+// DW17
1934+#define WF_LWTBL_OTHER_BW_TX_CNT_DW 17
1935+#define WF_LWTBL_OTHER_BW_TX_CNT_ADDR 68
1936+#define WF_LWTBL_OTHER_BW_TX_CNT_MASK \
1937+ 0x0000ffff // 15- 0
1938+#define WF_LWTBL_OTHER_BW_TX_CNT_SHIFT 0
1939+#define WF_LWTBL_OTHER_BW_FAIL_CNT_DW 17
1940+#define WF_LWTBL_OTHER_BW_FAIL_CNT_ADDR 68
1941+#define WF_LWTBL_OTHER_BW_FAIL_CNT_MASK \
1942+ 0xffff0000 // 31-16
1943+#define WF_LWTBL_OTHER_BW_FAIL_CNT_SHIFT 16
1944+// DW18
1945+#define WF_LWTBL_RTS_OK_CNT_DW 18
1946+#define WF_LWTBL_RTS_OK_CNT_ADDR 72
1947+#define WF_LWTBL_RTS_OK_CNT_MASK \
1948+ 0x0000ffff // 15- 0
1949+#define WF_LWTBL_RTS_OK_CNT_SHIFT 0
1950+#define WF_LWTBL_RTS_FAIL_CNT_DW 18
1951+#define WF_LWTBL_RTS_FAIL_CNT_ADDR 72
1952+#define WF_LWTBL_RTS_FAIL_CNT_MASK \
1953+ 0xffff0000 // 31-16
1954+#define WF_LWTBL_RTS_FAIL_CNT_SHIFT 16
1955+// DW19
1956+#define WF_LWTBL_DATA_RETRY_CNT_DW 19
1957+#define WF_LWTBL_DATA_RETRY_CNT_ADDR 76
1958+#define WF_LWTBL_DATA_RETRY_CNT_MASK \
1959+ 0x0000ffff // 15- 0
1960+#define WF_LWTBL_DATA_RETRY_CNT_SHIFT 0
1961+#define WF_LWTBL_MGNT_RETRY_CNT_DW 19
1962+#define WF_LWTBL_MGNT_RETRY_CNT_ADDR 76
1963+#define WF_LWTBL_MGNT_RETRY_CNT_MASK \
1964+ 0xffff0000 // 31-16
1965+#define WF_LWTBL_MGNT_RETRY_CNT_SHIFT 16
1966+// DW20
1967+#define WF_LWTBL_AC0_CTT_CDT_CRB_DW 20
1968+#define WF_LWTBL_AC0_CTT_CDT_CRB_ADDR 80
1969+#define WF_LWTBL_AC0_CTT_CDT_CRB_MASK \
1970+ 0xffffffff // 31- 0
1971+#define WF_LWTBL_AC0_CTT_CDT_CRB_SHIFT 0
1972+// DW21
1973+// DO NOT process repeat field(adm[0])
1974+// DW22
1975+#define WF_LWTBL_AC1_CTT_CDT_CRB_DW 22
1976+#define WF_LWTBL_AC1_CTT_CDT_CRB_ADDR 88
1977+#define WF_LWTBL_AC1_CTT_CDT_CRB_MASK \
1978+ 0xffffffff // 31- 0
1979+#define WF_LWTBL_AC1_CTT_CDT_CRB_SHIFT 0
1980+// DW23
1981+// DO NOT process repeat field(adm[1])
1982+// DW24
1983+#define WF_LWTBL_AC2_CTT_CDT_CRB_DW 24
1984+#define WF_LWTBL_AC2_CTT_CDT_CRB_ADDR 96
1985+#define WF_LWTBL_AC2_CTT_CDT_CRB_MASK \
1986+ 0xffffffff // 31- 0
1987+#define WF_LWTBL_AC2_CTT_CDT_CRB_SHIFT 0
1988+// DW25
1989+// DO NOT process repeat field(adm[2])
1990+// DW26
1991+#define WF_LWTBL_AC3_CTT_CDT_CRB_DW 26
1992+#define WF_LWTBL_AC3_CTT_CDT_CRB_ADDR 104
1993+#define WF_LWTBL_AC3_CTT_CDT_CRB_MASK \
1994+ 0xffffffff // 31- 0
1995+#define WF_LWTBL_AC3_CTT_CDT_CRB_SHIFT 0
1996+// DW27
1997+// DO NOT process repeat field(adm[3])
1998+// DW28
1999+#define WF_LWTBL_RELATED_IDX0_DW 28
2000+#define WF_LWTBL_RELATED_IDX0_ADDR 112
2001+#define WF_LWTBL_RELATED_IDX0_MASK \
2002+ 0x00000fff // 11- 0
2003+#define WF_LWTBL_RELATED_IDX0_SHIFT 0
2004+#define WF_LWTBL_RELATED_BAND0_DW 28
2005+#define WF_LWTBL_RELATED_BAND0_ADDR 112
2006+#define WF_LWTBL_RELATED_BAND0_MASK \
2007+ 0x00003000 // 13-12
2008+#define WF_LWTBL_RELATED_BAND0_SHIFT 12
2009+#define WF_LWTBL_PRIMARY_MLD_BAND_DW 28
2010+#define WF_LWTBL_PRIMARY_MLD_BAND_ADDR 112
2011+#define WF_LWTBL_PRIMARY_MLD_BAND_MASK \
2012+ 0x0000c000 // 15-14
2013+#define WF_LWTBL_PRIMARY_MLD_BAND_SHIFT 14
2014+#define WF_LWTBL_RELATED_IDX1_DW 28
2015+#define WF_LWTBL_RELATED_IDX1_ADDR 112
2016+#define WF_LWTBL_RELATED_IDX1_MASK \
2017+ 0x0fff0000 // 27-16
2018+#define WF_LWTBL_RELATED_IDX1_SHIFT 16
2019+#define WF_LWTBL_RELATED_BAND1_DW 28
2020+#define WF_LWTBL_RELATED_BAND1_ADDR 112
2021+#define WF_LWTBL_RELATED_BAND1_MASK \
2022+ 0x30000000 // 29-28
2023+#define WF_LWTBL_RELATED_BAND1_SHIFT 28
2024+#define WF_LWTBL_SECONDARY_MLD_BAND_DW 28
2025+#define WF_LWTBL_SECONDARY_MLD_BAND_ADDR 112
2026+#define WF_LWTBL_SECONDARY_MLD_BAND_MASK \
2027+ 0xc0000000 // 31-30
2028+#define WF_LWTBL_SECONDARY_MLD_BAND_SHIFT 30
2029+// DW29
2030+#define WF_LWTBL_DISPATCH_POLICY0_DW 29
2031+#define WF_LWTBL_DISPATCH_POLICY0_ADDR 116
2032+#define WF_LWTBL_DISPATCH_POLICY0_MASK \
2033+ 0x00000003 // 1- 0
2034+#define WF_LWTBL_DISPATCH_POLICY0_SHIFT 0
2035+#define WF_LWTBL_DISPATCH_POLICY1_DW 29
2036+#define WF_LWTBL_DISPATCH_POLICY1_ADDR 116
2037+#define WF_LWTBL_DISPATCH_POLICY1_MASK \
2038+ 0x0000000c // 3- 2
2039+#define WF_LWTBL_DISPATCH_POLICY1_SHIFT 2
2040+#define WF_LWTBL_DISPATCH_POLICY2_DW 29
2041+#define WF_LWTBL_DISPATCH_POLICY2_ADDR 116
2042+#define WF_LWTBL_DISPATCH_POLICY2_MASK \
2043+ 0x00000030 // 5- 4
2044+#define WF_LWTBL_DISPATCH_POLICY2_SHIFT 4
2045+#define WF_LWTBL_DISPATCH_POLICY3_DW 29
2046+#define WF_LWTBL_DISPATCH_POLICY3_ADDR 116
2047+#define WF_LWTBL_DISPATCH_POLICY3_MASK \
2048+ 0x000000c0 // 7- 6
2049+#define WF_LWTBL_DISPATCH_POLICY3_SHIFT 6
2050+#define WF_LWTBL_DISPATCH_POLICY4_DW 29
2051+#define WF_LWTBL_DISPATCH_POLICY4_ADDR 116
2052+#define WF_LWTBL_DISPATCH_POLICY4_MASK \
2053+ 0x00000300 // 9- 8
2054+#define WF_LWTBL_DISPATCH_POLICY4_SHIFT 8
2055+#define WF_LWTBL_DISPATCH_POLICY5_DW 29
2056+#define WF_LWTBL_DISPATCH_POLICY5_ADDR 116
2057+#define WF_LWTBL_DISPATCH_POLICY5_MASK \
2058+ 0x00000c00 // 11-10
2059+#define WF_LWTBL_DISPATCH_POLICY5_SHIFT 10
2060+#define WF_LWTBL_DISPATCH_POLICY6_DW 29
2061+#define WF_LWTBL_DISPATCH_POLICY6_ADDR 116
2062+#define WF_LWTBL_DISPATCH_POLICY6_MASK \
2063+ 0x00003000 // 13-12
2064+#define WF_LWTBL_DISPATCH_POLICY6_SHIFT 12
2065+#define WF_LWTBL_DISPATCH_POLICY7_DW 29
2066+#define WF_LWTBL_DISPATCH_POLICY7_ADDR 116
2067+#define WF_LWTBL_DISPATCH_POLICY7_MASK \
2068+ 0x0000c000 // 15-14
2069+#define WF_LWTBL_DISPATCH_POLICY7_SHIFT 14
2070+#define WF_LWTBL_OWN_MLD_ID_DW 29
2071+#define WF_LWTBL_OWN_MLD_ID_ADDR 116
2072+#define WF_LWTBL_OWN_MLD_ID_MASK \
2073+ 0x003f0000 // 21-16
2074+#define WF_LWTBL_OWN_MLD_ID_SHIFT 16
2075+#define WF_LWTBL_EMLSR0_DW 29
2076+#define WF_LWTBL_EMLSR0_ADDR 116
2077+#define WF_LWTBL_EMLSR0_MASK \
2078+ 0x00400000 // 22-22
2079+#define WF_LWTBL_EMLSR0_SHIFT 22
2080+#define WF_LWTBL_EMLMR0_DW 29
2081+#define WF_LWTBL_EMLMR0_ADDR 116
2082+#define WF_LWTBL_EMLMR0_MASK \
2083+ 0x00800000 // 23-23
2084+#define WF_LWTBL_EMLMR0_SHIFT 23
2085+#define WF_LWTBL_EMLSR1_DW 29
2086+#define WF_LWTBL_EMLSR1_ADDR 116
2087+#define WF_LWTBL_EMLSR1_MASK \
2088+ 0x01000000 // 24-24
2089+#define WF_LWTBL_EMLSR1_SHIFT 24
2090+#define WF_LWTBL_EMLMR1_DW 29
2091+#define WF_LWTBL_EMLMR1_ADDR 116
2092+#define WF_LWTBL_EMLMR1_MASK \
2093+ 0x02000000 // 25-25
2094+#define WF_LWTBL_EMLMR1_SHIFT 25
2095+#define WF_LWTBL_EMLSR2_DW 29
2096+#define WF_LWTBL_EMLSR2_ADDR 116
2097+#define WF_LWTBL_EMLSR2_MASK \
2098+ 0x04000000 // 26-26
2099+#define WF_LWTBL_EMLSR2_SHIFT 26
2100+#define WF_LWTBL_EMLMR2_DW 29
2101+#define WF_LWTBL_EMLMR2_ADDR 116
2102+#define WF_LWTBL_EMLMR2_MASK \
2103+ 0x08000000 // 27-27
2104+#define WF_LWTBL_EMLMR2_SHIFT 27
2105+#define WF_LWTBL_STR_BITMAP_DW 29
2106+#define WF_LWTBL_STR_BITMAP_ADDR 116
2107+#define WF_LWTBL_STR_BITMAP_MASK \
2108+ 0xe0000000 // 31-29
2109+#define WF_LWTBL_STR_BITMAP_SHIFT 29
2110+// DW30
2111+#define WF_LWTBL_DISPATCH_ORDER_DW 30
2112+#define WF_LWTBL_DISPATCH_ORDER_ADDR 120
2113+#define WF_LWTBL_DISPATCH_ORDER_MASK \
2114+ 0x0000007f // 6- 0
2115+#define WF_LWTBL_DISPATCH_ORDER_SHIFT 0
2116+#define WF_LWTBL_DISPATCH_RATIO_DW 30
2117+#define WF_LWTBL_DISPATCH_RATIO_ADDR 120
2118+#define WF_LWTBL_DISPATCH_RATIO_MASK \
2119+ 0x00003f80 // 13- 7
2120+#define WF_LWTBL_DISPATCH_RATIO_SHIFT 7
2121+#define WF_LWTBL_LINK_MGF_DW 30
2122+#define WF_LWTBL_LINK_MGF_ADDR 120
2123+#define WF_LWTBL_LINK_MGF_MASK \
2124+ 0xffff0000 // 31-16
2125+#define WF_LWTBL_LINK_MGF_SHIFT 16
2126+// DW31
developerc2cfe0f2023-09-22 04:11:09 +0800[diff] [blame]2127+#define WF_LWTBL_BFTX_TB_DW 31
2128+#define WF_LWTBL_BFTX_TB_ADDR 124
2129+#define WF_LWTBL_BFTX_TB_MASK \
2130+ 0x00800000 // 23-23
2131+#define WF_LWTBL_DROP_DW 31
2132+#define WF_LWTBL_DROP_ADDR 124
2133+#define WF_LWTBL_DROP_MASK \
2134+ 0x01000000 // 24-24
2135+#define WF_LWTBL_DROP_SHIFT 24
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]2136+#define WF_LWTBL_CASCAD_DW 31
2137+#define WF_LWTBL_CASCAD_ADDR 124
2138+#define WF_LWTBL_CASCAD_MASK \
2139+ 0x02000000 // 25-25
2140+#define WF_LWTBL_CASCAD_SHIFT 25
2141+#define WF_LWTBL_ALL_ACK_DW 31
2142+#define WF_LWTBL_ALL_ACK_ADDR 124
2143+#define WF_LWTBL_ALL_ACK_MASK \
2144+ 0x04000000 // 26-26
2145+#define WF_LWTBL_ALL_ACK_SHIFT 26
2146+#define WF_LWTBL_MPDU_SIZE_DW 31
2147+#define WF_LWTBL_MPDU_SIZE_ADDR 124
2148+#define WF_LWTBL_MPDU_SIZE_MASK \
2149+ 0x18000000 // 28-27
2150+#define WF_LWTBL_MPDU_SIZE_SHIFT 27
developerc2cfe0f2023-09-22 04:11:09 +0800[diff] [blame]2151+#define WF_LWTBL_RXD_DUP_MODE_DW 31
2152+#define WF_LWTBL_RXD_DUP_MODE_ADDR 124
2153+#define WF_LWTBL_RXD_DUP_MODE_MASK \
2154+ 0x60000000 // 30-29
2155+#define WF_LWTBL_RXD_DUP_MODE_SHIFT 29
2156+#define WF_LWTBL_ACK_EN_DW 31
2157+#define WF_LWTBL_ACK_EN_ADDR 128
2158+#define WF_LWTBL_ACK_EN_MASK \
2159+ 0x80000000 // 31-31
2160+#define WF_LWTBL_ACK_EN_SHIFT 31
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]2161+// DW32
2162+#define WF_LWTBL_OM_INFO_DW 32
2163+#define WF_LWTBL_OM_INFO_ADDR 128
2164+#define WF_LWTBL_OM_INFO_MASK \
2165+ 0x00000fff // 11- 0
2166+#define WF_LWTBL_OM_INFO_SHIFT 0
developerc2cfe0f2023-09-22 04:11:09 +0800[diff] [blame]2167+#define WF_LWTBL_OM_INFO_EHT_DW 32
2168+#define WF_LWTBL_OM_INFO_EHT_ADDR 128
2169+#define WF_LWTBL_OM_INFO_EHT_MASK \
2170+ 0x0000f000 // 15-12
2171+#define WF_LWTBL_OM_INFO_EHT_SHIFT 12
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]2172+#define WF_LWTBL_RXD_DUP_FOR_OM_CHG_DW 32
2173+#define WF_LWTBL_RXD_DUP_FOR_OM_CHG_ADDR 128
2174+#define WF_LWTBL_RXD_DUP_FOR_OM_CHG_MASK \
developerc2cfe0f2023-09-22 04:11:09 +0800[diff] [blame]2175+ 0x00010000 // 16-16
2176+#define WF_LWTBL_RXD_DUP_FOR_OM_CHG_SHIFT 16
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]2177+#define WF_LWTBL_RXD_DUP_WHITE_LIST_DW 32
2178+#define WF_LWTBL_RXD_DUP_WHITE_LIST_ADDR 128
2179+#define WF_LWTBL_RXD_DUP_WHITE_LIST_MASK \
developerc2cfe0f2023-09-22 04:11:09 +0800[diff] [blame]2180+ 0x1ffe0000 // 28-17
2181+#define WF_LWTBL_RXD_DUP_WHITE_LIST_SHIFT 17
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]2182+// DW33
2183+#define WF_LWTBL_USER_RSSI_DW 33
2184+#define WF_LWTBL_USER_RSSI_ADDR 132
2185+#define WF_LWTBL_USER_RSSI_MASK \
2186+ 0x000001ff // 8- 0
2187+#define WF_LWTBL_USER_RSSI_SHIFT 0
2188+#define WF_LWTBL_USER_SNR_DW 33
2189+#define WF_LWTBL_USER_SNR_ADDR 132
2190+#define WF_LWTBL_USER_SNR_MASK \
2191+ 0x00007e00 // 14- 9
2192+#define WF_LWTBL_USER_SNR_SHIFT 9
2193+#define WF_LWTBL_RAPID_REACTION_RATE_DW 33
2194+#define WF_LWTBL_RAPID_REACTION_RATE_ADDR 132
2195+#define WF_LWTBL_RAPID_REACTION_RATE_MASK \
2196+ 0x0fff0000 // 27-16
2197+#define WF_LWTBL_RAPID_REACTION_RATE_SHIFT 16
2198+#define WF_LWTBL_HT_AMSDU_DW 33
2199+#define WF_LWTBL_HT_AMSDU_ADDR 132
2200+#define WF_LWTBL_HT_AMSDU_MASK \
2201+ 0x40000000 // 30-30
2202+#define WF_LWTBL_HT_AMSDU_SHIFT 30
2203+#define WF_LWTBL_AMSDU_CROSS_LG_DW 33
2204+#define WF_LWTBL_AMSDU_CROSS_LG_ADDR 132
2205+#define WF_LWTBL_AMSDU_CROSS_LG_MASK \
2206+ 0x80000000 // 31-31
2207+#define WF_LWTBL_AMSDU_CROSS_LG_SHIFT 31
2208+// DW34
2209+#define WF_LWTBL_RESP_RCPI0_DW 34
2210+#define WF_LWTBL_RESP_RCPI0_ADDR 136
2211+#define WF_LWTBL_RESP_RCPI0_MASK \
2212+ 0x000000ff // 7- 0
2213+#define WF_LWTBL_RESP_RCPI0_SHIFT 0
2214+#define WF_LWTBL_RESP_RCPI1_DW 34
2215+#define WF_LWTBL_RESP_RCPI1_ADDR 136
2216+#define WF_LWTBL_RESP_RCPI1_MASK \
2217+ 0x0000ff00 // 15- 8
2218+#define WF_LWTBL_RESP_RCPI1_SHIFT 8
2219+#define WF_LWTBL_RESP_RCPI2_DW 34
2220+#define WF_LWTBL_RESP_RCPI2_ADDR 136
2221+#define WF_LWTBL_RESP_RCPI2_MASK \
2222+ 0x00ff0000 // 23-16
2223+#define WF_LWTBL_RESP_RCPI2_SHIFT 16
2224+#define WF_LWTBL_RESP_RCPI3_DW 34
2225+#define WF_LWTBL_RESP_RCPI3_ADDR 136
2226+#define WF_LWTBL_RESP_RCPI3_MASK \
2227+ 0xff000000 // 31-24
2228+#define WF_LWTBL_RESP_RCPI3_SHIFT 24
2229+// DW35
2230+#define WF_LWTBL_SNR_RX0_DW 35
2231+#define WF_LWTBL_SNR_RX0_ADDR 140
2232+#define WF_LWTBL_SNR_RX0_MASK \
2233+ 0x0000003f // 5- 0
2234+#define WF_LWTBL_SNR_RX0_SHIFT 0
2235+#define WF_LWTBL_SNR_RX1_DW 35
2236+#define WF_LWTBL_SNR_RX1_ADDR 140
2237+#define WF_LWTBL_SNR_RX1_MASK \
2238+ 0x00000fc0 // 11- 6
2239+#define WF_LWTBL_SNR_RX1_SHIFT 6
2240+#define WF_LWTBL_SNR_RX2_DW 35
2241+#define WF_LWTBL_SNR_RX2_ADDR 140
2242+#define WF_LWTBL_SNR_RX2_MASK \
2243+ 0x0003f000 // 17-12
2244+#define WF_LWTBL_SNR_RX2_SHIFT 12
2245+#define WF_LWTBL_SNR_RX3_DW 35
2246+#define WF_LWTBL_SNR_RX3_ADDR 140
2247+#define WF_LWTBL_SNR_RX3_MASK \
2248+ 0x00fc0000 // 23-18
2249+#define WF_LWTBL_SNR_RX3_SHIFT 18
2250+
2251+/* WTBL Group - Packet Number */
2252+/* DW 2 */
2253+#define WTBL_PN0_MASK BITS(0, 7)
2254+#define WTBL_PN0_OFFSET 0
2255+#define WTBL_PN1_MASK BITS(8, 15)
2256+#define WTBL_PN1_OFFSET 8
2257+#define WTBL_PN2_MASK BITS(16, 23)
2258+#define WTBL_PN2_OFFSET 16
2259+#define WTBL_PN3_MASK BITS(24, 31)
2260+#define WTBL_PN3_OFFSET 24
2261+
2262+/* DW 3 */
2263+#define WTBL_PN4_MASK BITS(0, 7)
2264+#define WTBL_PN4_OFFSET 0
2265+#define WTBL_PN5_MASK BITS(8, 15)
2266+#define WTBL_PN5_OFFSET 8
2267+
2268+/* DW 4 */
2269+#define WTBL_BIPN0_MASK BITS(0, 7)
2270+#define WTBL_BIPN0_OFFSET 0
2271+#define WTBL_BIPN1_MASK BITS(8, 15)
2272+#define WTBL_BIPN1_OFFSET 8
2273+#define WTBL_BIPN2_MASK BITS(16, 23)
2274+#define WTBL_BIPN2_OFFSET 16
2275+#define WTBL_BIPN3_MASK BITS(24, 31)
2276+#define WTBL_BIPN3_OFFSET 24
2277+
2278+/* DW 5 */
2279+#define WTBL_BIPN4_MASK BITS(0, 7)
2280+#define WTBL_BIPN4_OFFSET 0
2281+#define WTBL_BIPN5_MASK BITS(8, 15)
2282+#define WTBL_BIPN5_OFFSET 8
2283+
2284+/* UWTBL DW 6 */
2285+#define WTBL_AMSDU_LEN_MASK BITS(0, 5)
2286+#define WTBL_AMSDU_LEN_OFFSET 0
2287+#define WTBL_AMSDU_NUM_MASK BITS(6, 10)
2288+#define WTBL_AMSDU_NUM_OFFSET 6
2289+#define WTBL_AMSDU_EN_MASK BIT(11)
2290+#define WTBL_AMSDU_EN_OFFSET 11
2291+
developerc2cfe0f2023-09-22 04:11:09 +0800[diff] [blame]2292+/* UWTBL DW 8 */
2293+#define WTBL_SEC_ADDR_MODE_MASK BITS(20, 21)
2294+#define WTBL_SEC_ADDR_MODE_OFFSET 20
2295+
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]2296+/* LWTBL Rate field */
2297+#define WTBL_RATE_TX_RATE_MASK BITS(0, 5)
2298+#define WTBL_RATE_TX_RATE_OFFSET 0
2299+#define WTBL_RATE_TX_MODE_MASK BITS(6, 9)
2300+#define WTBL_RATE_TX_MODE_OFFSET 6
2301+#define WTBL_RATE_NSTS_MASK BITS(10, 13)
2302+#define WTBL_RATE_NSTS_OFFSET 10
2303+#define WTBL_RATE_STBC_MASK BIT(14)
2304+#define WTBL_RATE_STBC_OFFSET 14
2305+
2306+/***** WTBL(LMAC) DW Offset *****/
2307+/* LMAC WTBL Group - Peer Unique Information */
2308+#define WTBL_GROUP_PEER_INFO_DW_0 0
2309+#define WTBL_GROUP_PEER_INFO_DW_1 1
2310+
2311+/* WTBL Group - TxRx Capability/Information */
2312+#define WTBL_GROUP_TRX_CAP_DW_2 2
2313+#define WTBL_GROUP_TRX_CAP_DW_3 3
2314+#define WTBL_GROUP_TRX_CAP_DW_4 4
2315+#define WTBL_GROUP_TRX_CAP_DW_5 5
2316+#define WTBL_GROUP_TRX_CAP_DW_6 6
2317+#define WTBL_GROUP_TRX_CAP_DW_7 7
2318+#define WTBL_GROUP_TRX_CAP_DW_8 8
2319+#define WTBL_GROUP_TRX_CAP_DW_9 9
2320+
2321+/* WTBL Group - Auto Rate Table*/
2322+#define WTBL_GROUP_AUTO_RATE_1_2 10
2323+#define WTBL_GROUP_AUTO_RATE_3_4 11
2324+#define WTBL_GROUP_AUTO_RATE_5_6 12
2325+#define WTBL_GROUP_AUTO_RATE_7_8 13
2326+
2327+/* WTBL Group - Tx Counter */
2328+#define WTBL_GROUP_TX_CNT_LINE_1 14
2329+#define WTBL_GROUP_TX_CNT_LINE_2 15
2330+#define WTBL_GROUP_TX_CNT_LINE_3 16
2331+#define WTBL_GROUP_TX_CNT_LINE_4 17
2332+#define WTBL_GROUP_TX_CNT_LINE_5 18
2333+#define WTBL_GROUP_TX_CNT_LINE_6 19
2334+
2335+/* WTBL Group - Admission Control Counter */
2336+#define WTBL_GROUP_ADM_CNT_LINE_1 20
2337+#define WTBL_GROUP_ADM_CNT_LINE_2 21
2338+#define WTBL_GROUP_ADM_CNT_LINE_3 22
2339+#define WTBL_GROUP_ADM_CNT_LINE_4 23
2340+#define WTBL_GROUP_ADM_CNT_LINE_5 24
2341+#define WTBL_GROUP_ADM_CNT_LINE_6 25
2342+#define WTBL_GROUP_ADM_CNT_LINE_7 26
2343+#define WTBL_GROUP_ADM_CNT_LINE_8 27
2344+
2345+/* WTBL Group -MLO Info */
2346+#define WTBL_GROUP_MLO_INFO_LINE_1 28
2347+#define WTBL_GROUP_MLO_INFO_LINE_2 29
2348+#define WTBL_GROUP_MLO_INFO_LINE_3 30
2349+
2350+/* WTBL Group -RESP Info */
2351+#define WTBL_GROUP_RESP_INFO_DW_31 31
2352+
2353+/* WTBL Group -RX DUP Info */
2354+#define WTBL_GROUP_RX_DUP_INFO_DW_32 32
2355+
2356+/* WTBL Group - Rx Statistics Counter */
2357+#define WTBL_GROUP_RX_STAT_CNT_LINE_1 33
2358+#define WTBL_GROUP_RX_STAT_CNT_LINE_2 34
2359+#define WTBL_GROUP_RX_STAT_CNT_LINE_3 35
2360+
2361+/* UWTBL Group - HW AMSDU */
2362+#define UWTBL_HW_AMSDU_DW WF_UWTBL_AMSDU_CFG_DW
2363+
2364+/* LWTBL DW 4 */
2365+#define WTBL_DIS_RHTR WF_LWTBL_DIS_RHTR_MASK
2366+
2367+/* UWTBL DW 5 */
2368+#define WTBL_KEY_LINK_DW_KEY_LOC0_MASK BITS(0, 10)
2369+#define WTBL_PSM WF_LWTBL_PSM_MASK
2370+
2371+/* Need to sync with FW define */
2372+#define INVALID_KEY_ENTRY WTBL_KEY_LINK_DW_KEY_LOC0_MASK
2373+
2374+// RATE
2375+#define WTBL_RATE_TX_RATE_MASK BITS(0, 5)
2376+#define WTBL_RATE_TX_RATE_OFFSET 0
2377+#define WTBL_RATE_TX_MODE_MASK BITS(6, 9)
2378+#define WTBL_RATE_TX_MODE_OFFSET 6
2379+#define WTBL_RATE_NSTS_MASK BITS(10, 13)
2380+#define WTBL_RATE_NSTS_OFFSET 10
2381+#define WTBL_RATE_STBC_MASK BIT(14)
2382+#define WTBL_RATE_STBC_OFFSET 14
2383+#endif
2384+
2385+#endif
2386diff --git a/mt7996/mtk_debugfs.c b/mt7996/mtk_debugfs.c
2387new file mode 100644
developerc2cfe0f2023-09-22 04:11:09 +0800[diff] [blame]2388index 000000000..5aa5c94f3
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]2389--- /dev/null
2390+++ b/mt7996/mtk_debugfs.c
developerc2cfe0f2023-09-22 04:11:09 +0800[diff] [blame]2391@@ -0,0 +1,2379 @@
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]2392+// SPDX-License-Identifier: ISC
2393+/*
2394+ * Copyright (C) 2023 MediaTek Inc.
2395+ */
2396+#include "mt7996.h"
2397+#include "../mt76.h"
2398+#include "mcu.h"
2399+#include "mac.h"
2400+#include "eeprom.h"
2401+#include "mtk_debug.h"
2402+#include "mtk_mcu.h"
developer064da3c2023-06-13 15:57:26 +0800[diff] [blame]2403+#include "coredump.h"
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]2404+
2405+#ifdef CONFIG_MTK_DEBUG
2406+
2407+/* AGG INFO */
2408+static int
2409+mt7996_agginfo_read_per_band(struct seq_file *s, int band_idx)
2410+{
2411+ struct mt7996_dev *dev = dev_get_drvdata(s->private);
2412+ u64 total_burst, total_ampdu, ampdu_cnt[16];
2413+ u32 value, idx, row_idx, col_idx, start_range, agg_rang_sel[16], burst_cnt[16], band_offset = 0;
developerc2cfe0f2023-09-22 04:11:09 +0800[diff] [blame]2414+ u8 partial_str[16] = {}, full_str[64] = {};
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]2415+
2416+ switch (band_idx) {
2417+ case 0:
2418+ band_offset = 0;
2419+ break;
2420+ case 1:
2421+ band_offset = BN1_WF_AGG_TOP_BASE - BN0_WF_AGG_TOP_BASE;
2422+ break;
2423+ case 2:
2424+ band_offset = IP1_BN0_WF_AGG_TOP_BASE - BN0_WF_AGG_TOP_BASE;
2425+ break;
2426+ default:
2427+ return 0;
2428+ }
2429+
2430+ seq_printf(s, "Band %d AGG Status\n", band_idx);
2431+ seq_printf(s, "===============================\n");
2432+ value = mt76_rr(dev, BN0_WF_AGG_TOP_AALCR0_ADDR + band_offset);
2433+ seq_printf(s, "AC00 Agg limit = %d\t", (value & BN0_WF_AGG_TOP_AALCR0_AC00_AGG_LIMIT_MASK) >> BN0_WF_AGG_TOP_AALCR0_AC00_AGG_LIMIT_SHFT);
2434+ seq_printf(s, "AC01 Agg limit = %d\t", (value & BN0_WF_AGG_TOP_AALCR0_AC01_AGG_LIMIT_MASK) >> BN0_WF_AGG_TOP_AALCR0_AC01_AGG_LIMIT_SHFT);
2435+ value = mt76_rr(dev, BN0_WF_AGG_TOP_AALCR1_ADDR + band_offset);
2436+ seq_printf(s, "AC02 Agg limit = %d\t", (value & BN0_WF_AGG_TOP_AALCR1_AC02_AGG_LIMIT_MASK) >> BN0_WF_AGG_TOP_AALCR1_AC02_AGG_LIMIT_SHFT);
2437+ seq_printf(s, "AC03 Agg limit = %d\t", (value & BN0_WF_AGG_TOP_AALCR1_AC03_AGG_LIMIT_MASK) >> BN0_WF_AGG_TOP_AALCR1_AC03_AGG_LIMIT_SHFT);
2438+ value = mt76_rr(dev, BN0_WF_AGG_TOP_AALCR2_ADDR + band_offset);
2439+ seq_printf(s, "AC10 Agg limit = %d\t", (value & BN0_WF_AGG_TOP_AALCR2_AC10_AGG_LIMIT_MASK) >> BN0_WF_AGG_TOP_AALCR2_AC10_AGG_LIMIT_SHFT);
2440+ seq_printf(s, "AC11 Agg limit = %d\t", (value & BN0_WF_AGG_TOP_AALCR2_AC11_AGG_LIMIT_MASK) >> BN0_WF_AGG_TOP_AALCR2_AC11_AGG_LIMIT_SHFT);
2441+ value = mt76_rr(dev, BN0_WF_AGG_TOP_AALCR3_ADDR + band_offset);
2442+ seq_printf(s, "AC12 Agg limit = %d\t", (value & BN0_WF_AGG_TOP_AALCR3_AC12_AGG_LIMIT_MASK) >> BN0_WF_AGG_TOP_AALCR3_AC12_AGG_LIMIT_SHFT);
2443+ seq_printf(s, "AC13 Agg limit = %d\t", (value & BN0_WF_AGG_TOP_AALCR3_AC13_AGG_LIMIT_MASK) >> BN0_WF_AGG_TOP_AALCR3_AC13_AGG_LIMIT_SHFT);
2444+ value = mt76_rr(dev, BN0_WF_AGG_TOP_AALCR4_ADDR + band_offset);
2445+ seq_printf(s, "AC20 Agg limit = %d\t", (value & BN0_WF_AGG_TOP_AALCR4_AC20_AGG_LIMIT_MASK) >> BN0_WF_AGG_TOP_AALCR4_AC20_AGG_LIMIT_SHFT);
2446+ seq_printf(s, "AC21 Agg limit = %d\t", (value & BN0_WF_AGG_TOP_AALCR4_AC21_AGG_LIMIT_MASK) >> BN0_WF_AGG_TOP_AALCR4_AC21_AGG_LIMIT_SHFT);
2447+ value = mt76_rr(dev, BN0_WF_AGG_TOP_AALCR5_ADDR + band_offset);
2448+ seq_printf(s, "AC22 Agg limit = %d\t", (value & BN0_WF_AGG_TOP_AALCR5_AC22_AGG_LIMIT_MASK) >> BN0_WF_AGG_TOP_AALCR5_AC22_AGG_LIMIT_SHFT);
2449+ seq_printf(s, "AC23 Agg limit = %d\t", (value & BN0_WF_AGG_TOP_AALCR5_AC23_AGG_LIMIT_MASK) >> BN0_WF_AGG_TOP_AALCR5_AC23_AGG_LIMIT_SHFT);
2450+ value = mt76_rr(dev, BN0_WF_AGG_TOP_AALCR6_ADDR + band_offset);
2451+ seq_printf(s, "AC30 Agg limit = %d\t", (value & BN0_WF_AGG_TOP_AALCR6_AC30_AGG_LIMIT_MASK) >> BN0_WF_AGG_TOP_AALCR6_AC30_AGG_LIMIT_SHFT);
2452+ seq_printf(s, "AC31 Agg limit = %d\t", (value & BN0_WF_AGG_TOP_AALCR6_AC31_AGG_LIMIT_MASK) >> BN0_WF_AGG_TOP_AALCR6_AC31_AGG_LIMIT_SHFT);
2453+ value = mt76_rr(dev, BN0_WF_AGG_TOP_AALCR7_ADDR + band_offset);
2454+ seq_printf(s, "AC32 Agg limit = %d\t", (value & BN0_WF_AGG_TOP_AALCR7_AC32_AGG_LIMIT_MASK) >> BN0_WF_AGG_TOP_AALCR7_AC32_AGG_LIMIT_SHFT);
2455+ seq_printf(s, "AC33 Agg limit = %d\t", (value & BN0_WF_AGG_TOP_AALCR7_AC33_AGG_LIMIT_MASK) >> BN0_WF_AGG_TOP_AALCR7_AC33_AGG_LIMIT_SHFT);
2456+
2457+ switch (band_idx) {
2458+ case 0:
2459+ band_offset = 0;
2460+ break;
2461+ case 1:
2462+ band_offset = BN1_WF_MIB_TOP_BASE - BN0_WF_MIB_TOP_BASE;
2463+ break;
2464+ case 2:
2465+ band_offset = IP1_BN0_WF_MIB_TOP_BASE - BN0_WF_MIB_TOP_BASE;
2466+ break;
2467+ default:
2468+ return 0;
2469+ }
2470+
2471+ seq_printf(s, "===AMPDU Related Counters===\n");
2472+
developerc2cfe0f2023-09-22 04:11:09 +0800[diff] [blame]2473+ value = mt76_rr(dev, BN0_WF_MIB_TOP_TRARC0_ADDR + band_offset);
2474+ agg_rang_sel[0] = (value & BN0_WF_MIB_TOP_TRARC0_AGG_RANG_SEL_0_MASK) >> BN0_WF_MIB_TOP_TRARC0_AGG_RANG_SEL_0_SHFT;
2475+ agg_rang_sel[1] = (value & BN0_WF_MIB_TOP_TRARC0_AGG_RANG_SEL_1_MASK) >> BN0_WF_MIB_TOP_TRARC0_AGG_RANG_SEL_1_SHFT;
2476+ value = mt76_rr(dev, BN0_WF_MIB_TOP_TRARC1_ADDR + band_offset);
2477+ agg_rang_sel[2] = (value & BN0_WF_MIB_TOP_TRARC1_AGG_RANG_SEL_2_MASK) >> BN0_WF_MIB_TOP_TRARC1_AGG_RANG_SEL_2_SHFT;
2478+ agg_rang_sel[3] = (value & BN0_WF_MIB_TOP_TRARC1_AGG_RANG_SEL_3_MASK) >> BN0_WF_MIB_TOP_TRARC1_AGG_RANG_SEL_3_SHFT;
2479+ value = mt76_rr(dev, BN0_WF_MIB_TOP_TRARC2_ADDR + band_offset);
2480+ agg_rang_sel[4] = (value & BN0_WF_MIB_TOP_TRARC2_AGG_RANG_SEL_4_MASK) >> BN0_WF_MIB_TOP_TRARC2_AGG_RANG_SEL_4_SHFT;
2481+ agg_rang_sel[5] = (value & BN0_WF_MIB_TOP_TRARC2_AGG_RANG_SEL_5_MASK) >> BN0_WF_MIB_TOP_TRARC2_AGG_RANG_SEL_5_SHFT;
2482+ value = mt76_rr(dev, BN0_WF_MIB_TOP_TRARC3_ADDR + band_offset);
2483+ agg_rang_sel[6] = (value & BN0_WF_MIB_TOP_TRARC3_AGG_RANG_SEL_6_MASK) >> BN0_WF_MIB_TOP_TRARC3_AGG_RANG_SEL_6_SHFT;
2484+ agg_rang_sel[7] = (value & BN0_WF_MIB_TOP_TRARC3_AGG_RANG_SEL_7_MASK) >> BN0_WF_MIB_TOP_TRARC3_AGG_RANG_SEL_7_SHFT;
2485+ value = mt76_rr(dev, BN0_WF_MIB_TOP_TRARC4_ADDR + band_offset);
2486+ agg_rang_sel[8] = (value & BN0_WF_MIB_TOP_TRARC4_AGG_RANG_SEL_8_MASK) >> BN0_WF_MIB_TOP_TRARC4_AGG_RANG_SEL_8_SHFT;
2487+ agg_rang_sel[9] = (value & BN0_WF_MIB_TOP_TRARC4_AGG_RANG_SEL_9_MASK) >> BN0_WF_MIB_TOP_TRARC4_AGG_RANG_SEL_9_SHFT;
2488+ value = mt76_rr(dev, BN0_WF_MIB_TOP_TRARC5_ADDR + band_offset);
2489+ agg_rang_sel[10] = (value & BN0_WF_MIB_TOP_TRARC5_AGG_RANG_SEL_10_MASK) >> BN0_WF_MIB_TOP_TRARC5_AGG_RANG_SEL_10_SHFT;
2490+ agg_rang_sel[11] = (value & BN0_WF_MIB_TOP_TRARC5_AGG_RANG_SEL_11_MASK) >> BN0_WF_MIB_TOP_TRARC5_AGG_RANG_SEL_11_SHFT;
2491+ value = mt76_rr(dev, BN0_WF_MIB_TOP_TRARC6_ADDR + band_offset);
2492+ agg_rang_sel[12] = (value & BN0_WF_MIB_TOP_TRARC6_AGG_RANG_SEL_12_MASK) >> BN0_WF_MIB_TOP_TRARC6_AGG_RANG_SEL_12_SHFT;
2493+ agg_rang_sel[13] = (value & BN0_WF_MIB_TOP_TRARC6_AGG_RANG_SEL_13_MASK) >> BN0_WF_MIB_TOP_TRARC6_AGG_RANG_SEL_13_SHFT;
2494+ value = mt76_rr(dev, BN0_WF_MIB_TOP_TRARC7_ADDR + band_offset);
2495+ agg_rang_sel[14] = (value & BN0_WF_MIB_TOP_TRARC7_AGG_RANG_SEL_14_MASK) >> BN0_WF_MIB_TOP_TRARC7_AGG_RANG_SEL_14_SHFT;
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]2496+
developerc2cfe0f2023-09-22 04:11:09 +0800[diff] [blame]2497+ burst_cnt[0] = mt76_rr(dev, BN0_WF_MIB_TOP_TRDR0_ADDR + band_offset);
2498+ burst_cnt[1] = mt76_rr(dev, BN0_WF_MIB_TOP_TRDR1_ADDR + band_offset);
2499+ burst_cnt[2] = mt76_rr(dev, BN0_WF_MIB_TOP_TRDR2_ADDR + band_offset);
2500+ burst_cnt[3] = mt76_rr(dev, BN0_WF_MIB_TOP_TRDR3_ADDR + band_offset);
2501+ burst_cnt[4] = mt76_rr(dev, BN0_WF_MIB_TOP_TRDR4_ADDR + band_offset);
2502+ burst_cnt[5] = mt76_rr(dev, BN0_WF_MIB_TOP_TRDR5_ADDR + band_offset);
2503+ burst_cnt[6] = mt76_rr(dev, BN0_WF_MIB_TOP_TRDR6_ADDR + band_offset);
2504+ burst_cnt[7] = mt76_rr(dev, BN0_WF_MIB_TOP_TRDR7_ADDR + band_offset);
2505+ burst_cnt[8] = mt76_rr(dev, BN0_WF_MIB_TOP_TRDR8_ADDR + band_offset);
2506+ burst_cnt[9] = mt76_rr(dev, BN0_WF_MIB_TOP_TRDR9_ADDR + band_offset);
2507+ burst_cnt[10] = mt76_rr(dev, BN0_WF_MIB_TOP_TRDR10_ADDR + band_offset);
2508+ burst_cnt[11] = mt76_rr(dev, BN0_WF_MIB_TOP_TRDR11_ADDR + band_offset);
2509+ burst_cnt[12] = mt76_rr(dev, BN0_WF_MIB_TOP_TRDR12_ADDR + band_offset);
2510+ burst_cnt[13] = mt76_rr(dev, BN0_WF_MIB_TOP_TRDR13_ADDR + band_offset);
2511+ burst_cnt[14] = mt76_rr(dev, BN0_WF_MIB_TOP_TRDR14_ADDR + band_offset);
2512+ burst_cnt[15] = mt76_rr(dev, BN0_WF_MIB_TOP_TRDR15_ADDR + band_offset);
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]2513+
2514+ start_range = 1;
2515+ total_burst = 0;
2516+ total_ampdu = 0;
2517+ agg_rang_sel[15] = 1023;
2518+
2519+ /* Need to add 1 after read from AGG_RANG_SEL CR */
2520+ for (idx = 0; idx < 16; idx++) {
2521+ agg_rang_sel[idx]++;
2522+ total_burst += burst_cnt[idx];
2523+
2524+ if (start_range == agg_rang_sel[idx])
2525+ ampdu_cnt[idx] = (u64) start_range * burst_cnt[idx];
2526+ else
2527+ ampdu_cnt[idx] = (u64) ((start_range + agg_rang_sel[idx]) >> 1) * burst_cnt[idx];
2528+
2529+ start_range = agg_rang_sel[idx] + 1;
2530+ total_ampdu += ampdu_cnt[idx];
2531+ }
2532+
2533+ start_range = 1;
2534+ sprintf(full_str, "%13s ", "Tx Agg Range:");
2535+
2536+ for (row_idx = 0; row_idx < 4; row_idx++) {
2537+ for (col_idx = 0; col_idx < 4; col_idx++, idx++) {
2538+ idx = 4 * row_idx + col_idx;
2539+
2540+ if (start_range == agg_rang_sel[idx])
2541+ sprintf(partial_str, "%d", agg_rang_sel[idx]);
2542+ else
2543+ sprintf(partial_str, "%d~%d", start_range, agg_rang_sel[idx]);
2544+
2545+ start_range = agg_rang_sel[idx] + 1;
2546+ sprintf(full_str + strlen(full_str), "%-11s ", partial_str);
2547+ }
2548+
2549+ idx = 4 * row_idx;
2550+
2551+ seq_printf(s, "%s\n", full_str);
2552+ seq_printf(s, "%13s 0x%-9x 0x%-9x 0x%-9x 0x%-9x\n",
2553+ row_idx ? "" : "Burst count:",
2554+ burst_cnt[idx], burst_cnt[idx + 1],
2555+ burst_cnt[idx + 2], burst_cnt[idx + 3]);
2556+
2557+ if (total_burst != 0) {
2558+ if (row_idx == 0)
2559+ sprintf(full_str, "%13s ",
2560+ "Burst ratio:");
2561+ else
2562+ sprintf(full_str, "%13s ", "");
2563+
2564+ for (col_idx = 0; col_idx < 4; col_idx++) {
2565+ u64 count = (u64) burst_cnt[idx + col_idx] * 100;
2566+
2567+ sprintf(partial_str, "(%llu%%)",
2568+ div64_u64(count, total_burst));
2569+ sprintf(full_str + strlen(full_str),
2570+ "%-11s ", partial_str);
2571+ }
2572+
2573+ seq_printf(s, "%s\n", full_str);
2574+
2575+ if (row_idx == 0)
2576+ sprintf(full_str, "%13s ",
2577+ "MDPU ratio:");
2578+ else
2579+ sprintf(full_str, "%13s ", "");
2580+
2581+ for (col_idx = 0; col_idx < 4; col_idx++) {
2582+ u64 count = ampdu_cnt[idx + col_idx] * 100;
2583+
2584+ sprintf(partial_str, "(%llu%%)",
2585+ div64_u64(count, total_ampdu));
2586+ sprintf(full_str + strlen(full_str),
2587+ "%-11s ", partial_str);
2588+ }
2589+
2590+ seq_printf(s, "%s\n", full_str);
2591+ }
2592+
2593+ sprintf(full_str, "%13s ", "");
2594+ }
2595+
2596+ return 0;
2597+}
2598+
2599+static int mt7996_agginfo_read_band0(struct seq_file *s, void *data)
2600+{
2601+ mt7996_agginfo_read_per_band(s, MT_BAND0);
2602+ return 0;
2603+}
2604+
2605+static int mt7996_agginfo_read_band1(struct seq_file *s, void *data)
2606+{
2607+ mt7996_agginfo_read_per_band(s, MT_BAND1);
2608+ return 0;
2609+}
2610+
2611+static int mt7996_agginfo_read_band2(struct seq_file *s, void *data)
2612+{
2613+ mt7996_agginfo_read_per_band(s, MT_BAND2);
2614+ return 0;
2615+}
2616+
2617+/* AMSDU INFO */
2618+static int mt7996_amsdu_result_read(struct seq_file *s, void *data)
2619+{
2620+#define HW_MSDU_CNT_ADDR 0xf400
2621+#define HW_MSDU_NUM_MAX 33
2622+ struct mt7996_dev *dev = dev_get_drvdata(s->private);
2623+ u32 ple_stat[HW_MSDU_NUM_MAX] = {0}, total_amsdu = 0;
2624+ u8 i;
2625+
2626+ for (i = 0; i < HW_MSDU_NUM_MAX; i++)
2627+ ple_stat[i] = mt76_rr(dev, HW_MSDU_CNT_ADDR + i * 0x04);
2628+
2629+ seq_printf(s, "TXD counter status of MSDU:\n");
2630+
2631+ for (i = 0; i < HW_MSDU_NUM_MAX; i++)
2632+ total_amsdu += ple_stat[i];
2633+
2634+ for (i = 0; i < HW_MSDU_NUM_MAX; i++) {
2635+ seq_printf(s, "AMSDU pack count of %d MSDU in TXD: 0x%x ", i, ple_stat[i]);
2636+ if (total_amsdu != 0)
2637+ seq_printf(s, "(%d%%)\n", ple_stat[i] * 100 / total_amsdu);
2638+ else
2639+ seq_printf(s, "\n");
2640+ }
2641+
2642+ return 0;
2643+}
2644+
2645+/* DBG MODLE */
2646+static int
2647+mt7996_fw_debug_module_set(void *data, u64 module)
2648+{
2649+ struct mt7996_dev *dev = data;
2650+
2651+ dev->dbg.fw_dbg_module = module;
2652+ return 0;
2653+}
2654+
2655+static int
2656+mt7996_fw_debug_module_get(void *data, u64 *module)
2657+{
2658+ struct mt7996_dev *dev = data;
2659+
2660+ *module = dev->dbg.fw_dbg_module;
2661+ return 0;
2662+}
2663+
2664+DEFINE_DEBUGFS_ATTRIBUTE(fops_fw_debug_module, mt7996_fw_debug_module_get,
2665+ mt7996_fw_debug_module_set, "%lld\n");
2666+
2667+static int
2668+mt7996_fw_debug_level_set(void *data, u64 level)
2669+{
2670+ struct mt7996_dev *dev = data;
2671+
2672+ dev->dbg.fw_dbg_lv = level;
2673+ mt7996_mcu_fw_dbg_ctrl(dev, dev->dbg.fw_dbg_module, dev->dbg.fw_dbg_lv);
2674+ return 0;
2675+}
2676+
2677+static int
2678+mt7996_fw_debug_level_get(void *data, u64 *level)
2679+{
2680+ struct mt7996_dev *dev = data;
2681+
2682+ *level = dev->dbg.fw_dbg_lv;
2683+ return 0;
2684+}
2685+
2686+DEFINE_DEBUGFS_ATTRIBUTE(fops_fw_debug_level, mt7996_fw_debug_level_get,
2687+ mt7996_fw_debug_level_set, "%lld\n");
2688+
2689+/* usage: echo 0x[arg3][arg2][arg1] > fw_wa_set */
2690+static int
2691+mt7996_wa_set(void *data, u64 val)
2692+{
2693+ struct mt7996_dev *dev = data;
2694+ u32 arg1, arg2, arg3;
2695+
2696+ arg1 = FIELD_GET(GENMASK_ULL(7, 0), val);
2697+ arg2 = FIELD_GET(GENMASK_ULL(15, 8), val);
2698+ arg3 = FIELD_GET(GENMASK_ULL(23, 16), val);
2699+
2700+ return mt7996_mcu_wa_cmd(dev, MCU_WA_PARAM_CMD(SET),
2701+ arg1, arg2, arg3);
2702+}
2703+
2704+DEFINE_DEBUGFS_ATTRIBUTE(fops_wa_set, NULL, mt7996_wa_set,
2705+ "0x%llx\n");
2706+
2707+/* usage: echo 0x[arg3][arg2][arg1] > fw_wa_query */
2708+static int
2709+mt7996_wa_query(void *data, u64 val)
2710+{
2711+ struct mt7996_dev *dev = data;
2712+ u32 arg1, arg2, arg3;
2713+
2714+ arg1 = FIELD_GET(GENMASK_ULL(7, 0), val);
2715+ arg2 = FIELD_GET(GENMASK_ULL(15, 8), val);
2716+ arg3 = FIELD_GET(GENMASK_ULL(23, 16), val);
2717+
2718+ return mt7996_mcu_wa_cmd(dev, MCU_WA_PARAM_CMD(QUERY),
2719+ arg1, arg2, arg3);
2720+ return 0;
2721+}
2722+
2723+DEFINE_DEBUGFS_ATTRIBUTE(fops_wa_query, NULL, mt7996_wa_query,
2724+ "0x%llx\n");
2725+
2726+static int mt7996_dump_version(struct seq_file *s, void *data)
2727+{
2728+ struct mt7996_dev *dev = dev_get_drvdata(s->private);
developer788eba72023-09-26 07:25:33 +0800[diff] [blame]2729+ seq_printf(s, "Version: 3.3.14.0\n");
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]2730+
2731+ if (!test_bit(MT76_STATE_MCU_RUNNING, &dev->mphy.state))
2732+ return 0;
2733+
developer064da3c2023-06-13 15:57:26 +0800[diff] [blame]2734+ seq_printf(s, "Rom Patch Build Time: %.16s\n", dev->patch_build_date);
2735+ seq_printf(s, "WM Patch Build Time: %.15s, Mode: %s\n",
2736+ dev->ram_build_date[MT7996_RAM_TYPE_WM],
2737+ dev->testmode_enable ? "Testmode" : "Normal mode");
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]2738+ seq_printf(s, "WA Patch Build Time: %.15s\n",
developer064da3c2023-06-13 15:57:26 +0800[diff] [blame]2739+ dev->ram_build_date[MT7996_RAM_TYPE_WA]);
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]2740+ seq_printf(s, "DSP Patch Build Time: %.15s\n",
developer064da3c2023-06-13 15:57:26 +0800[diff] [blame]2741+ dev->ram_build_date[MT7996_RAM_TYPE_DSP]);
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]2742+ return 0;
2743+}
2744+
developer064da3c2023-06-13 15:57:26 +0800[diff] [blame]2745+/* fw wm call trace info dump */
2746+void mt7996_show_lp_history(struct seq_file *s, u32 type)
2747+{
2748+ struct mt7996_dev *dev = dev_get_drvdata(s->private);
2749+ struct mt7996_crash_data *crash_data;
2750+ struct mt7996_coredump *dump;
2751+ u64 now = 0;
2752+ int i = 0;
2753+ u8 fw_type = !!type;
2754+
2755+ mutex_lock(&dev->dump_mutex);
2756+
2757+ crash_data = mt7996_coredump_new(dev, fw_type);
2758+ if (!crash_data) {
2759+ mutex_unlock(&dev->dump_mutex);
2760+ seq_printf(s, "the coredump is disable!\n");
2761+ return;
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]2762+ }
developer064da3c2023-06-13 15:57:26 +0800[diff] [blame]2763+ mutex_unlock(&dev->dump_mutex);
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]2764+
developer064da3c2023-06-13 15:57:26 +0800[diff] [blame]2765+ dump = mt7996_coredump_build(dev, fw_type, false);
2766+ if (!dump) {
2767+ seq_printf(s, "no call stack data found!\n");
2768+ return;
2769+ }
2770+
2771+ seq_printf(s, "\x1b[32m%s log output\x1b[0m\n", dump->fw_type);
2772+ seq_printf(s, "\x1b[32mfw status: %s\n", dump->fw_state);
2773+ mt7996_dump_version(s, NULL);
2774+ /* PC log */
2775+ now = jiffies;
2776+ for (i = 0; i < 10; i++)
2777+ seq_printf(s, "\tCurrent PC=%x\n", dump->pc_cur[i]);
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]2778+
developer064da3c2023-06-13 15:57:26 +0800[diff] [blame]2779+ seq_printf(s, "PC log contorl=0x%x(T=%llu)(latest PC index = 0x%x)\n",
2780+ dump->pc_dbg_ctrl, now, dump->pc_cur_idx);
2781+ for (i = 0; i < 32; i++)
2782+ seq_printf(s, "\tPC log(%d)=0x%08x\n", i, dump->pc_stack[i]);
2783+
2784+ /* LR log */
2785+ now = jiffies;
2786+ seq_printf(s, "\nLR log contorl=0x%x(T=%llu)(latest LR index = 0x%x)\n",
2787+ dump->lr_dbg_ctrl, now, dump->lr_cur_idx);
2788+ for (i = 0; i < 32; i++)
2789+ seq_printf(s, "\tLR log(%d)=0x%08x\n", i, dump->lr_stack[i]);
2790+
2791+ vfree(dump);
2792+}
2793+
2794+static int mt7996_fw_wa_info_read(struct seq_file *s, void *data)
2795+{
2796+ seq_printf(s, "======[ShowPcLpHistory]======\n");
2797+ mt7996_show_lp_history(s, MT7996_RAM_TYPE_WA);
2798+ seq_printf(s, "======[End ShowPcLpHistory]==\n");
2799+
2800+ return 0;
2801+}
2802+
2803+static int mt7996_fw_wm_info_read(struct seq_file *s, void *data)
2804+{
2805+ seq_printf(s, "======[ShowPcLpHistory]======\n");
2806+ mt7996_show_lp_history(s, MT7996_RAM_TYPE_WM);
2807+ seq_printf(s, "======[End ShowPcLpHistory]==\n");
2808+
2809+ return 0;
2810+}
2811+
2812+/* dma info dump */
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]2813+static void
2814+dump_dma_tx_ring_info(struct seq_file *s, struct mt7996_dev *dev, char *str1, char *str2, u32 ring_base)
2815+{
2816+ u32 base, cnt, cidx, didx, queue_cnt;
2817+
2818+ base= mt76_rr(dev, ring_base);
2819+ cnt = mt76_rr(dev, ring_base + 4);
2820+ cidx = mt76_rr(dev, ring_base + 8);
2821+ didx = mt76_rr(dev, ring_base + 12);
2822+ queue_cnt = (cidx >= didx) ? (cidx - didx) : (cidx - didx + cnt);
2823+
2824+ seq_printf(s, "%20s %6s %10x %15x %10x %10x %10x\n", str1, str2, base, cnt, cidx, didx, queue_cnt);
2825+}
2826+
2827+static void
2828+dump_dma_rx_ring_info(struct seq_file *s, struct mt7996_dev *dev, char *str1, char *str2, u32 ring_base)
2829+{
2830+ u32 base, ctrl1, cnt, cidx, didx, queue_cnt;
2831+
2832+ base= mt76_rr(dev, ring_base);
2833+ ctrl1 = mt76_rr(dev, ring_base + 4);
2834+ cidx = mt76_rr(dev, ring_base + 8) & 0xfff;
2835+ didx = mt76_rr(dev, ring_base + 12) & 0xfff;
2836+ cnt = ctrl1 & 0xfff;
2837+ queue_cnt = (didx > cidx) ? (didx - cidx - 1) : (didx - cidx + cnt - 1);
2838+
2839+ seq_printf(s, "%20s %6s %10x %10x(%3x) %10x %10x %10x\n",
2840+ str1, str2, base, ctrl1, cnt, cidx, didx, queue_cnt);
2841+}
2842+
2843+static void
2844+mt7996_show_dma_info(struct seq_file *s, struct mt7996_dev *dev)
2845+{
2846+ u32 sys_ctrl[10];
2847+
2848+ /* HOST DMA0 information */
2849+ sys_ctrl[0] = mt76_rr(dev, WF_WFDMA_HOST_DMA0_HOST_INT_STA_ADDR);
2850+ sys_ctrl[1] = mt76_rr(dev, WF_WFDMA_HOST_DMA0_HOST_INT_ENA_ADDR);
2851+ sys_ctrl[2] = mt76_rr(dev, WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_ADDR);
2852+
2853+ seq_printf(s, "HOST_DMA Configuration\n");
2854+ seq_printf(s, "%10s %10s %10s %10s %10s %10s\n",
2855+ "DMA", "IntCSR", "IntMask", "Glocfg", "Tx/RxEn", "Tx/RxBusy");
2856+ seq_printf(s, "%10s %10x %10x %10x %4x/%5x %4x/%5x\n",
2857+ "DMA0", sys_ctrl[0], sys_ctrl[1], sys_ctrl[2],
2858+ (sys_ctrl[2] & WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_TX_DMA_EN_MASK)
2859+ >> WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_TX_DMA_EN_SHFT,
2860+ (sys_ctrl[2] & WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_RX_DMA_EN_MASK)
2861+ >> WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_RX_DMA_EN_SHFT,
2862+ (sys_ctrl[2] & WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK)
2863+ >> WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT,
2864+ (sys_ctrl[2] & WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK)
2865+ >> WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT);
2866+
2867+ if (dev->hif2) {
2868+ /* HOST DMA1 information */
2869+ sys_ctrl[0] = mt76_rr(dev, WF_WFDMA_HOST_DMA0_PCIE1_HOST_INT_STA_ADDR);
2870+ sys_ctrl[1] = mt76_rr(dev, WF_WFDMA_HOST_DMA0_PCIE1_HOST_INT_ENA_ADDR);
2871+ sys_ctrl[2] = mt76_rr(dev, WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_GLO_CFG_ADDR);
2872+
2873+ seq_printf(s, "%10s %10x %10x %10x %4x/%5x %4x/%5x\n",
2874+ "DMA0P1", sys_ctrl[0], sys_ctrl[1], sys_ctrl[2],
2875+ (sys_ctrl[2] & WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_GLO_CFG_TX_DMA_EN_MASK)
2876+ >> WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_GLO_CFG_TX_DMA_EN_SHFT,
2877+ (sys_ctrl[2] & WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_GLO_CFG_RX_DMA_EN_MASK)
2878+ >> WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_GLO_CFG_RX_DMA_EN_SHFT,
2879+ (sys_ctrl[2] & WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK)
2880+ >> WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT,
2881+ (sys_ctrl[2] & WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK)
2882+ >> WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT);
2883+ }
2884+
2885+ seq_printf(s, "HOST_DMA0 Ring Configuration\n");
2886+ seq_printf(s, "%20s %6s %10s %15s %10s %10s %10s\n",
2887+ "Name", "Used", "Base", "Ctrl1(Cnt)", "CIDX", "DIDX", "QCnt");
2888+ dump_dma_tx_ring_info(s, dev, "T0:TXD0(H2MAC)", "STA",
2889+ WF_WFDMA_HOST_DMA0_WPDMA_TX_RING0_CTRL0_ADDR);
2890+ dump_dma_tx_ring_info(s, dev, "T1:TXD1(H2MAC)", "STA",
2891+ WF_WFDMA_HOST_DMA0_WPDMA_TX_RING1_CTRL0_ADDR);
2892+ dump_dma_tx_ring_info(s, dev, "T2:TXD2(H2MAC)", "STA",
2893+ WF_WFDMA_HOST_DMA0_WPDMA_TX_RING2_CTRL0_ADDR);
2894+ dump_dma_tx_ring_info(s, dev, "T3:", "STA",
2895+ WF_WFDMA_HOST_DMA0_WPDMA_TX_RING3_CTRL0_ADDR);
2896+ dump_dma_tx_ring_info(s, dev, "T4:", "STA",
2897+ WF_WFDMA_HOST_DMA0_WPDMA_TX_RING4_CTRL0_ADDR);
2898+ dump_dma_tx_ring_info(s, dev, "T5:", "STA",
2899+ WF_WFDMA_HOST_DMA0_WPDMA_TX_RING5_CTRL0_ADDR);
2900+ dump_dma_tx_ring_info(s, dev, "T6:", "STA",
2901+ WF_WFDMA_HOST_DMA0_WPDMA_TX_RING6_CTRL0_ADDR);
2902+ dump_dma_tx_ring_info(s, dev, "T16:FWDL", "Both",
2903+ WF_WFDMA_HOST_DMA0_WPDMA_TX_RING16_CTRL0_ADDR);
2904+ dump_dma_tx_ring_info(s, dev, "T17:Cmd(H2WM)", "Both",
2905+ WF_WFDMA_HOST_DMA0_WPDMA_TX_RING17_CTRL0_ADDR);
2906+ dump_dma_tx_ring_info(s, dev, "T18:TXD0(H2WA)", "AP",
2907+ WF_WFDMA_HOST_DMA0_WPDMA_TX_RING18_CTRL0_ADDR);
2908+ dump_dma_tx_ring_info(s, dev, "T19:TXD1(H2WA)", "AP",
2909+ WF_WFDMA_HOST_DMA0_WPDMA_TX_RING19_CTRL0_ADDR);
2910+ dump_dma_tx_ring_info(s, dev, "T20:Cmd(H2WA)", "AP",
2911+ WF_WFDMA_HOST_DMA0_WPDMA_TX_RING20_CTRL0_ADDR);
2912+ dump_dma_tx_ring_info(s, dev, "T21:TXD2(H2WA)", "AP",
2913+ WF_WFDMA_HOST_DMA0_WPDMA_TX_RING21_CTRL0_ADDR);
2914+ dump_dma_tx_ring_info(s, dev, "T22:TXD3(H2WA)", "AP",
2915+ WF_WFDMA_HOST_DMA0_WPDMA_TX_RING22_CTRL0_ADDR);
2916+
2917+
2918+ dump_dma_rx_ring_info(s, dev, "R0:Event(WM2H)", "Both",
2919+ WF_WFDMA_HOST_DMA0_WPDMA_RX_RING0_CTRL0_ADDR);
2920+ dump_dma_rx_ring_info(s, dev, "R1:Event(WA2H)", "AP",
2921+ WF_WFDMA_HOST_DMA0_WPDMA_RX_RING1_CTRL0_ADDR);
2922+ dump_dma_rx_ring_info(s, dev, "R2:TxDone0(WA2H)", "AP",
2923+ WF_WFDMA_HOST_DMA0_WPDMA_RX_RING2_CTRL0_ADDR);
2924+ dump_dma_rx_ring_info(s, dev, "R3:TxDone1(WA2H)", "AP",
2925+ WF_WFDMA_HOST_DMA0_WPDMA_RX_RING3_CTRL0_ADDR);
2926+ dump_dma_rx_ring_info(s, dev, "R4:Data0(MAC2H)", "Both",
2927+ WF_WFDMA_HOST_DMA0_WPDMA_RX_RING4_CTRL0_ADDR);
2928+ dump_dma_rx_ring_info(s, dev, "R5:Data1(MAC2H)", "Both",
2929+ WF_WFDMA_HOST_DMA0_WPDMA_RX_RING5_CTRL0_ADDR);
2930+ dump_dma_rx_ring_info(s, dev, "R6:BUF1(MAC2H)", "Both",
2931+ WF_WFDMA_HOST_DMA0_WPDMA_RX_RING6_CTRL0_ADDR);
2932+ dump_dma_rx_ring_info(s, dev, "R7:TxDone1(MAC2H)", "Both",
2933+ WF_WFDMA_HOST_DMA0_WPDMA_RX_RING7_CTRL0_ADDR);
2934+ dump_dma_rx_ring_info(s, dev, "R8:BUF0(MAC2H)", "Both",
2935+ WF_WFDMA_HOST_DMA0_WPDMA_RX_RING8_CTRL0_ADDR);
2936+ dump_dma_rx_ring_info(s, dev, "R9:TxDone0(MAC2H)", "Both",
2937+ WF_WFDMA_HOST_DMA0_WPDMA_RX_RING9_CTRL0_ADDR);
2938+ dump_dma_rx_ring_info(s, dev, "R10:MSDU_PG0(MAC2H)", "Both",
2939+ WF_WFDMA_HOST_DMA0_WPDMA_RX_RING10_CTRL0_ADDR);
2940+ dump_dma_rx_ring_info(s, dev, "R11:MSDU_PG1(MAC2H)", "Both",
2941+ WF_WFDMA_HOST_DMA0_WPDMA_RX_RING11_CTRL0_ADDR);
2942+ dump_dma_rx_ring_info(s, dev, "R12:MSDU_PG2(MAC2H)", "Both",
2943+ WF_WFDMA_HOST_DMA0_WPDMA_RX_RING12_CTRL0_ADDR);
2944+ dump_dma_rx_ring_info(s, dev, "IND:IND_CMD(MAC2H)", "Both",
2945+ WF_RRO_TOP_IND_CMD_0_CTRL0_ADDR);
2946+
2947+ if (dev->hif2) {
2948+ seq_printf(s, "HOST_DMA0 PCIe1 Ring Configuration\n");
2949+ seq_printf(s, "%20s %6s %10s %15s %10s %10s %10s\n",
2950+ "Name", "Used", "Base", "Ctrl1(Cnt)", "CIDX", "DIDX", "QCnt");
2951+ dump_dma_tx_ring_info(s, dev, "T21:TXD2(H2WA)", "AP",
2952+ WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_TX_RING21_CTRL0_ADDR);
2953+ dump_dma_tx_ring_info(s, dev, "T22:TXD?(H2WA)", "AP",
2954+ WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_TX_RING22_CTRL0_ADDR);
2955+
2956+ dump_dma_rx_ring_info(s, dev, "R3:TxDone1(WA2H)", "AP",
2957+ WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_RX_RING3_CTRL0_ADDR);
2958+ dump_dma_rx_ring_info(s, dev, "R5:Data1(MAC2H)", "Both",
2959+ WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_RX_RING5_CTRL0_ADDR);
2960+ dump_dma_rx_ring_info(s, dev, "R6:BUF1(MAC2H)", "Both",
2961+ WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_RX_RING6_CTRL0_ADDR);
2962+ dump_dma_rx_ring_info(s, dev, "R7:TxDone1(MAC2H)", "Both",
2963+ WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_RX_RING7_CTRL0_ADDR);
2964+ }
2965+
2966+ /* MCU DMA information */
2967+ sys_ctrl[0] = mt76_rr(dev, WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_ADDR);
2968+ sys_ctrl[1] = mt76_rr(dev, WF_WFDMA_MCU_DMA0_HOST_INT_STA_ADDR);
2969+ sys_ctrl[2] = mt76_rr(dev, WF_WFDMA_MCU_DMA0_HOST_INT_ENA_ADDR);
2970+
2971+ seq_printf(s, "MCU_DMA Configuration\n");
2972+ seq_printf(s, "%10s %10s %10s %10s %10s %10s\n",
2973+ "DMA", "IntCSR", "IntMask", "Glocfg", "Tx/RxEn", "Tx/RxBusy");
2974+ seq_printf(s, "%10s %10x %10x %10x %4x/%5x %4x/%5x\n",
2975+ "DMA0", sys_ctrl[1], sys_ctrl[2], sys_ctrl[0],
2976+ (sys_ctrl[0] & WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_EN_MASK)
2977+ >> WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_EN_SHFT,
2978+ (sys_ctrl[0] & WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_EN_MASK)
2979+ >> WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_EN_SHFT,
2980+ (sys_ctrl[0] & WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK)
2981+ >> WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT,
2982+ (sys_ctrl[0] & WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK)
2983+ >> WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT);
2984+
2985+ seq_printf(s, "MCU_DMA0 Ring Configuration\n");
2986+ seq_printf(s, "%20s %6s %10s %15s %10s %10s %10s\n",
2987+ "Name", "Used", "Base", "Cnt", "CIDX", "DIDX", "QCnt");
2988+ dump_dma_tx_ring_info(s, dev, "T0:Event(WM2H)", "Both",
2989+ WF_WFDMA_MCU_DMA0_WPDMA_TX_RING0_CTRL0_ADDR);
2990+ dump_dma_tx_ring_info(s, dev, "T1:Event(WA2H)", "AP",
2991+ WF_WFDMA_MCU_DMA0_WPDMA_TX_RING1_CTRL0_ADDR);
2992+ dump_dma_tx_ring_info(s, dev, "T2:TxDone0(WA2H)", "AP",
2993+ WF_WFDMA_MCU_DMA0_WPDMA_TX_RING2_CTRL0_ADDR);
2994+ dump_dma_tx_ring_info(s, dev, "T3:TxDone1(WA2H)", "AP",
2995+ WF_WFDMA_MCU_DMA0_WPDMA_TX_RING3_CTRL0_ADDR);
2996+ dump_dma_tx_ring_info(s, dev, "T4:TXD(WM2MAC)", "Both",
2997+ WF_WFDMA_MCU_DMA0_WPDMA_TX_RING4_CTRL0_ADDR);
2998+ dump_dma_tx_ring_info(s, dev, "T5:TXCMD(WM2MAC)", "Both",
2999+ WF_WFDMA_MCU_DMA0_WPDMA_TX_RING5_CTRL0_ADDR);
3000+ dump_dma_tx_ring_info(s, dev, "T6:TXD(WA2MAC)", "AP",
3001+ WF_WFDMA_MCU_DMA0_WPDMA_TX_RING6_CTRL0_ADDR);
3002+ dump_dma_rx_ring_info(s, dev, "R0:FWDL", "Both",
3003+ WF_WFDMA_MCU_DMA0_WPDMA_RX_RING0_CTRL0_ADDR);
3004+ dump_dma_rx_ring_info(s, dev, "R1:Cmd(H2WM)", "Both",
3005+ WF_WFDMA_MCU_DMA0_WPDMA_RX_RING1_CTRL0_ADDR);
3006+ dump_dma_rx_ring_info(s, dev, "R2:TXD0(H2WA)", "AP",
3007+ WF_WFDMA_MCU_DMA0_WPDMA_RX_RING2_CTRL0_ADDR);
3008+ dump_dma_rx_ring_info(s, dev, "R3:TXD1(H2WA)", "AP",
3009+ WF_WFDMA_MCU_DMA0_WPDMA_RX_RING3_CTRL0_ADDR);
3010+ dump_dma_rx_ring_info(s, dev, "R4:Cmd(H2WA)", "AP",
3011+ WF_WFDMA_MCU_DMA0_WPDMA_RX_RING4_CTRL0_ADDR);
3012+ dump_dma_rx_ring_info(s, dev, "R5:Data0(MAC2WM)", "Both",
3013+ WF_WFDMA_MCU_DMA0_WPDMA_RX_RING5_CTRL0_ADDR);
3014+ dump_dma_rx_ring_info(s, dev, "R6:TxDone(MAC2WM)", "Both",
3015+ WF_WFDMA_MCU_DMA0_WPDMA_RX_RING6_CTRL0_ADDR);
3016+ dump_dma_rx_ring_info(s, dev, "R7:SPL/RPT(MAC2WM)", "Both",
3017+ WF_WFDMA_MCU_DMA0_WPDMA_RX_RING7_CTRL0_ADDR);
3018+ dump_dma_rx_ring_info(s, dev, "R8:TxDone(MAC2WA)", "AP",
3019+ WF_WFDMA_MCU_DMA0_WPDMA_RX_RING8_CTRL0_ADDR);
3020+ dump_dma_rx_ring_info(s, dev, "R9:Data1(MAC2WM)", "Both",
3021+ WF_WFDMA_MCU_DMA0_WPDMA_RX_RING9_CTRL0_ADDR);
3022+ dump_dma_rx_ring_info(s, dev, "R10:TXD2(H2WA)", "AP",
3023+ WF_WFDMA_MCU_DMA0_WPDMA_RX_RING10_CTRL0_ADDR);
3024+
3025+ /* MEM DMA information */
3026+ sys_ctrl[0] = mt76_rr(dev, WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_ADDR);
3027+ sys_ctrl[1] = mt76_rr(dev, WF_WFDMA_MEM_DMA_HOST_INT_STA_ADDR);
3028+ sys_ctrl[2] = mt76_rr(dev, WF_WFDMA_MEM_DMA_HOST_INT_ENA_ADDR);
3029+
3030+ seq_printf(s, "MEM_DMA Configuration\n");
3031+ seq_printf(s, "%10s %10s %10s %10s %10s %10s\n",
3032+ "DMA", "IntCSR", "IntMask", "Glocfg", "Tx/RxEn", "Tx/RxBusy");
3033+ seq_printf(s, "%10s %10x %10x %10x %4x/%5x %4x/%5x\n",
3034+ "MEM", sys_ctrl[1], sys_ctrl[2], sys_ctrl[0],
3035+ (sys_ctrl[0] & WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_EN_MASK)
3036+ >> WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_EN_SHFT,
3037+ (sys_ctrl[0] & WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_EN_MASK)
3038+ >> WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_EN_SHFT,
3039+ (sys_ctrl[0] & WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK)
3040+ >> WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT,
3041+ (sys_ctrl[0] & WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK)
3042+ >> WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT);
3043+
3044+ seq_printf(s, "MEM_DMA Ring Configuration\n");
3045+ seq_printf(s, "%20s %6s %10s %10s %10s %10s %10s\n",
3046+ "Name", "Used", "Base", "Cnt", "CIDX", "DIDX", "QCnt");
3047+ dump_dma_tx_ring_info(s, dev, "T0:CmdEvent(WM2WA)", "AP",
3048+ WF_WFDMA_MEM_DMA_WPDMA_TX_RING0_CTRL0_ADDR);
3049+ dump_dma_tx_ring_info(s, dev, "T1:CmdEvent(WA2WM)", "AP",
3050+ WF_WFDMA_MEM_DMA_WPDMA_TX_RING1_CTRL0_ADDR);
3051+ dump_dma_rx_ring_info(s, dev, "R0:CmdEvent(WM2WA)", "AP",
3052+ WF_WFDMA_MEM_DMA_WPDMA_RX_RING0_CTRL0_ADDR);
3053+ dump_dma_rx_ring_info(s, dev, "R1:CmdEvent(WA2WM)", "AP",
3054+ WF_WFDMA_MEM_DMA_WPDMA_RX_RING1_CTRL0_ADDR);
3055+}
3056+
3057+static int mt7996_trinfo_read(struct seq_file *s, void *data)
3058+{
3059+ struct mt7996_dev *dev = dev_get_drvdata(s->private);
3060+ mt7996_show_dma_info(s, dev);
3061+ return 0;
3062+}
3063+
3064+/* MIB INFO */
3065+static int mt7996_mibinfo_read_per_band(struct seq_file *s, int band_idx)
3066+{
3067+#define BSS_NUM 4
3068+ struct mt7996_dev *dev = dev_get_drvdata(s->private);
3069+ u8 bss_nums = BSS_NUM;
3070+ u32 idx;
3071+ u32 mac_val, band_offset = 0, band_offset_umib = 0;
3072+ u32 msdr6, msdr9, msdr18;
3073+ u32 rvsr0, rscr26, rscr35, mctr5, mctr6, msr0, msr1, msr2;
3074+ u32 tbcr0, tbcr1, tbcr2, tbcr3, tbcr4;
3075+ u32 btscr[7];
3076+ u32 tdrcr[5];
3077+ u32 mbtocr[16], mbtbcr[16], mbrocr[16], mbrbcr[16];
3078+ u32 btcr, btbcr, brocr, brbcr, btdcr, brdcr;
3079+ u32 mu_cnt[5];
3080+ u32 ampdu_cnt[3];
3081+ u64 per;
3082+
3083+ switch (band_idx) {
3084+ case 0:
3085+ band_offset = 0;
3086+ band_offset_umib = 0;
3087+ break;
3088+ case 1:
3089+ band_offset = BN1_WF_MIB_TOP_BASE - BN0_WF_MIB_TOP_BASE;
3090+ band_offset_umib = WF_UMIB_TOP_B1BROCR_ADDR - WF_UMIB_TOP_B0BROCR_ADDR;
3091+ break;
3092+ case 2:
3093+ band_offset = IP1_BN0_WF_MIB_TOP_BASE - BN0_WF_MIB_TOP_BASE;
3094+ band_offset_umib = WF_UMIB_TOP_B2BROCR_ADDR - WF_UMIB_TOP_B0BROCR_ADDR;
3095+ break;
3096+ default:
3097+ return true;
3098+ }
3099+
3100+ seq_printf(s, "Band %d MIB Status\n", band_idx);
3101+ seq_printf(s, "===============================\n");
3102+ mac_val = mt76_rr(dev, BN0_WF_MIB_TOP_M0SCR0_ADDR + band_offset);
3103+ seq_printf(s, "MIB Status Control=0x%x\n", mac_val);
3104+
3105+ msdr6 = mt76_rr(dev, BN0_WF_MIB_TOP_M0SDR6_ADDR + band_offset);
3106+ rvsr0 = mt76_rr(dev, BN0_WF_MIB_TOP_RVSR0_ADDR + band_offset);
3107+ rscr35 = mt76_rr(dev, BN0_WF_MIB_TOP_RSCR35_ADDR + band_offset);
3108+ msdr9 = mt76_rr(dev, BN0_WF_MIB_TOP_M0SDR9_ADDR + band_offset);
3109+ rscr26 = mt76_rr(dev, BN0_WF_MIB_TOP_RSCR26_ADDR + band_offset);
3110+ mctr5 = mt76_rr(dev, BN0_WF_MIB_TOP_MCTR5_ADDR + band_offset);
3111+ mctr6 = mt76_rr(dev, BN0_WF_MIB_TOP_MCTR6_ADDR + band_offset);
3112+ msdr18 = mt76_rr(dev, BN0_WF_MIB_TOP_M0SDR18_ADDR + band_offset);
3113+ msr0 = mt76_rr(dev, BN0_WF_MIB_TOP_MSR0_ADDR + band_offset);
3114+ msr1 = mt76_rr(dev, BN0_WF_MIB_TOP_MSR1_ADDR + band_offset);
3115+ msr2 = mt76_rr(dev, BN0_WF_MIB_TOP_MSR2_ADDR + band_offset);
3116+ ampdu_cnt[0] = mt76_rr(dev, BN0_WF_MIB_TOP_TSCR0_ADDR + band_offset);
3117+ ampdu_cnt[1] = mt76_rr(dev, BN0_WF_MIB_TOP_TSCR3_ADDR + band_offset);
3118+ ampdu_cnt[2] = mt76_rr(dev, BN0_WF_MIB_TOP_TSCR4_ADDR + band_offset);
3119+ ampdu_cnt[1] &= BN0_WF_MIB_TOP_TSCR3_AMPDU_MPDU_COUNT_MASK;
3120+ ampdu_cnt[2] &= BN0_WF_MIB_TOP_TSCR4_AMPDU_ACKED_COUNT_MASK;
3121+
3122+ seq_printf(s, "===Phy/Timing Related Counters===\n");
3123+ seq_printf(s, "\tChannelIdleCnt=0x%x\n",
3124+ msdr6 & BN0_WF_MIB_TOP_M0SDR6_CHANNEL_IDLE_COUNT_MASK);
3125+ seq_printf(s, "\tCCA_NAV_Tx_Time=0x%x\n",
3126+ msdr9 & BN0_WF_MIB_TOP_M0SDR9_CCA_NAV_TX_TIME_MASK);
3127+ seq_printf(s, "\tRx_MDRDY_CNT=0x%x\n",
3128+ rscr26 & BN0_WF_MIB_TOP_RSCR26_RX_MDRDY_COUNT_MASK);
3129+ seq_printf(s, "\tCCK_MDRDY_TIME=0x%x, OFDM_MDRDY_TIME=0x%x",
3130+ msr0 & BN0_WF_MIB_TOP_MSR0_CCK_MDRDY_TIME_MASK,
3131+ msr1 & BN0_WF_MIB_TOP_MSR1_OFDM_LG_MIXED_VHT_MDRDY_TIME_MASK);
3132+ seq_printf(s, ", OFDM_GREEN_MDRDY_TIME=0x%x\n",
3133+ msr2 & BN0_WF_MIB_TOP_MSR2_OFDM_GREEN_MDRDY_TIME_MASK);
3134+ seq_printf(s, "\tPrim CCA Time=0x%x\n",
3135+ mctr5 & BN0_WF_MIB_TOP_MCTR5_P_CCA_TIME_MASK);
3136+ seq_printf(s, "\tSec CCA Time=0x%x\n",
3137+ mctr6 & BN0_WF_MIB_TOP_MCTR6_S_CCA_TIME_MASK);
3138+ seq_printf(s, "\tPrim ED Time=0x%x\n",
3139+ msdr18 & BN0_WF_MIB_TOP_M0SDR18_P_ED_TIME_MASK);
3140+
3141+ seq_printf(s, "===Tx Related Counters(Generic)===\n");
3142+ mac_val = mt76_rr(dev, BN0_WF_MIB_TOP_TSCR18_ADDR + band_offset);
3143+ dev->dbg.bcn_total_cnt[band_idx] +=
3144+ (mac_val & BN0_WF_MIB_TOP_TSCR18_BEACONTXCOUNT_MASK);
3145+ seq_printf(s, "\tBeaconTxCnt=0x%x\n", dev->dbg.bcn_total_cnt[band_idx]);
3146+ dev->dbg.bcn_total_cnt[band_idx] = 0;
3147+
3148+ tbcr0 = mt76_rr(dev, BN0_WF_MIB_TOP_TBCR0_ADDR + band_offset);
3149+ seq_printf(s, "\tTx 20MHz Cnt=0x%x\n",
3150+ tbcr0 & BN0_WF_MIB_TOP_TBCR0_TX_20MHZ_CNT_MASK);
3151+ tbcr1 = mt76_rr(dev, BN0_WF_MIB_TOP_TBCR1_ADDR + band_offset);
3152+ seq_printf(s, "\tTx 40MHz Cnt=0x%x\n",
3153+ tbcr1 & BN0_WF_MIB_TOP_TBCR1_TX_40MHZ_CNT_MASK);
3154+ tbcr2 = mt76_rr(dev, BN0_WF_MIB_TOP_TBCR2_ADDR + band_offset);
3155+ seq_printf(s, "\tTx 80MHz Cnt=0x%x\n",
3156+ tbcr2 & BN0_WF_MIB_TOP_TBCR2_TX_80MHZ_CNT_MASK);
3157+ tbcr3 = mt76_rr(dev, BN0_WF_MIB_TOP_TBCR3_ADDR + band_offset);
3158+ seq_printf(s, "\tTx 160MHz Cnt=0x%x\n",
3159+ tbcr3 & BN0_WF_MIB_TOP_TBCR3_TX_160MHZ_CNT_MASK);
3160+ tbcr4 = mt76_rr(dev, BN0_WF_MIB_TOP_TBCR4_ADDR + band_offset);
3161+ seq_printf(s, "\tTx 320MHz Cnt=0x%x\n",
3162+ tbcr4 & BN0_WF_MIB_TOP_TBCR4_TX_320MHZ_CNT_MASK);
3163+ seq_printf(s, "\tAMPDU Cnt=0x%x\n", ampdu_cnt[0]);
3164+ seq_printf(s, "\tAMPDU MPDU Cnt=0x%x\n", ampdu_cnt[1]);
3165+ seq_printf(s, "\tAMPDU MPDU Ack Cnt=0x%x\n", ampdu_cnt[2]);
3166+ per = (ampdu_cnt[2] == 0 ?
3167+ 0 : 1000 * (ampdu_cnt[1] - ampdu_cnt[2]) / ampdu_cnt[1]);
3168+ seq_printf(s, "\tAMPDU MPDU PER=%llu.%1llu%%\n", per / 10, per % 10);
3169+
3170+ seq_printf(s, "===MU Related Counters===\n");
3171+ mu_cnt[0] = mt76_rr(dev, BN0_WF_MIB_TOP_BSCR2_ADDR + band_offset);
3172+ mu_cnt[1] = mt76_rr(dev, BN0_WF_MIB_TOP_TSCR5_ADDR + band_offset);
3173+ mu_cnt[2] = mt76_rr(dev, BN0_WF_MIB_TOP_TSCR6_ADDR + band_offset);
3174+ mu_cnt[3] = mt76_rr(dev, BN0_WF_MIB_TOP_TSCR8_ADDR + band_offset);
3175+ mu_cnt[4] = mt76_rr(dev, BN0_WF_MIB_TOP_TSCR7_ADDR + band_offset);
3176+
3177+ seq_printf(s, "\tMUBF_TX_COUNT=0x%x\n",
3178+ mu_cnt[0] & BN0_WF_MIB_TOP_BSCR2_MUBF_TX_COUNT_MASK);
3179+ seq_printf(s, "\tMU_TX_MPDU_COUNT(Ok+Fail)=0x%x\n", mu_cnt[1]);
3180+ seq_printf(s, "\tMU_TX_OK_MPDU_COUNT=0x%x\n", mu_cnt[2]);
3181+ seq_printf(s, "\tMU_TO_MU_FAIL_PPDU_COUNT=0x%x\n", mu_cnt[3]);
3182+ seq_printf(s, "\tSU_TX_OK_MPDU_COUNT=0x%x\n", mu_cnt[4]);
3183+
3184+ seq_printf(s, "===Rx Related Counters(Generic)===\n");
3185+ seq_printf(s, "\tVector Mismacth Cnt=0x%x\n",
3186+ rvsr0 & BN0_WF_MIB_TOP_RVSR0_VEC_MISS_COUNT_MASK);
3187+ seq_printf(s, "\tDelimiter Fail Cnt=0x%x\n",
3188+ rscr35 & BN0_WF_MIB_TOP_RSCR35_DELIMITER_FAIL_COUNT_MASK);
3189+
3190+ mac_val = mt76_rr(dev, BN0_WF_MIB_TOP_RSCR1_ADDR + band_offset);
3191+ seq_printf(s, "\tRxFCSErrCnt=0x%x\n",
3192+ (mac_val & BN0_WF_MIB_TOP_RSCR1_RX_FCS_ERROR_COUNT_MASK));
3193+ mac_val = mt76_rr(dev, BN0_WF_MIB_TOP_RSCR33_ADDR + band_offset);
3194+ seq_printf(s, "\tRxFifoFullCnt=0x%x\n",
3195+ (mac_val & BN0_WF_MIB_TOP_RSCR33_RX_FIFO_FULL_COUNT_MASK));
3196+ mac_val = mt76_rr(dev, BN0_WF_MIB_TOP_RSCR36_ADDR + band_offset);
3197+ seq_printf(s, "\tRxLenMismatch=0x%x\n",
3198+ (mac_val & BN0_WF_MIB_TOP_RSCR36_RX_LEN_MISMATCH_MASK));
3199+ mac_val = mt76_rr(dev, BN0_WF_MIB_TOP_RSCR31_ADDR + band_offset);
3200+ seq_printf(s, "\tRxMPDUCnt=0x%x\n",
3201+ (mac_val & BN0_WF_MIB_TOP_RSCR31_RX_MPDU_COUNT_MASK));
3202+ mac_val = mt76_rr(dev, BN0_WF_MIB_TOP_RSCR27_ADDR + band_offset);
3203+ seq_printf(s, "\tRx AMPDU Cnt=0x%x\n", mac_val);
3204+ mac_val = mt76_rr(dev, BN0_WF_MIB_TOP_RSCR28_ADDR + band_offset);
3205+ seq_printf(s, "\tRx Total ByteCnt=0x%x\n", mac_val);
3206+
3207+
3208+ /* Per-BSS T/RX Counters */
3209+ seq_printf(s, "===Per-BSS Related Tx/Rx Counters===\n");
3210+ seq_printf(s, "BSS Idx TxCnt/DataCnt TxByteCnt RxOkCnt/DataCnt RxByteCnt\n");
3211+ for (idx = 0; idx < bss_nums; idx++) {
3212+ btcr = mt76_rr(dev, BN0_WF_MIB_TOP_BTCR_ADDR + band_offset + idx * 4);
3213+ btdcr = mt76_rr(dev, BN0_WF_MIB_TOP_BTDCR_ADDR + band_offset + idx * 4);
3214+ btbcr = mt76_rr(dev, BN0_WF_MIB_TOP_BTBCR_ADDR + band_offset + idx * 4);
3215+
3216+ brocr = mt76_rr(dev, WF_UMIB_TOP_B0BROCR_ADDR + band_offset_umib + idx * 4);
3217+ brdcr = mt76_rr(dev, WF_UMIB_TOP_B0BRDCR_ADDR + band_offset_umib + idx * 4);
3218+ brbcr = mt76_rr(dev, WF_UMIB_TOP_B0BRBCR_ADDR + band_offset_umib + idx * 4);
3219+
3220+ seq_printf(s, "%d\t 0x%x/0x%x\t 0x%x \t 0x%x/0x%x \t 0x%x\n",
3221+ idx, btcr, btdcr, btbcr, brocr, brdcr, brbcr);
3222+ }
3223+
3224+ seq_printf(s, "===Per-BSS Related MIB Counters===\n");
3225+ seq_printf(s, "BSS Idx RTSTx/RetryCnt BAMissCnt AckFailCnt FrmRetry1/2/3Cnt\n");
3226+
3227+ /* Per-BSS TX Status */
3228+ for (idx = 0; idx < bss_nums; idx++) {
3229+ btscr[0] = mt76_rr(dev, BN0_WF_MIB_TOP_BTSCR5_ADDR + band_offset + idx * 4);
3230+ btscr[1] = mt76_rr(dev, BN0_WF_MIB_TOP_BTSCR6_ADDR + band_offset + idx * 4);
3231+ btscr[2] = mt76_rr(dev, BN0_WF_MIB_TOP_BTSCR0_ADDR + band_offset + idx * 4);
3232+ btscr[3] = mt76_rr(dev, BN0_WF_MIB_TOP_BTSCR1_ADDR + band_offset + idx * 4);
3233+ btscr[4] = mt76_rr(dev, BN0_WF_MIB_TOP_BTSCR2_ADDR + band_offset + idx * 4);
3234+ btscr[5] = mt76_rr(dev, BN0_WF_MIB_TOP_BTSCR3_ADDR + band_offset + idx * 4);
3235+ btscr[6] = mt76_rr(dev, BN0_WF_MIB_TOP_BTSCR4_ADDR + band_offset + idx * 4);
3236+
3237+ seq_printf(s, "%d:\t0x%x/0x%x 0x%x \t 0x%x \t 0x%x/0x%x/0x%x\n",
3238+ idx, (btscr[0] & BN0_WF_MIB_TOP_BTSCR5_RTSTXCOUNTn_MASK),
3239+ (btscr[1] & BN0_WF_MIB_TOP_BTSCR6_RTSRETRYCOUNTn_MASK),
3240+ (btscr[2] & BN0_WF_MIB_TOP_BTSCR0_BAMISSCOUNTn_MASK),
3241+ (btscr[3] & BN0_WF_MIB_TOP_BTSCR1_ACKFAILCOUNTn_MASK),
3242+ (btscr[4] & BN0_WF_MIB_TOP_BTSCR2_FRAMERETRYCOUNTn_MASK),
3243+ (btscr[5] & BN0_WF_MIB_TOP_BTSCR3_FRAMERETRY2COUNTn_MASK),
3244+ (btscr[6] & BN0_WF_MIB_TOP_BTSCR4_FRAMERETRY3COUNTn_MASK));
3245+ }
3246+
3247+ /* Dummy delimiter insertion result */
3248+ seq_printf(s, "===Dummy delimiter insertion result===\n");
3249+ tdrcr[0] = mt76_rr(dev, BN0_WF_MIB_TOP_TDRCR0_ADDR + band_offset);
3250+ tdrcr[1] = mt76_rr(dev, BN0_WF_MIB_TOP_TDRCR1_ADDR + band_offset);
3251+ tdrcr[2] = mt76_rr(dev, BN0_WF_MIB_TOP_TDRCR2_ADDR + band_offset);
3252+ tdrcr[3] = mt76_rr(dev, BN0_WF_MIB_TOP_TDRCR3_ADDR + band_offset);
3253+ tdrcr[4] = mt76_rr(dev, BN0_WF_MIB_TOP_TDRCR4_ADDR + band_offset);
3254+
3255+ seq_printf(s, "Range0 = %d\t Range1 = %d\t Range2 = %d\t Range3 = %d\t Range4 = %d\n",
3256+ tdrcr[0],
3257+ tdrcr[1],
3258+ tdrcr[2],
3259+ tdrcr[3],
3260+ tdrcr[4]);
3261+
3262+ /* Per-MBSS T/RX Counters */
3263+ seq_printf(s, "===Per-MBSS Related Tx/Rx Counters===\n");
3264+ seq_printf(s, "MBSSIdx TxOkCnt TxByteCnt RxOkCnt RxByteCnt\n");
3265+
3266+ for (idx = 0; idx < 16; idx++) {
3267+ mbtocr[idx] = mt76_rr(dev, BN0_WF_MIB_TOP_BTOCR_ADDR + band_offset + (bss_nums + idx) * 4);
3268+ mbtbcr[idx] = mt76_rr(dev, BN0_WF_MIB_TOP_BTBCR_ADDR + band_offset + (bss_nums + idx) * 4);
3269+
3270+ mbrocr[idx] = mt76_rr(dev, WF_UMIB_TOP_B0BROCR_ADDR + band_offset_umib + (bss_nums + idx) * 4);
3271+ mbrbcr[idx] = mt76_rr(dev, WF_UMIB_TOP_B0BRBCR_ADDR + band_offset_umib + (bss_nums + idx) * 4);
3272+ }
3273+
3274+ for (idx = 0; idx < 16; idx++) {
3275+ seq_printf(s, "%d\t 0x%x\t 0x%x \t 0x%x \t 0x%x\n",
3276+ idx, mbtocr[idx], mbtbcr[idx], mbrocr[idx], mbrbcr[idx]);
3277+ }
3278+
3279+ return 0;
3280+}
3281+
3282+static int mt7996_mibinfo_band0(struct seq_file *s, void *data)
3283+{
3284+ mt7996_mibinfo_read_per_band(s, MT_BAND0);
3285+ return 0;
3286+}
3287+
3288+static int mt7996_mibinfo_band1(struct seq_file *s, void *data)
3289+{
3290+ mt7996_mibinfo_read_per_band(s, MT_BAND1);
3291+ return 0;
3292+}
3293+
3294+static int mt7996_mibinfo_band2(struct seq_file *s, void *data)
3295+{
3296+ mt7996_mibinfo_read_per_band(s, MT_BAND2);
3297+ return 0;
3298+}
3299+
3300+/* WTBL INFO */
3301+static int
3302+mt7996_wtbl_read_raw(struct mt7996_dev *dev, u16 idx,
3303+ enum mt7996_wtbl_type type, u16 start_dw,
3304+ u16 len, void *buf)
3305+{
3306+ u32 *dest_cpy = (u32 *)buf;
3307+ u32 size_dw = len;
3308+ u32 src = 0;
3309+
3310+ if (!buf)
3311+ return 0xFF;
3312+
3313+ if (type == WTBL_TYPE_LMAC) {
3314+ mt76_wr(dev, MT_DBG_WTBLON_TOP_WDUCR_ADDR,
3315+ FIELD_PREP(MT_DBG_WTBLON_TOP_WDUCR_GROUP, (idx >> 7)));
3316+ src = LWTBL_IDX2BASE(idx, start_dw);
3317+ } else if (type == WTBL_TYPE_UMAC) {
3318+ mt76_wr(dev, MT_DBG_UWTBL_TOP_WDUCR_ADDR,
3319+ FIELD_PREP(MT_DBG_UWTBL_TOP_WDUCR_GROUP, (idx >> 7)));
3320+ src = UWTBL_IDX2BASE(idx, start_dw);
3321+ } else if (type == WTBL_TYPE_KEY) {
3322+ mt76_wr(dev, MT_DBG_UWTBL_TOP_WDUCR_ADDR,
3323+ MT_DBG_UWTBL_TOP_WDUCR_TARGET |
3324+ FIELD_PREP(MT_DBG_UWTBL_TOP_WDUCR_GROUP, (idx >> 7)));
3325+ src = KEYTBL_IDX2BASE(idx, start_dw);
3326+ }
3327+
3328+ while (size_dw--) {
3329+ *dest_cpy++ = mt76_rr(dev, src);
3330+ src += 4;
3331+ };
3332+
3333+ return 0;
3334+}
3335+
3336+#if 0
3337+static int
3338+mt7996_wtbl_write_raw(struct mt7996_dev *dev, u16 idx,
3339+ enum mt7996_wtbl_type type, u16 start_dw,
3340+ u32 val)
3341+{
3342+ u32 addr = 0;
3343+
3344+ if (type == WTBL_TYPE_LMAC) {
3345+ mt76_wr(dev, MT_DBG_WTBLON_TOP_WDUCR_ADDR,
3346+ FIELD_PREP(MT_DBG_WTBLON_TOP_WDUCR_GROUP, (idx >> 7)));
3347+ addr = LWTBL_IDX2BASE(idx, start_dw);
3348+ } else if (type == WTBL_TYPE_UMAC) {
3349+ mt76_wr(dev, MT_DBG_UWTBL_TOP_WDUCR_ADDR,
3350+ FIELD_PREP(MT_DBG_UWTBL_TOP_WDUCR_GROUP, (idx >> 7)));
3351+ addr = UWTBL_IDX2BASE(idx, start_dw);
3352+ } else if (type == WTBL_TYPE_KEY) {
3353+ mt76_wr(dev, MT_DBG_UWTBL_TOP_WDUCR_ADDR,
3354+ MT_DBG_UWTBL_TOP_WDUCR_TARGET |
3355+ FIELD_PREP(MT_DBG_UWTBL_TOP_WDUCR_GROUP, (idx >> 7)));
3356+ addr = KEYTBL_IDX2BASE(idx, start_dw);
3357+ }
3358+
3359+ mt76_wr(dev, addr, val);
3360+
3361+ return 0;
3362+}
3363+#endif
3364+
3365+static const struct berse_wtbl_parse WTBL_LMAC_DW0[] = {
3366+ {"MUAR_IDX", WF_LWTBL_MUAR_MASK, WF_LWTBL_MUAR_SHIFT,false},
3367+ {"RCA1", WF_LWTBL_RCA1_MASK, NO_SHIFT_DEFINE, false},
3368+ {"KID", WF_LWTBL_KID_MASK, WF_LWTBL_KID_SHIFT, false},
3369+ {"RCID", WF_LWTBL_RCID_MASK, NO_SHIFT_DEFINE, false},
3370+ {"BAND", WF_LWTBL_BAND_MASK, WF_LWTBL_BAND_SHIFT,false},
3371+ {"RV", WF_LWTBL_RV_MASK, NO_SHIFT_DEFINE, false},
3372+ {"RCA2", WF_LWTBL_RCA2_MASK, NO_SHIFT_DEFINE, false},
3373+ {"WPI_FLAG", WF_LWTBL_WPI_FLAG_MASK, NO_SHIFT_DEFINE,true},
3374+ {NULL,}
3375+};
3376+
3377+static void parse_fmac_lwtbl_dw0_1(struct seq_file *s, u8 *lwtbl)
3378+{
3379+ u32 *addr = 0;
3380+ u32 dw_value = 0;
3381+ u16 i = 0;
3382+
3383+ seq_printf(s, "\t\n");
3384+ seq_printf(s, "LinkAddr: %02x:%02x:%02x:%02x:%02x:%02x(D0[B0~15], D1[B0~31])\n",
3385+ lwtbl[4], lwtbl[5], lwtbl[6], lwtbl[7], lwtbl[0], lwtbl[1]);
3386+
3387+ /* LMAC WTBL DW 0 */
3388+ seq_printf(s, "\t\n");
3389+ seq_printf(s, "LWTBL DW 0/1\n");
3390+ addr = (u32 *)&(lwtbl[WTBL_GROUP_PEER_INFO_DW_0*4]);
3391+ dw_value = *addr;
3392+
3393+ while (WTBL_LMAC_DW0[i].name) {
3394+
3395+ if (WTBL_LMAC_DW0[i].shift == NO_SHIFT_DEFINE)
3396+ seq_printf(s, "\t%s:%d\n", WTBL_LMAC_DW0[i].name,
3397+ (dw_value & WTBL_LMAC_DW0[i].mask) ? 1 : 0);
3398+ else
3399+ seq_printf(s, "\t%s:%u\n", WTBL_LMAC_DW0[i].name,
3400+ (dw_value & WTBL_LMAC_DW0[i].mask) >> WTBL_LMAC_DW0[i].shift);
3401+ i++;
3402+ }
3403+}
3404+
3405+static const struct berse_wtbl_parse WTBL_LMAC_DW2[] = {
3406+ {"AID", WF_LWTBL_AID_MASK, WF_LWTBL_AID_SHIFT, false},
3407+ {"GID_SU", WF_LWTBL_GID_SU_MASK, NO_SHIFT_DEFINE, false},
3408+ {"SPP_EN", WF_LWTBL_SPP_EN_MASK, NO_SHIFT_DEFINE, false},
3409+ {"WPI_EVEN", WF_LWTBL_WPI_EVEN_MASK, NO_SHIFT_DEFINE, false},
3410+ {"AAD_OM", WF_LWTBL_AAD_OM_MASK, NO_SHIFT_DEFINE, false},
3411+ {"CIPHER_PGTK",WF_LWTBL_CIPHER_SUIT_PGTK_MASK, WF_LWTBL_CIPHER_SUIT_PGTK_SHIFT, true},
3412+ {"FROM_DS", WF_LWTBL_FD_MASK, NO_SHIFT_DEFINE, false},
3413+ {"TO_DS", WF_LWTBL_TD_MASK, NO_SHIFT_DEFINE, false},
3414+ {"SW", WF_LWTBL_SW_MASK, NO_SHIFT_DEFINE, false},
3415+ {"UL", WF_LWTBL_UL_MASK, NO_SHIFT_DEFINE, false},
3416+ {"TX_POWER_SAVE", WF_LWTBL_TX_PS_MASK, NO_SHIFT_DEFINE, true},
3417+ {"QOS", WF_LWTBL_QOS_MASK, NO_SHIFT_DEFINE, false},
3418+ {"HT", WF_LWTBL_HT_MASK, NO_SHIFT_DEFINE, false},
3419+ {"VHT", WF_LWTBL_VHT_MASK, NO_SHIFT_DEFINE, false},
3420+ {"HE", WF_LWTBL_HE_MASK, NO_SHIFT_DEFINE, false},
3421+ {"EHT", WF_LWTBL_EHT_MASK, NO_SHIFT_DEFINE, false},
3422+ {"MESH", WF_LWTBL_MESH_MASK, NO_SHIFT_DEFINE, true},
3423+ {NULL,}
3424+};
3425+
3426+static void parse_fmac_lwtbl_dw2(struct seq_file *s, u8 *lwtbl)
3427+{
3428+ u32 *addr = 0;
3429+ u32 dw_value = 0;
3430+ u16 i = 0;
3431+
3432+ /* LMAC WTBL DW 2 */
3433+ seq_printf(s, "\t\n");
3434+ seq_printf(s, "LWTBL DW 2\n");
3435+ addr = (u32 *)&(lwtbl[WTBL_GROUP_TRX_CAP_DW_2*4]);
3436+ dw_value = *addr;
3437+
3438+ while (WTBL_LMAC_DW2[i].name) {
3439+
3440+ if (WTBL_LMAC_DW2[i].shift == NO_SHIFT_DEFINE)
3441+ seq_printf(s, "\t%s:%d\n", WTBL_LMAC_DW2[i].name,
3442+ (dw_value & WTBL_LMAC_DW2[i].mask) ? 1 : 0);
3443+ else
3444+ seq_printf(s, "\t%s:%u\n", WTBL_LMAC_DW2[i].name,
3445+ (dw_value & WTBL_LMAC_DW2[i].mask) >> WTBL_LMAC_DW2[i].shift);
3446+ i++;
3447+ }
3448+}
3449+
3450+static const struct berse_wtbl_parse WTBL_LMAC_DW3[] = {
3451+ {"WMM_Q", WF_LWTBL_WMM_Q_MASK, WF_LWTBL_WMM_Q_SHIFT, false},
3452+ {"EHT_SIG_MCS", WF_LWTBL_EHT_SIG_MCS_MASK, WF_LWTBL_EHT_SIG_MCS_SHIFT, false},
3453+ {"HDRT_MODE", WF_LWTBL_HDRT_MODE_MASK, NO_SHIFT_DEFINE, false},
3454+ {"BEAM_CHG", WF_LWTBL_BEAM_CHG_MASK, NO_SHIFT_DEFINE, false},
3455+ {"EHT_LTF_SYM_NUM", WF_LWTBL_EHT_LTF_SYM_NUM_OPT_MASK, WF_LWTBL_EHT_LTF_SYM_NUM_OPT_SHIFT, true},
3456+ {"PFMU_IDX", WF_LWTBL_PFMU_IDX_MASK, WF_LWTBL_PFMU_IDX_SHIFT, false},
3457+ {"ULPF_IDX", WF_LWTBL_ULPF_IDX_MASK, WF_LWTBL_ULPF_IDX_SHIFT, false},
3458+ {"RIBF", WF_LWTBL_RIBF_MASK, NO_SHIFT_DEFINE, false},
developerc2cfe0f2023-09-22 04:11:09 +0800[diff] [blame]3459+ {"ULPF", WF_LWTBL_ULPF_MASK, NO_SHIFT_DEFINE, false},
3460+ {"BYPASS_TXSMM", WF_LWTBL_BYPASS_TXSMM_MASK, NO_SHIFT_DEFINE, true},
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]3461+ {"TBF_HT", WF_LWTBL_TBF_HT_MASK, NO_SHIFT_DEFINE, false},
3462+ {"TBF_VHT", WF_LWTBL_TBF_VHT_MASK, NO_SHIFT_DEFINE, false},
3463+ {"TBF_HE", WF_LWTBL_TBF_HE_MASK, NO_SHIFT_DEFINE, false},
3464+ {"TBF_EHT", WF_LWTBL_TBF_EHT_MASK, NO_SHIFT_DEFINE, false},
3465+ {"IGN_FBK", WF_LWTBL_IGN_FBK_MASK, NO_SHIFT_DEFINE, true},
3466+ {NULL,}
3467+};
3468+
3469+static void parse_fmac_lwtbl_dw3(struct seq_file *s, u8 *lwtbl)
3470+{
3471+ u32 *addr = 0;
3472+ u32 dw_value = 0;
3473+ u16 i = 0;
3474+
3475+ /* LMAC WTBL DW 3 */
3476+ seq_printf(s, "\t\n");
3477+ seq_printf(s, "LWTBL DW 3\n");
3478+ addr = (u32 *)&(lwtbl[WTBL_GROUP_TRX_CAP_DW_3*4]);
3479+ dw_value = *addr;
3480+
3481+ while (WTBL_LMAC_DW3[i].name) {
3482+
3483+ if (WTBL_LMAC_DW3[i].shift == NO_SHIFT_DEFINE)
3484+ seq_printf(s, "\t%s:%d\n", WTBL_LMAC_DW3[i].name,
3485+ (dw_value & WTBL_LMAC_DW3[i].mask) ? 1 : 0);
3486+ else
3487+ seq_printf(s, "\t%s:%u\n", WTBL_LMAC_DW3[i].name,
3488+ (dw_value & WTBL_LMAC_DW3[i].mask) >> WTBL_LMAC_DW3[i].shift);
3489+ i++;
3490+ }
3491+}
3492+
3493+static const struct berse_wtbl_parse WTBL_LMAC_DW4[] = {
developerc2cfe0f2023-09-22 04:11:09 +0800[diff] [blame]3494+ {"NEGOTIATED_WINSIZE0", WF_LWTBL_NEGOTIATED_WINSIZE0_MASK, WF_LWTBL_NEGOTIATED_WINSIZE0_SHIFT, false},
3495+ {"WINSIZE1", WF_LWTBL_NEGOTIATED_WINSIZE1_MASK, WF_LWTBL_NEGOTIATED_WINSIZE1_SHIFT, false},
3496+ {"WINSIZE2", WF_LWTBL_NEGOTIATED_WINSIZE2_MASK, WF_LWTBL_NEGOTIATED_WINSIZE2_SHIFT, false},
3497+ {"WINSIZE3", WF_LWTBL_NEGOTIATED_WINSIZE3_MASK, WF_LWTBL_NEGOTIATED_WINSIZE3_SHIFT, true},
3498+ {"WINSIZE4", WF_LWTBL_NEGOTIATED_WINSIZE4_MASK, WF_LWTBL_NEGOTIATED_WINSIZE4_SHIFT, false},
3499+ {"WINSIZE5", WF_LWTBL_NEGOTIATED_WINSIZE5_MASK, WF_LWTBL_NEGOTIATED_WINSIZE5_SHIFT, false},
3500+ {"WINSIZE6", WF_LWTBL_NEGOTIATED_WINSIZE6_MASK, WF_LWTBL_NEGOTIATED_WINSIZE6_SHIFT, false},
3501+ {"WINSIZE7", WF_LWTBL_NEGOTIATED_WINSIZE7_MASK, WF_LWTBL_NEGOTIATED_WINSIZE7_SHIFT, true},
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]3502+ {"PE", WF_LWTBL_PE_MASK, WF_LWTBL_PE_SHIFT, false},
3503+ {"DIS_RHTR", WF_LWTBL_DIS_RHTR_MASK, NO_SHIFT_DEFINE, false},
3504+ {"LDPC_HT", WF_LWTBL_LDPC_HT_MASK, NO_SHIFT_DEFINE, false},
3505+ {"LDPC_VHT", WF_LWTBL_LDPC_VHT_MASK, NO_SHIFT_DEFINE, false},
3506+ {"LDPC_HE", WF_LWTBL_LDPC_HE_MASK, NO_SHIFT_DEFINE, false},
3507+ {"LDPC_EHT", WF_LWTBL_LDPC_EHT_MASK, NO_SHIFT_DEFINE, true},
developerc2cfe0f2023-09-22 04:11:09 +0800[diff] [blame]3508+ {"BA_MODE", WF_LWTBL_BA_MODE_MASK, NO_SHIFT_DEFINE, true},
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]3509+ {NULL,}
3510+};
3511+
3512+static void parse_fmac_lwtbl_dw4(struct seq_file *s, u8 *lwtbl)
3513+{
3514+ u32 *addr = 0;
3515+ u32 dw_value = 0;
3516+ u16 i = 0;
3517+
3518+ /* LMAC WTBL DW 4 */
3519+ seq_printf(s, "\t\n");
3520+ seq_printf(s, "LWTBL DW 4\n");
3521+ addr = (u32 *)&(lwtbl[WTBL_GROUP_TRX_CAP_DW_4*4]);
3522+ dw_value = *addr;
3523+
3524+ while (WTBL_LMAC_DW4[i].name) {
3525+ if (WTBL_LMAC_DW4[i].shift == NO_SHIFT_DEFINE)
3526+ seq_printf(s, "\t%s:%d\n", WTBL_LMAC_DW4[i].name,
3527+ (dw_value & WTBL_LMAC_DW4[i].mask) ? 1 : 0);
3528+ else
3529+ seq_printf(s, "\t%s:%u\n", WTBL_LMAC_DW4[i].name,
3530+ (dw_value & WTBL_LMAC_DW4[i].mask) >> WTBL_LMAC_DW4[i].shift);
3531+ i++;
3532+ }
3533+}
3534+
3535+static const struct berse_wtbl_parse WTBL_LMAC_DW5[] = {
3536+ {"AF", WF_LWTBL_AF_MASK, WF_LWTBL_AF_SHIFT, false},
3537+ {"AF_HE", WF_LWTBL_AF_HE_MASK, WF_LWTBL_AF_HE_SHIFT,false},
3538+ {"RTS", WF_LWTBL_RTS_MASK, NO_SHIFT_DEFINE, false},
3539+ {"SMPS", WF_LWTBL_SMPS_MASK, NO_SHIFT_DEFINE, false},
3540+ {"DYN_BW", WF_LWTBL_DYN_BW_MASK, NO_SHIFT_DEFINE, true},
3541+ {"MMSS", WF_LWTBL_MMSS_MASK, WF_LWTBL_MMSS_SHIFT,false},
3542+ {"USR", WF_LWTBL_USR_MASK, NO_SHIFT_DEFINE, false},
3543+ {"SR_RATE", WF_LWTBL_SR_R_MASK, WF_LWTBL_SR_R_SHIFT,false},
3544+ {"SR_ABORT", WF_LWTBL_SR_ABORT_MASK, NO_SHIFT_DEFINE, true},
3545+ {"TX_POWER_OFFSET", WF_LWTBL_TX_POWER_OFFSET_MASK, WF_LWTBL_TX_POWER_OFFSET_SHIFT, false},
3546+ {"LTF_EHT", WF_LWTBL_LTF_EHT_MASK, WF_LWTBL_LTF_EHT_SHIFT, false},
3547+ {"GI_EHT", WF_LWTBL_GI_EHT_MASK, WF_LWTBL_GI_EHT_SHIFT, false},
3548+ {"DOPPL", WF_LWTBL_DOPPL_MASK, NO_SHIFT_DEFINE, false},
3549+ {"TXOP_PS_CAP", WF_LWTBL_TXOP_PS_CAP_MASK, NO_SHIFT_DEFINE, false},
3550+ {"DONOT_UPDATE_I_PSM", WF_LWTBL_DU_I_PSM_MASK, NO_SHIFT_DEFINE, true},
3551+ {"I_PSM", WF_LWTBL_I_PSM_MASK, NO_SHIFT_DEFINE, false},
3552+ {"PSM", WF_LWTBL_PSM_MASK, NO_SHIFT_DEFINE, false},
3553+ {"SKIP_TX", WF_LWTBL_SKIP_TX_MASK, NO_SHIFT_DEFINE, true},
3554+ {NULL,}
3555+};
3556+
3557+static void parse_fmac_lwtbl_dw5(struct seq_file *s, u8 *lwtbl)
3558+{
3559+ u32 *addr = 0;
3560+ u32 dw_value = 0;
3561+ u16 i = 0;
3562+
3563+ /* LMAC WTBL DW 5 */
3564+ seq_printf(s, "\t\n");
3565+ seq_printf(s, "LWTBL DW 5\n");
3566+ addr = (u32 *)&(lwtbl[WTBL_GROUP_TRX_CAP_DW_5*4]);
3567+ dw_value = *addr;
3568+
3569+ while (WTBL_LMAC_DW5[i].name) {
3570+ if (WTBL_LMAC_DW5[i].shift == NO_SHIFT_DEFINE)
3571+ seq_printf(s, "\t%s:%d\n", WTBL_LMAC_DW5[i].name,
3572+ (dw_value & WTBL_LMAC_DW5[i].mask) ? 1 : 0);
3573+ else
3574+ seq_printf(s, "\t%s:%u\n", WTBL_LMAC_DW5[i].name,
3575+ (dw_value & WTBL_LMAC_DW5[i].mask) >> WTBL_LMAC_DW5[i].shift);
3576+ i++;
3577+ }
3578+}
3579+
3580+static const struct berse_wtbl_parse WTBL_LMAC_DW6[] = {
3581+ {"CBRN", WF_LWTBL_CBRN_MASK, WF_LWTBL_CBRN_SHIFT, false},
3582+ {"DBNSS_EN", WF_LWTBL_DBNSS_EN_MASK, NO_SHIFT_DEFINE, false},
3583+ {"BAF_EN", WF_LWTBL_BAF_EN_MASK, NO_SHIFT_DEFINE, false},
3584+ {"RDGBA", WF_LWTBL_RDGBA_MASK, NO_SHIFT_DEFINE, false},
3585+ {"RDG", WF_LWTBL_R_MASK, NO_SHIFT_DEFINE, false},
3586+ {"SPE_IDX", WF_LWTBL_SPE_IDX_MASK, WF_LWTBL_SPE_IDX_SHIFT, true},
3587+ {"G2", WF_LWTBL_G2_MASK, NO_SHIFT_DEFINE, false},
3588+ {"G4", WF_LWTBL_G4_MASK, NO_SHIFT_DEFINE, false},
3589+ {"G8", WF_LWTBL_G8_MASK, NO_SHIFT_DEFINE, false},
3590+ {"G16", WF_LWTBL_G16_MASK, NO_SHIFT_DEFINE, true},
3591+ {"G2_LTF", WF_LWTBL_G2_LTF_MASK, WF_LWTBL_G2_LTF_SHIFT, false},
3592+ {"G4_LTF", WF_LWTBL_G4_LTF_MASK, WF_LWTBL_G4_LTF_SHIFT, false},
3593+ {"G8_LTF", WF_LWTBL_G8_LTF_MASK, WF_LWTBL_G8_LTF_SHIFT, false},
3594+ {"G16_LTF", WF_LWTBL_G16_LTF_MASK, WF_LWTBL_G16_LTF_SHIFT, true},
3595+ {"G2_HE", WF_LWTBL_G2_HE_MASK, WF_LWTBL_G2_HE_SHIFT, false},
3596+ {"G4_HE", WF_LWTBL_G4_HE_MASK, WF_LWTBL_G4_HE_SHIFT, false},
3597+ {"G8_HE", WF_LWTBL_G8_HE_MASK, WF_LWTBL_G8_HE_SHIFT, false},
3598+ {"G16_HE", WF_LWTBL_G16_HE_MASK, WF_LWTBL_G16_HE_SHIFT, true},
3599+ {NULL,}
3600+};
3601+
3602+static void parse_fmac_lwtbl_dw6(struct seq_file *s, u8 *lwtbl)
3603+{
3604+ u32 *addr = 0;
3605+ u32 dw_value = 0;
3606+ u16 i = 0;
3607+
3608+ /* LMAC WTBL DW 6 */
3609+ seq_printf(s, "\t\n");
3610+ seq_printf(s, "LWTBL DW 6\n");
3611+ addr = (u32 *)&(lwtbl[WTBL_GROUP_TRX_CAP_DW_6*4]);
3612+ dw_value = *addr;
3613+
3614+ while (WTBL_LMAC_DW6[i].name) {
3615+ if (WTBL_LMAC_DW6[i].shift == NO_SHIFT_DEFINE)
3616+ seq_printf(s, "\t%s:%d\n", WTBL_LMAC_DW6[i].name,
3617+ (dw_value & WTBL_LMAC_DW6[i].mask) ? 1 : 0);
3618+ else
3619+ seq_printf(s, "\t%s:%u\n", WTBL_LMAC_DW6[i].name,
3620+ (dw_value & WTBL_LMAC_DW6[i].mask) >> WTBL_LMAC_DW6[i].shift);
3621+ i++;
3622+ }
3623+}
3624+
3625+static void parse_fmac_lwtbl_dw7(struct seq_file *s, u8 *lwtbl)
3626+{
3627+ u32 *addr = 0;
3628+ u32 dw_value = 0;
3629+ int i = 0;
3630+
3631+ /* LMAC WTBL DW 7 */
3632+ seq_printf(s, "\t\n");
3633+ seq_printf(s, "LWTBL DW 7\n");
3634+ addr = (u32 *)&(lwtbl[WTBL_GROUP_TRX_CAP_DW_7*4]);
3635+ dw_value = *addr;
3636+
3637+ for (i = 0; i < 8; i++) {
3638+ seq_printf(s, "\tBA_WIN_SIZE%u:%lu\n", i, ((dw_value & BITS(i*4, i*4+3)) >> i*4));
3639+ }
3640+}
3641+
3642+static const struct berse_wtbl_parse WTBL_LMAC_DW8[] = {
3643+ {"RTS_FAIL_CNT_AC0", WF_LWTBL_AC0_RTS_FAIL_CNT_MASK, WF_LWTBL_AC0_RTS_FAIL_CNT_SHIFT, false},
3644+ {"AC1", WF_LWTBL_AC1_RTS_FAIL_CNT_MASK, WF_LWTBL_AC1_RTS_FAIL_CNT_SHIFT, false},
3645+ {"AC2", WF_LWTBL_AC2_RTS_FAIL_CNT_MASK, WF_LWTBL_AC2_RTS_FAIL_CNT_SHIFT, false},
3646+ {"AC3", WF_LWTBL_AC3_RTS_FAIL_CNT_MASK, WF_LWTBL_AC3_RTS_FAIL_CNT_SHIFT, true},
3647+ {"PARTIAL_AID", WF_LWTBL_PARTIAL_AID_MASK, WF_LWTBL_PARTIAL_AID_SHIFT, false},
3648+ {"CHK_PER", WF_LWTBL_CHK_PER_MASK, NO_SHIFT_DEFINE, true},
3649+ {NULL,}
3650+};
3651+
3652+static void parse_fmac_lwtbl_dw8(struct seq_file *s, u8 *lwtbl)
3653+{
3654+ u32 *addr = 0;
3655+ u32 dw_value = 0;
3656+ u16 i = 0;
3657+
3658+ /* LMAC WTBL DW 8 */
3659+ seq_printf(s, "\t\n");
3660+ seq_printf(s, "LWTBL DW 8\n");
3661+ addr = (u32 *)&(lwtbl[WTBL_GROUP_TRX_CAP_DW_8*4]);
3662+ dw_value = *addr;
3663+
3664+ while (WTBL_LMAC_DW8[i].name) {
3665+ if (WTBL_LMAC_DW8[i].shift == NO_SHIFT_DEFINE)
3666+ seq_printf(s, "\t%s:%d\n", WTBL_LMAC_DW8[i].name,
3667+ (dw_value & WTBL_LMAC_DW8[i].mask) ? 1 : 0);
3668+ else
3669+ seq_printf(s, "\t%s:%u\n", WTBL_LMAC_DW8[i].name,
3670+ (dw_value & WTBL_LMAC_DW8[i].mask) >> WTBL_LMAC_DW8[i].shift);
3671+ i++;
3672+ }
3673+}
3674+
3675+static const struct berse_wtbl_parse WTBL_LMAC_DW9[] = {
3676+ {"RX_AVG_MPDU_SIZE", WF_LWTBL_RX_AVG_MPDU_SIZE_MASK, WF_LWTBL_RX_AVG_MPDU_SIZE_SHIFT, false},
3677+ {"PRITX_SW_MODE", WF_LWTBL_PRITX_SW_MODE_MASK, NO_SHIFT_DEFINE, false},
3678+ {"PRITX_ERSU", WF_LWTBL_PRITX_ERSU_MASK, NO_SHIFT_DEFINE, false},
3679+ {"PRITX_PLR", WF_LWTBL_PRITX_PLR_MASK, NO_SHIFT_DEFINE, true},
3680+ {"PRITX_DCM", WF_LWTBL_PRITX_DCM_MASK, NO_SHIFT_DEFINE, false},
3681+ {"PRITX_ER106T", WF_LWTBL_PRITX_ER106T_MASK, NO_SHIFT_DEFINE, true},
3682+ /* {"FCAP(0:20 1:~40)", WTBL_FCAP_20_TO_160_MHZ, WTBL_FCAP_20_TO_160_MHZ_OFFSET}, */
3683+ {"MPDU_FAIL_CNT", WF_LWTBL_MPDU_FAIL_CNT_MASK, WF_LWTBL_MPDU_FAIL_CNT_SHIFT, false},
3684+ {"MPDU_OK_CNT", WF_LWTBL_MPDU_OK_CNT_MASK, WF_LWTBL_MPDU_OK_CNT_SHIFT, false},
3685+ {"RATE_IDX", WF_LWTBL_RATE_IDX_MASK, WF_LWTBL_RATE_IDX_SHIFT, true},
3686+ {NULL,}
3687+};
3688+
3689+char *fcap_name[] = {"20MHz", "20/40MHz", "20/40/80MHz", "20/40/80/160/80+80MHz", "20/40/80/160/80+80/320MHz"};
3690+
3691+static void parse_fmac_lwtbl_dw9(struct seq_file *s, u8 *lwtbl)
3692+{
3693+ u32 *addr = 0;
3694+ u32 dw_value = 0;
3695+ u16 i = 0;
3696+
3697+ /* LMAC WTBL DW 9 */
3698+ seq_printf(s, "\t\n");
3699+ seq_printf(s, "LWTBL DW 9\n");
3700+ addr = (u32 *)&(lwtbl[WTBL_GROUP_TRX_CAP_DW_9*4]);
3701+ dw_value = *addr;
3702+
3703+ while (WTBL_LMAC_DW9[i].name) {
3704+ if (WTBL_LMAC_DW9[i].shift == NO_SHIFT_DEFINE)
3705+ seq_printf(s, "\t%s:%d\n", WTBL_LMAC_DW9[i].name,
3706+ (dw_value & WTBL_LMAC_DW9[i].mask) ? 1 : 0);
3707+ else
3708+ seq_printf(s, "\t%s:%u\n", WTBL_LMAC_DW9[i].name,
3709+ (dw_value & WTBL_LMAC_DW9[i].mask) >> WTBL_LMAC_DW9[i].shift);
3710+ i++;
3711+ }
3712+
3713+ /* FCAP parser */
3714+ seq_printf(s, "\t\n");
3715+ seq_printf(s, "FCAP:%s\n", fcap_name[(dw_value & WF_LWTBL_FCAP_MASK) >> WF_LWTBL_FCAP_SHIFT]);
3716+}
3717+
3718+#define HW_TX_RATE_TO_MODE(_x) (((_x) & WTBL_RATE_TX_MODE_MASK) >> WTBL_RATE_TX_MODE_OFFSET)
3719+#define HW_TX_RATE_TO_MCS(_x, _mode) ((_x) & WTBL_RATE_TX_RATE_MASK >> WTBL_RATE_TX_RATE_OFFSET)
3720+#define HW_TX_RATE_TO_NSS(_x) (((_x) & WTBL_RATE_NSTS_MASK) >> WTBL_RATE_NSTS_OFFSET)
3721+#define HW_TX_RATE_TO_STBC(_x) (((_x) & WTBL_RATE_STBC_MASK) >> WTBL_RATE_STBC_OFFSET)
3722+
3723+#define MAX_TX_MODE 16
3724+static char *HW_TX_MODE_STR[] = {"CCK", "OFDM", "HT-Mix", "HT-GF", "VHT",
3725+ "N/A", "N/A", "N/A",
3726+ "HE_SU", "HE_EXT_SU", "HE_TRIG", "HE_MU",
3727+ "N/A",
3728+ "EHT_EXT_SU", "EHT_TRIG", "EHT_MU",
3729+ "N/A"};
3730+static char *HW_TX_RATE_CCK_STR[] = {"1M", "2Mlong", "5.5Mlong", "11Mlong", "N/A", "2Mshort", "5.5Mshort", "11Mshort", "N/A"};
3731+static char *HW_TX_RATE_OFDM_STR[] = {"6M", "9M", "12M", "18M", "24M", "36M", "48M", "54M", "N/A"};
3732+
3733+static char *hw_rate_ofdm_str(uint16_t ofdm_idx)
3734+{
3735+ switch (ofdm_idx) {
3736+ case 11: /* 6M */
3737+ return HW_TX_RATE_OFDM_STR[0];
3738+
3739+ case 15: /* 9M */
3740+ return HW_TX_RATE_OFDM_STR[1];
3741+
3742+ case 10: /* 12M */
3743+ return HW_TX_RATE_OFDM_STR[2];
3744+
3745+ case 14: /* 18M */
3746+ return HW_TX_RATE_OFDM_STR[3];
3747+
3748+ case 9: /* 24M */
3749+ return HW_TX_RATE_OFDM_STR[4];
3750+
3751+ case 13: /* 36M */
3752+ return HW_TX_RATE_OFDM_STR[5];
3753+
3754+ case 8: /* 48M */
3755+ return HW_TX_RATE_OFDM_STR[6];
3756+
3757+ case 12: /* 54M */
3758+ return HW_TX_RATE_OFDM_STR[7];
3759+
3760+ default:
3761+ return HW_TX_RATE_OFDM_STR[8];
3762+ }
3763+}
3764+
3765+static char *hw_rate_str(u8 mode, uint16_t rate_idx)
3766+{
3767+ if (mode == 0)
3768+ return rate_idx < 8 ? HW_TX_RATE_CCK_STR[rate_idx] : HW_TX_RATE_CCK_STR[8];
3769+ else if (mode == 1)
3770+ return hw_rate_ofdm_str(rate_idx);
3771+ else
3772+ return "MCS";
3773+}
3774+
3775+static void
3776+parse_rate(struct seq_file *s, uint16_t rate_idx, uint16_t txrate)
3777+{
3778+ uint16_t txmode, mcs, nss, stbc;
3779+
3780+ txmode = HW_TX_RATE_TO_MODE(txrate);
3781+ mcs = HW_TX_RATE_TO_MCS(txrate, txmode);
3782+ nss = HW_TX_RATE_TO_NSS(txrate);
3783+ stbc = HW_TX_RATE_TO_STBC(txrate);
3784+
3785+ seq_printf(s, "\tRate%d(0x%x):TxMode=%d(%s), TxRate=%d(%s), Nsts=%d, STBC=%d\n",
3786+ rate_idx + 1, txrate,
3787+ txmode, (txmode < MAX_TX_MODE ? HW_TX_MODE_STR[txmode] : HW_TX_MODE_STR[MAX_TX_MODE]),
3788+ mcs, hw_rate_str(txmode, mcs), nss, stbc);
3789+}
3790+
3791+
3792+static const struct berse_wtbl_parse WTBL_LMAC_DW10[] = {
3793+ {"RATE1", WF_LWTBL_RATE1_MASK, WF_LWTBL_RATE1_SHIFT},
3794+ {"RATE2", WF_LWTBL_RATE2_MASK, WF_LWTBL_RATE2_SHIFT},
3795+ {NULL,}
3796+};
3797+
3798+static void parse_fmac_lwtbl_dw10(struct seq_file *s, u8 *lwtbl)
3799+{
3800+ u32 *addr = 0;
3801+ u32 dw_value = 0;
3802+ u16 i = 0;
3803+
3804+ /* LMAC WTBL DW 10 */
3805+ seq_printf(s, "\t\n");
3806+ seq_printf(s, "LWTBL DW 10\n");
3807+ addr = (u32 *)&(lwtbl[WTBL_GROUP_AUTO_RATE_1_2*4]);
3808+ dw_value = *addr;
3809+
3810+ while (WTBL_LMAC_DW10[i].name) {
3811+ parse_rate(s, i, (dw_value & WTBL_LMAC_DW10[i].mask) >> WTBL_LMAC_DW10[i].shift);
3812+ i++;
3813+ }
3814+}
3815+
3816+static const struct berse_wtbl_parse WTBL_LMAC_DW11[] = {
3817+ {"RATE3", WF_LWTBL_RATE3_MASK, WF_LWTBL_RATE3_SHIFT},
3818+ {"RATE4", WF_LWTBL_RATE4_MASK, WF_LWTBL_RATE4_SHIFT},
3819+ {NULL,}
3820+};
3821+
3822+static void parse_fmac_lwtbl_dw11(struct seq_file *s, u8 *lwtbl)
3823+{
3824+ u32 *addr = 0;
3825+ u32 dw_value = 0;
3826+ u16 i = 0;
3827+
3828+ /* LMAC WTBL DW 11 */
3829+ seq_printf(s, "\t\n");
3830+ seq_printf(s, "LWTBL DW 11\n");
3831+ addr = (u32 *)&(lwtbl[WTBL_GROUP_AUTO_RATE_3_4*4]);
3832+ dw_value = *addr;
3833+
3834+ while (WTBL_LMAC_DW11[i].name) {
3835+ parse_rate(s, i+2, (dw_value & WTBL_LMAC_DW11[i].mask) >> WTBL_LMAC_DW11[i].shift);
3836+ i++;
3837+ }
3838+}
3839+
3840+static const struct berse_wtbl_parse WTBL_LMAC_DW12[] = {
3841+ {"RATE5", WF_LWTBL_RATE5_MASK, WF_LWTBL_RATE5_SHIFT},
3842+ {"RATE6", WF_LWTBL_RATE6_MASK, WF_LWTBL_RATE6_SHIFT},
3843+ {NULL,}
3844+};
3845+
3846+static void parse_fmac_lwtbl_dw12(struct seq_file *s, u8 *lwtbl)
3847+{
3848+ u32 *addr = 0;
3849+ u32 dw_value = 0;
3850+ u16 i = 0;
3851+
3852+ /* LMAC WTBL DW 12 */
3853+ seq_printf(s, "\t\n");
3854+ seq_printf(s, "LWTBL DW 12\n");
3855+ addr = (u32 *)&(lwtbl[WTBL_GROUP_AUTO_RATE_5_6*4]);
3856+ dw_value = *addr;
3857+
3858+ while (WTBL_LMAC_DW12[i].name) {
3859+ parse_rate(s, i+4, (dw_value & WTBL_LMAC_DW12[i].mask) >> WTBL_LMAC_DW12[i].shift);
3860+ i++;
3861+ }
3862+}
3863+
3864+static const struct berse_wtbl_parse WTBL_LMAC_DW13[] = {
3865+ {"RATE7", WF_LWTBL_RATE7_MASK, WF_LWTBL_RATE7_SHIFT},
3866+ {"RATE8", WF_LWTBL_RATE8_MASK, WF_LWTBL_RATE8_SHIFT},
3867+ {NULL,}
3868+};
3869+
3870+static void parse_fmac_lwtbl_dw13(struct seq_file *s, u8 *lwtbl)
3871+{
3872+ u32 *addr = 0;
3873+ u32 dw_value = 0;
3874+ u16 i = 0;
3875+
3876+ /* LMAC WTBL DW 13 */
3877+ seq_printf(s, "\t\n");
3878+ seq_printf(s, "LWTBL DW 13\n");
3879+ addr = (u32 *)&(lwtbl[WTBL_GROUP_AUTO_RATE_7_8*4]);
3880+ dw_value = *addr;
3881+
3882+ while (WTBL_LMAC_DW13[i].name) {
3883+ parse_rate(s, i+6, (dw_value & WTBL_LMAC_DW13[i].mask) >> WTBL_LMAC_DW13[i].shift);
3884+ i++;
3885+ }
3886+}
3887+
3888+static const struct berse_wtbl_parse WTBL_LMAC_DW14_BMC[] = {
3889+ {"CIPHER_IGTK", WF_LWTBL_CIPHER_SUIT_IGTK_MASK, WF_LWTBL_CIPHER_SUIT_IGTK_SHIFT, false},
3890+ {"CIPHER_BIGTK", WF_LWTBL_CIPHER_SUIT_BIGTK_MASK, WF_LWTBL_CIPHER_SUIT_BIGTK_SHIFT, true},
3891+ {NULL,}
3892+};
3893+
developerc2cfe0f2023-09-22 04:11:09 +0800[diff] [blame]3894+static const struct berse_wtbl_parse WTBL_LMAC_DW14[] = {
3895+ {"RATE1_TX_CNT", WF_LWTBL_RATE1_TX_CNT_MASK, WF_LWTBL_RATE1_TX_CNT_SHIFT, false},
3896+ {"RATE1_FAIL_CNT", WF_LWTBL_RATE1_FAIL_CNT_MASK, WF_LWTBL_RATE1_FAIL_CNT_SHIFT, true},
3897+ {NULL,}
3898+};
3899+
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]3900+static void parse_fmac_lwtbl_dw14(struct seq_file *s, u8 *lwtbl)
3901+{
3902+ u32 *addr, *muar_addr = 0;
3903+ u32 dw_value, muar_dw_value = 0;
3904+ u16 i = 0;
3905+
3906+ /* DUMP DW14 for BMC entry only */
3907+ muar_addr = (u32 *)&(lwtbl[WF_LWTBL_MUAR_DW*4]);
3908+ muar_dw_value = *muar_addr;
3909+ if (((muar_dw_value & WF_LWTBL_MUAR_MASK) >> WF_LWTBL_MUAR_SHIFT)
3910+ == MUAR_INDEX_OWN_MAC_ADDR_BC_MC) {
3911+ /* LMAC WTBL DW 14 */
3912+ seq_printf(s, "\t\n");
3913+ seq_printf(s, "LWTBL DW 14\n");
3914+ addr = (u32 *)&(lwtbl[WF_LWTBL_CIPHER_SUIT_IGTK_DW*4]);
3915+ dw_value = *addr;
3916+
3917+ while (WTBL_LMAC_DW14_BMC[i].name) {
developerc2cfe0f2023-09-22 04:11:09 +0800[diff] [blame]3918+ if (WTBL_LMAC_DW14_BMC[i].shift == NO_SHIFT_DEFINE)
3919+ seq_printf(s, "\t%s:%d\n", WTBL_LMAC_DW14_BMC[i].name,
3920+ (dw_value & WTBL_LMAC_DW14_BMC[i].mask) ? 1 : 0);
3921+ else
3922+ seq_printf(s, "\t%s:%u\n", WTBL_LMAC_DW14_BMC[i].name,
3923+ (dw_value & WTBL_LMAC_DW14_BMC[i].mask) >> WTBL_LMAC_DW14_BMC[i].shift);
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]3924+ i++;
3925+ }
developerc2cfe0f2023-09-22 04:11:09 +0800[diff] [blame]3926+ } else {
3927+ seq_printf(s, "\t\n");
3928+ seq_printf(s, "LWTBL DW 14\n");
3929+ addr = (u32 *)&(lwtbl[WF_LWTBL_CIPHER_SUIT_IGTK_DW*4]);
3930+ dw_value = *addr;
3931+
3932+ while (WTBL_LMAC_DW14[i].name) {
3933+ if (WTBL_LMAC_DW14[i].shift == NO_SHIFT_DEFINE)
3934+ seq_printf(s, "\t%s:%d\n", WTBL_LMAC_DW14[i].name,
3935+ (dw_value & WTBL_LMAC_DW14[i].mask) ? 1 : 0);
3936+ else
3937+ seq_printf(s, "\t%s:%u\n", WTBL_LMAC_DW14[i].name,
3938+ (dw_value & WTBL_LMAC_DW14[i].mask) >> WTBL_LMAC_DW14[i].shift);
3939+ i++;
3940+ }
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]3941+ }
3942+}
3943+
3944+static const struct berse_wtbl_parse WTBL_LMAC_DW28[] = {
3945+ {"RELATED_IDX0", WF_LWTBL_RELATED_IDX0_MASK, WF_LWTBL_RELATED_IDX0_SHIFT, false},
3946+ {"RELATED_BAND0", WF_LWTBL_RELATED_BAND0_MASK, WF_LWTBL_RELATED_BAND0_SHIFT, false},
3947+ {"PRI_MLD_BAND", WF_LWTBL_PRIMARY_MLD_BAND_MASK, WF_LWTBL_PRIMARY_MLD_BAND_SHIFT, true},
developerc2cfe0f2023-09-22 04:11:09 +0800[diff] [blame]3948+ {"RELATED_IDX1", WF_LWTBL_RELATED_IDX1_MASK, WF_LWTBL_RELATED_IDX1_SHIFT, false},
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]3949+ {"RELATED_BAND1", WF_LWTBL_RELATED_BAND1_MASK, WF_LWTBL_RELATED_BAND1_SHIFT, false},
3950+ {"SEC_MLD_BAND", WF_LWTBL_SECONDARY_MLD_BAND_MASK, WF_LWTBL_SECONDARY_MLD_BAND_SHIFT, true},
3951+ {NULL,}
3952+};
3953+
3954+static void parse_fmac_lwtbl_dw28(struct seq_file *s, u8 *lwtbl)
3955+{
3956+ u32 *addr = 0;
3957+ u32 dw_value = 0;
3958+ u16 i = 0;
3959+
3960+ /* LMAC WTBL DW 28 */
3961+ seq_printf(s, "\t\n");
3962+ seq_printf(s, "LWTBL DW 28\n");
3963+ addr = (u32 *)&(lwtbl[WTBL_GROUP_MLO_INFO_LINE_1*4]);
3964+ dw_value = *addr;
3965+
3966+ while (WTBL_LMAC_DW28[i].name) {
3967+ if (WTBL_LMAC_DW28[i].shift == NO_SHIFT_DEFINE)
3968+ seq_printf(s, "\t%s:%d\n", WTBL_LMAC_DW28[i].name,
3969+ (dw_value & WTBL_LMAC_DW28[i].mask) ? 1 : 0);
3970+ else
3971+ seq_printf(s, "\t%s:%u\n", WTBL_LMAC_DW28[i].name,
3972+ (dw_value & WTBL_LMAC_DW28[i].mask) >>
3973+ WTBL_LMAC_DW28[i].shift);
3974+ i++;
3975+ }
3976+}
3977+
3978+static const struct berse_wtbl_parse WTBL_LMAC_DW29[] = {
3979+ {"DISPATCH_POLICY_MLD_TID0", WF_LWTBL_DISPATCH_POLICY0_MASK, WF_LWTBL_DISPATCH_POLICY0_SHIFT, false},
3980+ {"MLD_TID1", WF_LWTBL_DISPATCH_POLICY1_MASK, WF_LWTBL_DISPATCH_POLICY1_SHIFT, false},
3981+ {"MLD_TID2", WF_LWTBL_DISPATCH_POLICY2_MASK, WF_LWTBL_DISPATCH_POLICY2_SHIFT, false},
3982+ {"MLD_TID3", WF_LWTBL_DISPATCH_POLICY3_MASK, WF_LWTBL_DISPATCH_POLICY3_SHIFT, true},
3983+ {"MLD_TID4", WF_LWTBL_DISPATCH_POLICY4_MASK, WF_LWTBL_DISPATCH_POLICY4_SHIFT, false},
3984+ {"MLD_TID5", WF_LWTBL_DISPATCH_POLICY5_MASK, WF_LWTBL_DISPATCH_POLICY5_SHIFT, false},
3985+ {"MLD_TID6", WF_LWTBL_DISPATCH_POLICY6_MASK, WF_LWTBL_DISPATCH_POLICY6_SHIFT, false},
3986+ {"MLD_TID7", WF_LWTBL_DISPATCH_POLICY7_MASK, WF_LWTBL_DISPATCH_POLICY7_SHIFT, true},
3987+ {"OMLD_ID", WF_LWTBL_OWN_MLD_ID_MASK, WF_LWTBL_OWN_MLD_ID_SHIFT, false},
3988+ {"EMLSR0", WF_LWTBL_EMLSR0_MASK, NO_SHIFT_DEFINE, false},
3989+ {"EMLMR0", WF_LWTBL_EMLMR0_MASK, NO_SHIFT_DEFINE, false},
3990+ {"EMLSR1", WF_LWTBL_EMLSR1_MASK, NO_SHIFT_DEFINE, false},
3991+ {"EMLMR1", WF_LWTBL_EMLMR1_MASK, NO_SHIFT_DEFINE, true},
3992+ {"EMLSR2", WF_LWTBL_EMLSR2_MASK, NO_SHIFT_DEFINE, false},
3993+ {"EMLMR2", WF_LWTBL_EMLMR2_MASK, NO_SHIFT_DEFINE, false},
3994+ {"STR_BITMAP", WF_LWTBL_STR_BITMAP_MASK, WF_LWTBL_STR_BITMAP_SHIFT, true},
3995+ {NULL,}
3996+};
3997+
3998+static void parse_fmac_lwtbl_dw29(struct seq_file *s, u8 *lwtbl)
3999+{
4000+ u32 *addr = 0;
4001+ u32 dw_value = 0;
4002+ u16 i = 0;
4003+
4004+ /* LMAC WTBL DW 29 */
4005+ seq_printf(s, "\t\n");
4006+ seq_printf(s, "LWTBL DW 29\n");
4007+ addr = (u32 *)&(lwtbl[WTBL_GROUP_MLO_INFO_LINE_2*4]);
4008+ dw_value = *addr;
4009+
4010+ while (WTBL_LMAC_DW29[i].name) {
4011+ if (WTBL_LMAC_DW29[i].shift == NO_SHIFT_DEFINE)
4012+ seq_printf(s, "\t%s:%d\n", WTBL_LMAC_DW29[i].name,
4013+ (dw_value & WTBL_LMAC_DW29[i].mask) ? 1 : 0);
4014+ else
4015+ seq_printf(s, "\t%s:%u\n", WTBL_LMAC_DW29[i].name,
4016+ (dw_value & WTBL_LMAC_DW29[i].mask) >>
4017+ WTBL_LMAC_DW29[i].shift);
4018+ i++;
4019+ }
4020+}
4021+
4022+static const struct berse_wtbl_parse WTBL_LMAC_DW30[] = {
4023+ {"DISPATCH_ORDER", WF_LWTBL_DISPATCH_ORDER_MASK, WF_LWTBL_DISPATCH_ORDER_SHIFT, false},
4024+ {"DISPATCH_RATIO", WF_LWTBL_DISPATCH_RATIO_MASK, WF_LWTBL_DISPATCH_RATIO_SHIFT, false},
4025+ {"LINK_MGF", WF_LWTBL_LINK_MGF_MASK, WF_LWTBL_LINK_MGF_SHIFT, true},
4026+ {NULL,}
4027+};
4028+
4029+static void parse_fmac_lwtbl_dw30(struct seq_file *s, u8 *lwtbl)
4030+{
4031+ u32 *addr = 0;
4032+ u32 dw_value = 0;
4033+ u16 i = 0;
4034+
4035+ /* LMAC WTBL DW 30 */
4036+ seq_printf(s, "\t\n");
4037+ seq_printf(s, "LWTBL DW 30\n");
4038+ addr = (u32 *)&(lwtbl[WTBL_GROUP_MLO_INFO_LINE_3*4]);
4039+ dw_value = *addr;
4040+
4041+
4042+ while (WTBL_LMAC_DW30[i].name) {
4043+ if (WTBL_LMAC_DW30[i].shift == NO_SHIFT_DEFINE)
4044+ seq_printf(s, "\t%s:%d\n", WTBL_LMAC_DW30[i].name,
4045+ (dw_value & WTBL_LMAC_DW30[i].mask) ? 1 : 0);
4046+ else
4047+ seq_printf(s, "\t%s:%u\n", WTBL_LMAC_DW30[i].name,
4048+ (dw_value & WTBL_LMAC_DW30[i].mask) >> WTBL_LMAC_DW30[i].shift);
4049+ i++;
4050+ }
4051+}
4052+
4053+static const struct berse_wtbl_parse WTBL_LMAC_DW31[] = {
developerc2cfe0f2023-09-22 04:11:09 +0800[diff] [blame]4054+ {"BFTX_TB", WF_LWTBL_BFTX_TB_MASK, NO_SHIFT_DEFINE, false},
4055+ {"DROP", WF_LWTBL_DROP_MASK, NO_SHIFT_DEFINE, false},
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]4056+ {"CASCAD", WF_LWTBL_CASCAD_MASK, NO_SHIFT_DEFINE, false},
4057+ {"ALL_ACK", WF_LWTBL_ALL_ACK_MASK, NO_SHIFT_DEFINE, false},
4058+ {"MPDU_SIZE", WF_LWTBL_MPDU_SIZE_MASK, WF_LWTBL_MPDU_SIZE_SHIFT, false},
developerc2cfe0f2023-09-22 04:11:09 +0800[diff] [blame]4059+ {"RXD_DUP_MODE", WF_LWTBL_RXD_DUP_MODE_MASK, WF_LWTBL_RXD_DUP_MODE_SHIFT, true},
4060+ {"ACK_EN", WF_LWTBL_ACK_EN_MASK, NO_SHIFT_DEFINE, true},
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]4061+ {NULL,}
4062+};
4063+
4064+static void parse_fmac_lwtbl_dw31(struct seq_file *s, u8 *lwtbl)
4065+{
4066+ u32 *addr = 0;
4067+ u32 dw_value = 0;
4068+ u16 i = 0;
4069+
4070+ /* LMAC WTBL DW 31 */
4071+ seq_printf(s, "\t\n");
4072+ seq_printf(s, "LWTBL DW 31\n");
4073+ addr = (u32 *)&(lwtbl[WTBL_GROUP_RESP_INFO_DW_31*4]);
4074+ dw_value = *addr;
4075+
4076+ while (WTBL_LMAC_DW31[i].name) {
4077+ if (WTBL_LMAC_DW31[i].shift == NO_SHIFT_DEFINE)
4078+ seq_printf(s, "\t%s:%d\n", WTBL_LMAC_DW31[i].name,
4079+ (dw_value & WTBL_LMAC_DW31[i].mask) ? 1 : 0);
4080+ else
4081+ seq_printf(s, "\t%s:%u\n", WTBL_LMAC_DW31[i].name,
4082+ (dw_value & WTBL_LMAC_DW31[i].mask) >>
4083+ WTBL_LMAC_DW31[i].shift);
4084+ i++;
4085+ }
4086+}
4087+
4088+static const struct berse_wtbl_parse WTBL_LMAC_DW32[] = {
4089+ {"OM_INFO", WF_LWTBL_OM_INFO_MASK, WF_LWTBL_OM_INFO_SHIFT, false},
developerc2cfe0f2023-09-22 04:11:09 +0800[diff] [blame]4090+ {"OM_INFO_EHT", WF_LWTBL_OM_INFO_EHT_MASK, WF_LWTBL_OM_INFO_EHT_SHIFT, false},
4091+ {"RXD_DUP_FOR_OM_CHG", WF_LWTBL_RXD_DUP_FOR_OM_CHG_MASK, NO_SHIFT_DEFINE, false},
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]4092+ {"RXD_DUP_WHITE_LIST", WF_LWTBL_RXD_DUP_WHITE_LIST_MASK, WF_LWTBL_RXD_DUP_WHITE_LIST_SHIFT, false},
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]4093+ {NULL,}
4094+};
4095+
4096+static void parse_fmac_lwtbl_dw32(struct seq_file *s, u8 *lwtbl)
4097+{
4098+ u32 *addr = 0;
4099+ u32 dw_value = 0;
4100+ u16 i = 0;
4101+
4102+ /* LMAC WTBL DW 32 */
4103+ seq_printf(s, "\t\n");
4104+ seq_printf(s, "LWTBL DW 32\n");
4105+ addr = (u32 *)&(lwtbl[WTBL_GROUP_RX_DUP_INFO_DW_32*4]);
4106+ dw_value = *addr;
4107+
4108+ while (WTBL_LMAC_DW32[i].name) {
4109+ if (WTBL_LMAC_DW32[i].shift == NO_SHIFT_DEFINE)
4110+ seq_printf(s, "\t%s:%d\n", WTBL_LMAC_DW32[i].name,
4111+ (dw_value & WTBL_LMAC_DW32[i].mask) ? 1 : 0);
4112+ else
4113+ seq_printf(s, "\t%s:%u\n", WTBL_LMAC_DW32[i].name,
4114+ (dw_value & WTBL_LMAC_DW32[i].mask) >>
4115+ WTBL_LMAC_DW32[i].shift);
4116+ i++;
4117+ }
4118+}
4119+
4120+static const struct berse_wtbl_parse WTBL_LMAC_DW33[] = {
4121+ {"USER_RSSI", WF_LWTBL_USER_RSSI_MASK, WF_LWTBL_USER_RSSI_SHIFT, false},
4122+ {"USER_SNR", WF_LWTBL_USER_SNR_MASK, WF_LWTBL_USER_SNR_SHIFT, false},
4123+ {"RAPID_REACTION_RATE", WF_LWTBL_RAPID_REACTION_RATE_MASK, WF_LWTBL_RAPID_REACTION_RATE_SHIFT, true},
4124+ {"HT_AMSDU(Read Only)", WF_LWTBL_HT_AMSDU_MASK, NO_SHIFT_DEFINE, false},
4125+ {"AMSDU_CROSS_LG(Read Only)", WF_LWTBL_AMSDU_CROSS_LG_MASK, NO_SHIFT_DEFINE, true},
4126+ {NULL,}
4127+};
4128+
4129+static void parse_fmac_lwtbl_dw33(struct seq_file *s, u8 *lwtbl)
4130+{
4131+ u32 *addr = 0;
4132+ u32 dw_value = 0;
4133+ u16 i = 0;
4134+
4135+ /* LMAC WTBL DW 33 */
4136+ seq_printf(s, "\t\n");
4137+ seq_printf(s, "LWTBL DW 33\n");
4138+ addr = (u32 *)&(lwtbl[WTBL_GROUP_RX_STAT_CNT_LINE_1*4]);
4139+ dw_value = *addr;
4140+
4141+ while (WTBL_LMAC_DW33[i].name) {
4142+ if (WTBL_LMAC_DW33[i].shift == NO_SHIFT_DEFINE)
4143+ seq_printf(s, "\t%s:%d\n", WTBL_LMAC_DW33[i].name,
4144+ (dw_value & WTBL_LMAC_DW33[i].mask) ? 1 : 0);
4145+ else
4146+ seq_printf(s, "\t%s:%u\n", WTBL_LMAC_DW33[i].name,
4147+ (dw_value & WTBL_LMAC_DW33[i].mask) >>
4148+ WTBL_LMAC_DW33[i].shift);
4149+ i++;
4150+ }
4151+}
4152+
4153+static const struct berse_wtbl_parse WTBL_LMAC_DW34[] = {
4154+ {"RESP_RCPI0", WF_LWTBL_RESP_RCPI0_MASK, WF_LWTBL_RESP_RCPI0_SHIFT, false},
4155+ {"RCPI1", WF_LWTBL_RESP_RCPI1_MASK, WF_LWTBL_RESP_RCPI1_SHIFT, false},
4156+ {"RCPI2", WF_LWTBL_RESP_RCPI2_MASK, WF_LWTBL_RESP_RCPI2_SHIFT, false},
4157+ {"RCPI3", WF_LWTBL_RESP_RCPI3_MASK, WF_LWTBL_RESP_RCPI3_SHIFT, true},
4158+ {NULL,}
4159+};
4160+
4161+static void parse_fmac_lwtbl_dw34(struct seq_file *s, u8 *lwtbl)
4162+{
4163+ u32 *addr = 0;
4164+ u32 dw_value = 0;
4165+ u16 i = 0;
4166+
4167+ /* LMAC WTBL DW 34 */
4168+ seq_printf(s, "\t\n");
4169+ seq_printf(s, "LWTBL DW 34\n");
4170+ addr = (u32 *)&(lwtbl[WTBL_GROUP_RX_STAT_CNT_LINE_2*4]);
4171+ dw_value = *addr;
4172+
4173+
4174+ while (WTBL_LMAC_DW34[i].name) {
4175+ if (WTBL_LMAC_DW34[i].shift == NO_SHIFT_DEFINE)
4176+ seq_printf(s, "\t%s:%d\n", WTBL_LMAC_DW34[i].name,
4177+ (dw_value & WTBL_LMAC_DW34[i].mask) ? 1 : 0);
4178+ else
4179+ seq_printf(s, "\t%s:%u\n", WTBL_LMAC_DW34[i].name,
4180+ (dw_value & WTBL_LMAC_DW34[i].mask) >>
4181+ WTBL_LMAC_DW34[i].shift);
4182+ i++;
4183+ }
4184+}
4185+
4186+static const struct berse_wtbl_parse WTBL_LMAC_DW35[] = {
4187+ {"SNR 0", WF_LWTBL_SNR_RX0_MASK, WF_LWTBL_SNR_RX0_SHIFT, false},
4188+ {"SNR 1", WF_LWTBL_SNR_RX1_MASK, WF_LWTBL_SNR_RX1_SHIFT, false},
4189+ {"SNR 2", WF_LWTBL_SNR_RX2_MASK, WF_LWTBL_SNR_RX2_SHIFT, false},
4190+ {"SNR 3", WF_LWTBL_SNR_RX3_MASK, WF_LWTBL_SNR_RX3_SHIFT, true},
4191+ {NULL,}
4192+};
4193+
4194+static void parse_fmac_lwtbl_dw35(struct seq_file *s, u8 *lwtbl)
4195+{
4196+ u32 *addr = 0;
4197+ u32 dw_value = 0;
4198+ u16 i = 0;
4199+
4200+ /* LMAC WTBL DW 35 */
4201+ seq_printf(s, "\t\n");
4202+ seq_printf(s, "LWTBL DW 35\n");
4203+ addr = (u32 *)&(lwtbl[WTBL_GROUP_RX_STAT_CNT_LINE_3*4]);
4204+ dw_value = *addr;
4205+
4206+
4207+ while (WTBL_LMAC_DW35[i].name) {
4208+ if (WTBL_LMAC_DW35[i].shift == NO_SHIFT_DEFINE)
4209+ seq_printf(s, "\t%s:%d\n", WTBL_LMAC_DW35[i].name,
4210+ (dw_value & WTBL_LMAC_DW35[i].mask) ? 1 : 0);
4211+ else
4212+ seq_printf(s, "\t%s:%u\n", WTBL_LMAC_DW35[i].name,
4213+ (dw_value & WTBL_LMAC_DW35[i].mask) >>
4214+ WTBL_LMAC_DW35[i].shift);
4215+ i++;
4216+ }
4217+}
4218+
4219+static void parse_fmac_lwtbl_rx_stats(struct seq_file *s, u8 *lwtbl)
4220+{
4221+ parse_fmac_lwtbl_dw33(s, lwtbl);
4222+ parse_fmac_lwtbl_dw34(s, lwtbl);
4223+ parse_fmac_lwtbl_dw35(s, lwtbl);
4224+}
4225+
4226+static void parse_fmac_lwtbl_mlo_info(struct seq_file *s, u8 *lwtbl)
4227+{
4228+ parse_fmac_lwtbl_dw28(s, lwtbl);
4229+ parse_fmac_lwtbl_dw29(s, lwtbl);
4230+ parse_fmac_lwtbl_dw30(s, lwtbl);
4231+}
4232+
4233+static const struct berse_wtbl_parse WTBL_UMAC_DW9[] = {
4234+ {"RELATED_IDX0", WF_UWTBL_RELATED_IDX0_MASK, WF_UWTBL_RELATED_IDX0_SHIFT, false},
4235+ {"RELATED_BAND0", WF_UWTBL_RELATED_BAND0_MASK, WF_UWTBL_RELATED_BAND0_SHIFT, false},
4236+ {"PRI_MLD_BAND", WF_UWTBL_PRIMARY_MLD_BAND_MASK, WF_UWTBL_PRIMARY_MLD_BAND_SHIFT, true},
developerc2cfe0f2023-09-22 04:11:09 +0800[diff] [blame]4237+ {"RELATED_IDX1", WF_UWTBL_RELATED_IDX1_MASK, WF_UWTBL_RELATED_IDX1_SHIFT, false},
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]4238+ {"RELATED_BAND1", WF_UWTBL_RELATED_BAND1_MASK, WF_UWTBL_RELATED_BAND1_SHIFT, false},
4239+ {"SEC_MLD_BAND", WF_UWTBL_SECONDARY_MLD_BAND_MASK, WF_UWTBL_SECONDARY_MLD_BAND_SHIFT, true},
4240+ {NULL,}
4241+};
4242+
4243+static void parse_fmac_uwtbl_mlo_info(struct seq_file *s, u8 *uwtbl)
4244+{
4245+ u32 *addr = 0;
4246+ u32 dw_value = 0;
4247+ u16 i = 0;
4248+
4249+ seq_printf(s, "\t\n");
4250+ seq_printf(s, "MldAddr: %02x:%02x:%02x:%02x:%02x:%02x(D0[B0~15], D1[B0~31])\n",
4251+ uwtbl[4], uwtbl[5], uwtbl[6], uwtbl[7], uwtbl[0], uwtbl[1]);
4252+
4253+ /* UMAC WTBL DW 0 */
4254+ seq_printf(s, "\t\n");
4255+ seq_printf(s, "UWTBL DW 0\n");
4256+ addr = (u32 *)&(uwtbl[WF_UWTBL_OWN_MLD_ID_DW*4]);
4257+ dw_value = *addr;
4258+
4259+ seq_printf(s, "\t%s:%u\n", "OMLD_ID",
4260+ (dw_value & WF_UWTBL_OWN_MLD_ID_MASK) >> WF_UWTBL_OWN_MLD_ID_SHIFT);
4261+
4262+ /* UMAC WTBL DW 9 */
4263+ seq_printf(s, "\t\n");
4264+ seq_printf(s, "UWTBL DW 9\n");
4265+ addr = (u32 *)&(uwtbl[WF_UWTBL_RELATED_IDX0_DW*4]);
4266+ dw_value = *addr;
4267+
4268+ while (WTBL_UMAC_DW9[i].name) {
4269+
4270+ if (WTBL_UMAC_DW9[i].shift == NO_SHIFT_DEFINE)
4271+ seq_printf(s, "\t%s:%d\n", WTBL_UMAC_DW9[i].name,
4272+ (dw_value & WTBL_UMAC_DW9[i].mask) ? 1 : 0);
4273+ else
4274+ seq_printf(s, "\t%s:%u\n", WTBL_UMAC_DW9[i].name,
4275+ (dw_value & WTBL_UMAC_DW9[i].mask) >>
4276+ WTBL_UMAC_DW9[i].shift);
4277+ i++;
4278+ }
4279+}
4280+
4281+static bool
4282+is_wtbl_bigtk_exist(u8 *lwtbl)
4283+{
4284+ u32 *addr = 0;
4285+ u32 dw_value = 0;
4286+
4287+ addr = (u32 *)&(lwtbl[WF_LWTBL_MUAR_DW*4]);
4288+ dw_value = *addr;
4289+ if (((dw_value & WF_LWTBL_MUAR_MASK) >> WF_LWTBL_MUAR_SHIFT) ==
4290+ MUAR_INDEX_OWN_MAC_ADDR_BC_MC) {
4291+ addr = (u32 *)&(lwtbl[WF_LWTBL_CIPHER_SUIT_BIGTK_DW*4]);
4292+ dw_value = *addr;
4293+ if (((dw_value & WF_LWTBL_CIPHER_SUIT_BIGTK_MASK) >>
4294+ WF_LWTBL_CIPHER_SUIT_BIGTK_SHIFT) != IGTK_CIPHER_SUIT_NONE)
4295+ return true;
4296+ }
4297+
4298+ return false;
4299+}
4300+
4301+static const struct berse_wtbl_parse WTBL_UMAC_DW2[] = {
4302+ {"PN0", WTBL_PN0_MASK, WTBL_PN0_OFFSET, false},
4303+ {"PN1", WTBL_PN1_MASK, WTBL_PN1_OFFSET, false},
4304+ {"PN2", WTBL_PN2_MASK, WTBL_PN2_OFFSET, true},
4305+ {"PN3", WTBL_PN3_MASK, WTBL_PN3_OFFSET, false},
4306+ {NULL,}
4307+};
4308+
4309+static const struct berse_wtbl_parse WTBL_UMAC_DW3[] = {
4310+ {"PN4", WTBL_PN4_MASK, WTBL_PN4_OFFSET, false},
4311+ {"PN5", WTBL_PN5_MASK, WTBL_PN5_OFFSET, true},
developerc2cfe0f2023-09-22 04:11:09 +0800[diff] [blame]4312+ {"COM_SN", WF_UWTBL_COM_SN_MASK, WF_UWTBL_COM_SN_SHIFT, true},
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]4313+ {NULL,}
4314+};
4315+
4316+static const struct berse_wtbl_parse WTBL_UMAC_DW4_BIPN[] = {
4317+ {"BIPN0", WTBL_BIPN0_MASK, WTBL_BIPN0_OFFSET, false},
4318+ {"BIPN1", WTBL_BIPN1_MASK, WTBL_BIPN1_OFFSET, false},
4319+ {"BIPN2", WTBL_BIPN2_MASK, WTBL_BIPN2_OFFSET, true},
4320+ {"BIPN3", WTBL_BIPN3_MASK, WTBL_BIPN3_OFFSET, false},
4321+ {NULL,}
4322+};
4323+
4324+static const struct berse_wtbl_parse WTBL_UMAC_DW5_BIPN[] = {
developerc2cfe0f2023-09-22 04:11:09 +0800[diff] [blame]4325+ {"BIPN4", WTBL_BIPN4_MASK, WTBL_BIPN4_OFFSET, false},
4326+ {"BIPN5", WTBL_BIPN5_MASK, WTBL_BIPN5_OFFSET, true},
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]4327+ {NULL,}
4328+};
4329+
4330+static void parse_fmac_uwtbl_pn(struct seq_file *s, u8 *uwtbl, u8 *lwtbl)
4331+{
4332+ u32 *addr = 0;
4333+ u32 dw_value = 0;
4334+ u16 i = 0;
4335+
4336+ seq_printf(s, "\t\n");
4337+ seq_printf(s, "UWTBL PN\n");
4338+
4339+ /* UMAC WTBL DW 2/3 */
4340+ addr = (u32 *)&(uwtbl[WF_UWTBL_PN_31_0__DW*4]);
4341+ dw_value = *addr;
4342+
4343+ while (WTBL_UMAC_DW2[i].name) {
4344+ seq_printf(s, "\t%s:%u\n", WTBL_UMAC_DW2[i].name,
4345+ (dw_value & WTBL_UMAC_DW2[i].mask) >>
4346+ WTBL_UMAC_DW2[i].shift);
4347+ i++;
4348+ }
4349+
4350+ i = 0;
4351+ addr = (u32 *)&(uwtbl[WF_UWTBL_PN_47_32__DW*4]);
4352+ dw_value = *addr;
4353+
4354+ while (WTBL_UMAC_DW3[i].name) {
4355+ seq_printf(s, "\t%s:%u\n", WTBL_UMAC_DW3[i].name,
4356+ (dw_value & WTBL_UMAC_DW3[i].mask) >>
4357+ WTBL_UMAC_DW3[i].shift);
4358+ i++;
4359+ }
4360+
4361+
4362+ /* UMAC WTBL DW 4/5 for BIGTK */
4363+ if (is_wtbl_bigtk_exist(lwtbl) == true) {
4364+ i = 0;
4365+ addr = (u32 *)&(uwtbl[WF_UWTBL_RX_BIPN_31_0__DW*4]);
4366+ dw_value = *addr;
4367+
4368+ while (WTBL_UMAC_DW4_BIPN[i].name) {
4369+ seq_printf(s, "\t%s:%u\n", WTBL_UMAC_DW4_BIPN[i].name,
4370+ (dw_value & WTBL_UMAC_DW4_BIPN[i].mask) >>
4371+ WTBL_UMAC_DW4_BIPN[i].shift);
4372+ i++;
4373+ }
4374+
4375+ i = 0;
4376+ addr = (u32 *)&(uwtbl[WF_UWTBL_RX_BIPN_47_32__DW*4]);
4377+ dw_value = *addr;
4378+
4379+ while (WTBL_UMAC_DW5_BIPN[i].name) {
4380+ seq_printf(s, "\t%s:%u\n", WTBL_UMAC_DW5_BIPN[i].name,
4381+ (dw_value & WTBL_UMAC_DW5_BIPN[i].mask) >>
4382+ WTBL_UMAC_DW5_BIPN[i].shift);
4383+ i++;
4384+ }
4385+ }
4386+}
4387+
4388+static void parse_fmac_uwtbl_sn(struct seq_file *s, u8 *uwtbl)
4389+{
4390+ u32 *addr = 0;
4391+ u32 u2SN = 0;
4392+
4393+ /* UMAC WTBL DW SN part */
4394+ seq_printf(s, "\t\n");
4395+ seq_printf(s, "UWTBL SN\n");
4396+
4397+ addr = (u32 *)&(uwtbl[WF_UWTBL_TID0_SN_DW*4]);
4398+ u2SN = ((*addr) & WF_UWTBL_TID0_SN_MASK) >> WF_UWTBL_TID0_SN_SHIFT;
4399+ seq_printf(s, "\t%s:%u\n", "TID0_AC0_SN", u2SN);
4400+
4401+ addr = (u32 *)&(uwtbl[WF_UWTBL_TID1_SN_DW*4]);
4402+ u2SN = ((*addr) & WF_UWTBL_TID1_SN_MASK) >> WF_UWTBL_TID1_SN_SHIFT;
4403+ seq_printf(s, "\t%s:%u\n", "TID1_AC1_SN", u2SN);
4404+
4405+ addr = (u32 *)&(uwtbl[WF_UWTBL_TID2_SN_7_0__DW*4]);
4406+ u2SN = ((*addr) & WF_UWTBL_TID2_SN_7_0__MASK) >>
4407+ WF_UWTBL_TID2_SN_7_0__SHIFT;
4408+ addr = (u32 *)&(uwtbl[WF_UWTBL_TID2_SN_11_8__DW*4]);
4409+ u2SN |= (((*addr) & WF_UWTBL_TID2_SN_11_8__MASK) >>
4410+ WF_UWTBL_TID2_SN_11_8__SHIFT) << 8;
4411+ seq_printf(s, "\t%s:%u\n", "TID2_AC2_SN", u2SN);
4412+
4413+ addr = (u32 *)&(uwtbl[WF_UWTBL_TID3_SN_DW*4]);
4414+ u2SN = ((*addr) & WF_UWTBL_TID3_SN_MASK) >> WF_UWTBL_TID3_SN_SHIFT;
4415+ seq_printf(s, "\t%s:%u\n", "TID3_AC3_SN", u2SN);
4416+
4417+ addr = (u32 *)&(uwtbl[WF_UWTBL_TID4_SN_DW*4]);
4418+ u2SN = ((*addr) & WF_UWTBL_TID4_SN_MASK) >> WF_UWTBL_TID4_SN_SHIFT;
4419+ seq_printf(s, "\t%s:%u\n", "TID4_SN", u2SN);
4420+
4421+ addr = (u32 *)&(uwtbl[WF_UWTBL_TID5_SN_3_0__DW*4]);
4422+ u2SN = ((*addr) & WF_UWTBL_TID5_SN_3_0__MASK) >>
4423+ WF_UWTBL_TID5_SN_3_0__SHIFT;
4424+ addr = (u32 *)&(uwtbl[WF_UWTBL_TID5_SN_11_4__DW*4]);
4425+ u2SN |= (((*addr) & WF_UWTBL_TID5_SN_11_4__MASK) >>
4426+ WF_UWTBL_TID5_SN_11_4__SHIFT) << 4;
4427+ seq_printf(s, "\t%s:%u\n", "TID5_SN", u2SN);
4428+
4429+ addr = (u32 *)&(uwtbl[WF_UWTBL_TID6_SN_DW*4]);
4430+ u2SN = ((*addr) & WF_UWTBL_TID6_SN_MASK) >> WF_UWTBL_TID6_SN_SHIFT;
4431+ seq_printf(s, "\t%s:%u\n", "TID6_SN", u2SN);
4432+
4433+ addr = (u32 *)&(uwtbl[WF_UWTBL_TID7_SN_DW*4]);
4434+ u2SN = ((*addr) & WF_UWTBL_TID7_SN_MASK) >> WF_UWTBL_TID7_SN_SHIFT;
4435+ seq_printf(s, "\t%s:%u\n", "TID7_SN", u2SN);
4436+
4437+ addr = (u32 *)&(uwtbl[WF_UWTBL_COM_SN_DW*4]);
4438+ u2SN = ((*addr) & WF_UWTBL_COM_SN_MASK) >> WF_UWTBL_COM_SN_SHIFT;
4439+ seq_printf(s, "\t%s:%u\n", "COM_SN", u2SN);
4440+}
4441+
4442+static void dump_key_table(
4443+ struct seq_file *s,
4444+ uint16_t keyloc0,
4445+ uint16_t keyloc1,
4446+ uint16_t keyloc2
4447+)
4448+{
4449+#define ONE_KEY_ENTRY_LEN_IN_DW 8
4450+ struct mt7996_dev *dev = dev_get_drvdata(s->private);
4451+ u8 keytbl[ONE_KEY_ENTRY_LEN_IN_DW*4] = {0};
4452+ uint16_t x;
4453+
4454+ seq_printf(s, "\t\n");
4455+ seq_printf(s, "\t%s:%d\n", "keyloc0", keyloc0);
4456+ if (keyloc0 != INVALID_KEY_ENTRY) {
4457+
4458+ /* Don't swap below two lines, halWtblReadRaw will
4459+ * write new value WF_WTBLON_TOP_WDUCR_ADDR
4460+ */
4461+ mt7996_wtbl_read_raw(dev, keyloc0,
4462+ WTBL_TYPE_KEY, 0, ONE_KEY_ENTRY_LEN_IN_DW, keytbl);
4463+ seq_printf(s, "\t\tKEY WTBL Addr: group:0x%x=0x%x addr: 0x%lx\n",
4464+ MT_DBG_UWTBL_TOP_WDUCR_ADDR,
4465+ mt76_rr(dev, MT_DBG_UWTBL_TOP_WDUCR_ADDR),
4466+ KEYTBL_IDX2BASE(keyloc0, 0));
4467+ for (x = 0; x < ONE_KEY_ENTRY_LEN_IN_DW; x++) {
4468+ seq_printf(s, "\t\tDW%02d: %02x %02x %02x %02x\n",
4469+ x,
4470+ keytbl[x * 4 + 3],
4471+ keytbl[x * 4 + 2],
4472+ keytbl[x * 4 + 1],
4473+ keytbl[x * 4]);
4474+ }
4475+ }
4476+
4477+ seq_printf(s, "\t%s:%d\n", "keyloc1", keyloc1);
4478+ if (keyloc1 != INVALID_KEY_ENTRY) {
4479+ /* Don't swap below two lines, halWtblReadRaw will
4480+ * write new value WF_WTBLON_TOP_WDUCR_ADDR
4481+ */
4482+ mt7996_wtbl_read_raw(dev, keyloc1,
4483+ WTBL_TYPE_KEY, 0, ONE_KEY_ENTRY_LEN_IN_DW, keytbl);
4484+ seq_printf(s, "\t\tKEY WTBL Addr: group:0x%x=0x%x addr: 0x%lx\n",
4485+ MT_DBG_UWTBL_TOP_WDUCR_ADDR,
4486+ mt76_rr(dev, MT_DBG_UWTBL_TOP_WDUCR_ADDR),
4487+ KEYTBL_IDX2BASE(keyloc1, 0));
4488+ for (x = 0; x < ONE_KEY_ENTRY_LEN_IN_DW; x++) {
4489+ seq_printf(s, "\t\tDW%02d: %02x %02x %02x %02x\n",
4490+ x,
4491+ keytbl[x * 4 + 3],
4492+ keytbl[x * 4 + 2],
4493+ keytbl[x * 4 + 1],
4494+ keytbl[x * 4]);
4495+ }
4496+ }
4497+
4498+ seq_printf(s, "\t%s:%d\n", "keyloc2", keyloc2);
4499+ if (keyloc2 != INVALID_KEY_ENTRY) {
4500+ /* Don't swap below two lines, halWtblReadRaw will
4501+ * write new value WF_WTBLON_TOP_WDUCR_ADDR
4502+ */
4503+ mt7996_wtbl_read_raw(dev, keyloc2,
4504+ WTBL_TYPE_KEY, 0, ONE_KEY_ENTRY_LEN_IN_DW, keytbl);
4505+ seq_printf(s, "\t\tKEY WTBL Addr: group:0x%x=0x%x addr: 0x%lx\n",
4506+ MT_DBG_UWTBL_TOP_WDUCR_ADDR,
4507+ mt76_rr(dev, MT_DBG_UWTBL_TOP_WDUCR_ADDR),
4508+ KEYTBL_IDX2BASE(keyloc2, 0));
4509+ for (x = 0; x < ONE_KEY_ENTRY_LEN_IN_DW; x++) {
4510+ seq_printf(s, "\t\tDW%02d: %02x %02x %02x %02x\n",
4511+ x,
4512+ keytbl[x * 4 + 3],
4513+ keytbl[x * 4 + 2],
4514+ keytbl[x * 4 + 1],
4515+ keytbl[x * 4]);
4516+ }
4517+ }
4518+}
4519+
4520+static void parse_fmac_uwtbl_key_info(struct seq_file *s, u8 *uwtbl, u8 *lwtbl)
4521+{
4522+ u32 *addr = 0;
4523+ u32 dw_value = 0;
4524+ uint16_t keyloc0 = INVALID_KEY_ENTRY;
4525+ uint16_t keyloc1 = INVALID_KEY_ENTRY;
4526+ uint16_t keyloc2 = INVALID_KEY_ENTRY;
4527+
4528+ /* UMAC WTBL DW 7 */
4529+ seq_printf(s, "\t\n");
4530+ seq_printf(s, "UWTBL key info\n");
4531+
4532+ addr = (u32 *)&(uwtbl[WF_UWTBL_KEY_LOC0_DW*4]);
4533+ dw_value = *addr;
4534+ keyloc0 = (dw_value & WF_UWTBL_KEY_LOC0_MASK) >> WF_UWTBL_KEY_LOC0_SHIFT;
4535+ keyloc1 = (dw_value & WF_UWTBL_KEY_LOC1_MASK) >> WF_UWTBL_KEY_LOC1_SHIFT;
4536+
4537+ seq_printf(s, "\t%s:%u/%u\n", "Key Loc 0/1", keyloc0, keyloc1);
4538+
4539+ /* UMAC WTBL DW 6 for BIGTK */
4540+ if (is_wtbl_bigtk_exist(lwtbl) == true) {
developerc2cfe0f2023-09-22 04:11:09 +0800[diff] [blame]4541+ addr = (u32 *)&(uwtbl[WF_UWTBL_KEY_LOC2_DW*4]);
4542+ dw_value = *addr;
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]4543+ keyloc2 = (dw_value & WF_UWTBL_KEY_LOC2_MASK) >>
4544+ WF_UWTBL_KEY_LOC2_SHIFT;
4545+ seq_printf(s, "\t%s:%u\n", "Key Loc 2", keyloc2);
4546+ }
4547+
4548+ /* Parse KEY link */
4549+ dump_key_table(s, keyloc0, keyloc1, keyloc2);
4550+}
4551+
4552+static const struct berse_wtbl_parse WTBL_UMAC_DW8[] = {
4553+ {"UWTBL_WMM_Q", WF_UWTBL_WMM_Q_MASK, WF_UWTBL_WMM_Q_SHIFT, false},
4554+ {"UWTBL_QOS", WF_UWTBL_QOS_MASK, NO_SHIFT_DEFINE, false},
4555+ {"UWTBL_HT_VHT_HE", WF_UWTBL_HT_MASK, NO_SHIFT_DEFINE, false},
4556+ {"UWTBL_HDRT_MODE", WF_UWTBL_HDRT_MODE_MASK, NO_SHIFT_DEFINE, true},
4557+ {NULL,}
4558+};
4559+
4560+static void parse_fmac_uwtbl_msdu_info(struct seq_file *s, u8 *uwtbl)
4561+{
4562+ u32 *addr = 0;
4563+ u32 dw_value = 0;
4564+ u32 amsdu_len = 0;
4565+ u16 i = 0;
4566+
4567+ /* UMAC WTBL DW 8 */
4568+ seq_printf(s, "\t\n");
4569+ seq_printf(s, "UWTBL DW8\n");
4570+
4571+ addr = (u32 *)&(uwtbl[WF_UWTBL_AMSDU_CFG_DW*4]);
4572+ dw_value = *addr;
4573+
4574+ while (WTBL_UMAC_DW8[i].name) {
4575+
4576+ if (WTBL_UMAC_DW8[i].shift == NO_SHIFT_DEFINE)
4577+ seq_printf(s, "\t%s:%d\n", WTBL_UMAC_DW8[i].name,
4578+ (dw_value & WTBL_UMAC_DW8[i].mask) ? 1 : 0);
4579+ else
4580+ seq_printf(s, "\t%s:%u\n", WTBL_UMAC_DW8[i].name,
4581+ (dw_value & WTBL_UMAC_DW8[i].mask) >>
4582+ WTBL_UMAC_DW8[i].shift);
4583+ i++;
4584+ }
4585+
developerc2cfe0f2023-09-22 04:11:09 +0800[diff] [blame]4586+ /* UMAC WTBL DW 8 - SEC_ADDR_MODE */
4587+ addr = (u32 *)&(uwtbl[WF_UWTBL_SEC_ADDR_MODE_DW*4]);
4588+ dw_value = *addr;
4589+ seq_printf(s, "\t%s:%lu\n", "SEC_ADDR_MODE",
4590+ (dw_value & WTBL_SEC_ADDR_MODE_MASK) >> WTBL_SEC_ADDR_MODE_OFFSET);
4591+
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]4592+ /* UMAC WTBL DW 8 - AMSDU_CFG */
4593+ seq_printf(s, "\t%s:%d\n", "HW AMSDU Enable",
4594+ (dw_value & WTBL_AMSDU_EN_MASK) ? 1 : 0);
4595+
4596+ amsdu_len = (dw_value & WTBL_AMSDU_LEN_MASK) >> WTBL_AMSDU_LEN_OFFSET;
4597+ if (amsdu_len == 0)
4598+ seq_printf(s, "\t%s:invalid (WTBL value=0x%x)\n", "HW AMSDU Len",
4599+ amsdu_len);
4600+ else if (amsdu_len == 1)
4601+ seq_printf(s, "\t%s:%d~%d (WTBL value=0x%x)\n", "HW AMSDU Len",
4602+ 1,
4603+ 255,
4604+ amsdu_len);
4605+ else if (amsdu_len == 2)
4606+ seq_printf(s, "\t%s:%d~%d (WTBL value=0x%x)\n", "HW AMSDU Len",
4607+ 256,
4608+ 511,
4609+ amsdu_len);
4610+ else if (amsdu_len == 3)
4611+ seq_printf(s, "\t%s:%d~%d (WTBL value=0x%x)\n", "HW AMSDU Len",
4612+ 512,
4613+ 767,
4614+ amsdu_len);
4615+ else
4616+ seq_printf(s, "\t%s:%d~%d (WTBL value=0x%x)\n", "HW AMSDU Len",
4617+ 256 * (amsdu_len - 1),
4618+ 256 * (amsdu_len - 1) + 255,
4619+ amsdu_len);
4620+
4621+ seq_printf(s, "\t%s:%lu (WTBL value=0x%lx)\n", "HW AMSDU Num",
4622+ ((dw_value & WTBL_AMSDU_NUM_MASK) >> WTBL_AMSDU_NUM_OFFSET) + 1,
4623+ (dw_value & WTBL_AMSDU_NUM_MASK) >> WTBL_AMSDU_NUM_OFFSET);
4624+}
4625+
4626+static int mt7996_wtbl_read(struct seq_file *s, void *data)
4627+{
4628+ struct mt7996_dev *dev = dev_get_drvdata(s->private);
4629+ u8 lwtbl[LWTBL_LEN_IN_DW * 4] = {0};
4630+ u8 uwtbl[UWTBL_LEN_IN_DW * 4] = {0};
4631+ int x;
4632+
4633+ mt7996_wtbl_read_raw(dev, dev->wlan_idx, WTBL_TYPE_LMAC, 0,
4634+ LWTBL_LEN_IN_DW, lwtbl);
4635+ seq_printf(s, "Dump WTBL info of WLAN_IDX:%d\n", dev->wlan_idx);
4636+ seq_printf(s, "LMAC WTBL Addr: group:0x%x=0x%x addr: 0x%lx\n",
4637+ MT_DBG_WTBLON_TOP_WDUCR_ADDR,
4638+ mt76_rr(dev, MT_DBG_WTBLON_TOP_WDUCR_ADDR),
4639+ LWTBL_IDX2BASE(dev->wlan_idx, 0));
4640+ for (x = 0; x < LWTBL_LEN_IN_DW; x++) {
4641+ seq_printf(s, "DW%02d: %02x %02x %02x %02x\n",
4642+ x,
4643+ lwtbl[x * 4 + 3],
4644+ lwtbl[x * 4 + 2],
4645+ lwtbl[x * 4 + 1],
4646+ lwtbl[x * 4]);
4647+ }
4648+
4649+ /* Parse LWTBL */
4650+ parse_fmac_lwtbl_dw0_1(s, lwtbl);
4651+ parse_fmac_lwtbl_dw2(s, lwtbl);
4652+ parse_fmac_lwtbl_dw3(s, lwtbl);
4653+ parse_fmac_lwtbl_dw4(s, lwtbl);
4654+ parse_fmac_lwtbl_dw5(s, lwtbl);
4655+ parse_fmac_lwtbl_dw6(s, lwtbl);
4656+ parse_fmac_lwtbl_dw7(s, lwtbl);
4657+ parse_fmac_lwtbl_dw8(s, lwtbl);
4658+ parse_fmac_lwtbl_dw9(s, lwtbl);
4659+ parse_fmac_lwtbl_dw10(s, lwtbl);
4660+ parse_fmac_lwtbl_dw11(s, lwtbl);
4661+ parse_fmac_lwtbl_dw12(s, lwtbl);
4662+ parse_fmac_lwtbl_dw13(s, lwtbl);
4663+ parse_fmac_lwtbl_dw14(s, lwtbl);
4664+ parse_fmac_lwtbl_mlo_info(s, lwtbl);
4665+ parse_fmac_lwtbl_dw31(s, lwtbl);
4666+ parse_fmac_lwtbl_dw32(s, lwtbl);
4667+ parse_fmac_lwtbl_rx_stats(s, lwtbl);
4668+
4669+ mt7996_wtbl_read_raw(dev, dev->wlan_idx, WTBL_TYPE_UMAC, 0,
4670+ UWTBL_LEN_IN_DW, uwtbl);
4671+ seq_printf(s, "Dump WTBL info of WLAN_IDX:%d\n", dev->wlan_idx);
4672+ seq_printf(s, "UMAC WTBL Addr: group:0x%x=0x%x addr: 0x%lx\n",
4673+ MT_DBG_UWTBL_TOP_WDUCR_ADDR,
4674+ mt76_rr(dev, MT_DBG_UWTBL_TOP_WDUCR_ADDR),
4675+ UWTBL_IDX2BASE(dev->wlan_idx, 0));
4676+ for (x = 0; x < UWTBL_LEN_IN_DW; x++) {
4677+ seq_printf(s, "DW%02d: %02x %02x %02x %02x\n",
4678+ x,
4679+ uwtbl[x * 4 + 3],
4680+ uwtbl[x * 4 + 2],
4681+ uwtbl[x * 4 + 1],
4682+ uwtbl[x * 4]);
4683+ }
4684+
4685+ /* Parse UWTBL */
4686+ parse_fmac_uwtbl_mlo_info(s, uwtbl);
4687+ parse_fmac_uwtbl_pn(s, uwtbl, lwtbl);
4688+ parse_fmac_uwtbl_sn(s, uwtbl);
4689+ parse_fmac_uwtbl_key_info(s, uwtbl, lwtbl);
4690+ parse_fmac_uwtbl_msdu_info(s, uwtbl);
4691+
4692+ return 0;
4693+}
4694+
4695+static int mt7996_sta_info(struct seq_file *s, void *data)
4696+{
4697+ struct mt7996_dev *dev = dev_get_drvdata(s->private);
4698+ u8 lwtbl[LWTBL_LEN_IN_DW*4] = {0};
4699+ u16 i = 0;
4700+
4701+ for (i=0; i < mt7996_wtbl_size(dev); i++) {
4702+ mt7996_wtbl_read_raw(dev, i, WTBL_TYPE_LMAC, 0,
4703+ LWTBL_LEN_IN_DW, lwtbl);
4704+
4705+ if (lwtbl[4] || lwtbl[5] || lwtbl[6] || lwtbl[7] || lwtbl[0] || lwtbl[1]) {
4706+ u32 *addr = (u32 *)&(lwtbl[WTBL_GROUP_TRX_CAP_DW_2*4]);
4707+ u32 dw_value = *addr;
4708+
4709+ seq_printf(s, "wcid:%d\tAddr: %02x:%02x:%02x:%02x:%02x:%02x",
4710+ i, lwtbl[4], lwtbl[5], lwtbl[6], lwtbl[7], lwtbl[0], lwtbl[1]);
4711+ seq_printf(s, "\t%s:%u\n", WTBL_LMAC_DW2[0].name,
4712+ (dw_value & WTBL_LMAC_DW2[0].mask) >> WTBL_LMAC_DW2[0].shift);
4713+ }
4714+ }
4715+
4716+ return 0;
4717+}
4718+
4719+int mt7996_mtk_init_debugfs(struct mt7996_phy *phy, struct dentry *dir)
4720+{
4721+ struct mt7996_dev *dev = phy->dev;
4722+
4723+ mt7996_mcu_fw_log_2_host(dev, MCU_FW_LOG_WM, 0);
4724+
4725+ /* agg */
4726+ debugfs_create_devm_seqfile(dev->mt76.dev, "agg_info0", dir,
4727+ mt7996_agginfo_read_band0);
4728+ debugfs_create_devm_seqfile(dev->mt76.dev, "agg_info1", dir,
4729+ mt7996_agginfo_read_band1);
4730+ debugfs_create_devm_seqfile(dev->mt76.dev, "agg_info2", dir,
4731+ mt7996_agginfo_read_band2);
4732+ /* amsdu */
4733+ debugfs_create_devm_seqfile(dev->mt76.dev, "amsdu_info", dir,
4734+ mt7996_amsdu_result_read);
4735+
4736+ debugfs_create_file("fw_debug_module", 0600, dir, dev,
4737+ &fops_fw_debug_module);
4738+ debugfs_create_file("fw_debug_level", 0600, dir, dev,
4739+ &fops_fw_debug_level);
4740+ debugfs_create_file("fw_wa_query", 0600, dir, dev, &fops_wa_query);
4741+ debugfs_create_file("fw_wa_set", 0600, dir, dev, &fops_wa_set);
4742+ debugfs_create_devm_seqfile(dev->mt76.dev, "fw_version", dir,
4743+ mt7996_dump_version);
developer064da3c2023-06-13 15:57:26 +0800[diff] [blame]4744+ debugfs_create_devm_seqfile(dev->mt76.dev, "fw_wa_info", dir,
4745+ mt7996_fw_wa_info_read);
4746+ debugfs_create_devm_seqfile(dev->mt76.dev, "fw_wm_info", dir,
4747+ mt7996_fw_wm_info_read);
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]4748+
4749+ debugfs_create_devm_seqfile(dev->mt76.dev, "mib_info0", dir,
4750+ mt7996_mibinfo_band0);
4751+ debugfs_create_devm_seqfile(dev->mt76.dev, "mib_info1", dir,
4752+ mt7996_mibinfo_band1);
4753+ debugfs_create_devm_seqfile(dev->mt76.dev, "mib_info2", dir,
4754+ mt7996_mibinfo_band2);
4755+
4756+ debugfs_create_devm_seqfile(dev->mt76.dev, "sta_info", dir,
4757+ mt7996_sta_info);
4758+
4759+ debugfs_create_devm_seqfile(dev->mt76.dev, "tr_info", dir,
4760+ mt7996_trinfo_read);
4761+
4762+ debugfs_create_devm_seqfile(dev->mt76.dev, "wtbl_info", dir,
4763+ mt7996_wtbl_read);
4764+
developer064da3c2023-06-13 15:57:26 +0800[diff] [blame]4765+ debugfs_create_u8("sku_disable", 0600, dir, &dev->dbg.sku_disable);
4766+
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]4767+ return 0;
4768+}
4769+
4770+#endif
4771diff --git a/mt7996/mtk_mcu.c b/mt7996/mtk_mcu.c
4772new file mode 100644
developerc2cfe0f2023-09-22 04:11:09 +0800[diff] [blame]4773index 000000000..e88701667
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]4774--- /dev/null
4775+++ b/mt7996/mtk_mcu.c
4776@@ -0,0 +1,18 @@
4777+// SPDX-License-Identifier: ISC
4778+/*
4779+ * Copyright (C) 2023 MediaTek Inc.
4780+ */
4781+
4782+#include <linux/firmware.h>
4783+#include <linux/fs.h>
4784+#include "mt7996.h"
4785+#include "mcu.h"
4786+#include "mac.h"
4787+#include "mtk_mcu.h"
4788+
4789+#ifdef CONFIG_MTK_DEBUG
4790+
4791+
4792+
4793+
4794+#endif
4795diff --git a/mt7996/mtk_mcu.h b/mt7996/mtk_mcu.h
4796new file mode 100644
developerc2cfe0f2023-09-22 04:11:09 +0800[diff] [blame]4797index 000000000..e741aa278
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]4798--- /dev/null
4799+++ b/mt7996/mtk_mcu.h
4800@@ -0,0 +1,16 @@
4801+/* SPDX-License-Identifier: ISC */
4802+/*
4803+ * Copyright (C) 2023 MediaTek Inc.
4804+ */
4805+
4806+#ifndef __MT7996_MTK_MCU_H
4807+#define __MT7996_MTK_MCU_H
4808+
4809+#include "../mt76_connac_mcu.h"
4810+
4811+#ifdef CONFIG_MTK_DEBUG
4812+
4813+
4814+#endif
4815+
4816+#endif
4817diff --git a/tools/fwlog.c b/tools/fwlog.c
developerc2cfe0f2023-09-22 04:11:09 +0800[diff] [blame]4818index e5d4a1051..3c6a61d71 100644
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]4819--- a/tools/fwlog.c
4820+++ b/tools/fwlog.c
4821@@ -26,7 +26,7 @@ static const char *debugfs_path(const char *phyname, const char *file)
4822 return path;
4823 }
4824
4825-static int mt76_set_fwlog_en(const char *phyname, bool en)
4826+static int mt76_set_fwlog_en(const char *phyname, bool en, char *val)
4827 {
4828 FILE *f = fopen(debugfs_path(phyname, "fw_debug_bin"), "w");
4829
4830@@ -35,7 +35,13 @@ static int mt76_set_fwlog_en(const char *phyname, bool en)
4831 return 1;
4832 }
4833
4834- fprintf(f, "7");
4835+ if (en && val)
4836+ fprintf(f, "%s", val);
4837+ else if (en)
4838+ fprintf(f, "7");
4839+ else
4840+ fprintf(f, "0");
4841+
4842 fclose(f);
4843
4844 return 0;
4845@@ -76,6 +82,7 @@ static void handle_signal(int sig)
4846
4847 int mt76_fwlog(const char *phyname, int argc, char **argv)
4848 {
4849+#define BUF_SIZE 1504
4850 struct sockaddr_in local = {
4851 .sin_family = AF_INET,
4852 .sin_addr.s_addr = INADDR_ANY,
4853@@ -84,9 +91,9 @@ int mt76_fwlog(const char *phyname, int argc, char **argv)
4854 .sin_family = AF_INET,
4855 .sin_port = htons(55688),
4856 };
4857- char buf[1504];
4858+ char *buf = calloc(BUF_SIZE, sizeof(char));
4859 int ret = 0;
4860- int yes = 1;
4861+ /* int yes = 1; */
4862 int s, fd;
4863
4864 if (argc < 1) {
4865@@ -105,13 +112,13 @@ int mt76_fwlog(const char *phyname, int argc, char **argv)
4866 return 1;
4867 }
4868
4869- setsockopt(s, SOL_SOCKET, SO_BROADCAST, &yes, sizeof(yes));
4870+ /* setsockopt(s, SOL_SOCKET, SO_BROADCAST, &yes, sizeof(yes)); */
4871 if (bind(s, (struct sockaddr *)&local, sizeof(local)) < 0) {
4872 perror("bind");
4873 return 1;
4874 }
4875
4876- if (mt76_set_fwlog_en(phyname, true))
4877+ if (mt76_set_fwlog_en(phyname, true, argv[1]))
4878 return 1;
4879
4880 fd = open(debugfs_path(phyname, "fwlog_data"), O_RDONLY);
4881@@ -145,8 +152,8 @@ int mt76_fwlog(const char *phyname, int argc, char **argv)
4882 if (!r)
4883 continue;
4884
4885- if (len > sizeof(buf)) {
4886- fprintf(stderr, "Length error: %d > %d\n", len, (int)sizeof(buf));
4887+ if (len > BUF_SIZE) {
4888+ fprintf(stderr, "Length error: %d > %d\n", len, BUF_SIZE);
4889 ret = 1;
4890 break;
4891 }
4892@@ -171,7 +178,7 @@ int mt76_fwlog(const char *phyname, int argc, char **argv)
4893 close(fd);
4894
4895 out:
4896- mt76_set_fwlog_en(phyname, false);
4897+ mt76_set_fwlog_en(phyname, false, NULL);
4898
4899 return ret;
4900 }
4901--
developerde9ecce2023-05-22 11:17:16 +0800[diff] [blame]49022.39.2
developer1bc2ce22023-03-25 00:47:41 +0800[diff] [blame]4903