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git01.mediatek.com / openwrt / feeds / mtk-openwrt-feeds / 02e6591eb0105ded56f511ace512fe87f67a1491 / . / package-21.02 / kernel / crypto-eip / src / ddk / kit / eip197 / eip97_global_event.c
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developer02e65912023-08-17 16:33:10 +0800[diff] [blame^]1/* eip97_global_event.c
2 *
3 * EIP-97 Global Control Driver Library
4 * Event Management Module
5 */
6
7/* -------------------------------------------------------------------------- */
8/* */
9/* Module : ddk197 */
10/* Version : 5.6.1 */
11/* Configuration : DDK-197-GPL */
12/* */
13/* Date : 2022-Dec-16 */
14/* */
15/* Copyright (c) 2008-2022 by Rambus, Inc. and/or its subsidiaries. */
16/* */
17/* This program is free software: you can redistribute it and/or modify */
18/* it under the terms of the GNU General Public License as published by */
19/* the Free Software Foundation, either version 2 of the License, or */
20/* any later version. */
21/* */
22/* This program is distributed in the hope that it will be useful, */
23/* but WITHOUT ANY WARRANTY; without even the implied warranty of */
24/* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the */
25/* GNU General Public License for more details. */
26/* */
27/* You should have received a copy of the GNU General Public License */
28/* along with this program. If not, see <http://www.gnu.org/licenses/>. */
29/* -------------------------------------------------------------------------- */
30
31/*----------------------------------------------------------------------------
32 * This module implements (provides) the following interface(s):
33 */
34
35#include "eip97_global_event.h"
36
37
38/*----------------------------------------------------------------------------
39 * This module uses (requires) the following interface(s):
40 */
41
42// Default configuration
43#include "c_eip97_global.h"
44
45// Driver Framework Basic Definitions API
46#include "basic_defs.h" // uint32_t
47
48// Driver Framework Device API
49#include "device_types.h" // Device_Handle_t
50
51// EIP-97 Global Control Driver Library Internal interfaces
52#include "eip97_global_internal.h"
53#include "eip202_global_level0.h" // EIP-202 Level 0 macros
54#include "eip96_level0.h" // EIP-96 Level 0 macros
55#include "eip97_global_fsm.h" // State machine
56#include "eip97_global_level0.h"
57
58/*----------------------------------------------------------------------------
59 * Definitions and macros
60 */
61
62
63/*----------------------------------------------------------------------------
64 * Local variables
65 */
66
67#ifdef EIP97_REG_DBG_BASE
68/*----------------------------------------------------------------------------
69 * EIP97_Global_Debug_Statistics_Get
70 */
71EIP97_Global_Error_t
72EIP97_Global_Debug_Statistics_Get(
73 EIP97_Global_IOArea_t * const IOArea_p,
74 EIP97_Global_Debug_Statistics_t * const Debug_Statistics_p)
75{
76 Device_Handle_t Device;
77 unsigned int i;
78 volatile EIP97_True_IOArea_t * const TrueIOArea_p = IOAREA(IOArea_p);
79
80 EIP97_GLOBAL_CHECK_POINTER(IOArea_p);
81 EIP97_GLOBAL_CHECK_POINTER(Debug_Statistics_p);
82
83 Device = TrueIOArea_p->Device;
84
85 for (i = 0; i < 16; i++)
86 {
87 EIP97_DBG_RING_IN_COUNT_RD(Device,
88 i,
89 &Debug_Statistics_p->Ifc_Packets_In[i]);
90 EIP97_DBG_RING_OUT_COUNT_RD(Device,
91 i,
92 &Debug_Statistics_p->Ifc_Packets_Out[i]);
93
94 }
95 for (i = 0; i < EIP97_GLOBAL_MAX_NOF_PE_TO_USE; i++)
96 {
97 EIP97_DBG_PIPE_COUNT_RD(Device,
98 i,
99 &Debug_Statistics_p->Pipe_Total_Packets[i],
100 &Debug_Statistics_p->Pipe_Current_Packets[i],
101 &Debug_Statistics_p->Pipe_Max_Packets[i]);
102 EIP97_DBG_PIPE_DCOUNT_RD(Device,
103 i,
104 &Debug_Statistics_p->Pipe_Data_Count[i]);
105 }
106 for (i = EIP97_GLOBAL_MAX_NOF_PE_TO_USE; i < 16; i++)
107 {
108 Debug_Statistics_p->Pipe_Total_Packets[i] = 0;
109 Debug_Statistics_p->Pipe_Current_Packets[i] = 0;
110 Debug_Statistics_p->Pipe_Max_Packets[i] = 0;
111 Debug_Statistics_p->Pipe_Data_Count[i] = 0;
112 }
113 return 0;
114}
115#endif
116
117/*----------------------------------------------------------------------------
118 * EIP97_Global_DFE_Status_Get
119 */
120EIP97_Global_Error_t
121EIP97_Global_DFE_Status_Get(
122 EIP97_Global_IOArea_t * const IOArea_p,
123 const unsigned int PE_Number,
124 EIP97_Global_DFE_Status_t * const DFE_Status_p)
125{
126 Device_Handle_t Device;
127 volatile EIP97_True_IOArea_t * const TrueIOArea_p = IOAREA(IOArea_p);
128 unsigned int DFEDSEOffset;
129 DFEDSEOffset = EIP97_DFEDSE_Offset_Get();
130
131 EIP97_GLOBAL_CHECK_POINTER(IOArea_p);
132 EIP97_GLOBAL_CHECK_POINTER(DFE_Status_p);
133
134 if(PE_Number >= EIP97_GLOBAL_MAX_NOF_PE_TO_USE)
135 return EIP97_GLOBAL_ARGUMENT_ERROR;
136
137 Device = TrueIOArea_p->Device;
138
139 EIP202_DFE_TRD_STAT_RD(Device,
140 DFEDSEOffset,
141 PE_Number,
142 &DFE_Status_p->CDFifoWord32Count,
143 &DFE_Status_p->CDR_ID,
144 &DFE_Status_p->DMASize,
145 &DFE_Status_p->fAtDMABusy,
146 &DFE_Status_p->fDataDMABusy,
147 &DFE_Status_p->fDMAError);
148
149#ifdef EIP97_GLOBAL_DEBUG_FSM
150 {
151 EIP97_Global_Error_t rv;
152
153 if(DFE_Status_p->fDMAError)
154 rv = EIP97_Global_State_Set(
155 (volatile EIP97_Global_State_t*)&TrueIOArea_p->State,
156 EIP97_GLOBAL_STATE_FATAL_ERROR);
157 else
158 // Remain in the current state
159 rv = EIP97_Global_State_Set(
160 (volatile EIP97_Global_State_t*)&TrueIOArea_p->State,
161 (EIP97_Global_State_t)TrueIOArea_p->State);
162 if(rv != EIP97_GLOBAL_NO_ERROR)
163 return EIP97_GLOBAL_ILLEGAL_IN_STATE;
164 }
165#endif // EIP97_GLOBAL_DEBUG_FSM
166
167 return EIP97_GLOBAL_NO_ERROR;
168}
169
170
171/*----------------------------------------------------------------------------
172 * EIP97_Global_DSE_Status_Get
173 */
174EIP97_Global_Error_t
175EIP97_Global_DSE_Status_Get(
176 EIP97_Global_IOArea_t * const IOArea_p,
177 const unsigned int PE_Number,
178 EIP97_Global_DSE_Status_t * const DSE_Status_p)
179{
180 Device_Handle_t Device;
181 volatile EIP97_True_IOArea_t * const TrueIOArea_p = IOAREA(IOArea_p);
182 unsigned int DFEDSEOffset;
183 DFEDSEOffset = EIP97_DFEDSE_Offset_Get();
184
185 EIP97_GLOBAL_CHECK_POINTER(IOArea_p);
186 EIP97_GLOBAL_CHECK_POINTER(DSE_Status_p);
187
188 if(PE_Number >= EIP97_GLOBAL_MAX_NOF_PE_TO_USE)
189 return EIP97_GLOBAL_ARGUMENT_ERROR;
190
191 Device = TrueIOArea_p->Device;
192
193 EIP202_DSE_TRD_STAT_RD(Device,
194 DFEDSEOffset,
195 PE_Number,
196 &DSE_Status_p->RDFifoWord32Count,
197 &DSE_Status_p->RDR_ID,
198 &DSE_Status_p->DMASize,
199 &DSE_Status_p->fDataFlushBusy,
200 &DSE_Status_p->fDataDMABusy,
201 &DSE_Status_p->fDMAError);
202
203#ifdef EIP97_GLOBAL_DEBUG_FSM
204 {
205 EIP97_Global_Error_t rv;
206
207 if(DSE_Status_p->fDMAError)
208 rv = EIP97_Global_State_Set(
209 (volatile EIP97_Global_State_t*)&TrueIOArea_p->State,
210 EIP97_GLOBAL_STATE_FATAL_ERROR);
211 else
212 // Remain in the current state
213 rv = EIP97_Global_State_Set(
214 (volatile EIP97_Global_State_t*)&TrueIOArea_p->State,
215 (EIP97_Global_State_t)TrueIOArea_p->State);
216 if(rv != EIP97_GLOBAL_NO_ERROR)
217 return EIP97_GLOBAL_ILLEGAL_IN_STATE;
218 }
219#endif // EIP97_GLOBAL_DEBUG_FSM
220
221 return EIP97_GLOBAL_NO_ERROR;
222}
223
224
225/*----------------------------------------------------------------------------
226 * EIP97_Global_EIP96_Token_Status_Get
227 */
228EIP97_Global_Error_t
229EIP97_Global_EIP96_Token_Status_Get(
230 EIP97_Global_IOArea_t * const IOArea_p,
231 const unsigned int PE_Number,
232 EIP96_Token_Status_t * const Token_Status_p)
233{
234 Device_Handle_t Device;
235 volatile EIP97_True_IOArea_t * const TrueIOArea_p = IOAREA(IOArea_p);
236
237 EIP97_GLOBAL_CHECK_POINTER(IOArea_p);
238 EIP97_GLOBAL_CHECK_POINTER(Token_Status_p);
239
240 if(PE_Number >= EIP97_GLOBAL_MAX_NOF_PE_TO_USE)
241 return EIP97_GLOBAL_UNSUPPORTED_FEATURE_ERROR;
242
243 Device = TrueIOArea_p->Device;
244
245#ifdef EIP97_GLOBAL_DEBUG_FSM
246 {
247 EIP97_Global_Error_t rv;
248
249 // Remain in the current state
250 rv = EIP97_Global_State_Set(
251 (volatile EIP97_Global_State_t*)&TrueIOArea_p->State,
252 (EIP97_Global_State_t)TrueIOArea_p->State);
253 if(rv != EIP97_GLOBAL_NO_ERROR)
254 return EIP97_GLOBAL_ILLEGAL_IN_STATE;
255 }
256#endif // EIP97_GLOBAL_DEBUG_FSM
257
258 EIP96_TOKEN_CTRL_STAT_RD(Device,
259 PE_Number,
260 &Token_Status_p->ActiveTokenCount,
261 &Token_Status_p->fTokenLocationAvailable,
262 &Token_Status_p->fResultTokenAvailable,
263 &Token_Status_p->fTokenReadActive,
264 &Token_Status_p->fContextCacheActive,
265 &Token_Status_p->fContextFetch,
266 &Token_Status_p->fResultContext,
267 &Token_Status_p->fProcessingHeld,
268 &Token_Status_p->fBusy);
269
270 return EIP97_GLOBAL_NO_ERROR;
271}
272
273
274/*----------------------------------------------------------------------------
275 * EIP97_Global_EIP96_Context_Status_Get
276 */
277EIP97_Global_Error_t
278EIP97_Global_EIP96_Context_Status_Get(
279 EIP97_Global_IOArea_t * const IOArea_p,
280 const unsigned int PE_Number,
281 EIP96_Context_Status_t * const Context_Status_p)
282{
283 Device_Handle_t Device;
284 volatile EIP97_True_IOArea_t * const TrueIOArea_p = IOAREA(IOArea_p);
285
286 EIP97_GLOBAL_CHECK_POINTER(IOArea_p);
287 EIP97_GLOBAL_CHECK_POINTER(Context_Status_p);
288
289 if(PE_Number >= EIP97_GLOBAL_MAX_NOF_PE_TO_USE)
290 return EIP97_GLOBAL_ARGUMENT_ERROR;
291
292 Device = TrueIOArea_p->Device;
293
294 EIP96_CONTEXT_STAT_RD(Device,
295 PE_Number,
296 &Context_Status_p->Error,
297 &Context_Status_p->AvailableTokenCount,
298 &Context_Status_p->fActiveContext,
299 &Context_Status_p->fNextContext,
300 &Context_Status_p->fResultContext,
301 &Context_Status_p->fErrorRecovery);
302
303#ifdef EIP97_GLOBAL_DEBUG_FSM
304 {
305 EIP97_Global_Error_t rv;
306
307 if((Context_Status_p->Error & EIP96_TIMEOUT_FATAL_ERROR_MASK) != 0)
308 rv = EIP97_Global_State_Set(
309 (volatile EIP97_Global_State_t*)&TrueIOArea_p->State,
310 EIP97_GLOBAL_STATE_FATAL_ERROR);
311 else
312 // Remain in the current state
313 rv = EIP97_Global_State_Set(
314 (volatile EIP97_Global_State_t*)&TrueIOArea_p->State,
315 (EIP97_Global_State_t)TrueIOArea_p->State);
316 if(rv != EIP97_GLOBAL_NO_ERROR)
317 return EIP97_GLOBAL_ILLEGAL_IN_STATE;
318 }
319#endif // EIP97_GLOBAL_DEBUG_FSM
320
321 return EIP97_GLOBAL_NO_ERROR;
322}
323
324
325/*----------------------------------------------------------------------------
326 * EIP97_Global_EIP96_OutXfer_Status_Get
327 */
328EIP97_Global_Error_t
329EIP97_Global_EIP96_OutXfer_Status_Get(
330 EIP97_Global_IOArea_t * const IOArea_p,
331 const unsigned int PE_Number,
332 EIP96_Output_Transfer_Status_t * const OutXfer_Status_p)
333{
334 Device_Handle_t Device;
335 volatile EIP97_True_IOArea_t * const TrueIOArea_p = IOAREA(IOArea_p);
336
337 EIP97_GLOBAL_CHECK_POINTER(IOArea_p);
338 EIP97_GLOBAL_CHECK_POINTER(OutXfer_Status_p);
339
340 if(PE_Number >= EIP97_GLOBAL_MAX_NOF_PE_TO_USE)
341 return EIP97_GLOBAL_ARGUMENT_ERROR;
342
343 Device = TrueIOArea_p->Device;
344
345#ifdef EIP97_GLOBAL_DEBUG_FSM
346 {
347 EIP97_Global_Error_t rv;
348
349 // Remain in the current state
350 rv = EIP97_Global_State_Set((volatile EIP97_Global_State_t*)&TrueIOArea_p->State,
351 (EIP97_Global_State_t)TrueIOArea_p->State);
352 if(rv != EIP97_GLOBAL_NO_ERROR)
353 return EIP97_GLOBAL_ILLEGAL_IN_STATE;
354 }
355#endif // EIP97_GLOBAL_DEBUG_FSM
356
357 EIP96_OUT_TRANS_CTRL_STAT_RD(Device,
358 PE_Number,
359 &OutXfer_Status_p->AvailableWord32Count,
360 &OutXfer_Status_p->MinTransferWordCount,
361 &OutXfer_Status_p->MaxTransferWordCount,
362 &OutXfer_Status_p->TransferSizeMask);
363
364 return EIP97_GLOBAL_NO_ERROR;
365}
366
367
368/*----------------------------------------------------------------------------
369 * EIP97_Global_EIP96_PRNG_Status_Get
370 */
371EIP97_Global_Error_t
372EIP97_Global_EIP96_PRNG_Status_Get(
373 EIP97_Global_IOArea_t * const IOArea_p,
374 const unsigned int PE_Number,
375 EIP96_PRNG_Status_t * const PRNG_Status_p)
376{
377 Device_Handle_t Device;
378 volatile EIP97_True_IOArea_t * const TrueIOArea_p = IOAREA(IOArea_p);
379
380 EIP97_GLOBAL_CHECK_POINTER(IOArea_p);
381 EIP97_GLOBAL_CHECK_POINTER(PRNG_Status_p);
382
383 if(PE_Number >= EIP97_GLOBAL_MAX_NOF_PE_TO_USE)
384 return EIP97_GLOBAL_ARGUMENT_ERROR;
385
386 Device = TrueIOArea_p->Device;
387
388#ifdef EIP97_GLOBAL_DEBUG_FSM
389 {
390 EIP97_Global_Error_t rv;
391
392 // Remain in the current state
393 rv = EIP97_Global_State_Set((volatile EIP97_Global_State_t*)&TrueIOArea_p->State,
394 (EIP97_Global_State_t)TrueIOArea_p->State);
395 if(rv != EIP97_GLOBAL_NO_ERROR)
396 return EIP97_GLOBAL_ILLEGAL_IN_STATE;
397 }
398#endif // EIP97_GLOBAL_DEBUG_FSM
399
400 EIP96_PRNG_STAT_RD(Device,
401 PE_Number,
402 &PRNG_Status_p->fBusy,
403 &PRNG_Status_p->fResultReady);
404
405 return EIP97_GLOBAL_NO_ERROR;
406}
407
408
409/* end of file eip97_global_event.c */