| From 2f8ed664925318dacb6a92ca6383b5589cc2f7e1 Mon Sep 17 00:00:00 2001 |
| From: Sam Shih <sam.shih@mediatek.com> |
| Date: Fri, 2 Jun 2023 13:06:09 +0800 |
| Subject: [PATCH] |
| [spi-and-storage][999-2311-mtd-spinand-gigadevice-Support-GD5F1GQ5UExxG.patch] |
| |
| --- |
| drivers/mtd/nand/spi/gigadevice.c | 69 +++++++++++++++++++++++++++---- |
| 1 file changed, 60 insertions(+), 9 deletions(-) |
| |
| diff --git a/drivers/mtd/nand/spi/gigadevice.c b/drivers/mtd/nand/spi/gigadevice.c |
| index a34c5ede1..937a04ce6 100644 |
| --- a/drivers/mtd/nand/spi/gigadevice.c |
| +++ b/drivers/mtd/nand/spi/gigadevice.c |
| @@ -13,7 +13,10 @@ |
| #define GD5FXGQ4XA_STATUS_ECC_1_7_BITFLIPS (1 << 4) |
| #define GD5FXGQ4XA_STATUS_ECC_8_BITFLIPS (3 << 4) |
| |
| -#define GD5FXGQ4UEXXG_REG_STATUS2 0xf0 |
| +#define GD5FXGQ5XE_STATUS_ECC_1_4_BITFLIPS (1 << 4) |
| +#define GD5FXGQ5XE_STATUS_ECC_4_BITFLIPS (3 << 4) |
| + |
| +#define GD5FXGQXXEXXG_REG_STATUS2 0xf0 |
| |
| #define GD5FXGQ4UXFXXG_STATUS_ECC_MASK (7 << 4) |
| #define GD5FXGQ4UXFXXG_STATUS_ECC_NO_BITFLIPS (0 << 4) |
| @@ -102,7 +105,7 @@ static int gd5fxgq4xa_ecc_get_status(struct spinand_device *spinand, |
| return -EINVAL; |
| } |
| |
| -static int gd5fxgq4_variant2_ooblayout_ecc(struct mtd_info *mtd, int section, |
| +static int gd5fxgqx_variant2_ooblayout_ecc(struct mtd_info *mtd, int section, |
| struct mtd_oob_region *region) |
| { |
| if (section) |
| @@ -114,7 +117,7 @@ static int gd5fxgq4_variant2_ooblayout_ecc(struct mtd_info *mtd, int section, |
| return 0; |
| } |
| |
| -static int gd5fxgq4_variant2_ooblayout_free(struct mtd_info *mtd, int section, |
| +static int gd5fxgqx_variant2_ooblayout_free(struct mtd_info *mtd, int section, |
| struct mtd_oob_region *region) |
| { |
| if (section) |
| @@ -127,16 +130,17 @@ static int gd5fxgq4_variant2_ooblayout_free(struct mtd_info *mtd, int section, |
| return 0; |
| } |
| |
| -static const struct mtd_ooblayout_ops gd5fxgq4_variant2_ooblayout = { |
| - .ecc = gd5fxgq4_variant2_ooblayout_ecc, |
| - .free = gd5fxgq4_variant2_ooblayout_free, |
| +/* Valid for Q4/Q5 and Q6 (untested) devices */ |
| +static const struct mtd_ooblayout_ops gd5fxgqx_variant2_ooblayout = { |
| + .ecc = gd5fxgqx_variant2_ooblayout_ecc, |
| + .free = gd5fxgqx_variant2_ooblayout_free, |
| }; |
| |
| static int gd5fxgq4uexxg_ecc_get_status(struct spinand_device *spinand, |
| u8 status) |
| { |
| u8 status2; |
| - struct spi_mem_op op = SPINAND_GET_FEATURE_OP(GD5FXGQ4UEXXG_REG_STATUS2, |
| + struct spi_mem_op op = SPINAND_GET_FEATURE_OP(GD5FXGQXXEXXG_REG_STATUS2, |
| &status2); |
| int ret; |
| |
| @@ -174,6 +178,43 @@ static int gd5fxgq4uexxg_ecc_get_status(struct spinand_device *spinand, |
| return -EINVAL; |
| } |
| |
| +static int gd5fxgq5xexxg_ecc_get_status(struct spinand_device *spinand, |
| + u8 status) |
| +{ |
| + u8 status2; |
| + struct spi_mem_op op = SPINAND_GET_FEATURE_OP(GD5FXGQXXEXXG_REG_STATUS2, |
| + &status2); |
| + int ret; |
| + |
| + switch (status & STATUS_ECC_MASK) { |
| + case STATUS_ECC_NO_BITFLIPS: |
| + return 0; |
| + |
| + case GD5FXGQ5XE_STATUS_ECC_1_4_BITFLIPS: |
| + /* |
| + * Read status2 register to determine a more fine grained |
| + * bit error status |
| + */ |
| + ret = spi_mem_exec_op(spinand->spimem, &op); |
| + if (ret) |
| + return ret; |
| + |
| + /* |
| + * 1 ... 4 bits are flipped (and corrected) |
| + */ |
| + /* bits sorted this way (1...0): ECCSE1, ECCSE0 */ |
| + return ((status2 & STATUS_ECC_MASK) >> 4) + 1; |
| + |
| + case STATUS_ECC_UNCOR_ERROR: |
| + return -EBADMSG; |
| + |
| + default: |
| + break; |
| + } |
| + |
| + return -EINVAL; |
| +} |
| + |
| static int gd5fxgq4ufxxg_ecc_get_status(struct spinand_device *spinand, |
| u8 status) |
| { |
| @@ -233,7 +274,7 @@ static const struct spinand_info gigadevice_spinand_table[] = { |
| &write_cache_variants, |
| &update_cache_variants), |
| SPINAND_HAS_QE_BIT, |
| - SPINAND_ECCINFO(&gd5fxgq4_variant2_ooblayout, |
| + SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout, |
| gd5fxgq4uexxg_ecc_get_status)), |
| SPINAND_INFO("GD5F1GQ4UFxxG", |
| SPINAND_ID(SPINAND_READID_METHOD_OPCODE, 0xb1, 0x48), |
| @@ -243,8 +284,18 @@ static const struct spinand_info gigadevice_spinand_table[] = { |
| &write_cache_variants, |
| &update_cache_variants), |
| SPINAND_HAS_QE_BIT, |
| - SPINAND_ECCINFO(&gd5fxgq4_variant2_ooblayout, |
| + SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout, |
| gd5fxgq4ufxxg_ecc_get_status)), |
| + SPINAND_INFO("GD5F1GQ5UExxG", |
| + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x51), |
| + NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1), |
| + NAND_ECCREQ(4, 512), |
| + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, |
| + &write_cache_variants, |
| + &update_cache_variants), |
| + SPINAND_HAS_QE_BIT, |
| + SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout, |
| + gd5fxgq5xexxg_ecc_get_status)), |
| }; |
| |
| static const struct spinand_manufacturer_ops gigadevice_spinand_manuf_ops = { |
| -- |
| 2.34.1 |
| |