| --- a/drivers/mtd/nand/spi/gigadevice.c |
| +++ b/drivers/mtd/nand/spi/gigadevice.c |
| @@ -39,8 +39,9 @@ static SPINAND_OP_VARIANTS(read_cache_va |
| SPINAND_PAGE_READ_FROM_CACHE_OP_3A(true, 0, 1, NULL, 0), |
| SPINAND_PAGE_READ_FROM_CACHE_OP_3A(false, 0, 0, NULL, 0)); |
| |
| -/* Q5 devices, QUADIO: Dummy bytes only valid for 1 GBit variants */ |
| -static SPINAND_OP_VARIANTS(gd5f1gq5_read_cache_variants, |
| +/* For Q5 devices, QUADIO use different dummy byte settings */ |
| +/* Q5 1Gb */ |
| +static SPINAND_OP_VARIANTS(dummy2_read_cache_variants, |
| SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0), |
| SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0), |
| SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0), |
| @@ -48,6 +49,15 @@ static SPINAND_OP_VARIANTS(gd5f1gq5_read |
| SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0), |
| SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0)); |
| |
| +/* Q5 2Gb & 4Gb */ |
| +static SPINAND_OP_VARIANTS(dummy4_read_cache_variants, |
| + SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 4, NULL, 0), |
| + SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0), |
| + SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 2, NULL, 0), |
| + SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0), |
| + SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0), |
| + SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0)); |
| + |
| static SPINAND_OP_VARIANTS(write_cache_variants, |
| SPINAND_PROG_LOAD_X4(true, 0, NULL, 0), |
| SPINAND_PROG_LOAD(true, 0, NULL, 0)); |
| @@ -249,7 +259,7 @@ static const struct spinand_info gigadev |
| SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x01), |
| NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1), |
| NAND_ECCREQ(8, 512), |
| - SPINAND_INFO_OP_VARIANTS(&gd5f1gq5_read_cache_variants, |
| + SPINAND_INFO_OP_VARIANTS(&dummy2_read_cache_variants, |
| &write_cache_variants, |
| &update_cache_variants), |
| 0, |
| @@ -309,7 +319,87 @@ static const struct spinand_info gigadev |
| SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x51), |
| NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1), |
| NAND_ECCREQ(4, 512), |
| - SPINAND_INFO_OP_VARIANTS(&gd5f1gq5_read_cache_variants, |
| + SPINAND_INFO_OP_VARIANTS(&dummy2_read_cache_variants, |
| + &write_cache_variants, |
| + &update_cache_variants), |
| + SPINAND_HAS_QE_BIT, |
| + SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout, |
| + gd5fxgq5xexxg_ecc_get_status)), |
| + SPINAND_INFO("GD5F2GQ5UExxG", |
| + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x52), |
| + NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1), |
| + NAND_ECCREQ(4, 512), |
| + SPINAND_INFO_OP_VARIANTS(&dummy4_read_cache_variants, |
| + &write_cache_variants, |
| + &update_cache_variants), |
| + SPINAND_HAS_QE_BIT, |
| + SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout, |
| + gd5fxgq5xexxg_ecc_get_status)), |
| + SPINAND_INFO("GD5F4GQ6UExxG", |
| + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x55), |
| + NAND_MEMORG(1, 2048, 128, 64, 4096, 80, 1, 1, 1), |
| + NAND_ECCREQ(4, 512), |
| + SPINAND_INFO_OP_VARIANTS(&dummy4_read_cache_variants, |
| + &write_cache_variants, |
| + &update_cache_variants), |
| + SPINAND_HAS_QE_BIT, |
| + SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout, |
| + gd5fxgq5xexxg_ecc_get_status)), |
| + SPINAND_INFO("GD5F1GM7UExxG", |
| + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x91), |
| + NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1), |
| + NAND_ECCREQ(8, 512), |
| + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, |
| + &write_cache_variants, |
| + &update_cache_variants), |
| + SPINAND_HAS_QE_BIT, |
| + SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout, |
| + gd5fxgq4uexxg_ecc_get_status)), |
| + SPINAND_INFO("GD5F2GM7UExxG", |
| + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x92), |
| + NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1), |
| + NAND_ECCREQ(8, 512), |
| + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, |
| + &write_cache_variants, |
| + &update_cache_variants), |
| + SPINAND_HAS_QE_BIT, |
| + SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout, |
| + gd5fxgq4uexxg_ecc_get_status)), |
| + SPINAND_INFO("GD5F4GM8UExxG", |
| + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x95), |
| + NAND_MEMORG(1, 2048, 128, 64, 4096, 80, 1, 1, 1), |
| + NAND_ECCREQ(8, 512), |
| + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, |
| + &write_cache_variants, |
| + &update_cache_variants), |
| + SPINAND_HAS_QE_BIT, |
| + SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout, |
| + gd5fxgq4uexxg_ecc_get_status)), |
| + SPINAND_INFO("GD5F1GQ5UExxH", |
| + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x31), |
| + NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1), |
| + NAND_ECCREQ(4, 512), |
| + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, |
| + &write_cache_variants, |
| + &update_cache_variants), |
| + SPINAND_HAS_QE_BIT, |
| + SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout, |
| + gd5fxgq5xexxg_ecc_get_status)), |
| + SPINAND_INFO("GD5F2GQ5UExxH", |
| + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x32), |
| + NAND_MEMORG(1, 2048, 64, 64, 2048, 40, 1, 1, 1), |
| + NAND_ECCREQ(4, 512), |
| + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, |
| + &write_cache_variants, |
| + &update_cache_variants), |
| + SPINAND_HAS_QE_BIT, |
| + SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout, |
| + gd5fxgq5xexxg_ecc_get_status)), |
| + SPINAND_INFO("GD5F4GQ6UExxH", |
| + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x32), |
| + NAND_MEMORG(1, 2048, 64, 64, 4096, 80, 1, 1, 1), |
| + NAND_ECCREQ(4, 512), |
| + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, |
| &write_cache_variants, |
| &update_cache_variants), |
| SPINAND_HAS_QE_BIT, |