| From 520aea1caf199f454a0988f23d000c18256caa2b Mon Sep 17 00:00:00 2001 |
| From: Sam Shih <sam.shih@mediatek.com> |
| Date: Fri, 2 Jun 2023 13:06:32 +0800 |
| Subject: [PATCH] [networking][999-2721-net-mt753x-phy-coverity-scan.patch] |
| |
| --- |
| drivers/net/phy/mtk/mt753x/mt753x_common.c | 3 ++ |
| drivers/net/phy/mtk/mt753x/mt753x_phy.c | 56 +++++++++++----------- |
| 2 files changed, 32 insertions(+), 27 deletions(-) |
| |
| diff --git a/drivers/net/phy/mtk/mt753x/mt753x_common.c b/drivers/net/phy/mtk/mt753x/mt753x_common.c |
| index 4015ddf12..0e08c8532 100644 |
| --- a/drivers/net/phy/mtk/mt753x/mt753x_common.c |
| +++ b/drivers/net/phy/mtk/mt753x/mt753x_common.c |
| @@ -49,6 +49,9 @@ static void display_port_link_status(struct gsw_mt753x *gsw, u32 port) |
| case MAC_SPD_2500: |
| speed = "2.5Gbps"; |
| break; |
| + default: |
| + dev_info(gsw->dev, "Invalid speed\n"); |
| + return; |
| } |
| |
| if (pmsr & MAC_LNK_STS) { |
| diff --git a/drivers/net/phy/mtk/mt753x/mt753x_phy.c b/drivers/net/phy/mtk/mt753x/mt753x_phy.c |
| index 0c6f9c930..afc46cdd8 100644 |
| --- a/drivers/net/phy/mtk/mt753x/mt753x_phy.c |
| +++ b/drivers/net/phy/mtk/mt753x/mt753x_phy.c |
| @@ -141,7 +141,7 @@ int ge_cal_rext(struct gsw_mt753x *gsw, u8 phyaddr, u32 delay) |
| u16 dev1e_17a_tmp, dev1e_e0_tmp; |
| |
| /* *** Iext/Rext Cal start ************ */ |
| - all_ana_cal_status = ANACAL_INIT; |
| + //all_ana_cal_status = ANACAL_INIT; |
| /* analog calibration enable, Rext calibration enable */ |
| /* 1e_db[12]:rg_cal_ckinv, [8]:rg_ana_calen, [4]:rg_rext_calen, [0]:rg_zcalen_a */ |
| /* 1e_dc[0]:rg_txvos_calen */ |
| @@ -185,7 +185,7 @@ int ge_cal_rext(struct gsw_mt753x *gsw, u8 phyaddr, u32 delay) |
| all_ana_cal_status = ANACAL_FINISH; |
| //printk(" GE Rext AnaCal Done! (%d)(0x%x) \r\n", cnt, rg_zcal_ctrl); |
| } else { |
| - dev1e_17a_tmp = tc_phy_read_dev_reg(gsw, PHY0, 0x1e, 0x017a); |
| + //dev1e_17a_tmp = tc_phy_read_dev_reg(gsw, PHY0, 0x1e, 0x017a); |
| dev1e_e0_tmp = tc_phy_read_dev_reg(gsw, PHY0, 0x1e, 0xe0); |
| if ((rg_zcal_ctrl == 0x3F) || (rg_zcal_ctrl == 0x00)) { |
| all_ana_cal_status = ANACAL_SATURATION; /* need to FT(IC fail?) */ |
| @@ -580,33 +580,35 @@ int ge_cal_tx_amp(struct gsw_mt753x *gsw, u8 phyaddr, u32 delay) |
| } else if (phyaddr == 1) { |
| if (calibration_pair == ANACAL_PAIR_A) |
| tx_amp_temp = tx_amp_temp - 1; |
| - else if(calibration_pair == ANACAL_PAIR_B) |
| - tx_amp_temp = tx_amp_temp ; |
| + //else if(calibration_pair == ANACAL_PAIR_B) |
| + // tx_amp_temp = tx_amp_temp; |
| else if(calibration_pair == ANACAL_PAIR_C) |
| tx_amp_temp = tx_amp_temp - 1; |
| else if(calibration_pair == ANACAL_PAIR_D) |
| tx_amp_temp = tx_amp_temp - 1; |
| } else if (phyaddr == 2) { |
| - if (calibration_pair == ANACAL_PAIR_A) |
| - tx_amp_temp = tx_amp_temp; |
| - else if(calibration_pair == ANACAL_PAIR_B) |
| + //if (calibration_pair == ANACAL_PAIR_A) |
| + // tx_amp_temp = tx_amp_temp; |
| + //else if(calibration_pair == ANACAL_PAIR_B) |
| + if(calibration_pair == ANACAL_PAIR_B) |
| tx_amp_temp = tx_amp_temp - 1; |
| - else if(calibration_pair == ANACAL_PAIR_C) |
| - tx_amp_temp = tx_amp_temp; |
| + //else if(calibration_pair == ANACAL_PAIR_C) |
| + // tx_amp_temp = tx_amp_temp; |
| else if(calibration_pair == ANACAL_PAIR_D) |
| tx_amp_temp = tx_amp_temp - 1; |
| - } else if (phyaddr == 3) { |
| - tx_amp_temp = tx_amp_temp; |
| + //} else if (phyaddr == 3) { |
| + // tx_amp_temp = tx_amp_temp; |
| } else if (phyaddr == 4) { |
| - if (calibration_pair == ANACAL_PAIR_A) |
| - tx_amp_temp = tx_amp_temp; |
| - else if(calibration_pair == ANACAL_PAIR_B) |
| + //if (calibration_pair == ANACAL_PAIR_A) |
| + // tx_amp_temp = tx_amp_temp; |
| + //else if(calibration_pair == ANACAL_PAIR_B) |
| + if(calibration_pair == ANACAL_PAIR_B) |
| tx_amp_temp = tx_amp_temp - 1; |
| - else if(calibration_pair == ANACAL_PAIR_C) |
| - tx_amp_temp = tx_amp_temp; |
| - else if(calibration_pair == ANACAL_PAIR_D) |
| - tx_amp_temp = tx_amp_temp; |
| - } |
| + //else if(calibration_pair == ANACAL_PAIR_C) |
| + // tx_amp_temp = tx_amp_temp; |
| + //else if(calibration_pair == ANACAL_PAIR_D) |
| + // tx_amp_temp = tx_amp_temp; |
| + } |
| reg_temp = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg)&(~0xff00); |
| tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100,(tx_amp_temp|((tx_amp_temp)<<tx_amp_reg_shift))); |
| tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg, (tx_amp_temp|((tx_amp_temp)<<tx_amp_reg_shift))); |
| @@ -704,7 +706,7 @@ int ge_cal_tx_amp(struct gsw_mt753x *gsw, u8 phyaddr, u32 delay) |
| reg_backup = 0x0000; |
| reg_backup |= ((reg_tmp << 10) | (reg_tmp << 0)); |
| tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x12, reg_backup); |
| - reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x12); |
| + //reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x12); |
| //printk("PORT[%d] 1e.012 = %x (OFFSET_1000M_PAIR_A)\n", phyaddr, reg_backup); |
| reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x16); |
| reg_tmp = ((reg_backup & 0x3f) >> 0); |
| @@ -712,7 +714,7 @@ int ge_cal_tx_amp(struct gsw_mt753x *gsw, u8 phyaddr, u32 delay) |
| reg_backup = (reg_backup & (~0x3f)); |
| reg_backup |= (reg_tmp << 0); |
| tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x16, reg_backup); |
| - reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x16); |
| + //reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x16); |
| //printk("PORT[%d] 1e.016 = %x (OFFSET_TESTMODE_1000M_PAIR_A)\n", phyaddr, reg_backup); |
| } |
| else if(calibration_pair == ANACAL_PAIR_B){ |
| @@ -722,7 +724,7 @@ int ge_cal_tx_amp(struct gsw_mt753x *gsw, u8 phyaddr, u32 delay) |
| reg_backup = 0x0000; |
| reg_backup |= ((reg_tmp << 8) | (reg_tmp << 0)); |
| tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x17, reg_backup); |
| - reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x17); |
| + //reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x17); |
| //printk("PORT[%d] 1e.017 = %x (OFFSET_1000M_PAIR_B)\n", phyaddr, reg_backup); |
| reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x18); |
| reg_tmp = ((reg_backup & 0x3f) >> 0); |
| @@ -730,7 +732,7 @@ int ge_cal_tx_amp(struct gsw_mt753x *gsw, u8 phyaddr, u32 delay) |
| reg_backup = (reg_backup & (~0x3f)); |
| reg_backup |= (reg_tmp << 0); |
| tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x18, reg_backup); |
| - reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x18); |
| + //reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x18); |
| //printk("PORT[%d] 1e.018 = %x (OFFSET_TESTMODE_1000M_PAIR_B)\n", phyaddr, reg_backup); |
| } |
| else if(calibration_pair == ANACAL_PAIR_C){ |
| @@ -740,7 +742,7 @@ int ge_cal_tx_amp(struct gsw_mt753x *gsw, u8 phyaddr, u32 delay) |
| reg_backup = (reg_backup & (~0x3f00)); |
| reg_backup |= (reg_tmp << 8); |
| tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x19, reg_backup); |
| - reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x19); |
| + //reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x19); |
| //printk("PORT[%d] 1e.019 = %x (OFFSET_1000M_PAIR_C)\n", phyaddr, reg_backup); |
| reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x20); |
| reg_tmp = ((reg_backup & 0x3f) >> 0); |
| @@ -748,7 +750,7 @@ int ge_cal_tx_amp(struct gsw_mt753x *gsw, u8 phyaddr, u32 delay) |
| reg_backup = (reg_backup & (~0x3f)); |
| reg_backup |= (reg_tmp << 0); |
| tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x20, reg_backup); |
| - reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x20); |
| + //reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x20); |
| //printk("PORT[%d] 1e.020 = %x (OFFSET_TESTMODE_1000M_PAIR_C)\n", phyaddr, reg_backup); |
| } |
| else if(calibration_pair == ANACAL_PAIR_D){ |
| @@ -758,7 +760,7 @@ int ge_cal_tx_amp(struct gsw_mt753x *gsw, u8 phyaddr, u32 delay) |
| reg_backup = (reg_backup & (~0x3f00)); |
| reg_backup |= (reg_tmp << 8); |
| tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x21, reg_backup); |
| - reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x21); |
| + //reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x21); |
| //printk("PORT[%d] 1e.021 = %x (OFFSET_1000M_PAIR_D)\n", phyaddr, reg_backup); |
| reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x22); |
| reg_tmp = ((reg_backup & 0x3f) >> 0); |
| @@ -766,7 +768,7 @@ int ge_cal_tx_amp(struct gsw_mt753x *gsw, u8 phyaddr, u32 delay) |
| reg_backup = (reg_backup & (~0x3f)); |
| reg_backup |= (reg_tmp << 0); |
| tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x22, reg_backup); |
| - reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x22); |
| + //reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x22); |
| //printk("PORT[%d] 1e.022 = %x (OFFSET_TESTMODE_1000M_PAIR_D)\n", phyaddr, reg_backup); |
| } |
| |
| -- |
| 2.34.1 |
| |