blob: fcc450e0243b6df372155caa2fc508cb73c01a9c [file] [log] [blame]
From 16ea1c12d369ea1f315edcc7a8525efc6d78403a Mon Sep 17 00:00:00 2001
From: Shayne Chen <shayne.chen@mediatek.com>
Date: Fri, 24 Mar 2023 14:02:32 +0800
Subject: [PATCH] wifi: mt76: mt7996: add debug tool
Change-Id: Ie10390b01f17db893dbfbf3221bf63a4bd1fe38f
---
mt7996/Makefile | 3 +
mt7996/coredump.c | 10 +-
mt7996/coredump.h | 7 +
mt7996/debugfs.c | 24 +-
mt7996/mt7996.h | 14 +
mt7996/mtk_debug.h | 2165 ++++++++++++++++++++++++++++++++++++++
mt7996/mtk_debugfs.c | 2353 ++++++++++++++++++++++++++++++++++++++++++
mt7996/mtk_mcu.c | 18 +
mt7996/mtk_mcu.h | 16 +
tools/fwlog.c | 25 +-
10 files changed, 4617 insertions(+), 18 deletions(-)
create mode 100644 mt7996/mtk_debug.h
create mode 100644 mt7996/mtk_debugfs.c
create mode 100644 mt7996/mtk_mcu.c
create mode 100644 mt7996/mtk_mcu.h
diff --git a/mt7996/Makefile b/mt7996/Makefile
index 7c2514a6..df131869 100644
--- a/mt7996/Makefile
+++ b/mt7996/Makefile
@@ -1,5 +1,6 @@
# SPDX-License-Identifier: ISC
EXTRA_CFLAGS += -DCONFIG_MT76_LEDS
+EXTRA_CFLAGS += -DCONFIG_MTK_DEBUG
obj-$(CONFIG_MT7996E) += mt7996e.o
@@ -9,3 +10,5 @@ mt7996e-y := pci.o init.o dma.o eeprom.o main.o mcu.o mac.o \
mt7996e-$(CONFIG_DEV_COREDUMP) += coredump.o
mt7996e-$(CONFIG_NL80211_TESTMODE) += testmode.o
+
+mt7996e-y += mtk_debugfs.o mtk_mcu.o
diff --git a/mt7996/coredump.c b/mt7996/coredump.c
index 60b88085..a7f91b56 100644
--- a/mt7996/coredump.c
+++ b/mt7996/coredump.c
@@ -195,7 +195,7 @@ mt7996_coredump_fw_stack(struct mt7996_dev *dev, u8 type, struct mt7996_coredump
}
}
-static struct mt7996_coredump *mt7996_coredump_build(struct mt7996_dev *dev, u8 type)
+struct mt7996_coredump *mt7996_coredump_build(struct mt7996_dev *dev, u8 type, bool full_dump)
{
struct mt7996_crash_data *crash_data = dev->coredump.crash_data[type];
struct mt7996_coredump *dump;
@@ -206,7 +206,7 @@ static struct mt7996_coredump *mt7996_coredump_build(struct mt7996_dev *dev, u8
len = hdr_len;
- if (coredump_memdump && crash_data->memdump_buf_len)
+ if (full_dump && coredump_memdump && crash_data->memdump_buf_len)
len += sizeof(*dump_mem) + crash_data->memdump_buf_len;
sofar += hdr_len;
@@ -248,6 +248,9 @@ static struct mt7996_coredump *mt7996_coredump_build(struct mt7996_dev *dev, u8
mt7996_coredump_fw_state(dev, type, dump, &exception);
mt7996_coredump_fw_stack(dev, type, dump, exception);
+ if (!full_dump)
+ goto skip_dump_mem;
+
/* gather memory content */
dump_mem = (struct mt7996_coredump_mem *)(buf + sofar);
dump_mem->len = crash_data->memdump_buf_len;
@@ -255,6 +258,7 @@ static struct mt7996_coredump *mt7996_coredump_build(struct mt7996_dev *dev, u8
memcpy(dump_mem->data, crash_data->memdump_buf,
crash_data->memdump_buf_len);
+skip_dump_mem:
mutex_unlock(&dev->dump_mutex);
return dump;
@@ -264,7 +268,7 @@ int mt7996_coredump_submit(struct mt7996_dev *dev, u8 type)
{
struct mt7996_coredump *dump;
- dump = mt7996_coredump_build(dev, type);
+ dump = mt7996_coredump_build(dev, type, true);
if (!dump) {
dev_warn(dev->mt76.dev, "no crash dump data found\n");
return -ENODATA;
diff --git a/mt7996/coredump.h b/mt7996/coredump.h
index 01ed3731..93cd84a0 100644
--- a/mt7996/coredump.h
+++ b/mt7996/coredump.h
@@ -75,6 +75,7 @@ struct mt7996_mem_region {
const struct mt7996_mem_region *
mt7996_coredump_get_mem_layout(struct mt7996_dev *dev, u8 type, u32 *num);
struct mt7996_crash_data *mt7996_coredump_new(struct mt7996_dev *dev, u8 type);
+struct mt7996_coredump *mt7996_coredump_build(struct mt7996_dev *dev, u8 type, bool full_dump);
int mt7996_coredump_submit(struct mt7996_dev *dev, u8 type);
int mt7996_coredump_register(struct mt7996_dev *dev);
void mt7996_coredump_unregister(struct mt7996_dev *dev);
@@ -92,6 +93,12 @@ static inline int mt7996_coredump_submit(struct mt7996_dev *dev, u8 type)
return 0;
}
+static inline struct
+mt7996_coredump *mt7996_coredump_build(struct mt7996_dev *dev, u8 type, bool full_dump)
+{
+ return NULL;
+}
+
static inline struct
mt7996_crash_data *mt7996_coredump_new(struct mt7996_dev *dev, u8 type)
{
diff --git a/mt7996/debugfs.c b/mt7996/debugfs.c
index ca4d615d..93581fef 100644
--- a/mt7996/debugfs.c
+++ b/mt7996/debugfs.c
@@ -301,6 +301,9 @@ mt7996_fw_debug_wm_set(void *data, u64 val)
int ret;
dev->fw_debug_wm = val ? MCU_FW_LOG_TO_HOST : 0;
+#ifdef CONFIG_MTK_DEBUG
+ dev->fw_debug_wm = val;
+#endif
if (dev->fw_debug_bin)
val = MCU_FW_LOG_RELAY;
@@ -407,11 +410,12 @@ mt7996_fw_debug_bin_set(void *data, u64 val)
};
struct mt7996_dev *dev = data;
- if (!dev->relay_fwlog)
+ if (!dev->relay_fwlog) {
dev->relay_fwlog = relay_open("fwlog_data", dev->debugfs_dir,
1500, 512, &relay_cb, NULL);
- if (!dev->relay_fwlog)
- return -ENOMEM;
+ if (!dev->relay_fwlog)
+ return -ENOMEM;
+ }
dev->fw_debug_bin = val;
@@ -825,6 +829,11 @@ int mt7996_init_debugfs(struct mt7996_phy *phy)
if (phy == &dev->phy)
dev->debugfs_dir = dir;
+#ifdef CONFIG_MTK_DEBUG
+ debugfs_create_u16("wlan_idx", 0600, dir, &dev->wlan_idx);
+ mt7996_mtk_init_debugfs(phy, dir);
+#endif
+
return 0;
}
@@ -837,6 +846,12 @@ mt7996_debugfs_write_fwlog(struct mt7996_dev *dev, const void *hdr, int hdrlen,
void *dest;
spin_lock_irqsave(&lock, flags);
+
+ if (!dev->relay_fwlog) {
+ spin_unlock_irqrestore(&lock, flags);
+ return;
+ }
+
dest = relay_reserve(dev->relay_fwlog, hdrlen + len + 4);
if (dest) {
*(u32 *)dest = hdrlen + len;
@@ -869,9 +884,6 @@ void mt7996_debugfs_rx_fw_monitor(struct mt7996_dev *dev, const void *data, int
.msg_type = cpu_to_le16(PKT_TYPE_RX_FW_MONITOR),
};
- if (!dev->relay_fwlog)
- return;
-
hdr.serial_id = cpu_to_le16(dev->fw_debug_seq++);
hdr.timestamp = cpu_to_le32(mt76_rr(dev, MT_LPON_FRCR(0)));
hdr.len = *(__le16 *)data;
diff --git a/mt7996/mt7996.h b/mt7996/mt7996.h
index 286fc1eb..6c76ec20 100644
--- a/mt7996/mt7996.h
+++ b/mt7996/mt7996.h
@@ -363,6 +363,16 @@ struct mt7996_dev {
u32 reg_l2_backup;
u8 wtbl_size_group;
+
+#ifdef CONFIG_MTK_DEBUG
+ u16 wlan_idx;
+ struct {
+ u8 sku_disable;
+ u32 fw_dbg_module;
+ u8 fw_dbg_lv;
+ u32 bcn_total_cnt[__MT_MAX_BAND];
+ } dbg;
+#endif
};
enum {
@@ -659,4 +669,8 @@ void mt7996_sta_add_debugfs(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
struct ieee80211_sta *sta, struct dentry *dir);
#endif
+#ifdef CONFIG_MTK_DEBUG
+int mt7996_mtk_init_debugfs(struct mt7996_phy *phy, struct dentry *dir);
+#endif
+
#endif
diff --git a/mt7996/mtk_debug.h b/mt7996/mtk_debug.h
new file mode 100644
index 00000000..eb40f9cb
--- /dev/null
+++ b/mt7996/mtk_debug.h
@@ -0,0 +1,2165 @@
+#ifndef __MTK_DEBUG_H
+#define __MTK_DEBUG_H
+
+#ifdef CONFIG_MTK_DEBUG
+#define NO_SHIFT_DEFINE 0xFFFFFFFF
+#define BITS(m, n) (~(BIT(m)-1) & ((BIT(n) - 1) | BIT(n)))
+
+#define GET_FIELD(_field, _reg) \
+ ({ \
+ (((_reg) & (_field##_MASK)) >> (_field##_SHIFT)); \
+ })
+
+/* AGG */
+#define BN0_WF_AGG_TOP_BASE 0x820e2000
+#define BN1_WF_AGG_TOP_BASE 0x820f2000
+#define IP1_BN0_WF_AGG_TOP_BASE 0x830e2000
+
+#define BN0_WF_AGG_TOP_SCR_ADDR (BN0_WF_AGG_TOP_BASE + 0x0) // 2000
+#define BN0_WF_AGG_TOP_SCR0_ADDR (BN0_WF_AGG_TOP_BASE + 0x4) // 2004
+#define BN0_WF_AGG_TOP_SCR1_ADDR (BN0_WF_AGG_TOP_BASE + 0x8) // 2008
+#define BN0_WF_AGG_TOP_BCR_ADDR (BN0_WF_AGG_TOP_BASE + 0xc) // 200C
+#define BN0_WF_AGG_TOP_BWCR_ADDR (BN0_WF_AGG_TOP_BASE + 0x10) // 2010
+#define BN0_WF_AGG_TOP_ARCR0_ADDR (BN0_WF_AGG_TOP_BASE + 0x14) // 2014
+#define BN0_WF_AGG_TOP_ARUCR_ADDR (BN0_WF_AGG_TOP_BASE + 0x18) // 2018
+#define BN0_WF_AGG_TOP_ARDCR_ADDR (BN0_WF_AGG_TOP_BASE + 0x1c) // 201C
+#define BN0_WF_AGG_TOP_AALCR0_ADDR (BN0_WF_AGG_TOP_BASE + 0x20) // 2020
+#define BN0_WF_AGG_TOP_AALCR1_ADDR (BN0_WF_AGG_TOP_BASE + 0x24) // 2024
+#define BN0_WF_AGG_TOP_PCR0_ADDR (BN0_WF_AGG_TOP_BASE + 0x28) // 2028
+#define BN0_WF_AGG_TOP_PCR1_ADDR (BN0_WF_AGG_TOP_BASE + 0x2c) // 202C
+#define BN0_WF_AGG_TOP_TTCR0_ADDR (BN0_WF_AGG_TOP_BASE + 0x30) // 2030
+#define BN0_WF_AGG_TOP_TTCR1_ADDR (BN0_WF_AGG_TOP_BASE + 0x34) // 2034
+#define BN0_WF_AGG_TOP_ACR1_ADDR (BN0_WF_AGG_TOP_BASE + 0x38) // 2038
+#define BN0_WF_AGG_TOP_ACR4_ADDR (BN0_WF_AGG_TOP_BASE + 0x3c) // 203C
+#define BN0_WF_AGG_TOP_ACR5_ADDR (BN0_WF_AGG_TOP_BASE + 0x40) // 2040
+#define BN0_WF_AGG_TOP_ACR6_ADDR (BN0_WF_AGG_TOP_BASE + 0x44) // 2044
+#define BN0_WF_AGG_TOP_ACR8_ADDR (BN0_WF_AGG_TOP_BASE + 0x4c) // 204C
+#define BN0_WF_AGG_TOP_MRCR_ADDR (BN0_WF_AGG_TOP_BASE + 0x50) // 2050
+#define BN0_WF_AGG_TOP_MMPDR_ADDR (BN0_WF_AGG_TOP_BASE + 0x54) // 2054
+#define BN0_WF_AGG_TOP_GFPDR_ADDR (BN0_WF_AGG_TOP_BASE + 0x58) // 2058
+#define BN0_WF_AGG_TOP_VHTPDR_ADDR (BN0_WF_AGG_TOP_BASE + 0x5c) // 205C
+#define BN0_WF_AGG_TOP_HEPDR_ADDR (BN0_WF_AGG_TOP_BASE + 0x60) // 2060
+#define BN0_WF_AGG_TOP_CTCR_ADDR (BN0_WF_AGG_TOP_BASE + 0x64) // 2064
+#define BN0_WF_AGG_TOP_ATCR3_ADDR (BN0_WF_AGG_TOP_BASE + 0x68) // 2068
+#define BN0_WF_AGG_TOP_SRCR_ADDR (BN0_WF_AGG_TOP_BASE + 0x6c) // 206C
+#define BN0_WF_AGG_TOP_VBCR_ADDR (BN0_WF_AGG_TOP_BASE + 0x70) // 2070
+#define BN0_WF_AGG_TOP_TCR_ADDR (BN0_WF_AGG_TOP_BASE + 0x74) // 2074
+#define BN0_WF_AGG_TOP_SRHS_ADDR (BN0_WF_AGG_TOP_BASE + 0x78) // 2078
+#define BN0_WF_AGG_TOP_DBRCR0_ADDR (BN0_WF_AGG_TOP_BASE + 0x7c) // 207C
+#define BN0_WF_AGG_TOP_DBRCR1_ADDR (BN0_WF_AGG_TOP_BASE + 0x80) // 2080
+#define BN0_WF_AGG_TOP_CTETCR_ADDR (BN0_WF_AGG_TOP_BASE + 0x84) // 2084
+#define BN0_WF_AGG_TOP_WPDR_ADDR (BN0_WF_AGG_TOP_BASE + 0x88) // 2088
+#define BN0_WF_AGG_TOP_PLRPDR_ADDR (BN0_WF_AGG_TOP_BASE + 0x8c) // 208C
+#define BN0_WF_AGG_TOP_CECR_ADDR (BN0_WF_AGG_TOP_BASE + 0x90) // 2090
+#define BN0_WF_AGG_TOP_OMRCR0_ADDR (BN0_WF_AGG_TOP_BASE + 0x94) // 2094
+#define BN0_WF_AGG_TOP_OMRCR1_ADDR (BN0_WF_AGG_TOP_BASE + 0x98) // 2098
+#define BN0_WF_AGG_TOP_OMRCR2_ADDR (BN0_WF_AGG_TOP_BASE + 0x9c) // 209C
+#define BN0_WF_AGG_TOP_OMRCR3_ADDR (BN0_WF_AGG_TOP_BASE + 0xa0) // 20A0
+#define BN0_WF_AGG_TOP_TMCR_ADDR (BN0_WF_AGG_TOP_BASE + 0xa4) // 20A4
+#define BN0_WF_AGG_TOP_TWTCR_ADDR (BN0_WF_AGG_TOP_BASE + 0xa8) // 20A8
+#define BN0_WF_AGG_TOP_TWTSTACR_ADDR (BN0_WF_AGG_TOP_BASE + 0xac) // 20AC
+#define BN0_WF_AGG_TOP_TWTE0TB_ADDR (BN0_WF_AGG_TOP_BASE + 0xb0) // 20B0
+#define BN0_WF_AGG_TOP_TWTE1TB_ADDR (BN0_WF_AGG_TOP_BASE + 0xb4) // 20B4
+#define BN0_WF_AGG_TOP_TWTE2TB_ADDR (BN0_WF_AGG_TOP_BASE + 0xb8) // 20B8
+#define BN0_WF_AGG_TOP_TWTE3TB_ADDR (BN0_WF_AGG_TOP_BASE + 0xbc) // 20BC
+#define BN0_WF_AGG_TOP_TWTE4TB_ADDR (BN0_WF_AGG_TOP_BASE + 0xc0) // 20C0
+#define BN0_WF_AGG_TOP_TWTE5TB_ADDR (BN0_WF_AGG_TOP_BASE + 0xc4) // 20C4
+#define BN0_WF_AGG_TOP_TWTE6TB_ADDR (BN0_WF_AGG_TOP_BASE + 0xc8) // 20C8
+#define BN0_WF_AGG_TOP_TWTE7TB_ADDR (BN0_WF_AGG_TOP_BASE + 0xcc) // 20CC
+#define BN0_WF_AGG_TOP_TWTE8TB_ADDR (BN0_WF_AGG_TOP_BASE + 0xd0) // 20D0
+#define BN0_WF_AGG_TOP_TWTE9TB_ADDR (BN0_WF_AGG_TOP_BASE + 0xd4) // 20D4
+#define BN0_WF_AGG_TOP_TWTEATB_ADDR (BN0_WF_AGG_TOP_BASE + 0xd8) // 20D8
+#define BN0_WF_AGG_TOP_TWTEBTB_ADDR (BN0_WF_AGG_TOP_BASE + 0xdc) // 20DC
+#define BN0_WF_AGG_TOP_TWTECTB_ADDR (BN0_WF_AGG_TOP_BASE + 0xe0) // 20E0
+#define BN0_WF_AGG_TOP_TWTEDTB_ADDR (BN0_WF_AGG_TOP_BASE + 0xe4) // 20E4
+#define BN0_WF_AGG_TOP_TWTEETB_ADDR (BN0_WF_AGG_TOP_BASE + 0xe8) // 20E8
+#define BN0_WF_AGG_TOP_TWTEFTB_ADDR (BN0_WF_AGG_TOP_BASE + 0xec) // 20EC
+#define BN0_WF_AGG_TOP_AALCR2_ADDR (BN0_WF_AGG_TOP_BASE + 0xf0) // 20F0
+#define BN0_WF_AGG_TOP_AALCR3_ADDR (BN0_WF_AGG_TOP_BASE + 0xf4) // 20F4
+#define BN0_WF_AGG_TOP_AALCR4_ADDR (BN0_WF_AGG_TOP_BASE + 0xf8) // 20F8
+#define BN0_WF_AGG_TOP_AALCR5_ADDR (BN0_WF_AGG_TOP_BASE + 0xfc) // 20FC
+#define BN0_WF_AGG_TOP_AALCR6_ADDR (BN0_WF_AGG_TOP_BASE + 0x100) // 2100
+#define BN0_WF_AGG_TOP_AALCR7_ADDR (BN0_WF_AGG_TOP_BASE + 0x104) // 2104
+#define BN0_WF_AGG_TOP_ATCR0_ADDR (BN0_WF_AGG_TOP_BASE + 0x108) // 2108
+#define BN0_WF_AGG_TOP_ATCR1_ADDR (BN0_WF_AGG_TOP_BASE + 0x10c) // 210C
+#define BN0_WF_AGG_TOP_TCCR_ADDR (BN0_WF_AGG_TOP_BASE + 0x110) // 2110
+#define BN0_WF_AGG_TOP_TFCR_ADDR (BN0_WF_AGG_TOP_BASE + 0x114) // 2114
+#define BN0_WF_AGG_TOP_MUCR0_ADDR (BN0_WF_AGG_TOP_BASE + 0x118) // 2118
+#define BN0_WF_AGG_TOP_MUCR1_ADDR (BN0_WF_AGG_TOP_BASE + 0x11c) // 211C
+#define BN0_WF_AGG_TOP_CSDCR0_ADDR (BN0_WF_AGG_TOP_BASE + 0x120) // 2120
+#define BN0_WF_AGG_TOP_CSDCR1_ADDR (BN0_WF_AGG_TOP_BASE + 0x124) // 2124
+#define BN0_WF_AGG_TOP_CSDCR2_ADDR (BN0_WF_AGG_TOP_BASE + 0x128) // 2128
+#define BN0_WF_AGG_TOP_CSDCR3_ADDR (BN0_WF_AGG_TOP_BASE + 0x12c) // 212C
+#define BN0_WF_AGG_TOP_CSDCR4_ADDR (BN0_WF_AGG_TOP_BASE + 0x130) // 2130
+#define BN0_WF_AGG_TOP_DYNSCR_ADDR (BN0_WF_AGG_TOP_BASE + 0x178) // 2178
+#define BN0_WF_AGG_TOP_DYNSSCR_ADDR (BN0_WF_AGG_TOP_BASE + 0x198) // 2198
+#define BN0_WF_AGG_TOP_TCDCNT0_ADDR (BN0_WF_AGG_TOP_BASE + 0x2c8) // 22C8
+#define BN0_WF_AGG_TOP_TCDCNT1_ADDR (BN0_WF_AGG_TOP_BASE + 0x2cc) // 22CC
+#define BN0_WF_AGG_TOP_TCSR0_ADDR (BN0_WF_AGG_TOP_BASE + 0x2d0) // 22D0
+#define BN0_WF_AGG_TOP_TCSR1_ADDR (BN0_WF_AGG_TOP_BASE + 0x2d4) // 22D4
+#define BN0_WF_AGG_TOP_TCSR2_ADDR (BN0_WF_AGG_TOP_BASE + 0x2d8) // 22D8
+#define BN0_WF_AGG_TOP_DCR_ADDR (BN0_WF_AGG_TOP_BASE + 0x2e4) // 22E4
+#define BN0_WF_AGG_TOP_SMDCR_ADDR (BN0_WF_AGG_TOP_BASE + 0x2e8) // 22E8
+#define BN0_WF_AGG_TOP_TXCMDSMCR_ADDR (BN0_WF_AGG_TOP_BASE + 0x2ec) // 22EC
+#define BN0_WF_AGG_TOP_SMCR0_ADDR (BN0_WF_AGG_TOP_BASE + 0x2f0) // 22F0
+#define BN0_WF_AGG_TOP_SMCR1_ADDR (BN0_WF_AGG_TOP_BASE + 0x2f4) // 22F4
+#define BN0_WF_AGG_TOP_SMCR2_ADDR (BN0_WF_AGG_TOP_BASE + 0x2f8) // 22F8
+#define BN0_WF_AGG_TOP_SMCR3_ADDR (BN0_WF_AGG_TOP_BASE + 0x2fc) // 22FC
+
+#define BN0_WF_AGG_TOP_AALCR0_AC01_AGG_LIMIT_ADDR BN0_WF_AGG_TOP_AALCR0_ADDR
+#define BN0_WF_AGG_TOP_AALCR0_AC01_AGG_LIMIT_MASK 0x03FF0000 // AC01_AGG_LIMIT[25..16]
+#define BN0_WF_AGG_TOP_AALCR0_AC01_AGG_LIMIT_SHFT 16
+#define BN0_WF_AGG_TOP_AALCR0_AC00_AGG_LIMIT_ADDR BN0_WF_AGG_TOP_AALCR0_ADDR
+#define BN0_WF_AGG_TOP_AALCR0_AC00_AGG_LIMIT_MASK 0x000003FF // AC00_AGG_LIMIT[9..0]
+#define BN0_WF_AGG_TOP_AALCR0_AC00_AGG_LIMIT_SHFT 0
+
+#define BN0_WF_AGG_TOP_AALCR1_AC03_AGG_LIMIT_ADDR BN0_WF_AGG_TOP_AALCR1_ADDR
+#define BN0_WF_AGG_TOP_AALCR1_AC03_AGG_LIMIT_MASK 0x03FF0000 // AC03_AGG_LIMIT[25..16]
+#define BN0_WF_AGG_TOP_AALCR1_AC03_AGG_LIMIT_SHFT 16
+#define BN0_WF_AGG_TOP_AALCR1_AC02_AGG_LIMIT_ADDR BN0_WF_AGG_TOP_AALCR1_ADDR
+#define BN0_WF_AGG_TOP_AALCR1_AC02_AGG_LIMIT_MASK 0x000003FF // AC02_AGG_LIMIT[9..0]
+#define BN0_WF_AGG_TOP_AALCR1_AC02_AGG_LIMIT_SHFT 0
+
+#define BN0_WF_AGG_TOP_AALCR2_AC11_AGG_LIMIT_ADDR BN0_WF_AGG_TOP_AALCR2_ADDR
+#define BN0_WF_AGG_TOP_AALCR2_AC11_AGG_LIMIT_MASK 0x03FF0000 // AC11_AGG_LIMIT[25..16]
+#define BN0_WF_AGG_TOP_AALCR2_AC11_AGG_LIMIT_SHFT 16
+#define BN0_WF_AGG_TOP_AALCR2_AC10_AGG_LIMIT_ADDR BN0_WF_AGG_TOP_AALCR2_ADDR
+#define BN0_WF_AGG_TOP_AALCR2_AC10_AGG_LIMIT_MASK 0x000003FF // AC10_AGG_LIMIT[9..0]
+#define BN0_WF_AGG_TOP_AALCR2_AC10_AGG_LIMIT_SHFT 0
+
+#define BN0_WF_AGG_TOP_AALCR3_AC13_AGG_LIMIT_ADDR BN0_WF_AGG_TOP_AALCR3_ADDR
+#define BN0_WF_AGG_TOP_AALCR3_AC13_AGG_LIMIT_MASK 0x03FF0000 // AC13_AGG_LIMIT[25..16]
+#define BN0_WF_AGG_TOP_AALCR3_AC13_AGG_LIMIT_SHFT 16
+#define BN0_WF_AGG_TOP_AALCR3_AC12_AGG_LIMIT_ADDR BN0_WF_AGG_TOP_AALCR3_ADDR
+#define BN0_WF_AGG_TOP_AALCR3_AC12_AGG_LIMIT_MASK 0x000003FF // AC12_AGG_LIMIT[9..0]
+#define BN0_WF_AGG_TOP_AALCR3_AC12_AGG_LIMIT_SHFT 0
+
+#define BN0_WF_AGG_TOP_AALCR4_AC21_AGG_LIMIT_ADDR BN0_WF_AGG_TOP_AALCR4_ADDR
+#define BN0_WF_AGG_TOP_AALCR4_AC21_AGG_LIMIT_MASK 0x03FF0000 // AC21_AGG_LIMIT[25..16]
+#define BN0_WF_AGG_TOP_AALCR4_AC21_AGG_LIMIT_SHFT 16
+#define BN0_WF_AGG_TOP_AALCR4_AC20_AGG_LIMIT_ADDR BN0_WF_AGG_TOP_AALCR4_ADDR
+#define BN0_WF_AGG_TOP_AALCR4_AC20_AGG_LIMIT_MASK 0x000003FF // AC20_AGG_LIMIT[9..0]
+#define BN0_WF_AGG_TOP_AALCR4_AC20_AGG_LIMIT_SHFT 0
+
+#define BN0_WF_AGG_TOP_AALCR5_AC23_AGG_LIMIT_ADDR BN0_WF_AGG_TOP_AALCR5_ADDR
+#define BN0_WF_AGG_TOP_AALCR5_AC23_AGG_LIMIT_MASK 0x03FF0000 // AC23_AGG_LIMIT[25..16]
+#define BN0_WF_AGG_TOP_AALCR5_AC23_AGG_LIMIT_SHFT 16
+#define BN0_WF_AGG_TOP_AALCR5_AC22_AGG_LIMIT_ADDR BN0_WF_AGG_TOP_AALCR5_ADDR
+#define BN0_WF_AGG_TOP_AALCR5_AC22_AGG_LIMIT_MASK 0x000003FF // AC22_AGG_LIMIT[9..0]
+#define BN0_WF_AGG_TOP_AALCR5_AC22_AGG_LIMIT_SHFT 0
+
+#define BN0_WF_AGG_TOP_AALCR6_AC31_AGG_LIMIT_ADDR BN0_WF_AGG_TOP_AALCR6_ADDR
+#define BN0_WF_AGG_TOP_AALCR6_AC31_AGG_LIMIT_MASK 0x03FF0000 // AC31_AGG_LIMIT[25..16]
+#define BN0_WF_AGG_TOP_AALCR6_AC31_AGG_LIMIT_SHFT 16
+#define BN0_WF_AGG_TOP_AALCR6_AC30_AGG_LIMIT_ADDR BN0_WF_AGG_TOP_AALCR6_ADDR
+#define BN0_WF_AGG_TOP_AALCR6_AC30_AGG_LIMIT_MASK 0x000003FF // AC30_AGG_LIMIT[9..0]
+#define BN0_WF_AGG_TOP_AALCR6_AC30_AGG_LIMIT_SHFT 0
+#define BN0_WF_AGG_TOP_AALCR7_AC33_AGG_LIMIT_ADDR BN0_WF_AGG_TOP_AALCR7_ADDR
+#define BN0_WF_AGG_TOP_AALCR7_AC33_AGG_LIMIT_MASK 0x03FF0000 // AC33_AGG_LIMIT[25..16]
+#define BN0_WF_AGG_TOP_AALCR7_AC33_AGG_LIMIT_SHFT 16
+#define BN0_WF_AGG_TOP_AALCR7_AC32_AGG_LIMIT_ADDR BN0_WF_AGG_TOP_AALCR7_ADDR
+#define BN0_WF_AGG_TOP_AALCR7_AC32_AGG_LIMIT_MASK 0x000003FF // AC32_AGG_LIMIT[9..0]
+#define BN0_WF_AGG_TOP_AALCR7_AC32_AGG_LIMIT_SHFT 0
+
+/* DMA */
+struct queue_desc {
+ u32 hw_desc_base;
+ u16 ring_size;
+ char *const ring_info;
+};
+
+// HOST DMA
+#define WF_WFDMA_HOST_DMA0_BASE 0xd4000
+
+#define WF_WFDMA_HOST_DMA0_HOST_INT_STA_ADDR \
+ (WF_WFDMA_HOST_DMA0_BASE + 0x200) /* 4200 */
+#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_ADDR \
+ (WF_WFDMA_HOST_DMA0_BASE + 0X204) /* 4204 */
+#define WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_ADDR \
+ (WF_WFDMA_HOST_DMA0_BASE + 0x208) /* 4208 */
+
+#define WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_RX_DMA_BUSY_ADDR \
+ WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_ADDR
+#define WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK \
+ 0x00000008 /* RX_DMA_BUSY[3] */
+#define WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT 3
+#define WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_RX_DMA_EN_ADDR \
+ WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_ADDR
+#define WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_RX_DMA_EN_MASK \
+ 0x00000004 /* RX_DMA_EN[2] */
+#define WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_RX_DMA_EN_SHFT 2
+#define WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_TX_DMA_BUSY_ADDR \
+ WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_ADDR
+#define WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK \
+ 0x00000002 /* TX_DMA_BUSY[1] */
+#define WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT 1
+#define WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_TX_DMA_EN_ADDR \
+ WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_ADDR
+#define WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_TX_DMA_EN_MASK \
+ 0x00000001 /* TX_DMA_EN[0] */
+#define WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_TX_DMA_EN_SHFT 0
+
+
+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING0_CTRL0_ADDR \
+ (WF_WFDMA_HOST_DMA0_BASE + 0x300) /* 4300 */
+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING0_CTRL1_ADDR \
+ (WF_WFDMA_HOST_DMA0_BASE + 0x304) /* 4304 */
+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING0_CTRL2_ADDR \
+ (WF_WFDMA_HOST_DMA0_BASE + 0x308) /* 4308 */
+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING0_CTRL3_ADDR \
+ (WF_WFDMA_HOST_DMA0_BASE + 0x30c) /* 430C */
+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING1_CTRL0_ADDR \
+ (WF_WFDMA_HOST_DMA0_BASE + 0x310) /* 4310 */
+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING1_CTRL1_ADDR \
+ (WF_WFDMA_HOST_DMA0_BASE + 0x314) /* 4314 */
+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING1_CTRL2_ADDR \
+ (WF_WFDMA_HOST_DMA0_BASE + 0x318) /* 4318 */
+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING1_CTRL3_ADDR \
+ (WF_WFDMA_HOST_DMA0_BASE + 0x31c) /* 431C */
+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING2_CTRL0_ADDR \
+ (WF_WFDMA_HOST_DMA0_BASE + 0x320) /* 4320 */
+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING2_CTRL1_ADDR \
+ (WF_WFDMA_HOST_DMA0_BASE + 0x324) /* 4324 */
+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING2_CTRL2_ADDR \
+ (WF_WFDMA_HOST_DMA0_BASE + 0x328) /* 4328 */
+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING2_CTRL3_ADDR \
+ (WF_WFDMA_HOST_DMA0_BASE + 0x32c) /* 432C */
+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING3_CTRL0_ADDR \
+ (WF_WFDMA_HOST_DMA0_BASE + 0x330) /* 4330 */
+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING3_CTRL1_ADDR \
+ (WF_WFDMA_HOST_DMA0_BASE + 0x334) /* 4334 */
+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING3_CTRL2_ADDR \
+ (WF_WFDMA_HOST_DMA0_BASE + 0x338) /* 4338 */
+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING3_CTRL3_ADDR \
+ (WF_WFDMA_HOST_DMA0_BASE + 0x33c) /* 433C */
+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING4_CTRL0_ADDR \
+ (WF_WFDMA_HOST_DMA0_BASE + 0x340) /* 4340 */
+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING4_CTRL1_ADDR \
+ (WF_WFDMA_HOST_DMA0_BASE + 0x344) /* 4344 */
+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING4_CTRL2_ADDR \
+ (WF_WFDMA_HOST_DMA0_BASE + 0x348) /* 4348 */
+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING4_CTRL3_ADDR \
+ (WF_WFDMA_HOST_DMA0_BASE + 0x34c) /* 434C */
+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING5_CTRL0_ADDR \
+ (WF_WFDMA_HOST_DMA0_BASE + 0x350) /* 4350 */
+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING5_CTRL1_ADDR \
+ (WF_WFDMA_HOST_DMA0_BASE + 0x354) /* 4354 */
+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING5_CTRL2_ADDR \
+ (WF_WFDMA_HOST_DMA0_BASE + 0x358) /* 4358 */
+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING5_CTRL3_ADDR \
+ (WF_WFDMA_HOST_DMA0_BASE + 0x35c) /* 435C */
+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING6_CTRL0_ADDR \
+ (WF_WFDMA_HOST_DMA0_BASE + 0x360) /* 4360 */
+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING6_CTRL1_ADDR \
+ (WF_WFDMA_HOST_DMA0_BASE + 0x364) /* 4364 */
+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING6_CTRL2_ADDR \
+ (WF_WFDMA_HOST_DMA0_BASE + 0x368) /* 4368 */
+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING6_CTRL3_ADDR \
+ (WF_WFDMA_HOST_DMA0_BASE + 0x36c) /* 436C */
+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING16_CTRL0_ADDR \
+ (WF_WFDMA_HOST_DMA0_BASE + 0x400) /* 4400 */
+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING16_CTRL1_ADDR \
+ (WF_WFDMA_HOST_DMA0_BASE + 0x404) /* 4404 */
+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING16_CTRL2_ADDR \
+ (WF_WFDMA_HOST_DMA0_BASE + 0x408) /* 4408 */
+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING16_CTRL3_ADDR \
+ (WF_WFDMA_HOST_DMA0_BASE + 0x40c) /* 440C */
+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING17_CTRL0_ADDR \
+ (WF_WFDMA_HOST_DMA0_BASE + 0x410) /* 4410 */
+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING17_CTRL1_ADDR \
+ (WF_WFDMA_HOST_DMA0_BASE + 0x414) /* 4414 */
+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING17_CTRL2_ADDR \
+ (WF_WFDMA_HOST_DMA0_BASE + 0x418) /* 4418 */
+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING17_CTRL3_ADDR \
+ (WF_WFDMA_HOST_DMA0_BASE + 0x41c) /* 441C */
+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING18_CTRL0_ADDR \
+ (WF_WFDMA_HOST_DMA0_BASE + 0x420) /* 4420 */
+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING18_CTRL1_ADDR \
+ (WF_WFDMA_HOST_DMA0_BASE + 0x424) /* 4424 */
+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING18_CTRL2_ADDR \
+ (WF_WFDMA_HOST_DMA0_BASE + 0x428) /* 4428 */
+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING18_CTRL3_ADDR \
+ (WF_WFDMA_HOST_DMA0_BASE + 0x42c) /* 442C */
+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING19_CTRL0_ADDR \
+ (WF_WFDMA_HOST_DMA0_BASE + 0x430) /* 4430 */
+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING19_CTRL1_ADDR \
+ (WF_WFDMA_HOST_DMA0_BASE + 0x434) /* 4434 */
+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING19_CTRL2_ADDR \
+ (WF_WFDMA_HOST_DMA0_BASE + 0x438) /* 4438 */
+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING19_CTRL3_ADDR \
+ (WF_WFDMA_HOST_DMA0_BASE + 0x43c) /* 443C */
+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING20_CTRL0_ADDR \
+ (WF_WFDMA_HOST_DMA0_BASE + 0x440) /* 4440 */
+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING20_CTRL1_ADDR \
+ (WF_WFDMA_HOST_DMA0_BASE + 0x444) /* 4444 */
+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING20_CTRL2_ADDR \
+ (WF_WFDMA_HOST_DMA0_BASE + 0x448) /* 4448 */
+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING20_CTRL3_ADDR \
+ (WF_WFDMA_HOST_DMA0_BASE + 0x44c) /* 444C */
+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING21_CTRL0_ADDR \
+ (WF_WFDMA_HOST_DMA0_BASE + 0x450) /* 4450 */
+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING21_CTRL1_ADDR \
+ (WF_WFDMA_HOST_DMA0_BASE + 0x454) /* 4454 */
+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING21_CTRL2_ADDR \
+ (WF_WFDMA_HOST_DMA0_BASE + 0x458) /* 4458 */
+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING21_CTRL3_ADDR \
+ (WF_WFDMA_HOST_DMA0_BASE + 0x45c) /* 445c */
+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING22_CTRL0_ADDR (WF_WFDMA_HOST_DMA0_BASE + 0x460) // 4460
+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING22_CTRL1_ADDR (WF_WFDMA_HOST_DMA0_BASE + 0x464) // 4464
+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING22_CTRL2_ADDR (WF_WFDMA_HOST_DMA0_BASE + 0x468) // 4468
+#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING22_CTRL3_ADDR (WF_WFDMA_HOST_DMA0_BASE + 0x46c) // 446C
+
+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING0_CTRL0_ADDR \
+ (WF_WFDMA_HOST_DMA0_BASE + 0x500) /* 4500 */
+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING0_CTRL1_ADDR \
+ (WF_WFDMA_HOST_DMA0_BASE + 0x504) /* 4504 */
+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING0_CTRL2_ADDR \
+ (WF_WFDMA_HOST_DMA0_BASE + 0x508) /* 4508 */
+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING0_CTRL3_ADDR \
+ (WF_WFDMA_HOST_DMA0_BASE + 0x50c) /* 450C */
+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING1_CTRL0_ADDR \
+ (WF_WFDMA_HOST_DMA0_BASE + 0x510) /* 4510 */
+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING1_CTRL1_ADDR \
+ (WF_WFDMA_HOST_DMA0_BASE + 0x514) /* 4514 */
+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING1_CTRL2_ADDR \
+ (WF_WFDMA_HOST_DMA0_BASE + 0x518) /* 4518 */
+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING1_CTRL3_ADDR \
+ (WF_WFDMA_HOST_DMA0_BASE + 0x51c) /* 451C */
+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING2_CTRL0_ADDR \
+ (WF_WFDMA_HOST_DMA0_BASE + 0x520) /* 4520 */
+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING2_CTRL1_ADDR \
+ (WF_WFDMA_HOST_DMA0_BASE + 0x524) /* 4524 */
+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING2_CTRL2_ADDR \
+ (WF_WFDMA_HOST_DMA0_BASE + 0x528) /* 4528 */
+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING2_CTRL3_ADDR \
+ (WF_WFDMA_HOST_DMA0_BASE + 0x52C) /* 452C */
+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING3_CTRL0_ADDR \
+ (WF_WFDMA_HOST_DMA0_BASE + 0x530) /* 4530 */
+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING3_CTRL1_ADDR \
+ (WF_WFDMA_HOST_DMA0_BASE + 0x534) /* 4534 */
+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING3_CTRL2_ADDR \
+ (WF_WFDMA_HOST_DMA0_BASE + 0x538) /* 4538 */
+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING3_CTRL3_ADDR \
+ (WF_WFDMA_HOST_DMA0_BASE + 0x53C) /* 453C */
+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING4_CTRL0_ADDR \
+ (WF_WFDMA_HOST_DMA0_BASE + 0x540) /* 4540 */
+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING4_CTRL1_ADDR \
+ (WF_WFDMA_HOST_DMA0_BASE + 0x544) /* 4544 */
+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING4_CTRL2_ADDR \
+ (WF_WFDMA_HOST_DMA0_BASE + 0x548) /* 4548 */
+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING4_CTRL3_ADDR \
+ (WF_WFDMA_HOST_DMA0_BASE + 0x54c) /* 454C */
+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING5_CTRL0_ADDR \
+ (WF_WFDMA_HOST_DMA0_BASE + 0x550) /* 4550 */
+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING5_CTRL1_ADDR \
+ (WF_WFDMA_HOST_DMA0_BASE + 0x554) /* 4554 */
+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING5_CTRL2_ADDR \
+ (WF_WFDMA_HOST_DMA0_BASE + 0x558) /* 4558 */
+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING5_CTRL3_ADDR \
+ (WF_WFDMA_HOST_DMA0_BASE + 0x55c) /* 455C */
+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING6_CTRL0_ADDR \
+ (WF_WFDMA_HOST_DMA0_BASE + 0x560) /* 4560 */
+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING6_CTRL1_ADDR \
+ (WF_WFDMA_HOST_DMA0_BASE + 0x564) /* 4564 */
+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING6_CTRL2_ADDR \
+ (WF_WFDMA_HOST_DMA0_BASE + 0x568) /* 4568 */
+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING6_CTRL3_ADDR \
+ (WF_WFDMA_HOST_DMA0_BASE + 0x56c) /* 456C */
+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING7_CTRL0_ADDR \
+ (WF_WFDMA_HOST_DMA0_BASE + 0x570) /* 4570 */
+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING7_CTRL1_ADDR \
+ (WF_WFDMA_HOST_DMA0_BASE + 0x574) /* 4574 */
+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING7_CTRL2_ADDR \
+ (WF_WFDMA_HOST_DMA0_BASE + 0x578) /* 4578 */
+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING7_CTRL3_ADDR \
+ (WF_WFDMA_HOST_DMA0_BASE + 0x57c) /* 457C */
+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING8_CTRL0_ADDR \
+ (WF_WFDMA_HOST_DMA0_BASE + 0x580) /* 4580 */
+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING8_CTRL1_ADDR \
+ (WF_WFDMA_HOST_DMA0_BASE + 0x584) /* 4584 */
+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING8_CTRL2_ADDR \
+ (WF_WFDMA_HOST_DMA0_BASE + 0x588) /* 4588 */
+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING8_CTRL3_ADDR \
+ (WF_WFDMA_HOST_DMA0_BASE + 0x58c) /* 458C */
+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING9_CTRL0_ADDR \
+ (WF_WFDMA_HOST_DMA0_BASE + 0x590) /* 4590 */
+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING9_CTRL1_ADDR \
+ (WF_WFDMA_HOST_DMA0_BASE + 0x594) /* 4594 */
+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING9_CTRL2_ADDR \
+ (WF_WFDMA_HOST_DMA0_BASE + 0x598) /* 4598 */
+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING9_CTRL3_ADDR \
+ (WF_WFDMA_HOST_DMA0_BASE + 0x59c) /* 459C */
+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING10_CTRL0_ADDR (WF_WFDMA_HOST_DMA0_BASE + 0x5a0) // 45A0
+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING10_CTRL1_ADDR (WF_WFDMA_HOST_DMA0_BASE + 0x5a4) // 45A4
+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING10_CTRL2_ADDR (WF_WFDMA_HOST_DMA0_BASE + 0x5a8) // 45A8
+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING10_CTRL3_ADDR (WF_WFDMA_HOST_DMA0_BASE + 0x5ac) // 45AC
+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING11_CTRL0_ADDR (WF_WFDMA_HOST_DMA0_BASE + 0x5b0) // 45B0
+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING11_CTRL1_ADDR (WF_WFDMA_HOST_DMA0_BASE + 0x5b4) // 45B4
+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING11_CTRL2_ADDR (WF_WFDMA_HOST_DMA0_BASE + 0x5b8) // 45B8
+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING11_CTRL3_ADDR (WF_WFDMA_HOST_DMA0_BASE + 0x5bc) // 45BC
+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING12_CTRL0_ADDR (WF_WFDMA_HOST_DMA0_BASE + 0x5C0) // 45C0
+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING12_CTRL1_ADDR (WF_WFDMA_HOST_DMA0_BASE + 0x5C4) // 45C4
+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING12_CTRL2_ADDR (WF_WFDMA_HOST_DMA0_BASE + 0x5C8) // 45C8
+#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING12_CTRL3_ADDR (WF_WFDMA_HOST_DMA0_BASE + 0x5CC) // 45CC
+
+// HOST PCIE1 DMA
+#define WF_WFDMA_HOST_DMA0_PCIE1_BASE 0xd8000
+
+#define WF_WFDMA_HOST_DMA0_PCIE1_HOST_INT_STA_ADDR (WF_WFDMA_HOST_DMA0_PCIE1_BASE + 0x200) // 8200
+#define WF_WFDMA_HOST_DMA0_PCIE1_HOST_INT_ENA_ADDR (WF_WFDMA_HOST_DMA0_PCIE1_BASE + 0X204) // 8204
+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_GLO_CFG_ADDR (WF_WFDMA_HOST_DMA0_PCIE1_BASE + 0x208) // 8208
+
+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_GLO_CFG_PDMA_BT_SIZE_SHFT 4
+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK 0x00000008
+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT 3
+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_GLO_CFG_RX_DMA_EN_MASK 0x00000004
+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_GLO_CFG_RX_DMA_EN_SHFT 2
+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK 0x00000002
+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT 1
+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_GLO_CFG_TX_DMA_EN_MASK 0x00000001
+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_GLO_CFG_TX_DMA_EN_SHFT 0
+
+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_TX_RING21_CTRL0_ADDR (WF_WFDMA_HOST_DMA0_PCIE1_BASE + 0x450) // 8450
+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_TX_RING21_CTRL1_ADDR (WF_WFDMA_HOST_DMA0_PCIE1_BASE + 0x454) // 8454
+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_TX_RING21_CTRL2_ADDR (WF_WFDMA_HOST_DMA0_PCIE1_BASE + 0x458) // 8458
+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_TX_RING21_CTRL3_ADDR (WF_WFDMA_HOST_DMA0_PCIE1_BASE + 0x45c) // 845C
+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_TX_RING22_CTRL0_ADDR (WF_WFDMA_HOST_DMA0_PCIE1_BASE + 0x460) // 8460
+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_TX_RING22_CTRL1_ADDR (WF_WFDMA_HOST_DMA0_PCIE1_BASE + 0x464) // 8464
+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_TX_RING22_CTRL2_ADDR (WF_WFDMA_HOST_DMA0_PCIE1_BASE + 0x468) // 8468
+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_TX_RING22_CTRL3_ADDR (WF_WFDMA_HOST_DMA0_PCIE1_BASE + 0x46c) // 846C
+
+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_RX_RING3_CTRL0_ADDR (WF_WFDMA_HOST_DMA0_PCIE1_BASE + 0x530) // 8530
+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_RX_RING3_CTRL1_ADDR (WF_WFDMA_HOST_DMA0_PCIE1_BASE + 0x534) // 8534
+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_RX_RING3_CTRL2_ADDR (WF_WFDMA_HOST_DMA0_PCIE1_BASE + 0x538) // 8538
+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_RX_RING3_CTRL3_ADDR (WF_WFDMA_HOST_DMA0_PCIE1_BASE + 0x53C) // 853C
+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_RX_RING5_CTRL0_ADDR (WF_WFDMA_HOST_DMA0_PCIE1_BASE + 0x550) // 8550
+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_RX_RING5_CTRL1_ADDR (WF_WFDMA_HOST_DMA0_PCIE1_BASE + 0x554) // 8554
+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_RX_RING5_CTRL2_ADDR (WF_WFDMA_HOST_DMA0_PCIE1_BASE + 0x558) // 8558
+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_RX_RING5_CTRL3_ADDR (WF_WFDMA_HOST_DMA0_PCIE1_BASE + 0x55c) // 855C
+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_RX_RING6_CTRL0_ADDR (WF_WFDMA_HOST_DMA0_PCIE1_BASE + 0x560) // 8560
+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_RX_RING6_CTRL1_ADDR (WF_WFDMA_HOST_DMA0_PCIE1_BASE + 0x564) // 8564
+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_RX_RING6_CTRL2_ADDR (WF_WFDMA_HOST_DMA0_PCIE1_BASE + 0x568) // 8568
+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_RX_RING6_CTRL3_ADDR (WF_WFDMA_HOST_DMA0_PCIE1_BASE + 0x56c) // 856C
+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_RX_RING7_CTRL0_ADDR (WF_WFDMA_HOST_DMA0_PCIE1_BASE + 0x570) // 8570
+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_RX_RING7_CTRL1_ADDR (WF_WFDMA_HOST_DMA0_PCIE1_BASE + 0x574) // 8574
+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_RX_RING7_CTRL2_ADDR (WF_WFDMA_HOST_DMA0_PCIE1_BASE + 0x578) // 8578
+#define WF_WFDMA_HOST_DMA0_PCIE1_WPDMA_RX_RING7_CTRL3_ADDR (WF_WFDMA_HOST_DMA0_PCIE1_BASE + 0x57c) // 857C
+//MCU DMA
+//#define WF_WFDMA_MCU_DMA0_BASE 0x02000
+#define WF_WFDMA_MCU_DMA0_BASE 0x54000000
+
+#define WF_WFDMA_MCU_DMA0_HOST_INT_STA_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x200) // 0200
+#define WF_WFDMA_MCU_DMA0_HOST_INT_ENA_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0X204) // 0204
+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x208) // 0208
+
+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_BUSY_ADDR WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_ADDR
+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK 0x00000008 // RX_DMA_BUSY[3]
+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT 3
+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_EN_ADDR WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_ADDR
+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_EN_MASK 0x00000004 // RX_DMA_EN[2]
+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_EN_SHFT 2
+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_BUSY_ADDR WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_ADDR
+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK 0x00000002 // TX_DMA_BUSY[1]
+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT 1
+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_EN_ADDR WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_ADDR
+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_EN_MASK 0x00000001 // TX_DMA_EN[0]
+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_EN_SHFT 0
+
+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING0_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x300) // 0300
+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING0_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x304) // 0304
+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING0_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x308) // 0308
+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING0_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x30c) // 030C
+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING1_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x310) // 0310
+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING1_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x314) // 0314
+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING1_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x318) // 0318
+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING1_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x31c) // 031C
+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING2_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x320) // 0320
+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING2_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x324) // 0324
+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING2_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x328) // 0328
+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING2_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x32c) // 032C
+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING3_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x330) // 0330
+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING3_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x334) // 0334
+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING3_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x338) // 0338
+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING3_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x33c) // 033C
+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING4_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x340) // 0340
+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING4_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x344) // 0344
+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING4_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x348) // 0348
+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING4_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x34c) // 034C
+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING5_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x350) // 0350
+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING5_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x354) // 0354
+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING5_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x358) // 0358
+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING5_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x35c) // 035C
+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING6_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x360) // 0360
+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING6_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x364) // 0364
+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING6_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x368) // 0368
+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING6_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x36c) // 036C
+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING7_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x370) // 0370
+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING7_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x374) // 0374
+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING7_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x378) // 0378
+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING7_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x37c) // 037C
+
+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING0_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x500) // 0500
+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING0_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x504) // 0504
+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING0_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x508) // 0508
+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING0_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x50c) // 050C
+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING1_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x510) // 0510
+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING1_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x514) // 0514
+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING1_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x518) // 0518
+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING1_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x51c) // 051C
+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING2_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x520) // 0520
+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING2_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x524) // 0524
+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING2_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x528) // 0528
+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING2_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x52C) // 052C
+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING3_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x530) // 0530
+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING3_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x534) // 0534
+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING3_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x538) // 0538
+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING3_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x53C) // 053C
+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING4_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x540) // 0540
+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING4_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x544) // 0544
+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING4_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x548) // 0548
+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING4_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x54C) // 054C
+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING5_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x550) // 0550
+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING5_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x554) // 0554
+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING5_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x558) // 0558
+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING5_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x55C) // 055C
+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING6_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x560) // 0560
+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING6_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x564) // 0564
+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING6_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x568) // 0568
+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING6_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x56c) // 056C
+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING7_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x570) // 0570
+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING7_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x574) // 0574
+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING7_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x578) // 0578
+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING7_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x57c) // 057C
+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING8_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x580) // 0580
+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING8_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x584) // 0584
+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING8_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x588) // 0588
+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING8_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x58c) // 058C
+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING9_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x590) // 0590
+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING9_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x594) // 0594
+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING9_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x598) // 0598
+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING9_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x59c) // 059C
+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING10_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x5A0) // 05A0
+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING10_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x5A4) // 05A4
+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING10_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x5A8) // 05A8
+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING10_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x5Ac) // 05AC
+
+// MEM DMA
+#define WF_WFDMA_MEM_DMA_BASE 0x58000000
+
+#define WF_WFDMA_MEM_DMA_HOST_INT_STA_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x200) // 0200
+#define WF_WFDMA_MEM_DMA_HOST_INT_ENA_ADDR (WF_WFDMA_MEM_DMA_BASE + 0X204) // 0204
+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x208) // 0208
+
+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_BUSY_ADDR WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_ADDR
+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK 0x00000008 // RX_DMA_BUSY[3]
+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT 3
+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_EN_ADDR WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_ADDR
+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_EN_MASK 0x00000004 // RX_DMA_EN[2]
+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_EN_SHFT 2
+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_BUSY_ADDR WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_ADDR
+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK 0x00000002 // TX_DMA_BUSY[1]
+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT 1
+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_EN_ADDR WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_ADDR
+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_EN_MASK 0x00000001 // TX_DMA_EN[0]
+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_EN_SHFT 0
+
+#define WF_WFDMA_MEM_DMA_WPDMA_TX_RING0_CTRL0_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x300) // 0300
+#define WF_WFDMA_MEM_DMA_WPDMA_TX_RING0_CTRL1_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x304) // 0304
+#define WF_WFDMA_MEM_DMA_WPDMA_TX_RING0_CTRL2_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x308) // 0308
+#define WF_WFDMA_MEM_DMA_WPDMA_TX_RING0_CTRL3_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x30c) // 030C
+#define WF_WFDMA_MEM_DMA_WPDMA_TX_RING1_CTRL0_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x310) // 0310
+#define WF_WFDMA_MEM_DMA_WPDMA_TX_RING1_CTRL1_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x314) // 0314
+#define WF_WFDMA_MEM_DMA_WPDMA_TX_RING1_CTRL2_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x318) // 0318
+#define WF_WFDMA_MEM_DMA_WPDMA_TX_RING1_CTRL3_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x31c) // 031C
+#define WF_WFDMA_MEM_DMA_WPDMA_TX_RING2_CTRL0_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x320) // 0320
+#define WF_WFDMA_MEM_DMA_WPDMA_TX_RING2_CTRL1_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x324) // 0324
+#define WF_WFDMA_MEM_DMA_WPDMA_TX_RING2_CTRL2_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x328) // 0328
+#define WF_WFDMA_MEM_DMA_WPDMA_TX_RING2_CTRL3_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x32c) // 032C
+
+#define WF_WFDMA_MEM_DMA_WPDMA_RX_RING0_CTRL0_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x500) // 0500
+#define WF_WFDMA_MEM_DMA_WPDMA_RX_RING0_CTRL1_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x504) // 0504
+#define WF_WFDMA_MEM_DMA_WPDMA_RX_RING0_CTRL2_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x508) // 0508
+#define WF_WFDMA_MEM_DMA_WPDMA_RX_RING0_CTRL3_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x50c) // 050C
+#define WF_WFDMA_MEM_DMA_WPDMA_RX_RING1_CTRL0_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x510) // 0510
+#define WF_WFDMA_MEM_DMA_WPDMA_RX_RING1_CTRL1_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x514) // 0514
+#define WF_WFDMA_MEM_DMA_WPDMA_RX_RING1_CTRL2_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x518) // 0518
+#define WF_WFDMA_MEM_DMA_WPDMA_RX_RING1_CTRL3_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x51c) // 051C
+#define WF_WFDMA_MEM_DMA_WPDMA_RX_RING2_CTRL0_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x520) // 0520
+#define WF_WFDMA_MEM_DMA_WPDMA_RX_RING2_CTRL1_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x524) // 0524
+#define WF_WFDMA_MEM_DMA_WPDMA_RX_RING2_CTRL2_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x528) // 0528
+#define WF_WFDMA_MEM_DMA_WPDMA_RX_RING2_CTRL3_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x52C) // 052C
+
+/* MIB */
+#define WF_UMIB_TOP_BASE 0x820cd000
+#define BN0_WF_MIB_TOP_BASE 0x820ed000
+#define BN1_WF_MIB_TOP_BASE 0x820fd000
+#define IP1_BN0_WF_MIB_TOP_BASE 0x830ed000
+
+#define WF_UMIB_TOP_B0BROCR_ADDR (WF_UMIB_TOP_BASE + 0x484) // D484
+#define WF_UMIB_TOP_B0BRBCR_ADDR (WF_UMIB_TOP_BASE + 0x4D4) // D4D4
+#define WF_UMIB_TOP_B0BRDCR_ADDR (WF_UMIB_TOP_BASE + 0x524) // D524
+#define WF_UMIB_TOP_B1BROCR_ADDR (WF_UMIB_TOP_BASE + 0x5E8) // D5E8
+#define WF_UMIB_TOP_B2BROCR_ADDR (WF_UMIB_TOP_BASE + 0x74C) // D74C
+
+#define BN0_WF_MIB_TOP_M0SCR0_ADDR (BN0_WF_MIB_TOP_BASE + 0x000) // D000
+#define BN0_WF_MIB_TOP_M0SDR6_ADDR (BN0_WF_MIB_TOP_BASE + 0x020) // D020
+#define BN0_WF_MIB_TOP_M0SDR9_ADDR (BN0_WF_MIB_TOP_BASE + 0x024) // D024
+#define BN0_WF_MIB_TOP_M0SDR18_ADDR (BN0_WF_MIB_TOP_BASE + 0x030) // D030
+#define BN0_WF_MIB_TOP_BTOCR_ADDR (BN0_WF_MIB_TOP_BASE + 0x400) // D400
+#define BN0_WF_MIB_TOP_BTBCR_ADDR (BN0_WF_MIB_TOP_BASE + 0x450) // D450
+#define BN0_WF_MIB_TOP_BTDCR_ADDR (BN0_WF_MIB_TOP_BASE + 0x590) // D590
+#define BN0_WF_MIB_TOP_BTCR_ADDR (BN0_WF_MIB_TOP_BASE + 0x5A0) // D5A0
+#define BN0_WF_MIB_TOP_RVSR0_ADDR (BN0_WF_MIB_TOP_BASE + 0x720) // D720
+
+#define BN0_WF_MIB_TOP_TSCR0_ADDR (BN0_WF_MIB_TOP_BASE + 0x6B0) // D6B0
+#define BN0_WF_MIB_TOP_TSCR3_ADDR (BN0_WF_MIB_TOP_BASE + 0x6BC) // D6BC
+#define BN0_WF_MIB_TOP_TSCR4_ADDR (BN0_WF_MIB_TOP_BASE + 0x6C0) // D6C0
+#define BN0_WF_MIB_TOP_TSCR5_ADDR (BN0_WF_MIB_TOP_BASE + 0x6C4) // D6C4
+#define BN0_WF_MIB_TOP_TSCR6_ADDR (BN0_WF_MIB_TOP_BASE + 0x6C8) // D6C8
+#define BN0_WF_MIB_TOP_TSCR7_ADDR (BN0_WF_MIB_TOP_BASE + 0x6D0) // D6D0
+#define BN0_WF_MIB_TOP_TSCR8_ADDR (BN0_WF_MIB_TOP_BASE + 0x6CC) // D6CC
+
+#define BN0_WF_MIB_TOP_TBCR0_ADDR (BN0_WF_MIB_TOP_BASE + 0x6EC) // D6EC
+#define BN0_WF_MIB_TOP_TBCR1_ADDR (BN0_WF_MIB_TOP_BASE + 0x6F0) // D6F0
+#define BN0_WF_MIB_TOP_TBCR2_ADDR (BN0_WF_MIB_TOP_BASE + 0x6F4) // D6F4
+#define BN0_WF_MIB_TOP_TBCR3_ADDR (BN0_WF_MIB_TOP_BASE + 0x6F8) // D6F8
+#define BN0_WF_MIB_TOP_TBCR4_ADDR (BN0_WF_MIB_TOP_BASE + 0x6FC) // D6FC
+
+#define BN0_WF_MIB_TOP_TDRCR0_ADDR (BN0_WF_MIB_TOP_BASE + 0x728) // D728
+#define BN0_WF_MIB_TOP_TDRCR1_ADDR (BN0_WF_MIB_TOP_BASE + 0x72C) // D72C
+#define BN0_WF_MIB_TOP_TDRCR2_ADDR (BN0_WF_MIB_TOP_BASE + 0x730) // D730
+#define BN0_WF_MIB_TOP_TDRCR3_ADDR (BN0_WF_MIB_TOP_BASE + 0x734) // D734
+#define BN0_WF_MIB_TOP_TDRCR4_ADDR (BN0_WF_MIB_TOP_BASE + 0x738) // D738
+
+#define BN0_WF_MIB_TOP_BTSCR0_ADDR (BN0_WF_MIB_TOP_BASE + 0x5E0) // D5E0
+#define BN0_WF_MIB_TOP_BTSCR1_ADDR (BN0_WF_MIB_TOP_BASE + 0x5F0) // D5F0
+#define BN0_WF_MIB_TOP_BTSCR2_ADDR (BN0_WF_MIB_TOP_BASE + 0x600) // D600
+#define BN0_WF_MIB_TOP_BTSCR3_ADDR (BN0_WF_MIB_TOP_BASE + 0x610) // D610
+#define BN0_WF_MIB_TOP_BTSCR4_ADDR (BN0_WF_MIB_TOP_BASE + 0x620) // D620
+#define BN0_WF_MIB_TOP_BTSCR5_ADDR (BN0_WF_MIB_TOP_BASE + 0x788) // D788
+#define BN0_WF_MIB_TOP_BTSCR6_ADDR (BN0_WF_MIB_TOP_BASE + 0x798) // D798
+
+#define BN0_WF_MIB_TOP_RSCR1_ADDR (BN0_WF_MIB_TOP_BASE + 0x7AC) // D7AC
+#define BN0_WF_MIB_TOP_BSCR2_ADDR (BN0_WF_MIB_TOP_BASE + 0x9D4) // D9D4
+#define BN0_WF_MIB_TOP_TSCR18_ADDR (BN0_WF_MIB_TOP_BASE + 0xA1C) // DA1C
+
+#define BN0_WF_MIB_TOP_MSR0_ADDR (BN0_WF_MIB_TOP_BASE + 0xA64) // DA64
+#define BN0_WF_MIB_TOP_MSR1_ADDR (BN0_WF_MIB_TOP_BASE + 0xA68) // DA68
+#define BN0_WF_MIB_TOP_MSR2_ADDR (BN0_WF_MIB_TOP_BASE + 0xA6C) // DA6C
+#define BN0_WF_MIB_TOP_MCTR5_ADDR (BN0_WF_MIB_TOP_BASE + 0xA70) // DA70
+#define BN0_WF_MIB_TOP_MCTR6_ADDR (BN0_WF_MIB_TOP_BASE + 0xA74) // DA74
+
+#define BN0_WF_MIB_TOP_RSCR26_ADDR (BN0_WF_MIB_TOP_BASE + 0x950) // D950
+#define BN0_WF_MIB_TOP_RSCR27_ADDR (BN0_WF_MIB_TOP_BASE + 0x954) // D954
+#define BN0_WF_MIB_TOP_RSCR28_ADDR (BN0_WF_MIB_TOP_BASE + 0x958) // D958
+#define BN0_WF_MIB_TOP_RSCR31_ADDR (BN0_WF_MIB_TOP_BASE + 0x964) // D964
+#define BN0_WF_MIB_TOP_RSCR33_ADDR (BN0_WF_MIB_TOP_BASE + 0x96C) // D96C
+#define BN0_WF_MIB_TOP_RSCR35_ADDR (BN0_WF_MIB_TOP_BASE + 0x974) // D974
+#define BN0_WF_MIB_TOP_RSCR36_ADDR (BN0_WF_MIB_TOP_BASE + 0x978) // D978
+
+#define BN0_WF_MIB_TOP_TSCR3_AMPDU_MPDU_COUNT_MASK 0xFFFFFFFF // AMPDU_MPDU_COUNT[31..0]
+#define BN0_WF_MIB_TOP_TSCR4_AMPDU_ACKED_COUNT_MASK 0xFFFFFFFF // AMPDU_ACKED_COUNT[31..0]
+#define BN0_WF_MIB_TOP_M0SDR6_CHANNEL_IDLE_COUNT_MASK 0x0000FFFF // CHANNEL_IDLE_COUNT[15..0]
+#define BN0_WF_MIB_TOP_M0SDR9_CCA_NAV_TX_TIME_MASK 0x00FFFFFF // CCA_NAV_TX_TIME[23..0]
+#define BN0_WF_MIB_TOP_RSCR26_RX_MDRDY_COUNT_MASK 0xFFFFFFFF // RX_MDRDY_COUNT[31..0]
+#define BN0_WF_MIB_TOP_MSR0_CCK_MDRDY_TIME_MASK 0xFFFFFFFF // CCK_MDRDY_TIME[31..0]
+#define BN0_WF_MIB_TOP_MSR1_OFDM_LG_MIXED_VHT_MDRDY_TIME_MASK 0xFFFFFFFF // OFDM_LG_MIXED_VHT_MDRDY_TIME[31..0]
+#define BN0_WF_MIB_TOP_MSR2_OFDM_GREEN_MDRDY_TIME_MASK 0xFFFFFFFF // OFDM_GREEN_MDRDY_TIME[31..0]
+#define BN0_WF_MIB_TOP_MCTR5_P_CCA_TIME_MASK 0xFFFFFFFF // P_CCA_TIME[31..0]
+#define BN0_WF_MIB_TOP_MCTR6_S_CCA_TIME_MASK 0xFFFFFFFF // S_CCA_TIME[31..0]
+#define BN0_WF_MIB_TOP_M0SDR18_P_ED_TIME_MASK 0x00FFFFFF // P_ED_TIME[23..0]
+#define BN0_WF_MIB_TOP_TSCR18_BEACONTXCOUNT_MASK 0xFFFFFFFF // BEACONTXCOUNT[31..0]
+#define BN0_WF_MIB_TOP_TBCR0_TX_20MHZ_CNT_MASK 0xFFFFFFFF // TX_20MHZ_CNT[31..0]
+#define BN0_WF_MIB_TOP_TBCR1_TX_40MHZ_CNT_MASK 0xFFFFFFFF // TX_40MHZ_CNT[31..0]
+#define BN0_WF_MIB_TOP_TBCR2_TX_80MHZ_CNT_MASK 0xFFFFFFFF // TX_80MHZ_CNT[31..0]
+#define BN0_WF_MIB_TOP_TBCR3_TX_160MHZ_CNT_MASK 0xFFFFFFFF // TX_160MHZ_CNT[31..0]
+#define BN0_WF_MIB_TOP_TBCR4_TX_320MHZ_CNT_MASK 0xFFFFFFFF // TX_320MHZ_CNT[31..0]
+#define BN0_WF_MIB_TOP_BSCR2_MUBF_TX_COUNT_MASK 0xFFFFFFFF // MUBF_TX_COUNT[31..0]
+#define BN0_WF_MIB_TOP_RVSR0_VEC_MISS_COUNT_MASK 0xFFFFFFFF // VEC_MISS_COUNT[31..0]
+#define BN0_WF_MIB_TOP_RSCR35_DELIMITER_FAIL_COUNT_MASK 0xFFFFFFFF // DELIMITER_FAIL_COUNT[31..0]
+#define BN0_WF_MIB_TOP_RSCR1_RX_FCS_ERROR_COUNT_MASK 0xFFFFFFFF // RX_FCS_ERROR_COUNT[31..0]
+#define BN0_WF_MIB_TOP_RSCR33_RX_FIFO_FULL_COUNT_MASK 0xFFFFFFFF // RX_FIFO_FULL_COUNT[31..0]
+#define BN0_WF_MIB_TOP_RSCR36_RX_LEN_MISMATCH_MASK 0xFFFFFFFF // RX_LEN_MISMATCH[31..0]
+#define BN0_WF_MIB_TOP_RSCR31_RX_MPDU_COUNT_MASK 0xFFFFFFFF // RX_MPDU_COUNT[31..0]
+#define BN0_WF_MIB_TOP_BTSCR5_RTSTXCOUNTn_MASK 0xFFFFFFFF // RTSTXCOUNTn[31..0]
+#define BN0_WF_MIB_TOP_BTSCR6_RTSRETRYCOUNTn_MASK 0xFFFFFFFF // RTSRETRYCOUNTn[31..0]
+#define BN0_WF_MIB_TOP_BTSCR0_BAMISSCOUNTn_MASK 0xFFFFFFFF // BAMISSCOUNTn[31..0]
+#define BN0_WF_MIB_TOP_BTSCR1_ACKFAILCOUNTn_MASK 0xFFFFFFFF // ACKFAILCOUNTn[31..0]
+#define BN0_WF_MIB_TOP_BTSCR2_FRAMERETRYCOUNTn_MASK 0xFFFFFFFF // FRAMERETRYCOUNTn[31..0]
+#define BN0_WF_MIB_TOP_BTSCR3_FRAMERETRY2COUNTn_MASK 0xFFFFFFFF // FRAMERETRY2COUNTn[31..0]
+#define BN0_WF_MIB_TOP_BTSCR4_FRAMERETRY3COUNTn_MASK 0xFFFFFFFF // FRAMERETRY3COUNTn[31..0]
+#define BN0_WF_MIB_TOP_TRARC0_ADDR (BN0_WF_MIB_TOP_BASE + 0x0B0) // D0B0
+#define BN0_WF_MIB_TOP_TRARC1_ADDR (BN0_WF_MIB_TOP_BASE + 0x0B4) // D0B4
+#define BN0_WF_MIB_TOP_TRARC2_ADDR (BN0_WF_MIB_TOP_BASE + 0x0B8) // D0B8
+#define BN0_WF_MIB_TOP_TRARC3_ADDR (BN0_WF_MIB_TOP_BASE + 0x0BC) // D0BC
+#define BN0_WF_MIB_TOP_TRARC4_ADDR (BN0_WF_MIB_TOP_BASE + 0x0C0) // D0C0
+#define BN0_WF_MIB_TOP_TRARC5_ADDR (BN0_WF_MIB_TOP_BASE + 0x0C4) // D0C4
+#define BN0_WF_MIB_TOP_TRARC6_ADDR (BN0_WF_MIB_TOP_BASE + 0x0C8) // D0C8
+#define BN0_WF_MIB_TOP_TRARC7_ADDR (BN0_WF_MIB_TOP_BASE + 0x0CC) // D0CC
+
+#define BN0_WF_MIB_TOP_TRDR0_ADDR (BN0_WF_MIB_TOP_BASE + 0x9B4) // D9B4
+#define BN0_WF_MIB_TOP_TRDR1_ADDR (BN0_WF_MIB_TOP_BASE + 0x9B8) // D9B8
+#define BN0_WF_MIB_TOP_TRDR2_ADDR (BN0_WF_MIB_TOP_BASE + 0x9BC) // D9BC
+#define BN0_WF_MIB_TOP_TRDR3_ADDR (BN0_WF_MIB_TOP_BASE + 0x9C0) // D9C0
+#define BN0_WF_MIB_TOP_TRDR4_ADDR (BN0_WF_MIB_TOP_BASE + 0x9C4) // D9C4
+#define BN0_WF_MIB_TOP_TRDR5_ADDR (BN0_WF_MIB_TOP_BASE + 0x9C8) // D9C8
+#define BN0_WF_MIB_TOP_TRDR6_ADDR (BN0_WF_MIB_TOP_BASE + 0x9CC) // D9CC
+#define BN0_WF_MIB_TOP_TRDR7_ADDR (BN0_WF_MIB_TOP_BASE + 0x9D0) // D9D0
+#define BN0_WF_MIB_TOP_TRDR8_ADDR (BN0_WF_MIB_TOP_BASE + 0x9D4) // D9D4
+#define BN0_WF_MIB_TOP_TRDR9_ADDR (BN0_WF_MIB_TOP_BASE + 0x9D8) // D9D8
+#define BN0_WF_MIB_TOP_TRDR10_ADDR (BN0_WF_MIB_TOP_BASE + 0x9DC) // D9DC
+#define BN0_WF_MIB_TOP_TRDR11_ADDR (BN0_WF_MIB_TOP_BASE + 0x9E0) // D9E0
+#define BN0_WF_MIB_TOP_TRDR12_ADDR (BN0_WF_MIB_TOP_BASE + 0x9E4) // D9E4
+#define BN0_WF_MIB_TOP_TRDR13_ADDR (BN0_WF_MIB_TOP_BASE + 0x9E8) // D9E8
+#define BN0_WF_MIB_TOP_TRDR14_ADDR (BN0_WF_MIB_TOP_BASE + 0x9EC) // D9EC
+#define BN0_WF_MIB_TOP_TRDR15_ADDR (BN0_WF_MIB_TOP_BASE + 0x9F0) // D9F0
+
+#define BN0_WF_MIB_TOP_TRARC0_AGG_RANG_SEL_1_ADDR BN0_WF_MIB_TOP_TRARC0_ADDR
+#define BN0_WF_MIB_TOP_TRARC0_AGG_RANG_SEL_1_MASK 0x03FF0000 // AGG_RANG_SEL_1[25..16]
+#define BN0_WF_MIB_TOP_TRARC0_AGG_RANG_SEL_1_SHFT 16
+#define BN0_WF_MIB_TOP_TRARC0_AGG_RANG_SEL_0_ADDR BN0_WF_MIB_TOP_TRARC0_ADDR
+#define BN0_WF_MIB_TOP_TRARC0_AGG_RANG_SEL_0_MASK 0x000003FF // AGG_RANG_SEL_0[9..0]
+#define BN0_WF_MIB_TOP_TRARC0_AGG_RANG_SEL_0_SHFT 0
+
+#define BN0_WF_MIB_TOP_TRARC1_AGG_RANG_SEL_3_ADDR BN0_WF_MIB_TOP_TRARC1_ADDR
+#define BN0_WF_MIB_TOP_TRARC1_AGG_RANG_SEL_3_MASK 0x03FF0000 // AGG_RANG_SEL_3[25..16]
+#define BN0_WF_MIB_TOP_TRARC1_AGG_RANG_SEL_3_SHFT 16
+#define BN0_WF_MIB_TOP_TRARC1_AGG_RANG_SEL_2_ADDR BN0_WF_MIB_TOP_TRARC1_ADDR
+#define BN0_WF_MIB_TOP_TRARC1_AGG_RANG_SEL_2_MASK 0x000003FF // AGG_RANG_SEL_2[9..0]
+#define BN0_WF_MIB_TOP_TRARC1_AGG_RANG_SEL_2_SHFT 0
+
+#define BN0_WF_MIB_TOP_TRARC2_AGG_RANG_SEL_5_ADDR BN0_WF_MIB_TOP_TRARC2_ADDR
+#define BN0_WF_MIB_TOP_TRARC2_AGG_RANG_SEL_5_MASK 0x03FF0000 // AGG_RANG_SEL_5[25..16]
+#define BN0_WF_MIB_TOP_TRARC2_AGG_RANG_SEL_5_SHFT 16
+#define BN0_WF_MIB_TOP_TRARC2_AGG_RANG_SEL_4_ADDR BN0_WF_MIB_TOP_TRARC2_ADDR
+#define BN0_WF_MIB_TOP_TRARC2_AGG_RANG_SEL_4_MASK 0x000003FF // AGG_RANG_SEL_4[9..0]
+#define BN0_WF_MIB_TOP_TRARC2_AGG_RANG_SEL_4_SHFT 0
+
+#define BN0_WF_MIB_TOP_TRARC3_AGG_RANG_SEL_7_ADDR BN0_WF_MIB_TOP_TRARC3_ADDR
+#define BN0_WF_MIB_TOP_TRARC3_AGG_RANG_SEL_7_MASK 0x03FF0000 // AGG_RANG_SEL_7[25..16]
+#define BN0_WF_MIB_TOP_TRARC3_AGG_RANG_SEL_7_SHFT 16
+#define BN0_WF_MIB_TOP_TRARC3_AGG_RANG_SEL_6_ADDR BN0_WF_MIB_TOP_TRARC3_ADDR
+#define BN0_WF_MIB_TOP_TRARC3_AGG_RANG_SEL_6_MASK 0x000003FF // AGG_RANG_SEL_6[9..0]
+#define BN0_WF_MIB_TOP_TRARC3_AGG_RANG_SEL_6_SHFT 0
+
+#define BN0_WF_MIB_TOP_TRARC4_AGG_RANG_SEL_9_ADDR BN0_WF_MIB_TOP_TRARC4_ADDR
+#define BN0_WF_MIB_TOP_TRARC4_AGG_RANG_SEL_9_MASK 0x03FF0000 // AGG_RANG_SEL_9[25..16]
+#define BN0_WF_MIB_TOP_TRARC4_AGG_RANG_SEL_9_SHFT 16
+#define BN0_WF_MIB_TOP_TRARC4_AGG_RANG_SEL_8_ADDR BN0_WF_MIB_TOP_TRARC4_ADDR
+#define BN0_WF_MIB_TOP_TRARC4_AGG_RANG_SEL_8_MASK 0x000003FF // AGG_RANG_SEL_8[9..0]
+#define BN0_WF_MIB_TOP_TRARC4_AGG_RANG_SEL_8_SHFT 0
+
+#define BN0_WF_MIB_TOP_TRARC5_AGG_RANG_SEL_11_ADDR BN0_WF_MIB_TOP_TRARC5_ADDR
+#define BN0_WF_MIB_TOP_TRARC5_AGG_RANG_SEL_11_MASK 0x03FF0000 // AGG_RANG_SEL_11[25..16]
+#define BN0_WF_MIB_TOP_TRARC5_AGG_RANG_SEL_11_SHFT 16
+#define BN0_WF_MIB_TOP_TRARC5_AGG_RANG_SEL_10_ADDR BN0_WF_MIB_TOP_TRARC5_ADDR
+#define BN0_WF_MIB_TOP_TRARC5_AGG_RANG_SEL_10_MASK 0x000003FF // AGG_RANG_SEL_10[9..0]
+#define BN0_WF_MIB_TOP_TRARC5_AGG_RANG_SEL_10_SHFT 0
+
+#define BN0_WF_MIB_TOP_TRARC6_AGG_RANG_SEL_13_ADDR BN0_WF_MIB_TOP_TRARC6_ADDR
+#define BN0_WF_MIB_TOP_TRARC6_AGG_RANG_SEL_13_MASK 0x03FF0000 // AGG_RANG_SEL_13[25..16]
+#define BN0_WF_MIB_TOP_TRARC6_AGG_RANG_SEL_13_SHFT 16
+#define BN0_WF_MIB_TOP_TRARC6_AGG_RANG_SEL_12_ADDR BN0_WF_MIB_TOP_TRARC6_ADDR
+#define BN0_WF_MIB_TOP_TRARC6_AGG_RANG_SEL_12_MASK 0x000003FF // AGG_RANG_SEL_12[9..0]
+#define BN0_WF_MIB_TOP_TRARC6_AGG_RANG_SEL_12_SHFT 0
+
+#define BN0_WF_MIB_TOP_TRARC7_AGG_RANG_SEL_14_ADDR BN0_WF_MIB_TOP_TRARC7_ADDR
+#define BN0_WF_MIB_TOP_TRARC7_AGG_RANG_SEL_14_MASK 0x000003FF // AGG_RANG_SEL_14[9..0]
+#define BN0_WF_MIB_TOP_TRARC7_AGG_RANG_SEL_14_SHFT 0
+
+/* RRO TOP */
+#define WF_RRO_TOP_BASE 0xA000 /*0x820C2000 */
+#define WF_RRO_TOP_IND_CMD_0_CTRL0_ADDR (WF_RRO_TOP_BASE + 0x40) // 2040
+ //
+/* WTBL */
+enum mt7996_wtbl_type {
+ WTBL_TYPE_LMAC, /* WTBL in LMAC */
+ WTBL_TYPE_UMAC, /* WTBL in UMAC */
+ WTBL_TYPE_KEY, /* Key Table */
+ MAX_NUM_WTBL_TYPE
+};
+
+struct berse_wtbl_parse {
+ u8 *name;
+ u32 mask;
+ u32 shift;
+ u8 new_line;
+};
+
+enum muar_idx {
+ MUAR_INDEX_OWN_MAC_ADDR_0 = 0,
+ MUAR_INDEX_OWN_MAC_ADDR_1,
+ MUAR_INDEX_OWN_MAC_ADDR_2,
+ MUAR_INDEX_OWN_MAC_ADDR_3,
+ MUAR_INDEX_OWN_MAC_ADDR_4,
+ MUAR_INDEX_OWN_MAC_ADDR_BC_MC = 0xE,
+ MUAR_INDEX_UNMATCHED = 0xF,
+ MUAR_INDEX_OWN_MAC_ADDR_11 = 0x11,
+ MUAR_INDEX_OWN_MAC_ADDR_12,
+ MUAR_INDEX_OWN_MAC_ADDR_13,
+ MUAR_INDEX_OWN_MAC_ADDR_14,
+ MUAR_INDEX_OWN_MAC_ADDR_15,
+ MUAR_INDEX_OWN_MAC_ADDR_16,
+ MUAR_INDEX_OWN_MAC_ADDR_17,
+ MUAR_INDEX_OWN_MAC_ADDR_18,
+ MUAR_INDEX_OWN_MAC_ADDR_19,
+ MUAR_INDEX_OWN_MAC_ADDR_1A,
+ MUAR_INDEX_OWN_MAC_ADDR_1B,
+ MUAR_INDEX_OWN_MAC_ADDR_1C,
+ MUAR_INDEX_OWN_MAC_ADDR_1D,
+ MUAR_INDEX_OWN_MAC_ADDR_1E,
+ MUAR_INDEX_OWN_MAC_ADDR_1F,
+ MUAR_INDEX_OWN_MAC_ADDR_20,
+ MUAR_INDEX_OWN_MAC_ADDR_21,
+ MUAR_INDEX_OWN_MAC_ADDR_22,
+ MUAR_INDEX_OWN_MAC_ADDR_23,
+ MUAR_INDEX_OWN_MAC_ADDR_24,
+ MUAR_INDEX_OWN_MAC_ADDR_25,
+ MUAR_INDEX_OWN_MAC_ADDR_26,
+ MUAR_INDEX_OWN_MAC_ADDR_27,
+ MUAR_INDEX_OWN_MAC_ADDR_28,
+ MUAR_INDEX_OWN_MAC_ADDR_29,
+ MUAR_INDEX_OWN_MAC_ADDR_2A,
+ MUAR_INDEX_OWN_MAC_ADDR_2B,
+ MUAR_INDEX_OWN_MAC_ADDR_2C,
+ MUAR_INDEX_OWN_MAC_ADDR_2D,
+ MUAR_INDEX_OWN_MAC_ADDR_2E,
+ MUAR_INDEX_OWN_MAC_ADDR_2F
+};
+
+enum cipher_suit {
+ IGTK_CIPHER_SUIT_NONE = 0,
+ IGTK_CIPHER_SUIT_BIP,
+ IGTK_CIPHER_SUIT_BIP_256
+};
+
+#define LWTBL_LEN_IN_DW 36
+#define UWTBL_LEN_IN_DW 10
+
+#define MT_DBG_WTBL_BASE 0x820D8000
+
+#define MT_DBG_WTBLON_TOP_BASE 0x820d4000
+#define MT_DBG_WTBLON_TOP_WDUCR_ADDR (MT_DBG_WTBLON_TOP_BASE + 0x0370) // 4370
+#define MT_DBG_WTBLON_TOP_WDUCR_GROUP GENMASK(4, 0)
+
+#define MT_DBG_UWTBL_TOP_BASE 0x820c4000
+#define MT_DBG_UWTBL_TOP_WDUCR_ADDR (MT_DBG_UWTBL_TOP_BASE + 0x0104) // 4104
+#define MT_DBG_UWTBL_TOP_WDUCR_GROUP GENMASK(5, 0)
+#define MT_DBG_UWTBL_TOP_WDUCR_TARGET BIT(31)
+
+#define LWTBL_IDX2BASE_ID GENMASK(14, 8)
+#define LWTBL_IDX2BASE_DW GENMASK(7, 2)
+#define LWTBL_IDX2BASE(_id, _dw) (MT_DBG_WTBL_BASE | \
+ FIELD_PREP(LWTBL_IDX2BASE_ID, _id) | \
+ FIELD_PREP(LWTBL_IDX2BASE_DW, _dw))
+
+#define UWTBL_IDX2BASE_ID GENMASK(12, 6)
+#define UWTBL_IDX2BASE_DW GENMASK(5, 2)
+#define UWTBL_IDX2BASE(_id, _dw) (MT_DBG_UWTBL_TOP_BASE | 0x2000 | \
+ FIELD_PREP(UWTBL_IDX2BASE_ID, _id) | \
+ FIELD_PREP(UWTBL_IDX2BASE_DW, _dw))
+
+#define KEYTBL_IDX2BASE_KEY GENMASK(12, 6)
+#define KEYTBL_IDX2BASE_DW GENMASK(5, 2)
+#define KEYTBL_IDX2BASE(_key, _dw) (MT_DBG_UWTBL_TOP_BASE | 0x2000 | \
+ FIELD_PREP(KEYTBL_IDX2BASE_KEY, _key) | \
+ FIELD_PREP(KEYTBL_IDX2BASE_DW, _dw))
+
+// UMAC WTBL
+// DW0
+#define WF_UWTBL_PEER_MLD_ADDRESS_47_32__DW 0
+#define WF_UWTBL_PEER_MLD_ADDRESS_47_32__ADDR 0
+#define WF_UWTBL_PEER_MLD_ADDRESS_47_32__MASK 0x0000ffff // 15- 0
+#define WF_UWTBL_PEER_MLD_ADDRESS_47_32__SHIFT 0
+#define WF_UWTBL_OWN_MLD_ID_DW 0
+#define WF_UWTBL_OWN_MLD_ID_ADDR 0
+#define WF_UWTBL_OWN_MLD_ID_MASK 0x003f0000 // 21-16
+#define WF_UWTBL_OWN_MLD_ID_SHIFT 16
+// DW1
+#define WF_UWTBL_PEER_MLD_ADDRESS_31_0__DW 1
+#define WF_UWTBL_PEER_MLD_ADDRESS_31_0__ADDR 4
+#define WF_UWTBL_PEER_MLD_ADDRESS_31_0__MASK 0xffffffff // 31- 0
+#define WF_UWTBL_PEER_MLD_ADDRESS_31_0__SHIFT 0
+// DW2
+#define WF_UWTBL_PN_31_0__DW 2
+#define WF_UWTBL_PN_31_0__ADDR 8
+#define WF_UWTBL_PN_31_0__MASK 0xffffffff // 31- 0
+#define WF_UWTBL_PN_31_0__SHIFT 0
+// DW3
+#define WF_UWTBL_PN_47_32__DW 3
+#define WF_UWTBL_PN_47_32__ADDR 12
+#define WF_UWTBL_PN_47_32__MASK 0x0000ffff // 15- 0
+#define WF_UWTBL_PN_47_32__SHIFT 0
+#define WF_UWTBL_COM_SN_DW 3
+#define WF_UWTBL_COM_SN_ADDR 12
+#define WF_UWTBL_COM_SN_MASK 0x0fff0000 // 27-16
+#define WF_UWTBL_COM_SN_SHIFT 16
+// DW4
+#define WF_UWTBL_TID0_SN_DW 4
+#define WF_UWTBL_TID0_SN_ADDR 16
+#define WF_UWTBL_TID0_SN_MASK 0x00000fff // 11- 0
+#define WF_UWTBL_TID0_SN_SHIFT 0
+#define WF_UWTBL_RX_BIPN_31_0__DW 4
+#define WF_UWTBL_RX_BIPN_31_0__ADDR 16
+#define WF_UWTBL_RX_BIPN_31_0__MASK 0xffffffff // 31- 0
+#define WF_UWTBL_RX_BIPN_31_0__SHIFT 0
+#define WF_UWTBL_TID1_SN_DW 4
+#define WF_UWTBL_TID1_SN_ADDR 16
+#define WF_UWTBL_TID1_SN_MASK 0x00fff000 // 23-12
+#define WF_UWTBL_TID1_SN_SHIFT 12
+#define WF_UWTBL_TID2_SN_7_0__DW 4
+#define WF_UWTBL_TID2_SN_7_0__ADDR 16
+#define WF_UWTBL_TID2_SN_7_0__MASK 0xff000000 // 31-24
+#define WF_UWTBL_TID2_SN_7_0__SHIFT 24
+// DW5
+#define WF_UWTBL_TID2_SN_11_8__DW 5
+#define WF_UWTBL_TID2_SN_11_8__ADDR 20
+#define WF_UWTBL_TID2_SN_11_8__MASK 0x0000000f // 3- 0
+#define WF_UWTBL_TID2_SN_11_8__SHIFT 0
+#define WF_UWTBL_RX_BIPN_47_32__DW 5
+#define WF_UWTBL_RX_BIPN_47_32__ADDR 20
+#define WF_UWTBL_RX_BIPN_47_32__MASK 0x0000ffff // 15- 0
+#define WF_UWTBL_RX_BIPN_47_32__SHIFT 0
+#define WF_UWTBL_TID3_SN_DW 5
+#define WF_UWTBL_TID3_SN_ADDR 20
+#define WF_UWTBL_TID3_SN_MASK 0x0000fff0 // 15- 4
+#define WF_UWTBL_TID3_SN_SHIFT 4
+#define WF_UWTBL_TID4_SN_DW 5
+#define WF_UWTBL_TID4_SN_ADDR 20
+#define WF_UWTBL_TID4_SN_MASK 0x0fff0000 // 27-16
+#define WF_UWTBL_TID4_SN_SHIFT 16
+#define WF_UWTBL_TID5_SN_3_0__DW 5
+#define WF_UWTBL_TID5_SN_3_0__ADDR 20
+#define WF_UWTBL_TID5_SN_3_0__MASK 0xf0000000 // 31-28
+#define WF_UWTBL_TID5_SN_3_0__SHIFT 28
+// DW6
+#define WF_UWTBL_TID5_SN_11_4__DW 6
+#define WF_UWTBL_TID5_SN_11_4__ADDR 24
+#define WF_UWTBL_TID5_SN_11_4__MASK 0x000000ff // 7- 0
+#define WF_UWTBL_TID5_SN_11_4__SHIFT 0
+#define WF_UWTBL_KEY_LOC2_DW 6
+#define WF_UWTBL_KEY_LOC2_ADDR 24
+#define WF_UWTBL_KEY_LOC2_MASK 0x00001fff // 12- 0
+#define WF_UWTBL_KEY_LOC2_SHIFT 0
+#define WF_UWTBL_TID6_SN_DW 6
+#define WF_UWTBL_TID6_SN_ADDR 24
+#define WF_UWTBL_TID6_SN_MASK 0x000fff00 // 19- 8
+#define WF_UWTBL_TID6_SN_SHIFT 8
+#define WF_UWTBL_TID7_SN_DW 6
+#define WF_UWTBL_TID7_SN_ADDR 24
+#define WF_UWTBL_TID7_SN_MASK 0xfff00000 // 31-20
+#define WF_UWTBL_TID7_SN_SHIFT 20
+// DW7
+#define WF_UWTBL_KEY_LOC0_DW 7
+#define WF_UWTBL_KEY_LOC0_ADDR 28
+#define WF_UWTBL_KEY_LOC0_MASK 0x00001fff // 12- 0
+#define WF_UWTBL_KEY_LOC0_SHIFT 0
+#define WF_UWTBL_KEY_LOC1_DW 7
+#define WF_UWTBL_KEY_LOC1_ADDR 28
+#define WF_UWTBL_KEY_LOC1_MASK 0x1fff0000 // 28-16
+#define WF_UWTBL_KEY_LOC1_SHIFT 16
+// DW8
+#define WF_UWTBL_AMSDU_CFG_DW 8
+#define WF_UWTBL_AMSDU_CFG_ADDR 32
+#define WF_UWTBL_AMSDU_CFG_MASK 0x00000fff // 11- 0
+#define WF_UWTBL_AMSDU_CFG_SHIFT 0
+#define WF_UWTBL_WMM_Q_DW 8
+#define WF_UWTBL_WMM_Q_ADDR 32
+#define WF_UWTBL_WMM_Q_MASK 0x06000000 // 26-25
+#define WF_UWTBL_WMM_Q_SHIFT 25
+#define WF_UWTBL_QOS_DW 8
+#define WF_UWTBL_QOS_ADDR 32
+#define WF_UWTBL_QOS_MASK 0x08000000 // 27-27
+#define WF_UWTBL_QOS_SHIFT 27
+#define WF_UWTBL_HT_DW 8
+#define WF_UWTBL_HT_ADDR 32
+#define WF_UWTBL_HT_MASK 0x10000000 // 28-28
+#define WF_UWTBL_HT_SHIFT 28
+#define WF_UWTBL_HDRT_MODE_DW 8
+#define WF_UWTBL_HDRT_MODE_ADDR 32
+#define WF_UWTBL_HDRT_MODE_MASK 0x20000000 // 29-29
+#define WF_UWTBL_HDRT_MODE_SHIFT 29
+// DW9
+#define WF_UWTBL_RELATED_IDX0_DW 9
+#define WF_UWTBL_RELATED_IDX0_ADDR 36
+#define WF_UWTBL_RELATED_IDX0_MASK 0x00000fff // 11- 0
+#define WF_UWTBL_RELATED_IDX0_SHIFT 0
+#define WF_UWTBL_RELATED_BAND0_DW 9
+#define WF_UWTBL_RELATED_BAND0_ADDR 36
+#define WF_UWTBL_RELATED_BAND0_MASK 0x00003000 // 13-12
+#define WF_UWTBL_RELATED_BAND0_SHIFT 12
+#define WF_UWTBL_PRIMARY_MLD_BAND_DW 9
+#define WF_UWTBL_PRIMARY_MLD_BAND_ADDR 36
+#define WF_UWTBL_PRIMARY_MLD_BAND_MASK 0x0000c000 // 15-14
+#define WF_UWTBL_PRIMARY_MLD_BAND_SHIFT 14
+#define WF_UWTBL_RELATED_IDX1_DW 9
+#define WF_UWTBL_RELATED_IDX1_ADDR 36
+#define WF_UWTBL_RELATED_IDX1_MASK 0x0fff0000 // 27-16
+#define WF_UWTBL_RELATED_IDX1_SHIFT 16
+#define WF_UWTBL_RELATED_BAND1_DW 9
+#define WF_UWTBL_RELATED_BAND1_ADDR 36
+#define WF_UWTBL_RELATED_BAND1_MASK 0x30000000 // 29-28
+#define WF_UWTBL_RELATED_BAND1_SHIFT 28
+#define WF_UWTBL_SECONDARY_MLD_BAND_DW 9
+#define WF_UWTBL_SECONDARY_MLD_BAND_ADDR 36
+#define WF_UWTBL_SECONDARY_MLD_BAND_MASK 0xc0000000 // 31-30
+#define WF_UWTBL_SECONDARY_MLD_BAND_SHIFT 30
+
+/* LMAC WTBL */
+// DW0
+#define WF_LWTBL_PEER_LINK_ADDRESS_47_32__DW 0
+#define WF_LWTBL_PEER_LINK_ADDRESS_47_32__ADDR 0
+#define WF_LWTBL_PEER_LINK_ADDRESS_47_32__MASK \
+ 0x0000ffff // 15- 0
+#define WF_LWTBL_PEER_LINK_ADDRESS_47_32__SHIFT 0
+#define WF_LWTBL_MUAR_DW 0
+#define WF_LWTBL_MUAR_ADDR 0
+#define WF_LWTBL_MUAR_MASK \
+ 0x003f0000 // 21-16
+#define WF_LWTBL_MUAR_SHIFT 16
+#define WF_LWTBL_RCA1_DW 0
+#define WF_LWTBL_RCA1_ADDR 0
+#define WF_LWTBL_RCA1_MASK \
+ 0x00400000 // 22-22
+#define WF_LWTBL_RCA1_SHIFT 22
+#define WF_LWTBL_KID_DW 0
+#define WF_LWTBL_KID_ADDR 0
+#define WF_LWTBL_KID_MASK \
+ 0x01800000 // 24-23
+#define WF_LWTBL_KID_SHIFT 23
+#define WF_LWTBL_RCID_DW 0
+#define WF_LWTBL_RCID_ADDR 0
+#define WF_LWTBL_RCID_MASK \
+ 0x02000000 // 25-25
+#define WF_LWTBL_RCID_SHIFT 25
+#define WF_LWTBL_BAND_DW 0
+#define WF_LWTBL_BAND_ADDR 0
+#define WF_LWTBL_BAND_MASK \
+ 0x0c000000 // 27-26
+#define WF_LWTBL_BAND_SHIFT 26
+#define WF_LWTBL_RV_DW 0
+#define WF_LWTBL_RV_ADDR 0
+#define WF_LWTBL_RV_MASK \
+ 0x10000000 // 28-28
+#define WF_LWTBL_RV_SHIFT 28
+#define WF_LWTBL_RCA2_DW 0
+#define WF_LWTBL_RCA2_ADDR 0
+#define WF_LWTBL_RCA2_MASK \
+ 0x20000000 // 29-29
+#define WF_LWTBL_RCA2_SHIFT 29
+#define WF_LWTBL_WPI_FLAG_DW 0
+#define WF_LWTBL_WPI_FLAG_ADDR 0
+#define WF_LWTBL_WPI_FLAG_MASK \
+ 0x40000000 // 30-30
+#define WF_LWTBL_WPI_FLAG_SHIFT 30
+// DW1
+#define WF_LWTBL_PEER_LINK_ADDRESS_31_0__DW 1
+#define WF_LWTBL_PEER_LINK_ADDRESS_31_0__ADDR 4
+#define WF_LWTBL_PEER_LINK_ADDRESS_31_0__MASK \
+ 0xffffffff // 31- 0
+#define WF_LWTBL_PEER_LINK_ADDRESS_31_0__SHIFT 0
+// DW2
+#define WF_LWTBL_AID_DW 2
+#define WF_LWTBL_AID_ADDR 8
+#define WF_LWTBL_AID_MASK \
+ 0x00000fff // 11- 0
+#define WF_LWTBL_AID_SHIFT 0
+#define WF_LWTBL_GID_SU_DW 2
+#define WF_LWTBL_GID_SU_ADDR 8
+#define WF_LWTBL_GID_SU_MASK \
+ 0x00001000 // 12-12
+#define WF_LWTBL_GID_SU_SHIFT 12
+#define WF_LWTBL_SPP_EN_DW 2
+#define WF_LWTBL_SPP_EN_ADDR 8
+#define WF_LWTBL_SPP_EN_MASK \
+ 0x00002000 // 13-13
+#define WF_LWTBL_SPP_EN_SHIFT 13
+#define WF_LWTBL_WPI_EVEN_DW 2
+#define WF_LWTBL_WPI_EVEN_ADDR 8
+#define WF_LWTBL_WPI_EVEN_MASK \
+ 0x00004000 // 14-14
+#define WF_LWTBL_WPI_EVEN_SHIFT 14
+#define WF_LWTBL_AAD_OM_DW 2
+#define WF_LWTBL_AAD_OM_ADDR 8
+#define WF_LWTBL_AAD_OM_MASK \
+ 0x00008000 // 15-15
+#define WF_LWTBL_AAD_OM_SHIFT 15
+#define WF_LWTBL_CIPHER_SUIT_PGTK_DW 2
+#define WF_LWTBL_CIPHER_SUIT_PGTK_ADDR 8
+#define WF_LWTBL_CIPHER_SUIT_PGTK_MASK \
+ 0x001f0000 // 20-16
+#define WF_LWTBL_CIPHER_SUIT_PGTK_SHIFT 16
+#define WF_LWTBL_FD_DW 2
+#define WF_LWTBL_FD_ADDR 8
+#define WF_LWTBL_FD_MASK \
+ 0x00200000 // 21-21
+#define WF_LWTBL_FD_SHIFT 21
+#define WF_LWTBL_TD_DW 2
+#define WF_LWTBL_TD_ADDR 8
+#define WF_LWTBL_TD_MASK \
+ 0x00400000 // 22-22
+#define WF_LWTBL_TD_SHIFT 22
+#define WF_LWTBL_SW_DW 2
+#define WF_LWTBL_SW_ADDR 8
+#define WF_LWTBL_SW_MASK \
+ 0x00800000 // 23-23
+#define WF_LWTBL_SW_SHIFT 23
+#define WF_LWTBL_UL_DW 2
+#define WF_LWTBL_UL_ADDR 8
+#define WF_LWTBL_UL_MASK \
+ 0x01000000 // 24-24
+#define WF_LWTBL_UL_SHIFT 24
+#define WF_LWTBL_TX_PS_DW 2
+#define WF_LWTBL_TX_PS_ADDR 8
+#define WF_LWTBL_TX_PS_MASK \
+ 0x02000000 // 25-25
+#define WF_LWTBL_TX_PS_SHIFT 25
+#define WF_LWTBL_QOS_DW 2
+#define WF_LWTBL_QOS_ADDR 8
+#define WF_LWTBL_QOS_MASK \
+ 0x04000000 // 26-26
+#define WF_LWTBL_QOS_SHIFT 26
+#define WF_LWTBL_HT_DW 2
+#define WF_LWTBL_HT_ADDR 8
+#define WF_LWTBL_HT_MASK \
+ 0x08000000 // 27-27
+#define WF_LWTBL_HT_SHIFT 27
+#define WF_LWTBL_VHT_DW 2
+#define WF_LWTBL_VHT_ADDR 8
+#define WF_LWTBL_VHT_MASK \
+ 0x10000000 // 28-28
+#define WF_LWTBL_VHT_SHIFT 28
+#define WF_LWTBL_HE_DW 2
+#define WF_LWTBL_HE_ADDR 8
+#define WF_LWTBL_HE_MASK \
+ 0x20000000 // 29-29
+#define WF_LWTBL_HE_SHIFT 29
+#define WF_LWTBL_EHT_DW 2
+#define WF_LWTBL_EHT_ADDR 8
+#define WF_LWTBL_EHT_MASK \
+ 0x40000000 // 30-30
+#define WF_LWTBL_EHT_SHIFT 30
+#define WF_LWTBL_MESH_DW 2
+#define WF_LWTBL_MESH_ADDR 8
+#define WF_LWTBL_MESH_MASK \
+ 0x80000000 // 31-31
+#define WF_LWTBL_MESH_SHIFT 31
+// DW3
+#define WF_LWTBL_WMM_Q_DW 3
+#define WF_LWTBL_WMM_Q_ADDR 12
+#define WF_LWTBL_WMM_Q_MASK \
+ 0x00000003 // 1- 0
+#define WF_LWTBL_WMM_Q_SHIFT 0
+#define WF_LWTBL_EHT_SIG_MCS_DW 3
+#define WF_LWTBL_EHT_SIG_MCS_ADDR 12
+#define WF_LWTBL_EHT_SIG_MCS_MASK \
+ 0x0000000c // 3- 2
+#define WF_LWTBL_EHT_SIG_MCS_SHIFT 2
+#define WF_LWTBL_HDRT_MODE_DW 3
+#define WF_LWTBL_HDRT_MODE_ADDR 12
+#define WF_LWTBL_HDRT_MODE_MASK \
+ 0x00000010 // 4- 4
+#define WF_LWTBL_HDRT_MODE_SHIFT 4
+#define WF_LWTBL_BEAM_CHG_DW 3
+#define WF_LWTBL_BEAM_CHG_ADDR 12
+#define WF_LWTBL_BEAM_CHG_MASK \
+ 0x00000020 // 5- 5
+#define WF_LWTBL_BEAM_CHG_SHIFT 5
+#define WF_LWTBL_EHT_LTF_SYM_NUM_OPT_DW 3
+#define WF_LWTBL_EHT_LTF_SYM_NUM_OPT_ADDR 12
+#define WF_LWTBL_EHT_LTF_SYM_NUM_OPT_MASK \
+ 0x000000c0 // 7- 6
+#define WF_LWTBL_EHT_LTF_SYM_NUM_OPT_SHIFT 6
+#define WF_LWTBL_PFMU_IDX_DW 3
+#define WF_LWTBL_PFMU_IDX_ADDR 12
+#define WF_LWTBL_PFMU_IDX_MASK \
+ 0x0000ff00 // 15- 8
+#define WF_LWTBL_PFMU_IDX_SHIFT 8
+#define WF_LWTBL_ULPF_IDX_DW 3
+#define WF_LWTBL_ULPF_IDX_ADDR 12
+#define WF_LWTBL_ULPF_IDX_MASK \
+ 0x00ff0000 // 23-16
+#define WF_LWTBL_ULPF_IDX_SHIFT 16
+#define WF_LWTBL_RIBF_DW 3
+#define WF_LWTBL_RIBF_ADDR 12
+#define WF_LWTBL_RIBF_MASK \
+ 0x01000000 // 24-24
+#define WF_LWTBL_RIBF_SHIFT 24
+#define WF_LWTBL_ULPF_DW 3
+#define WF_LWTBL_ULPF_ADDR 12
+#define WF_LWTBL_ULPF_MASK \
+ 0x02000000 // 25-25
+#define WF_LWTBL_ULPF_SHIFT 25
+#define WF_LWTBL_TBF_HT_DW 3
+#define WF_LWTBL_TBF_HT_ADDR 12
+#define WF_LWTBL_TBF_HT_MASK \
+ 0x08000000 // 27-27
+#define WF_LWTBL_TBF_HT_SHIFT 27
+#define WF_LWTBL_TBF_VHT_DW 3
+#define WF_LWTBL_TBF_VHT_ADDR 12
+#define WF_LWTBL_TBF_VHT_MASK \
+ 0x10000000 // 28-28
+#define WF_LWTBL_TBF_VHT_SHIFT 28
+#define WF_LWTBL_TBF_HE_DW 3
+#define WF_LWTBL_TBF_HE_ADDR 12
+#define WF_LWTBL_TBF_HE_MASK \
+ 0x20000000 // 29-29
+#define WF_LWTBL_TBF_HE_SHIFT 29
+#define WF_LWTBL_TBF_EHT_DW 3
+#define WF_LWTBL_TBF_EHT_ADDR 12
+#define WF_LWTBL_TBF_EHT_MASK \
+ 0x40000000 // 30-30
+#define WF_LWTBL_TBF_EHT_SHIFT 30
+#define WF_LWTBL_IGN_FBK_DW 3
+#define WF_LWTBL_IGN_FBK_ADDR 12
+#define WF_LWTBL_IGN_FBK_MASK \
+ 0x80000000 // 31-31
+#define WF_LWTBL_IGN_FBK_SHIFT 31
+// DW4
+#define WF_LWTBL_ANT_ID0_DW 4
+#define WF_LWTBL_ANT_ID0_ADDR 16
+#define WF_LWTBL_ANT_ID0_MASK \
+ 0x00000007 // 2- 0
+#define WF_LWTBL_ANT_ID0_SHIFT 0
+#define WF_LWTBL_ANT_ID1_DW 4
+#define WF_LWTBL_ANT_ID1_ADDR 16
+#define WF_LWTBL_ANT_ID1_MASK \
+ 0x00000038 // 5- 3
+#define WF_LWTBL_ANT_ID1_SHIFT 3
+#define WF_LWTBL_ANT_ID2_DW 4
+#define WF_LWTBL_ANT_ID2_ADDR 16
+#define WF_LWTBL_ANT_ID2_MASK \
+ 0x000001c0 // 8- 6
+#define WF_LWTBL_ANT_ID2_SHIFT 6
+#define WF_LWTBL_ANT_ID3_DW 4
+#define WF_LWTBL_ANT_ID3_ADDR 16
+#define WF_LWTBL_ANT_ID3_MASK \
+ 0x00000e00 // 11- 9
+#define WF_LWTBL_ANT_ID3_SHIFT 9
+#define WF_LWTBL_ANT_ID4_DW 4
+#define WF_LWTBL_ANT_ID4_ADDR 16
+#define WF_LWTBL_ANT_ID4_MASK \
+ 0x00007000 // 14-12
+#define WF_LWTBL_ANT_ID4_SHIFT 12
+#define WF_LWTBL_ANT_ID5_DW 4
+#define WF_LWTBL_ANT_ID5_ADDR 16
+#define WF_LWTBL_ANT_ID5_MASK \
+ 0x00038000 // 17-15
+#define WF_LWTBL_ANT_ID5_SHIFT 15
+#define WF_LWTBL_ANT_ID6_DW 4
+#define WF_LWTBL_ANT_ID6_ADDR 16
+#define WF_LWTBL_ANT_ID6_MASK \
+ 0x001c0000 // 20-18
+#define WF_LWTBL_ANT_ID6_SHIFT 18
+#define WF_LWTBL_ANT_ID7_DW 4
+#define WF_LWTBL_ANT_ID7_ADDR 16
+#define WF_LWTBL_ANT_ID7_MASK \
+ 0x00e00000 // 23-21
+#define WF_LWTBL_ANT_ID7_SHIFT 21
+#define WF_LWTBL_PE_DW 4
+#define WF_LWTBL_PE_ADDR 16
+#define WF_LWTBL_PE_MASK \
+ 0x03000000 // 25-24
+#define WF_LWTBL_PE_SHIFT 24
+#define WF_LWTBL_DIS_RHTR_DW 4
+#define WF_LWTBL_DIS_RHTR_ADDR 16
+#define WF_LWTBL_DIS_RHTR_MASK \
+ 0x04000000 // 26-26
+#define WF_LWTBL_DIS_RHTR_SHIFT 26
+#define WF_LWTBL_LDPC_HT_DW 4
+#define WF_LWTBL_LDPC_HT_ADDR 16
+#define WF_LWTBL_LDPC_HT_MASK \
+ 0x08000000 // 27-27
+#define WF_LWTBL_LDPC_HT_SHIFT 27
+#define WF_LWTBL_LDPC_VHT_DW 4
+#define WF_LWTBL_LDPC_VHT_ADDR 16
+#define WF_LWTBL_LDPC_VHT_MASK \
+ 0x10000000 // 28-28
+#define WF_LWTBL_LDPC_VHT_SHIFT 28
+#define WF_LWTBL_LDPC_HE_DW 4
+#define WF_LWTBL_LDPC_HE_ADDR 16
+#define WF_LWTBL_LDPC_HE_MASK \
+ 0x20000000 // 29-29
+#define WF_LWTBL_LDPC_HE_SHIFT 29
+#define WF_LWTBL_LDPC_EHT_DW 4
+#define WF_LWTBL_LDPC_EHT_ADDR 16
+#define WF_LWTBL_LDPC_EHT_MASK \
+ 0x40000000 // 30-30
+#define WF_LWTBL_LDPC_EHT_SHIFT 30
+// DW5
+#define WF_LWTBL_AF_DW 5
+#define WF_LWTBL_AF_ADDR 20
+#define WF_LWTBL_AF_MASK \
+ 0x00000007 // 2- 0
+#define WF_LWTBL_AF_SHIFT 0
+#define WF_LWTBL_AF_HE_DW 5
+#define WF_LWTBL_AF_HE_ADDR 20
+#define WF_LWTBL_AF_HE_MASK \
+ 0x00000018 // 4- 3
+#define WF_LWTBL_AF_HE_SHIFT 3
+#define WF_LWTBL_RTS_DW 5
+#define WF_LWTBL_RTS_ADDR 20
+#define WF_LWTBL_RTS_MASK \
+ 0x00000020 // 5- 5
+#define WF_LWTBL_RTS_SHIFT 5
+#define WF_LWTBL_SMPS_DW 5
+#define WF_LWTBL_SMPS_ADDR 20
+#define WF_LWTBL_SMPS_MASK \
+ 0x00000040 // 6- 6
+#define WF_LWTBL_SMPS_SHIFT 6
+#define WF_LWTBL_DYN_BW_DW 5
+#define WF_LWTBL_DYN_BW_ADDR 20
+#define WF_LWTBL_DYN_BW_MASK \
+ 0x00000080 // 7- 7
+#define WF_LWTBL_DYN_BW_SHIFT 7
+#define WF_LWTBL_MMSS_DW 5
+#define WF_LWTBL_MMSS_ADDR 20
+#define WF_LWTBL_MMSS_MASK \
+ 0x00000700 // 10- 8
+#define WF_LWTBL_MMSS_SHIFT 8
+#define WF_LWTBL_USR_DW 5
+#define WF_LWTBL_USR_ADDR 20
+#define WF_LWTBL_USR_MASK \
+ 0x00000800 // 11-11
+#define WF_LWTBL_USR_SHIFT 11
+#define WF_LWTBL_SR_R_DW 5
+#define WF_LWTBL_SR_R_ADDR 20
+#define WF_LWTBL_SR_R_MASK \
+ 0x00007000 // 14-12
+#define WF_LWTBL_SR_R_SHIFT 12
+#define WF_LWTBL_SR_ABORT_DW 5
+#define WF_LWTBL_SR_ABORT_ADDR 20
+#define WF_LWTBL_SR_ABORT_MASK \
+ 0x00008000 // 15-15
+#define WF_LWTBL_SR_ABORT_SHIFT 15
+#define WF_LWTBL_TX_POWER_OFFSET_DW 5
+#define WF_LWTBL_TX_POWER_OFFSET_ADDR 20
+#define WF_LWTBL_TX_POWER_OFFSET_MASK \
+ 0x003f0000 // 21-16
+#define WF_LWTBL_TX_POWER_OFFSET_SHIFT 16
+#define WF_LWTBL_LTF_EHT_DW 5
+#define WF_LWTBL_LTF_EHT_ADDR 20
+#define WF_LWTBL_LTF_EHT_MASK \
+ 0x00c00000 // 23-22
+#define WF_LWTBL_LTF_EHT_SHIFT 22
+#define WF_LWTBL_GI_EHT_DW 5
+#define WF_LWTBL_GI_EHT_ADDR 20
+#define WF_LWTBL_GI_EHT_MASK \
+ 0x03000000 // 25-24
+#define WF_LWTBL_GI_EHT_SHIFT 24
+#define WF_LWTBL_DOPPL_DW 5
+#define WF_LWTBL_DOPPL_ADDR 20
+#define WF_LWTBL_DOPPL_MASK \
+ 0x04000000 // 26-26
+#define WF_LWTBL_DOPPL_SHIFT 26
+#define WF_LWTBL_TXOP_PS_CAP_DW 5
+#define WF_LWTBL_TXOP_PS_CAP_ADDR 20
+#define WF_LWTBL_TXOP_PS_CAP_MASK \
+ 0x08000000 // 27-27
+#define WF_LWTBL_TXOP_PS_CAP_SHIFT 27
+#define WF_LWTBL_DU_I_PSM_DW 5
+#define WF_LWTBL_DU_I_PSM_ADDR 20
+#define WF_LWTBL_DU_I_PSM_MASK \
+ 0x10000000 // 28-28
+#define WF_LWTBL_DU_I_PSM_SHIFT 28
+#define WF_LWTBL_I_PSM_DW 5
+#define WF_LWTBL_I_PSM_ADDR 20
+#define WF_LWTBL_I_PSM_MASK \
+ 0x20000000 // 29-29
+#define WF_LWTBL_I_PSM_SHIFT 29
+#define WF_LWTBL_PSM_DW 5
+#define WF_LWTBL_PSM_ADDR 20
+#define WF_LWTBL_PSM_MASK \
+ 0x40000000 // 30-30
+#define WF_LWTBL_PSM_SHIFT 30
+#define WF_LWTBL_SKIP_TX_DW 5
+#define WF_LWTBL_SKIP_TX_ADDR 20
+#define WF_LWTBL_SKIP_TX_MASK \
+ 0x80000000 // 31-31
+#define WF_LWTBL_SKIP_TX_SHIFT 31
+// DW6
+#define WF_LWTBL_CBRN_DW 6
+#define WF_LWTBL_CBRN_ADDR 24
+#define WF_LWTBL_CBRN_MASK \
+ 0x00000007 // 2- 0
+#define WF_LWTBL_CBRN_SHIFT 0
+#define WF_LWTBL_DBNSS_EN_DW 6
+#define WF_LWTBL_DBNSS_EN_ADDR 24
+#define WF_LWTBL_DBNSS_EN_MASK \
+ 0x00000008 // 3- 3
+#define WF_LWTBL_DBNSS_EN_SHIFT 3
+#define WF_LWTBL_BAF_EN_DW 6
+#define WF_LWTBL_BAF_EN_ADDR 24
+#define WF_LWTBL_BAF_EN_MASK \
+ 0x00000010 // 4- 4
+#define WF_LWTBL_BAF_EN_SHIFT 4
+#define WF_LWTBL_RDGBA_DW 6
+#define WF_LWTBL_RDGBA_ADDR 24
+#define WF_LWTBL_RDGBA_MASK \
+ 0x00000020 // 5- 5
+#define WF_LWTBL_RDGBA_SHIFT 5
+#define WF_LWTBL_R_DW 6
+#define WF_LWTBL_R_ADDR 24
+#define WF_LWTBL_R_MASK \
+ 0x00000040 // 6- 6
+#define WF_LWTBL_R_SHIFT 6
+#define WF_LWTBL_SPE_IDX_DW 6
+#define WF_LWTBL_SPE_IDX_ADDR 24
+#define WF_LWTBL_SPE_IDX_MASK \
+ 0x00000f80 // 11- 7
+#define WF_LWTBL_SPE_IDX_SHIFT 7
+#define WF_LWTBL_G2_DW 6
+#define WF_LWTBL_G2_ADDR 24
+#define WF_LWTBL_G2_MASK \
+ 0x00001000 // 12-12
+#define WF_LWTBL_G2_SHIFT 12
+#define WF_LWTBL_G4_DW 6
+#define WF_LWTBL_G4_ADDR 24
+#define WF_LWTBL_G4_MASK \
+ 0x00002000 // 13-13
+#define WF_LWTBL_G4_SHIFT 13
+#define WF_LWTBL_G8_DW 6
+#define WF_LWTBL_G8_ADDR 24
+#define WF_LWTBL_G8_MASK \
+ 0x00004000 // 14-14
+#define WF_LWTBL_G8_SHIFT 14
+#define WF_LWTBL_G16_DW 6
+#define WF_LWTBL_G16_ADDR 24
+#define WF_LWTBL_G16_MASK \
+ 0x00008000 // 15-15
+#define WF_LWTBL_G16_SHIFT 15
+#define WF_LWTBL_G2_LTF_DW 6
+#define WF_LWTBL_G2_LTF_ADDR 24
+#define WF_LWTBL_G2_LTF_MASK \
+ 0x00030000 // 17-16
+#define WF_LWTBL_G2_LTF_SHIFT 16
+#define WF_LWTBL_G4_LTF_DW 6
+#define WF_LWTBL_G4_LTF_ADDR 24
+#define WF_LWTBL_G4_LTF_MASK \
+ 0x000c0000 // 19-18
+#define WF_LWTBL_G4_LTF_SHIFT 18
+#define WF_LWTBL_G8_LTF_DW 6
+#define WF_LWTBL_G8_LTF_ADDR 24
+#define WF_LWTBL_G8_LTF_MASK \
+ 0x00300000 // 21-20
+#define WF_LWTBL_G8_LTF_SHIFT 20
+#define WF_LWTBL_G16_LTF_DW 6
+#define WF_LWTBL_G16_LTF_ADDR 24
+#define WF_LWTBL_G16_LTF_MASK \
+ 0x00c00000 // 23-22
+#define WF_LWTBL_G16_LTF_SHIFT 22
+#define WF_LWTBL_G2_HE_DW 6
+#define WF_LWTBL_G2_HE_ADDR 24
+#define WF_LWTBL_G2_HE_MASK \
+ 0x03000000 // 25-24
+#define WF_LWTBL_G2_HE_SHIFT 24
+#define WF_LWTBL_G4_HE_DW 6
+#define WF_LWTBL_G4_HE_ADDR 24
+#define WF_LWTBL_G4_HE_MASK \
+ 0x0c000000 // 27-26
+#define WF_LWTBL_G4_HE_SHIFT 26
+#define WF_LWTBL_G8_HE_DW 6
+#define WF_LWTBL_G8_HE_ADDR 24
+#define WF_LWTBL_G8_HE_MASK \
+ 0x30000000 // 29-28
+#define WF_LWTBL_G8_HE_SHIFT 28
+#define WF_LWTBL_G16_HE_DW 6
+#define WF_LWTBL_G16_HE_ADDR 24
+#define WF_LWTBL_G16_HE_MASK \
+ 0xc0000000 // 31-30
+#define WF_LWTBL_G16_HE_SHIFT 30
+// DW7
+#define WF_LWTBL_BA_WIN_SIZE0_DW 7
+#define WF_LWTBL_BA_WIN_SIZE0_ADDR 28
+#define WF_LWTBL_BA_WIN_SIZE0_MASK \
+ 0x0000000f // 3- 0
+#define WF_LWTBL_BA_WIN_SIZE0_SHIFT 0
+#define WF_LWTBL_BA_WIN_SIZE1_DW 7
+#define WF_LWTBL_BA_WIN_SIZE1_ADDR 28
+#define WF_LWTBL_BA_WIN_SIZE1_MASK \
+ 0x000000f0 // 7- 4
+#define WF_LWTBL_BA_WIN_SIZE1_SHIFT 4
+#define WF_LWTBL_BA_WIN_SIZE2_DW 7
+#define WF_LWTBL_BA_WIN_SIZE2_ADDR 28
+#define WF_LWTBL_BA_WIN_SIZE2_MASK \
+ 0x00000f00 // 11- 8
+#define WF_LWTBL_BA_WIN_SIZE2_SHIFT 8
+#define WF_LWTBL_BA_WIN_SIZE3_DW 7
+#define WF_LWTBL_BA_WIN_SIZE3_ADDR 28
+#define WF_LWTBL_BA_WIN_SIZE3_MASK \
+ 0x0000f000 // 15-12
+#define WF_LWTBL_BA_WIN_SIZE3_SHIFT 12
+#define WF_LWTBL_BA_WIN_SIZE4_DW 7
+#define WF_LWTBL_BA_WIN_SIZE4_ADDR 28
+#define WF_LWTBL_BA_WIN_SIZE4_MASK \
+ 0x000f0000 // 19-16
+#define WF_LWTBL_BA_WIN_SIZE4_SHIFT 16
+#define WF_LWTBL_BA_WIN_SIZE5_DW 7
+#define WF_LWTBL_BA_WIN_SIZE5_ADDR 28
+#define WF_LWTBL_BA_WIN_SIZE5_MASK \
+ 0x00f00000 // 23-20
+#define WF_LWTBL_BA_WIN_SIZE5_SHIFT 20
+#define WF_LWTBL_BA_WIN_SIZE6_DW 7
+#define WF_LWTBL_BA_WIN_SIZE6_ADDR 28
+#define WF_LWTBL_BA_WIN_SIZE6_MASK \
+ 0x0f000000 // 27-24
+#define WF_LWTBL_BA_WIN_SIZE6_SHIFT 24
+#define WF_LWTBL_BA_WIN_SIZE7_DW 7
+#define WF_LWTBL_BA_WIN_SIZE7_ADDR 28
+#define WF_LWTBL_BA_WIN_SIZE7_MASK \
+ 0xf0000000 // 31-28
+#define WF_LWTBL_BA_WIN_SIZE7_SHIFT 28
+// DW8
+#define WF_LWTBL_AC0_RTS_FAIL_CNT_DW 8
+#define WF_LWTBL_AC0_RTS_FAIL_CNT_ADDR 32
+#define WF_LWTBL_AC0_RTS_FAIL_CNT_MASK \
+ 0x0000001f // 4- 0
+#define WF_LWTBL_AC0_RTS_FAIL_CNT_SHIFT 0
+#define WF_LWTBL_AC1_RTS_FAIL_CNT_DW 8
+#define WF_LWTBL_AC1_RTS_FAIL_CNT_ADDR 32
+#define WF_LWTBL_AC1_RTS_FAIL_CNT_MASK \
+ 0x000003e0 // 9- 5
+#define WF_LWTBL_AC1_RTS_FAIL_CNT_SHIFT 5
+#define WF_LWTBL_AC2_RTS_FAIL_CNT_DW 8
+#define WF_LWTBL_AC2_RTS_FAIL_CNT_ADDR 32
+#define WF_LWTBL_AC2_RTS_FAIL_CNT_MASK \
+ 0x00007c00 // 14-10
+#define WF_LWTBL_AC2_RTS_FAIL_CNT_SHIFT 10
+#define WF_LWTBL_AC3_RTS_FAIL_CNT_DW 8
+#define WF_LWTBL_AC3_RTS_FAIL_CNT_ADDR 32
+#define WF_LWTBL_AC3_RTS_FAIL_CNT_MASK \
+ 0x000f8000 // 19-15
+#define WF_LWTBL_AC3_RTS_FAIL_CNT_SHIFT 15
+#define WF_LWTBL_PARTIAL_AID_DW 8
+#define WF_LWTBL_PARTIAL_AID_ADDR 32
+#define WF_LWTBL_PARTIAL_AID_MASK \
+ 0x1ff00000 // 28-20
+#define WF_LWTBL_PARTIAL_AID_SHIFT 20
+#define WF_LWTBL_CHK_PER_DW 8
+#define WF_LWTBL_CHK_PER_ADDR 32
+#define WF_LWTBL_CHK_PER_MASK \
+ 0x80000000 // 31-31
+#define WF_LWTBL_CHK_PER_SHIFT 31
+// DW9
+#define WF_LWTBL_RX_AVG_MPDU_SIZE_DW 9
+#define WF_LWTBL_RX_AVG_MPDU_SIZE_ADDR 36
+#define WF_LWTBL_RX_AVG_MPDU_SIZE_MASK \
+ 0x00003fff // 13- 0
+#define WF_LWTBL_RX_AVG_MPDU_SIZE_SHIFT 0
+#define WF_LWTBL_PRITX_SW_MODE_DW 9
+#define WF_LWTBL_PRITX_SW_MODE_ADDR 36
+#define WF_LWTBL_PRITX_SW_MODE_MASK \
+ 0x00008000 // 15-15
+#define WF_LWTBL_PRITX_SW_MODE_SHIFT 15
+#define WF_LWTBL_PRITX_ERSU_DW 9
+#define WF_LWTBL_PRITX_ERSU_ADDR 36
+#define WF_LWTBL_PRITX_ERSU_MASK \
+ 0x00010000 // 16-16
+#define WF_LWTBL_PRITX_ERSU_SHIFT 16
+#define WF_LWTBL_PRITX_PLR_DW 9
+#define WF_LWTBL_PRITX_PLR_ADDR 36
+#define WF_LWTBL_PRITX_PLR_MASK \
+ 0x00020000 // 17-17
+#define WF_LWTBL_PRITX_PLR_SHIFT 17
+#define WF_LWTBL_PRITX_DCM_DW 9
+#define WF_LWTBL_PRITX_DCM_ADDR 36
+#define WF_LWTBL_PRITX_DCM_MASK \
+ 0x00040000 // 18-18
+#define WF_LWTBL_PRITX_DCM_SHIFT 18
+#define WF_LWTBL_PRITX_ER106T_DW 9
+#define WF_LWTBL_PRITX_ER106T_ADDR 36
+#define WF_LWTBL_PRITX_ER106T_MASK \
+ 0x00080000 // 19-19
+#define WF_LWTBL_PRITX_ER106T_SHIFT 19
+#define WF_LWTBL_FCAP_DW 9
+#define WF_LWTBL_FCAP_ADDR 36
+#define WF_LWTBL_FCAP_MASK \
+ 0x00700000 // 22-20
+#define WF_LWTBL_FCAP_SHIFT 20
+#define WF_LWTBL_MPDU_FAIL_CNT_DW 9
+#define WF_LWTBL_MPDU_FAIL_CNT_ADDR 36
+#define WF_LWTBL_MPDU_FAIL_CNT_MASK \
+ 0x03800000 // 25-23
+#define WF_LWTBL_MPDU_FAIL_CNT_SHIFT 23
+#define WF_LWTBL_MPDU_OK_CNT_DW 9
+#define WF_LWTBL_MPDU_OK_CNT_ADDR 36
+#define WF_LWTBL_MPDU_OK_CNT_MASK \
+ 0x1c000000 // 28-26
+#define WF_LWTBL_MPDU_OK_CNT_SHIFT 26
+#define WF_LWTBL_RATE_IDX_DW 9
+#define WF_LWTBL_RATE_IDX_ADDR 36
+#define WF_LWTBL_RATE_IDX_MASK \
+ 0xe0000000 // 31-29
+#define WF_LWTBL_RATE_IDX_SHIFT 29
+// DW10
+#define WF_LWTBL_RATE1_DW 10
+#define WF_LWTBL_RATE1_ADDR 40
+#define WF_LWTBL_RATE1_MASK \
+ 0x00007fff // 14- 0
+#define WF_LWTBL_RATE1_SHIFT 0
+#define WF_LWTBL_RATE2_DW 10
+#define WF_LWTBL_RATE2_ADDR 40
+#define WF_LWTBL_RATE2_MASK \
+ 0x7fff0000 // 30-16
+#define WF_LWTBL_RATE2_SHIFT 16
+// DW11
+#define WF_LWTBL_RATE3_DW 11
+#define WF_LWTBL_RATE3_ADDR 44
+#define WF_LWTBL_RATE3_MASK \
+ 0x00007fff // 14- 0
+#define WF_LWTBL_RATE3_SHIFT 0
+#define WF_LWTBL_RATE4_DW 11
+#define WF_LWTBL_RATE4_ADDR 44
+#define WF_LWTBL_RATE4_MASK \
+ 0x7fff0000 // 30-16
+#define WF_LWTBL_RATE4_SHIFT 16
+// DW12
+#define WF_LWTBL_RATE5_DW 12
+#define WF_LWTBL_RATE5_ADDR 48
+#define WF_LWTBL_RATE5_MASK \
+ 0x00007fff // 14- 0
+#define WF_LWTBL_RATE5_SHIFT 0
+#define WF_LWTBL_RATE6_DW 12
+#define WF_LWTBL_RATE6_ADDR 48
+#define WF_LWTBL_RATE6_MASK \
+ 0x7fff0000 // 30-16
+#define WF_LWTBL_RATE6_SHIFT 16
+// DW13
+#define WF_LWTBL_RATE7_DW 13
+#define WF_LWTBL_RATE7_ADDR 52
+#define WF_LWTBL_RATE7_MASK \
+ 0x00007fff // 14- 0
+#define WF_LWTBL_RATE7_SHIFT 0
+#define WF_LWTBL_RATE8_DW 13
+#define WF_LWTBL_RATE8_ADDR 52
+#define WF_LWTBL_RATE8_MASK \
+ 0x7fff0000 // 30-16
+#define WF_LWTBL_RATE8_SHIFT 16
+// DW14
+#define WF_LWTBL_RATE1_TX_CNT_DW 14
+#define WF_LWTBL_RATE1_TX_CNT_ADDR 56
+#define WF_LWTBL_RATE1_TX_CNT_MASK \
+ 0x0000ffff // 15- 0
+#define WF_LWTBL_RATE1_TX_CNT_SHIFT 0
+#define WF_LWTBL_CIPHER_SUIT_IGTK_DW 14
+#define WF_LWTBL_CIPHER_SUIT_IGTK_ADDR 56
+#define WF_LWTBL_CIPHER_SUIT_IGTK_MASK \
+ 0x00003000 // 13-12
+#define WF_LWTBL_CIPHER_SUIT_IGTK_SHIFT 12
+#define WF_LWTBL_CIPHER_SUIT_BIGTK_DW 14
+#define WF_LWTBL_CIPHER_SUIT_BIGTK_ADDR 56
+#define WF_LWTBL_CIPHER_SUIT_BIGTK_MASK \
+ 0x0000c000 // 15-14
+#define WF_LWTBL_CIPHER_SUIT_BIGTK_SHIFT 14
+#define WF_LWTBL_RATE1_FAIL_CNT_DW 14
+#define WF_LWTBL_RATE1_FAIL_CNT_ADDR 56
+#define WF_LWTBL_RATE1_FAIL_CNT_MASK \
+ 0xffff0000 // 31-16
+#define WF_LWTBL_RATE1_FAIL_CNT_SHIFT 16
+// DW15
+#define WF_LWTBL_RATE2_OK_CNT_DW 15
+#define WF_LWTBL_RATE2_OK_CNT_ADDR 60
+#define WF_LWTBL_RATE2_OK_CNT_MASK \
+ 0x0000ffff // 15- 0
+#define WF_LWTBL_RATE2_OK_CNT_SHIFT 0
+#define WF_LWTBL_RATE3_OK_CNT_DW 15
+#define WF_LWTBL_RATE3_OK_CNT_ADDR 60
+#define WF_LWTBL_RATE3_OK_CNT_MASK \
+ 0xffff0000 // 31-16
+#define WF_LWTBL_RATE3_OK_CNT_SHIFT 16
+// DW16
+#define WF_LWTBL_CURRENT_BW_TX_CNT_DW 16
+#define WF_LWTBL_CURRENT_BW_TX_CNT_ADDR 64
+#define WF_LWTBL_CURRENT_BW_TX_CNT_MASK \
+ 0x0000ffff // 15- 0
+#define WF_LWTBL_CURRENT_BW_TX_CNT_SHIFT 0
+#define WF_LWTBL_CURRENT_BW_FAIL_CNT_DW 16
+#define WF_LWTBL_CURRENT_BW_FAIL_CNT_ADDR 64
+#define WF_LWTBL_CURRENT_BW_FAIL_CNT_MASK \
+ 0xffff0000 // 31-16
+#define WF_LWTBL_CURRENT_BW_FAIL_CNT_SHIFT 16
+// DW17
+#define WF_LWTBL_OTHER_BW_TX_CNT_DW 17
+#define WF_LWTBL_OTHER_BW_TX_CNT_ADDR 68
+#define WF_LWTBL_OTHER_BW_TX_CNT_MASK \
+ 0x0000ffff // 15- 0
+#define WF_LWTBL_OTHER_BW_TX_CNT_SHIFT 0
+#define WF_LWTBL_OTHER_BW_FAIL_CNT_DW 17
+#define WF_LWTBL_OTHER_BW_FAIL_CNT_ADDR 68
+#define WF_LWTBL_OTHER_BW_FAIL_CNT_MASK \
+ 0xffff0000 // 31-16
+#define WF_LWTBL_OTHER_BW_FAIL_CNT_SHIFT 16
+// DW18
+#define WF_LWTBL_RTS_OK_CNT_DW 18
+#define WF_LWTBL_RTS_OK_CNT_ADDR 72
+#define WF_LWTBL_RTS_OK_CNT_MASK \
+ 0x0000ffff // 15- 0
+#define WF_LWTBL_RTS_OK_CNT_SHIFT 0
+#define WF_LWTBL_RTS_FAIL_CNT_DW 18
+#define WF_LWTBL_RTS_FAIL_CNT_ADDR 72
+#define WF_LWTBL_RTS_FAIL_CNT_MASK \
+ 0xffff0000 // 31-16
+#define WF_LWTBL_RTS_FAIL_CNT_SHIFT 16
+// DW19
+#define WF_LWTBL_DATA_RETRY_CNT_DW 19
+#define WF_LWTBL_DATA_RETRY_CNT_ADDR 76
+#define WF_LWTBL_DATA_RETRY_CNT_MASK \
+ 0x0000ffff // 15- 0
+#define WF_LWTBL_DATA_RETRY_CNT_SHIFT 0
+#define WF_LWTBL_MGNT_RETRY_CNT_DW 19
+#define WF_LWTBL_MGNT_RETRY_CNT_ADDR 76
+#define WF_LWTBL_MGNT_RETRY_CNT_MASK \
+ 0xffff0000 // 31-16
+#define WF_LWTBL_MGNT_RETRY_CNT_SHIFT 16
+// DW20
+#define WF_LWTBL_AC0_CTT_CDT_CRB_DW 20
+#define WF_LWTBL_AC0_CTT_CDT_CRB_ADDR 80
+#define WF_LWTBL_AC0_CTT_CDT_CRB_MASK \
+ 0xffffffff // 31- 0
+#define WF_LWTBL_AC0_CTT_CDT_CRB_SHIFT 0
+// DW21
+// DO NOT process repeat field(adm[0])
+// DW22
+#define WF_LWTBL_AC1_CTT_CDT_CRB_DW 22
+#define WF_LWTBL_AC1_CTT_CDT_CRB_ADDR 88
+#define WF_LWTBL_AC1_CTT_CDT_CRB_MASK \
+ 0xffffffff // 31- 0
+#define WF_LWTBL_AC1_CTT_CDT_CRB_SHIFT 0
+// DW23
+// DO NOT process repeat field(adm[1])
+// DW24
+#define WF_LWTBL_AC2_CTT_CDT_CRB_DW 24
+#define WF_LWTBL_AC2_CTT_CDT_CRB_ADDR 96
+#define WF_LWTBL_AC2_CTT_CDT_CRB_MASK \
+ 0xffffffff // 31- 0
+#define WF_LWTBL_AC2_CTT_CDT_CRB_SHIFT 0
+// DW25
+// DO NOT process repeat field(adm[2])
+// DW26
+#define WF_LWTBL_AC3_CTT_CDT_CRB_DW 26
+#define WF_LWTBL_AC3_CTT_CDT_CRB_ADDR 104
+#define WF_LWTBL_AC3_CTT_CDT_CRB_MASK \
+ 0xffffffff // 31- 0
+#define WF_LWTBL_AC3_CTT_CDT_CRB_SHIFT 0
+// DW27
+// DO NOT process repeat field(adm[3])
+// DW28
+#define WF_LWTBL_RELATED_IDX0_DW 28
+#define WF_LWTBL_RELATED_IDX0_ADDR 112
+#define WF_LWTBL_RELATED_IDX0_MASK \
+ 0x00000fff // 11- 0
+#define WF_LWTBL_RELATED_IDX0_SHIFT 0
+#define WF_LWTBL_RELATED_BAND0_DW 28
+#define WF_LWTBL_RELATED_BAND0_ADDR 112
+#define WF_LWTBL_RELATED_BAND0_MASK \
+ 0x00003000 // 13-12
+#define WF_LWTBL_RELATED_BAND0_SHIFT 12
+#define WF_LWTBL_PRIMARY_MLD_BAND_DW 28
+#define WF_LWTBL_PRIMARY_MLD_BAND_ADDR 112
+#define WF_LWTBL_PRIMARY_MLD_BAND_MASK \
+ 0x0000c000 // 15-14
+#define WF_LWTBL_PRIMARY_MLD_BAND_SHIFT 14
+#define WF_LWTBL_RELATED_IDX1_DW 28
+#define WF_LWTBL_RELATED_IDX1_ADDR 112
+#define WF_LWTBL_RELATED_IDX1_MASK \
+ 0x0fff0000 // 27-16
+#define WF_LWTBL_RELATED_IDX1_SHIFT 16
+#define WF_LWTBL_RELATED_BAND1_DW 28
+#define WF_LWTBL_RELATED_BAND1_ADDR 112
+#define WF_LWTBL_RELATED_BAND1_MASK \
+ 0x30000000 // 29-28
+#define WF_LWTBL_RELATED_BAND1_SHIFT 28
+#define WF_LWTBL_SECONDARY_MLD_BAND_DW 28
+#define WF_LWTBL_SECONDARY_MLD_BAND_ADDR 112
+#define WF_LWTBL_SECONDARY_MLD_BAND_MASK \
+ 0xc0000000 // 31-30
+#define WF_LWTBL_SECONDARY_MLD_BAND_SHIFT 30
+// DW29
+#define WF_LWTBL_DISPATCH_POLICY0_DW 29
+#define WF_LWTBL_DISPATCH_POLICY0_ADDR 116
+#define WF_LWTBL_DISPATCH_POLICY0_MASK \
+ 0x00000003 // 1- 0
+#define WF_LWTBL_DISPATCH_POLICY0_SHIFT 0
+#define WF_LWTBL_DISPATCH_POLICY1_DW 29
+#define WF_LWTBL_DISPATCH_POLICY1_ADDR 116
+#define WF_LWTBL_DISPATCH_POLICY1_MASK \
+ 0x0000000c // 3- 2
+#define WF_LWTBL_DISPATCH_POLICY1_SHIFT 2
+#define WF_LWTBL_DISPATCH_POLICY2_DW 29
+#define WF_LWTBL_DISPATCH_POLICY2_ADDR 116
+#define WF_LWTBL_DISPATCH_POLICY2_MASK \
+ 0x00000030 // 5- 4
+#define WF_LWTBL_DISPATCH_POLICY2_SHIFT 4
+#define WF_LWTBL_DISPATCH_POLICY3_DW 29
+#define WF_LWTBL_DISPATCH_POLICY3_ADDR 116
+#define WF_LWTBL_DISPATCH_POLICY3_MASK \
+ 0x000000c0 // 7- 6
+#define WF_LWTBL_DISPATCH_POLICY3_SHIFT 6
+#define WF_LWTBL_DISPATCH_POLICY4_DW 29
+#define WF_LWTBL_DISPATCH_POLICY4_ADDR 116
+#define WF_LWTBL_DISPATCH_POLICY4_MASK \
+ 0x00000300 // 9- 8
+#define WF_LWTBL_DISPATCH_POLICY4_SHIFT 8
+#define WF_LWTBL_DISPATCH_POLICY5_DW 29
+#define WF_LWTBL_DISPATCH_POLICY5_ADDR 116
+#define WF_LWTBL_DISPATCH_POLICY5_MASK \
+ 0x00000c00 // 11-10
+#define WF_LWTBL_DISPATCH_POLICY5_SHIFT 10
+#define WF_LWTBL_DISPATCH_POLICY6_DW 29
+#define WF_LWTBL_DISPATCH_POLICY6_ADDR 116
+#define WF_LWTBL_DISPATCH_POLICY6_MASK \
+ 0x00003000 // 13-12
+#define WF_LWTBL_DISPATCH_POLICY6_SHIFT 12
+#define WF_LWTBL_DISPATCH_POLICY7_DW 29
+#define WF_LWTBL_DISPATCH_POLICY7_ADDR 116
+#define WF_LWTBL_DISPATCH_POLICY7_MASK \
+ 0x0000c000 // 15-14
+#define WF_LWTBL_DISPATCH_POLICY7_SHIFT 14
+#define WF_LWTBL_OWN_MLD_ID_DW 29
+#define WF_LWTBL_OWN_MLD_ID_ADDR 116
+#define WF_LWTBL_OWN_MLD_ID_MASK \
+ 0x003f0000 // 21-16
+#define WF_LWTBL_OWN_MLD_ID_SHIFT 16
+#define WF_LWTBL_EMLSR0_DW 29
+#define WF_LWTBL_EMLSR0_ADDR 116
+#define WF_LWTBL_EMLSR0_MASK \
+ 0x00400000 // 22-22
+#define WF_LWTBL_EMLSR0_SHIFT 22
+#define WF_LWTBL_EMLMR0_DW 29
+#define WF_LWTBL_EMLMR0_ADDR 116
+#define WF_LWTBL_EMLMR0_MASK \
+ 0x00800000 // 23-23
+#define WF_LWTBL_EMLMR0_SHIFT 23
+#define WF_LWTBL_EMLSR1_DW 29
+#define WF_LWTBL_EMLSR1_ADDR 116
+#define WF_LWTBL_EMLSR1_MASK \
+ 0x01000000 // 24-24
+#define WF_LWTBL_EMLSR1_SHIFT 24
+#define WF_LWTBL_EMLMR1_DW 29
+#define WF_LWTBL_EMLMR1_ADDR 116
+#define WF_LWTBL_EMLMR1_MASK \
+ 0x02000000 // 25-25
+#define WF_LWTBL_EMLMR1_SHIFT 25
+#define WF_LWTBL_EMLSR2_DW 29
+#define WF_LWTBL_EMLSR2_ADDR 116
+#define WF_LWTBL_EMLSR2_MASK \
+ 0x04000000 // 26-26
+#define WF_LWTBL_EMLSR2_SHIFT 26
+#define WF_LWTBL_EMLMR2_DW 29
+#define WF_LWTBL_EMLMR2_ADDR 116
+#define WF_LWTBL_EMLMR2_MASK \
+ 0x08000000 // 27-27
+#define WF_LWTBL_EMLMR2_SHIFT 27
+#define WF_LWTBL_STR_BITMAP_DW 29
+#define WF_LWTBL_STR_BITMAP_ADDR 116
+#define WF_LWTBL_STR_BITMAP_MASK \
+ 0xe0000000 // 31-29
+#define WF_LWTBL_STR_BITMAP_SHIFT 29
+// DW30
+#define WF_LWTBL_DISPATCH_ORDER_DW 30
+#define WF_LWTBL_DISPATCH_ORDER_ADDR 120
+#define WF_LWTBL_DISPATCH_ORDER_MASK \
+ 0x0000007f // 6- 0
+#define WF_LWTBL_DISPATCH_ORDER_SHIFT 0
+#define WF_LWTBL_DISPATCH_RATIO_DW 30
+#define WF_LWTBL_DISPATCH_RATIO_ADDR 120
+#define WF_LWTBL_DISPATCH_RATIO_MASK \
+ 0x00003f80 // 13- 7
+#define WF_LWTBL_DISPATCH_RATIO_SHIFT 7
+#define WF_LWTBL_LINK_MGF_DW 30
+#define WF_LWTBL_LINK_MGF_ADDR 120
+#define WF_LWTBL_LINK_MGF_MASK \
+ 0xffff0000 // 31-16
+#define WF_LWTBL_LINK_MGF_SHIFT 16
+// DW31
+#define WF_LWTBL_NEGOTIATED_WINSIZE0_DW 31
+#define WF_LWTBL_NEGOTIATED_WINSIZE0_ADDR 124
+#define WF_LWTBL_NEGOTIATED_WINSIZE0_MASK \
+ 0x00000007 // 2- 0
+#define WF_LWTBL_NEGOTIATED_WINSIZE0_SHIFT 0
+#define WF_LWTBL_NEGOTIATED_WINSIZE1_DW 31
+#define WF_LWTBL_NEGOTIATED_WINSIZE1_ADDR 124
+#define WF_LWTBL_NEGOTIATED_WINSIZE1_MASK \
+ 0x00000038 // 5- 3
+#define WF_LWTBL_NEGOTIATED_WINSIZE1_SHIFT 3
+#define WF_LWTBL_NEGOTIATED_WINSIZE2_DW 31
+#define WF_LWTBL_NEGOTIATED_WINSIZE2_ADDR 124
+#define WF_LWTBL_NEGOTIATED_WINSIZE2_MASK \
+ 0x000001c0 // 8- 6
+#define WF_LWTBL_NEGOTIATED_WINSIZE2_SHIFT 6
+#define WF_LWTBL_NEGOTIATED_WINSIZE3_DW 31
+#define WF_LWTBL_NEGOTIATED_WINSIZE3_ADDR 124
+#define WF_LWTBL_NEGOTIATED_WINSIZE3_MASK \
+ 0x00000e00 // 11- 9
+#define WF_LWTBL_NEGOTIATED_WINSIZE3_SHIFT 9
+#define WF_LWTBL_NEGOTIATED_WINSIZE4_DW 31
+#define WF_LWTBL_NEGOTIATED_WINSIZE4_ADDR 124
+#define WF_LWTBL_NEGOTIATED_WINSIZE4_MASK \
+ 0x00007000 // 14-12
+#define WF_LWTBL_NEGOTIATED_WINSIZE4_SHIFT 12
+#define WF_LWTBL_NEGOTIATED_WINSIZE5_DW 31
+#define WF_LWTBL_NEGOTIATED_WINSIZE5_ADDR 124
+#define WF_LWTBL_NEGOTIATED_WINSIZE5_MASK \
+ 0x00038000 // 17-15
+#define WF_LWTBL_NEGOTIATED_WINSIZE5_SHIFT 15
+#define WF_LWTBL_NEGOTIATED_WINSIZE6_DW 31
+#define WF_LWTBL_NEGOTIATED_WINSIZE6_ADDR 124
+#define WF_LWTBL_NEGOTIATED_WINSIZE6_MASK \
+ 0x001c0000 // 20-18
+#define WF_LWTBL_NEGOTIATED_WINSIZE6_SHIFT 18
+#define WF_LWTBL_NEGOTIATED_WINSIZE7_DW 31
+#define WF_LWTBL_NEGOTIATED_WINSIZE7_ADDR 124
+#define WF_LWTBL_NEGOTIATED_WINSIZE7_MASK \
+ 0x00e00000 // 23-21
+#define WF_LWTBL_NEGOTIATED_WINSIZE7_SHIFT 21
+#define WF_LWTBL_CASCAD_DW 31
+#define WF_LWTBL_CASCAD_ADDR 124
+#define WF_LWTBL_CASCAD_MASK \
+ 0x02000000 // 25-25
+#define WF_LWTBL_CASCAD_SHIFT 25
+#define WF_LWTBL_ALL_ACK_DW 31
+#define WF_LWTBL_ALL_ACK_ADDR 124
+#define WF_LWTBL_ALL_ACK_MASK \
+ 0x04000000 // 26-26
+#define WF_LWTBL_ALL_ACK_SHIFT 26
+#define WF_LWTBL_MPDU_SIZE_DW 31
+#define WF_LWTBL_MPDU_SIZE_ADDR 124
+#define WF_LWTBL_MPDU_SIZE_MASK \
+ 0x18000000 // 28-27
+#define WF_LWTBL_MPDU_SIZE_SHIFT 27
+#define WF_LWTBL_BA_MODE_DW 31
+#define WF_LWTBL_BA_MODE_ADDR 124
+#define WF_LWTBL_BA_MODE_MASK \
+ 0xe0000000 // 31-29
+#define WF_LWTBL_BA_MODE_SHIFT 29
+// DW32
+#define WF_LWTBL_OM_INFO_DW 32
+#define WF_LWTBL_OM_INFO_ADDR 128
+#define WF_LWTBL_OM_INFO_MASK \
+ 0x00000fff // 11- 0
+#define WF_LWTBL_OM_INFO_SHIFT 0
+#define WF_LWTBL_RXD_DUP_FOR_OM_CHG_DW 32
+#define WF_LWTBL_RXD_DUP_FOR_OM_CHG_ADDR 128
+#define WF_LWTBL_RXD_DUP_FOR_OM_CHG_MASK \
+ 0x00001000 // 12-12
+#define WF_LWTBL_RXD_DUP_FOR_OM_CHG_SHIFT 12
+#define WF_LWTBL_RXD_DUP_WHITE_LIST_DW 32
+#define WF_LWTBL_RXD_DUP_WHITE_LIST_ADDR 128
+#define WF_LWTBL_RXD_DUP_WHITE_LIST_MASK \
+ 0x01ffe000 // 24-13
+#define WF_LWTBL_RXD_DUP_WHITE_LIST_SHIFT 13
+#define WF_LWTBL_RXD_DUP_MODE_DW 32
+#define WF_LWTBL_RXD_DUP_MODE_ADDR 128
+#define WF_LWTBL_RXD_DUP_MODE_MASK \
+ 0x06000000 // 26-25
+#define WF_LWTBL_RXD_DUP_MODE_SHIFT 25
+#define WF_LWTBL_DROP_DW 32
+#define WF_LWTBL_DROP_ADDR 128
+#define WF_LWTBL_DROP_MASK \
+ 0x40000000 // 30-30
+#define WF_LWTBL_DROP_SHIFT 30
+#define WF_LWTBL_ACK_EN_DW 32
+#define WF_LWTBL_ACK_EN_ADDR 128
+#define WF_LWTBL_ACK_EN_MASK \
+ 0x80000000 // 31-31
+#define WF_LWTBL_ACK_EN_SHIFT 31
+// DW33
+#define WF_LWTBL_USER_RSSI_DW 33
+#define WF_LWTBL_USER_RSSI_ADDR 132
+#define WF_LWTBL_USER_RSSI_MASK \
+ 0x000001ff // 8- 0
+#define WF_LWTBL_USER_RSSI_SHIFT 0
+#define WF_LWTBL_USER_SNR_DW 33
+#define WF_LWTBL_USER_SNR_ADDR 132
+#define WF_LWTBL_USER_SNR_MASK \
+ 0x00007e00 // 14- 9
+#define WF_LWTBL_USER_SNR_SHIFT 9
+#define WF_LWTBL_RAPID_REACTION_RATE_DW 33
+#define WF_LWTBL_RAPID_REACTION_RATE_ADDR 132
+#define WF_LWTBL_RAPID_REACTION_RATE_MASK \
+ 0x0fff0000 // 27-16
+#define WF_LWTBL_RAPID_REACTION_RATE_SHIFT 16
+#define WF_LWTBL_HT_AMSDU_DW 33
+#define WF_LWTBL_HT_AMSDU_ADDR 132
+#define WF_LWTBL_HT_AMSDU_MASK \
+ 0x40000000 // 30-30
+#define WF_LWTBL_HT_AMSDU_SHIFT 30
+#define WF_LWTBL_AMSDU_CROSS_LG_DW 33
+#define WF_LWTBL_AMSDU_CROSS_LG_ADDR 132
+#define WF_LWTBL_AMSDU_CROSS_LG_MASK \
+ 0x80000000 // 31-31
+#define WF_LWTBL_AMSDU_CROSS_LG_SHIFT 31
+// DW34
+#define WF_LWTBL_RESP_RCPI0_DW 34
+#define WF_LWTBL_RESP_RCPI0_ADDR 136
+#define WF_LWTBL_RESP_RCPI0_MASK \
+ 0x000000ff // 7- 0
+#define WF_LWTBL_RESP_RCPI0_SHIFT 0
+#define WF_LWTBL_RESP_RCPI1_DW 34
+#define WF_LWTBL_RESP_RCPI1_ADDR 136
+#define WF_LWTBL_RESP_RCPI1_MASK \
+ 0x0000ff00 // 15- 8
+#define WF_LWTBL_RESP_RCPI1_SHIFT 8
+#define WF_LWTBL_RESP_RCPI2_DW 34
+#define WF_LWTBL_RESP_RCPI2_ADDR 136
+#define WF_LWTBL_RESP_RCPI2_MASK \
+ 0x00ff0000 // 23-16
+#define WF_LWTBL_RESP_RCPI2_SHIFT 16
+#define WF_LWTBL_RESP_RCPI3_DW 34
+#define WF_LWTBL_RESP_RCPI3_ADDR 136
+#define WF_LWTBL_RESP_RCPI3_MASK \
+ 0xff000000 // 31-24
+#define WF_LWTBL_RESP_RCPI3_SHIFT 24
+// DW35
+#define WF_LWTBL_SNR_RX0_DW 35
+#define WF_LWTBL_SNR_RX0_ADDR 140
+#define WF_LWTBL_SNR_RX0_MASK \
+ 0x0000003f // 5- 0
+#define WF_LWTBL_SNR_RX0_SHIFT 0
+#define WF_LWTBL_SNR_RX1_DW 35
+#define WF_LWTBL_SNR_RX1_ADDR 140
+#define WF_LWTBL_SNR_RX1_MASK \
+ 0x00000fc0 // 11- 6
+#define WF_LWTBL_SNR_RX1_SHIFT 6
+#define WF_LWTBL_SNR_RX2_DW 35
+#define WF_LWTBL_SNR_RX2_ADDR 140
+#define WF_LWTBL_SNR_RX2_MASK \
+ 0x0003f000 // 17-12
+#define WF_LWTBL_SNR_RX2_SHIFT 12
+#define WF_LWTBL_SNR_RX3_DW 35
+#define WF_LWTBL_SNR_RX3_ADDR 140
+#define WF_LWTBL_SNR_RX3_MASK \
+ 0x00fc0000 // 23-18
+#define WF_LWTBL_SNR_RX3_SHIFT 18
+
+/* WTBL Group - Packet Number */
+/* DW 2 */
+#define WTBL_PN0_MASK BITS(0, 7)
+#define WTBL_PN0_OFFSET 0
+#define WTBL_PN1_MASK BITS(8, 15)
+#define WTBL_PN1_OFFSET 8
+#define WTBL_PN2_MASK BITS(16, 23)
+#define WTBL_PN2_OFFSET 16
+#define WTBL_PN3_MASK BITS(24, 31)
+#define WTBL_PN3_OFFSET 24
+
+/* DW 3 */
+#define WTBL_PN4_MASK BITS(0, 7)
+#define WTBL_PN4_OFFSET 0
+#define WTBL_PN5_MASK BITS(8, 15)
+#define WTBL_PN5_OFFSET 8
+
+/* DW 4 */
+#define WTBL_BIPN0_MASK BITS(0, 7)
+#define WTBL_BIPN0_OFFSET 0
+#define WTBL_BIPN1_MASK BITS(8, 15)
+#define WTBL_BIPN1_OFFSET 8
+#define WTBL_BIPN2_MASK BITS(16, 23)
+#define WTBL_BIPN2_OFFSET 16
+#define WTBL_BIPN3_MASK BITS(24, 31)
+#define WTBL_BIPN3_OFFSET 24
+
+/* DW 5 */
+#define WTBL_BIPN4_MASK BITS(0, 7)
+#define WTBL_BIPN4_OFFSET 0
+#define WTBL_BIPN5_MASK BITS(8, 15)
+#define WTBL_BIPN5_OFFSET 8
+
+/* UWTBL DW 6 */
+#define WTBL_AMSDU_LEN_MASK BITS(0, 5)
+#define WTBL_AMSDU_LEN_OFFSET 0
+#define WTBL_AMSDU_NUM_MASK BITS(6, 10)
+#define WTBL_AMSDU_NUM_OFFSET 6
+#define WTBL_AMSDU_EN_MASK BIT(11)
+#define WTBL_AMSDU_EN_OFFSET 11
+
+/* LWTBL Rate field */
+#define WTBL_RATE_TX_RATE_MASK BITS(0, 5)
+#define WTBL_RATE_TX_RATE_OFFSET 0
+#define WTBL_RATE_TX_MODE_MASK BITS(6, 9)
+#define WTBL_RATE_TX_MODE_OFFSET 6
+#define WTBL_RATE_NSTS_MASK BITS(10, 13)
+#define WTBL_RATE_NSTS_OFFSET 10
+#define WTBL_RATE_STBC_MASK BIT(14)
+#define WTBL_RATE_STBC_OFFSET 14
+
+/***** WTBL(LMAC) DW Offset *****/
+/* LMAC WTBL Group - Peer Unique Information */
+#define WTBL_GROUP_PEER_INFO_DW_0 0
+#define WTBL_GROUP_PEER_INFO_DW_1 1
+
+/* WTBL Group - TxRx Capability/Information */
+#define WTBL_GROUP_TRX_CAP_DW_2 2
+#define WTBL_GROUP_TRX_CAP_DW_3 3
+#define WTBL_GROUP_TRX_CAP_DW_4 4
+#define WTBL_GROUP_TRX_CAP_DW_5 5
+#define WTBL_GROUP_TRX_CAP_DW_6 6
+#define WTBL_GROUP_TRX_CAP_DW_7 7
+#define WTBL_GROUP_TRX_CAP_DW_8 8
+#define WTBL_GROUP_TRX_CAP_DW_9 9
+
+/* WTBL Group - Auto Rate Table*/
+#define WTBL_GROUP_AUTO_RATE_1_2 10
+#define WTBL_GROUP_AUTO_RATE_3_4 11
+#define WTBL_GROUP_AUTO_RATE_5_6 12
+#define WTBL_GROUP_AUTO_RATE_7_8 13
+
+/* WTBL Group - Tx Counter */
+#define WTBL_GROUP_TX_CNT_LINE_1 14
+#define WTBL_GROUP_TX_CNT_LINE_2 15
+#define WTBL_GROUP_TX_CNT_LINE_3 16
+#define WTBL_GROUP_TX_CNT_LINE_4 17
+#define WTBL_GROUP_TX_CNT_LINE_5 18
+#define WTBL_GROUP_TX_CNT_LINE_6 19
+
+/* WTBL Group - Admission Control Counter */
+#define WTBL_GROUP_ADM_CNT_LINE_1 20
+#define WTBL_GROUP_ADM_CNT_LINE_2 21
+#define WTBL_GROUP_ADM_CNT_LINE_3 22
+#define WTBL_GROUP_ADM_CNT_LINE_4 23
+#define WTBL_GROUP_ADM_CNT_LINE_5 24
+#define WTBL_GROUP_ADM_CNT_LINE_6 25
+#define WTBL_GROUP_ADM_CNT_LINE_7 26
+#define WTBL_GROUP_ADM_CNT_LINE_8 27
+
+/* WTBL Group -MLO Info */
+#define WTBL_GROUP_MLO_INFO_LINE_1 28
+#define WTBL_GROUP_MLO_INFO_LINE_2 29
+#define WTBL_GROUP_MLO_INFO_LINE_3 30
+
+/* WTBL Group -RESP Info */
+#define WTBL_GROUP_RESP_INFO_DW_31 31
+
+/* WTBL Group -RX DUP Info */
+#define WTBL_GROUP_RX_DUP_INFO_DW_32 32
+
+/* WTBL Group - Rx Statistics Counter */
+#define WTBL_GROUP_RX_STAT_CNT_LINE_1 33
+#define WTBL_GROUP_RX_STAT_CNT_LINE_2 34
+#define WTBL_GROUP_RX_STAT_CNT_LINE_3 35
+
+/* UWTBL Group - HW AMSDU */
+#define UWTBL_HW_AMSDU_DW WF_UWTBL_AMSDU_CFG_DW
+
+/* LWTBL DW 4 */
+#define WTBL_DIS_RHTR WF_LWTBL_DIS_RHTR_MASK
+
+/* UWTBL DW 5 */
+#define WTBL_KEY_LINK_DW_KEY_LOC0_MASK BITS(0, 10)
+#define WTBL_PSM WF_LWTBL_PSM_MASK
+
+/* Need to sync with FW define */
+#define INVALID_KEY_ENTRY WTBL_KEY_LINK_DW_KEY_LOC0_MASK
+
+// RATE
+#define WTBL_RATE_TX_RATE_MASK BITS(0, 5)
+#define WTBL_RATE_TX_RATE_OFFSET 0
+#define WTBL_RATE_TX_MODE_MASK BITS(6, 9)
+#define WTBL_RATE_TX_MODE_OFFSET 6
+#define WTBL_RATE_NSTS_MASK BITS(10, 13)
+#define WTBL_RATE_NSTS_OFFSET 10
+#define WTBL_RATE_STBC_MASK BIT(14)
+#define WTBL_RATE_STBC_OFFSET 14
+#endif
+
+#endif
diff --git a/mt7996/mtk_debugfs.c b/mt7996/mtk_debugfs.c
new file mode 100644
index 00000000..f04c300f
--- /dev/null
+++ b/mt7996/mtk_debugfs.c
@@ -0,0 +1,2353 @@
+// SPDX-License-Identifier: ISC
+/*
+ * Copyright (C) 2023 MediaTek Inc.
+ */
+#include "mt7996.h"
+#include "../mt76.h"
+#include "mcu.h"
+#include "mac.h"
+#include "eeprom.h"
+#include "mtk_debug.h"
+#include "mtk_mcu.h"
+#include "coredump.h"
+
+#ifdef CONFIG_MTK_DEBUG
+
+/* AGG INFO */
+static int
+mt7996_agginfo_read_per_band(struct seq_file *s, int band_idx)
+{
+ struct mt7996_dev *dev = dev_get_drvdata(s->private);
+ u64 total_burst, total_ampdu, ampdu_cnt[16];
+ u32 value, idx, row_idx, col_idx, start_range, agg_rang_sel[16], burst_cnt[16], band_offset = 0;
+ u8 readFW = 0, partial_str[16] = {}, full_str[64] = {};
+
+ switch (band_idx) {
+ case 0:
+ band_offset = 0;
+ break;
+ case 1:
+ band_offset = BN1_WF_AGG_TOP_BASE - BN0_WF_AGG_TOP_BASE;
+ break;
+ case 2:
+ band_offset = IP1_BN0_WF_AGG_TOP_BASE - BN0_WF_AGG_TOP_BASE;
+ break;
+ default:
+ return 0;
+ }
+
+ seq_printf(s, "Band %d AGG Status\n", band_idx);
+ seq_printf(s, "===============================\n");
+ value = mt76_rr(dev, BN0_WF_AGG_TOP_AALCR0_ADDR + band_offset);
+ seq_printf(s, "AC00 Agg limit = %d\t", (value & BN0_WF_AGG_TOP_AALCR0_AC00_AGG_LIMIT_MASK) >> BN0_WF_AGG_TOP_AALCR0_AC00_AGG_LIMIT_SHFT);
+ seq_printf(s, "AC01 Agg limit = %d\t", (value & BN0_WF_AGG_TOP_AALCR0_AC01_AGG_LIMIT_MASK) >> BN0_WF_AGG_TOP_AALCR0_AC01_AGG_LIMIT_SHFT);
+ value = mt76_rr(dev, BN0_WF_AGG_TOP_AALCR1_ADDR + band_offset);
+ seq_printf(s, "AC02 Agg limit = %d\t", (value & BN0_WF_AGG_TOP_AALCR1_AC02_AGG_LIMIT_MASK) >> BN0_WF_AGG_TOP_AALCR1_AC02_AGG_LIMIT_SHFT);
+ seq_printf(s, "AC03 Agg limit = %d\t", (value & BN0_WF_AGG_TOP_AALCR1_AC03_AGG_LIMIT_MASK) >> BN0_WF_AGG_TOP_AALCR1_AC03_AGG_LIMIT_SHFT);
+ value = mt76_rr(dev, BN0_WF_AGG_TOP_AALCR2_ADDR + band_offset);
+ seq_printf(s, "AC10 Agg limit = %d\t", (value & BN0_WF_AGG_TOP_AALCR2_AC10_AGG_LIMIT_MASK) >> BN0_WF_AGG_TOP_AALCR2_AC10_AGG_LIMIT_SHFT);
+ seq_printf(s, "AC11 Agg limit = %d\t", (value & BN0_WF_AGG_TOP_AALCR2_AC11_AGG_LIMIT_MASK) >> BN0_WF_AGG_TOP_AALCR2_AC11_AGG_LIMIT_SHFT);
+ value = mt76_rr(dev, BN0_WF_AGG_TOP_AALCR3_ADDR + band_offset);
+ seq_printf(s, "AC12 Agg limit = %d\t", (value & BN0_WF_AGG_TOP_AALCR3_AC12_AGG_LIMIT_MASK) >> BN0_WF_AGG_TOP_AALCR3_AC12_AGG_LIMIT_SHFT);
+ seq_printf(s, "AC13 Agg limit = %d\t", (value & BN0_WF_AGG_TOP_AALCR3_AC13_AGG_LIMIT_MASK) >> BN0_WF_AGG_TOP_AALCR3_AC13_AGG_LIMIT_SHFT);
+ value = mt76_rr(dev, BN0_WF_AGG_TOP_AALCR4_ADDR + band_offset);
+ seq_printf(s, "AC20 Agg limit = %d\t", (value & BN0_WF_AGG_TOP_AALCR4_AC20_AGG_LIMIT_MASK) >> BN0_WF_AGG_TOP_AALCR4_AC20_AGG_LIMIT_SHFT);
+ seq_printf(s, "AC21 Agg limit = %d\t", (value & BN0_WF_AGG_TOP_AALCR4_AC21_AGG_LIMIT_MASK) >> BN0_WF_AGG_TOP_AALCR4_AC21_AGG_LIMIT_SHFT);
+ value = mt76_rr(dev, BN0_WF_AGG_TOP_AALCR5_ADDR + band_offset);
+ seq_printf(s, "AC22 Agg limit = %d\t", (value & BN0_WF_AGG_TOP_AALCR5_AC22_AGG_LIMIT_MASK) >> BN0_WF_AGG_TOP_AALCR5_AC22_AGG_LIMIT_SHFT);
+ seq_printf(s, "AC23 Agg limit = %d\t", (value & BN0_WF_AGG_TOP_AALCR5_AC23_AGG_LIMIT_MASK) >> BN0_WF_AGG_TOP_AALCR5_AC23_AGG_LIMIT_SHFT);
+ value = mt76_rr(dev, BN0_WF_AGG_TOP_AALCR6_ADDR + band_offset);
+ seq_printf(s, "AC30 Agg limit = %d\t", (value & BN0_WF_AGG_TOP_AALCR6_AC30_AGG_LIMIT_MASK) >> BN0_WF_AGG_TOP_AALCR6_AC30_AGG_LIMIT_SHFT);
+ seq_printf(s, "AC31 Agg limit = %d\t", (value & BN0_WF_AGG_TOP_AALCR6_AC31_AGG_LIMIT_MASK) >> BN0_WF_AGG_TOP_AALCR6_AC31_AGG_LIMIT_SHFT);
+ value = mt76_rr(dev, BN0_WF_AGG_TOP_AALCR7_ADDR + band_offset);
+ seq_printf(s, "AC32 Agg limit = %d\t", (value & BN0_WF_AGG_TOP_AALCR7_AC32_AGG_LIMIT_MASK) >> BN0_WF_AGG_TOP_AALCR7_AC32_AGG_LIMIT_SHFT);
+ seq_printf(s, "AC33 Agg limit = %d\t", (value & BN0_WF_AGG_TOP_AALCR7_AC33_AGG_LIMIT_MASK) >> BN0_WF_AGG_TOP_AALCR7_AC33_AGG_LIMIT_SHFT);
+
+ switch (band_idx) {
+ case 0:
+ band_offset = 0;
+ break;
+ case 1:
+ band_offset = BN1_WF_MIB_TOP_BASE - BN0_WF_MIB_TOP_BASE;
+ break;
+ case 2:
+ band_offset = IP1_BN0_WF_MIB_TOP_BASE - BN0_WF_MIB_TOP_BASE;
+ break;
+ default:
+ return 0;
+ }
+
+ seq_printf(s, "===AMPDU Related Counters===\n");
+
+ if (readFW) {
+ /* BELLWETHER TODO: Wait MIB counter API implement complete */
+ } else {
+ value = mt76_rr(dev, BN0_WF_MIB_TOP_TRARC0_ADDR + band_offset);
+ agg_rang_sel[0] = (value & BN0_WF_MIB_TOP_TRARC0_AGG_RANG_SEL_0_MASK) >> BN0_WF_MIB_TOP_TRARC0_AGG_RANG_SEL_0_SHFT;
+ agg_rang_sel[1] = (value & BN0_WF_MIB_TOP_TRARC0_AGG_RANG_SEL_1_MASK) >> BN0_WF_MIB_TOP_TRARC0_AGG_RANG_SEL_1_SHFT;
+ value = mt76_rr(dev, BN0_WF_MIB_TOP_TRARC1_ADDR + band_offset);
+ agg_rang_sel[2] = (value & BN0_WF_MIB_TOP_TRARC1_AGG_RANG_SEL_2_MASK) >> BN0_WF_MIB_TOP_TRARC1_AGG_RANG_SEL_2_SHFT;
+ agg_rang_sel[3] = (value & BN0_WF_MIB_TOP_TRARC1_AGG_RANG_SEL_3_MASK) >> BN0_WF_MIB_TOP_TRARC1_AGG_RANG_SEL_3_SHFT;
+ value = mt76_rr(dev, BN0_WF_MIB_TOP_TRARC2_ADDR + band_offset);
+ agg_rang_sel[4] = (value & BN0_WF_MIB_TOP_TRARC2_AGG_RANG_SEL_4_MASK) >> BN0_WF_MIB_TOP_TRARC2_AGG_RANG_SEL_4_SHFT;
+ agg_rang_sel[5] = (value & BN0_WF_MIB_TOP_TRARC2_AGG_RANG_SEL_5_MASK) >> BN0_WF_MIB_TOP_TRARC2_AGG_RANG_SEL_5_SHFT;
+ value = mt76_rr(dev, BN0_WF_MIB_TOP_TRARC3_ADDR + band_offset);
+ agg_rang_sel[6] = (value & BN0_WF_MIB_TOP_TRARC3_AGG_RANG_SEL_6_MASK) >> BN0_WF_MIB_TOP_TRARC3_AGG_RANG_SEL_6_SHFT;
+ agg_rang_sel[7] = (value & BN0_WF_MIB_TOP_TRARC3_AGG_RANG_SEL_7_MASK) >> BN0_WF_MIB_TOP_TRARC3_AGG_RANG_SEL_7_SHFT;
+ value = mt76_rr(dev, BN0_WF_MIB_TOP_TRARC4_ADDR + band_offset);
+ agg_rang_sel[8] = (value & BN0_WF_MIB_TOP_TRARC4_AGG_RANG_SEL_8_MASK) >> BN0_WF_MIB_TOP_TRARC4_AGG_RANG_SEL_8_SHFT;
+ agg_rang_sel[9] = (value & BN0_WF_MIB_TOP_TRARC4_AGG_RANG_SEL_9_MASK) >> BN0_WF_MIB_TOP_TRARC4_AGG_RANG_SEL_9_SHFT;
+ value = mt76_rr(dev, BN0_WF_MIB_TOP_TRARC5_ADDR + band_offset);
+ agg_rang_sel[10] = (value & BN0_WF_MIB_TOP_TRARC5_AGG_RANG_SEL_10_MASK) >> BN0_WF_MIB_TOP_TRARC5_AGG_RANG_SEL_10_SHFT;
+ agg_rang_sel[11] = (value & BN0_WF_MIB_TOP_TRARC5_AGG_RANG_SEL_11_MASK) >> BN0_WF_MIB_TOP_TRARC5_AGG_RANG_SEL_11_SHFT;
+ value = mt76_rr(dev, BN0_WF_MIB_TOP_TRARC6_ADDR + band_offset);
+ agg_rang_sel[12] = (value & BN0_WF_MIB_TOP_TRARC6_AGG_RANG_SEL_12_MASK) >> BN0_WF_MIB_TOP_TRARC6_AGG_RANG_SEL_12_SHFT;
+ agg_rang_sel[13] = (value & BN0_WF_MIB_TOP_TRARC6_AGG_RANG_SEL_13_MASK) >> BN0_WF_MIB_TOP_TRARC6_AGG_RANG_SEL_13_SHFT;
+ value = mt76_rr(dev, BN0_WF_MIB_TOP_TRARC7_ADDR + band_offset);
+ agg_rang_sel[14] = (value & BN0_WF_MIB_TOP_TRARC7_AGG_RANG_SEL_14_MASK) >> BN0_WF_MIB_TOP_TRARC7_AGG_RANG_SEL_14_SHFT;
+
+ burst_cnt[0] = mt76_rr(dev, BN0_WF_MIB_TOP_TRDR0_ADDR + band_offset);
+ burst_cnt[1] = mt76_rr(dev, BN0_WF_MIB_TOP_TRDR1_ADDR + band_offset);
+ burst_cnt[2] = mt76_rr(dev, BN0_WF_MIB_TOP_TRDR2_ADDR + band_offset);
+ burst_cnt[3] = mt76_rr(dev, BN0_WF_MIB_TOP_TRDR3_ADDR + band_offset);
+ burst_cnt[4] = mt76_rr(dev, BN0_WF_MIB_TOP_TRDR4_ADDR + band_offset);
+ burst_cnt[5] = mt76_rr(dev, BN0_WF_MIB_TOP_TRDR5_ADDR + band_offset);
+ burst_cnt[6] = mt76_rr(dev, BN0_WF_MIB_TOP_TRDR6_ADDR + band_offset);
+ burst_cnt[7] = mt76_rr(dev, BN0_WF_MIB_TOP_TRDR7_ADDR + band_offset);
+ burst_cnt[8] = mt76_rr(dev, BN0_WF_MIB_TOP_TRDR8_ADDR + band_offset);
+ burst_cnt[9] = mt76_rr(dev, BN0_WF_MIB_TOP_TRDR9_ADDR + band_offset);
+ burst_cnt[10] = mt76_rr(dev, BN0_WF_MIB_TOP_TRDR10_ADDR + band_offset);
+ burst_cnt[11] = mt76_rr(dev, BN0_WF_MIB_TOP_TRDR11_ADDR + band_offset);
+ burst_cnt[12] = mt76_rr(dev, BN0_WF_MIB_TOP_TRDR12_ADDR + band_offset);
+ burst_cnt[13] = mt76_rr(dev, BN0_WF_MIB_TOP_TRDR13_ADDR + band_offset);
+ burst_cnt[14] = mt76_rr(dev, BN0_WF_MIB_TOP_TRDR14_ADDR + band_offset);
+ burst_cnt[15] = mt76_rr(dev, BN0_WF_MIB_TOP_TRDR15_ADDR + band_offset);
+ }
+
+ start_range = 1;
+ total_burst = 0;
+ total_ampdu = 0;
+ agg_rang_sel[15] = 1023;
+
+ /* Need to add 1 after read from AGG_RANG_SEL CR */
+ for (idx = 0; idx < 16; idx++) {
+ agg_rang_sel[idx]++;
+ total_burst += burst_cnt[idx];
+
+ if (start_range == agg_rang_sel[idx])
+ ampdu_cnt[idx] = (u64) start_range * burst_cnt[idx];
+ else
+ ampdu_cnt[idx] = (u64) ((start_range + agg_rang_sel[idx]) >> 1) * burst_cnt[idx];
+
+ start_range = agg_rang_sel[idx] + 1;
+ total_ampdu += ampdu_cnt[idx];
+ }
+
+ start_range = 1;
+ sprintf(full_str, "%13s ", "Tx Agg Range:");
+
+ for (row_idx = 0; row_idx < 4; row_idx++) {
+ for (col_idx = 0; col_idx < 4; col_idx++, idx++) {
+ idx = 4 * row_idx + col_idx;
+
+ if (start_range == agg_rang_sel[idx])
+ sprintf(partial_str, "%d", agg_rang_sel[idx]);
+ else
+ sprintf(partial_str, "%d~%d", start_range, agg_rang_sel[idx]);
+
+ start_range = agg_rang_sel[idx] + 1;
+ sprintf(full_str + strlen(full_str), "%-11s ", partial_str);
+ }
+
+ idx = 4 * row_idx;
+
+ seq_printf(s, "%s\n", full_str);
+ seq_printf(s, "%13s 0x%-9x 0x%-9x 0x%-9x 0x%-9x\n",
+ row_idx ? "" : "Burst count:",
+ burst_cnt[idx], burst_cnt[idx + 1],
+ burst_cnt[idx + 2], burst_cnt[idx + 3]);
+
+ if (total_burst != 0) {
+ if (row_idx == 0)
+ sprintf(full_str, "%13s ",
+ "Burst ratio:");
+ else
+ sprintf(full_str, "%13s ", "");
+
+ for (col_idx = 0; col_idx < 4; col_idx++) {
+ u64 count = (u64) burst_cnt[idx + col_idx] * 100;
+
+ sprintf(partial_str, "(%llu%%)",
+ div64_u64(count, total_burst));
+ sprintf(full_str + strlen(full_str),
+ "%-11s ", partial_str);
+ }
+
+ seq_printf(s, "%s\n", full_str);
+
+ if (row_idx == 0)
+ sprintf(full_str, "%13s ",
+ "MDPU ratio:");
+ else
+ sprintf(full_str, "%13s ", "");
+
+ for (col_idx = 0; col_idx < 4; col_idx++) {
+ u64 count = ampdu_cnt[idx + col_idx] * 100;
+
+ sprintf(partial_str, "(%llu%%)",
+ div64_u64(count, total_ampdu));
+ sprintf(full_str + strlen(full_str),
+ "%-11s ", partial_str);
+ }
+
+ seq_printf(s, "%s\n", full_str);
+ }
+
+ sprintf(full_str, "%13s ", "");
+ }
+
+ return 0;
+}
+
+static int mt7996_agginfo_read_band0(struct seq_file *s, void *data)
+{
+ mt7996_agginfo_read_per_band(s, MT_BAND0);
+ return 0;
+}
+
+static int mt7996_agginfo_read_band1(struct seq_file *s, void *data)
+{
+ mt7996_agginfo_read_per_band(s, MT_BAND1);
+ return 0;
+}
+
+static int mt7996_agginfo_read_band2(struct seq_file *s, void *data)
+{
+ mt7996_agginfo_read_per_band(s, MT_BAND2);
+ return 0;
+}
+
+/* AMSDU INFO */
+static int mt7996_amsdu_result_read(struct seq_file *s, void *data)
+{
+#define HW_MSDU_CNT_ADDR 0xf400
+#define HW_MSDU_NUM_MAX 33
+ struct mt7996_dev *dev = dev_get_drvdata(s->private);
+ u32 ple_stat[HW_MSDU_NUM_MAX] = {0}, total_amsdu = 0;
+ u8 i;
+
+ for (i = 0; i < HW_MSDU_NUM_MAX; i++)
+ ple_stat[i] = mt76_rr(dev, HW_MSDU_CNT_ADDR + i * 0x04);
+
+ seq_printf(s, "TXD counter status of MSDU:\n");
+
+ for (i = 0; i < HW_MSDU_NUM_MAX; i++)
+ total_amsdu += ple_stat[i];
+
+ for (i = 0; i < HW_MSDU_NUM_MAX; i++) {
+ seq_printf(s, "AMSDU pack count of %d MSDU in TXD: 0x%x ", i, ple_stat[i]);
+ if (total_amsdu != 0)
+ seq_printf(s, "(%d%%)\n", ple_stat[i] * 100 / total_amsdu);
+ else
+ seq_printf(s, "\n");
+ }
+
+ return 0;
+}
+
+/* DBG MODLE */
+static int
+mt7996_fw_debug_module_set(void *data, u64 module)
+{
+ struct mt7996_dev *dev = data;
+
+ dev->dbg.fw_dbg_module = module;
+ return 0;
+}
+
+static int
+mt7996_fw_debug_module_get(void *data, u64 *module)
+{
+ struct mt7996_dev *dev = data;
+
+ *module = dev->dbg.fw_dbg_module;
+ return 0;
+}
+
+DEFINE_DEBUGFS_ATTRIBUTE(fops_fw_debug_module, mt7996_fw_debug_module_get,
+ mt7996_fw_debug_module_set, "%lld\n");
+
+static int
+mt7996_fw_debug_level_set(void *data, u64 level)
+{
+ struct mt7996_dev *dev = data;
+
+ dev->dbg.fw_dbg_lv = level;
+ mt7996_mcu_fw_dbg_ctrl(dev, dev->dbg.fw_dbg_module, dev->dbg.fw_dbg_lv);
+ return 0;
+}
+
+static int
+mt7996_fw_debug_level_get(void *data, u64 *level)
+{
+ struct mt7996_dev *dev = data;
+
+ *level = dev->dbg.fw_dbg_lv;
+ return 0;
+}
+
+DEFINE_DEBUGFS_ATTRIBUTE(fops_fw_debug_level, mt7996_fw_debug_level_get,
+ mt7996_fw_debug_level_set, "%lld\n");
+
+/* usage: echo 0x[arg3][arg2][arg1] > fw_wa_set */
+static int
+mt7996_wa_set(void *data, u64 val)
+{
+ struct mt7996_dev *dev = data;
+ u32 arg1, arg2, arg3;
+
+ arg1 = FIELD_GET(GENMASK_ULL(7, 0), val);
+ arg2 = FIELD_GET(GENMASK_ULL(15, 8), val);
+ arg3 = FIELD_GET(GENMASK_ULL(23, 16), val);
+
+ return mt7996_mcu_wa_cmd(dev, MCU_WA_PARAM_CMD(SET),
+ arg1, arg2, arg3);
+}
+
+DEFINE_DEBUGFS_ATTRIBUTE(fops_wa_set, NULL, mt7996_wa_set,
+ "0x%llx\n");
+
+/* usage: echo 0x[arg3][arg2][arg1] > fw_wa_query */
+static int
+mt7996_wa_query(void *data, u64 val)
+{
+ struct mt7996_dev *dev = data;
+ u32 arg1, arg2, arg3;
+
+ arg1 = FIELD_GET(GENMASK_ULL(7, 0), val);
+ arg2 = FIELD_GET(GENMASK_ULL(15, 8), val);
+ arg3 = FIELD_GET(GENMASK_ULL(23, 16), val);
+
+ return mt7996_mcu_wa_cmd(dev, MCU_WA_PARAM_CMD(QUERY),
+ arg1, arg2, arg3);
+ return 0;
+}
+
+DEFINE_DEBUGFS_ATTRIBUTE(fops_wa_query, NULL, mt7996_wa_query,
+ "0x%llx\n");
+
+static int mt7996_dump_version(struct seq_file *s, void *data)
+{
+ struct mt7996_dev *dev = dev_get_drvdata(s->private);
+ seq_printf(s, "Version: 3.3.10.0\n");
+
+ if (!test_bit(MT76_STATE_MCU_RUNNING, &dev->mphy.state))
+ return 0;
+
+ seq_printf(s, "Rom Patch Build Time: %.16s\n", dev->patch_build_date);
+ seq_printf(s, "WM Patch Build Time: %.15s, Mode: %s\n",
+ dev->ram_build_date[MT7996_RAM_TYPE_WM],
+ dev->testmode_enable ? "Testmode" : "Normal mode");
+ seq_printf(s, "WA Patch Build Time: %.15s\n",
+ dev->ram_build_date[MT7996_RAM_TYPE_WA]);
+ seq_printf(s, "DSP Patch Build Time: %.15s\n",
+ dev->ram_build_date[MT7996_RAM_TYPE_DSP]);
+ return 0;
+}
+
+/* fw wm call trace info dump */
+void mt7996_show_lp_history(struct seq_file *s, u32 type)
+{
+ struct mt7996_dev *dev = dev_get_drvdata(s->private);
+ struct mt7996_crash_data *crash_data;
+ struct mt7996_coredump *dump;
+ u64 now = 0;
+ int i = 0;
+ u8 fw_type = !!type;
+
+ mutex_lock(&dev->dump_mutex);
+
+ crash_data = mt7996_coredump_new(dev, fw_type);
+ if (!crash_data) {
+ mutex_unlock(&dev->dump_mutex);
+ seq_printf(s, "the coredump is disable!\n");
+ return;
+ }
+ mutex_unlock(&dev->dump_mutex);
+
+ dump = mt7996_coredump_build(dev, fw_type, false);
+ if (!dump) {
+ seq_printf(s, "no call stack data found!\n");
+ return;
+ }
+
+ seq_printf(s, "\x1b[32m%s log output\x1b[0m\n", dump->fw_type);
+ seq_printf(s, "\x1b[32mfw status: %s\n", dump->fw_state);
+ mt7996_dump_version(s, NULL);
+ /* PC log */
+ now = jiffies;
+ for (i = 0; i < 10; i++)
+ seq_printf(s, "\tCurrent PC=%x\n", dump->pc_cur[i]);
+
+ seq_printf(s, "PC log contorl=0x%x(T=%llu)(latest PC index = 0x%x)\n",
+ dump->pc_dbg_ctrl, now, dump->pc_cur_idx);
+ for (i = 0; i < 32; i++)
+ seq_printf(s, "\tPC log(%d)=0x%08x\n", i, dump->pc_stack[i]);
+
+ /* LR log */
+ now = jiffies;
+ seq_printf(s, "\nLR log contorl=0x%x(T=%llu)(latest LR index = 0x%x)\n",
+ dump->lr_dbg_ctrl, now, dump->lr_cur_idx);
+ for (i = 0; i < 32; i++)
+ seq_printf(s, "\tLR log(%d)=0x%08x\n", i, dump->lr_stack[i]);
+
+ vfree(dump);