| From 7af1b6dfec852291fa4d2a21cba350a46a1b7c49 Mon Sep 17 00:00:00 2001 |
| From: Peter Chiu <chui-hao.chiu@mediatek.com> |
| Date: Wed, 4 May 2022 20:39:07 +0800 |
| Subject: [PATCH] mt76: mt7915: add debugfs for ser show and ser trigger |
| |
| --- |
| mt7915/debugfs.c | 103 ++++++++++++++++++++++++++++++++++++++++++++++- |
| mt7915/mcu.c | 5 +-- |
| mt7915/mmio.c | 3 ++ |
| mt7915/regs.h | 18 ++++++++- |
| 4 files changed, 122 insertions(+), 7 deletions(-) |
| |
| diff --git a/mt7915/debugfs.c b/mt7915/debugfs.c |
| index e8e26ac1..61e1c126 100644 |
| --- a/mt7915/debugfs.c |
| +++ b/mt7915/debugfs.c |
| @@ -47,7 +47,8 @@ mt7915_implicit_txbf_get(void *data, u64 *val) |
| DEFINE_DEBUGFS_ATTRIBUTE(fops_implicit_txbf, mt7915_implicit_txbf_get, |
| mt7915_implicit_txbf_set, "%lld\n"); |
| |
| -/* test knob of system layer 1/2 error recovery */ |
| +/* test knob of system layer 0.5/1/2 error recovery */ |
| +/* |
| static int mt7915_ser_trigger_set(void *data, u64 val) |
| { |
| enum { |
| @@ -74,9 +75,107 @@ static int mt7915_ser_trigger_set(void *data, u64 val) |
| return ret; |
| } |
| |
| +*/ |
| +static int mt7915_ser_trigger_set(void *data, u64 val) |
| +{ |
| +#define SER_SET GENMASK(3, 0) |
| +#define SER_BAND GENMASK(7, 4) |
| +#define SER_ACTION GENMASK(11, 8) |
| + enum { |
| + SER_ACTION_SET = 1, |
| + SER_ACTION_SET_MASK = 2, |
| + SER_ACTION_TRIGGER = 3, |
| + }; |
| + |
| + struct mt7915_dev *dev = data; |
| + u8 ser_action, ser_band, ser_set, set_val; |
| + |
| + ser_action = FIELD_GET(SER_ACTION, val); |
| + ser_set = set_val = FIELD_GET(SER_SET, val); |
| + ser_band = (ser_action == SER_ACTION_TRIGGER) ? |
| + FIELD_GET(SER_BAND, val) : 0; |
| + |
| + if (ser_band > 1) |
| + return -1; |
| + |
| + switch (ser_action) { |
| + case SER_ACTION_SET: |
| + /* |
| + * 0x100: disable system error recovery function. |
| + * 0x101: enable system error recovery function. |
| + */ |
| + ser_set = !!set_val; |
| + break; |
| + case SER_ACTION_SET_MASK: |
| + /* |
| + * 0x200: enable system error tracking. |
| + * 0x201: enable system error L1 recover. |
| + * 0x202: enable system error L2 recover. |
| + * 0x203: enable system error L3 rx abort. |
| + * 0x204: enable system error L3 tx abort. |
| + * 0x205: enable system error L3 tx disable. |
| + * 0x206: enable system error L3 bf recover. |
| + * 0x207: enable system error all recover. |
| + */ |
| + ser_set = set_val > 7 ? 0x7f : BIT(set_val); |
| + break; |
| + case SER_ACTION_TRIGGER: |
| + /* |
| + * 0x301/0x311: trigger L1 recover for band0/band1. |
| + * 0x302/0x312: trigger L2 recover for band0/band1. |
| + * 0x303/0x313: trigger L3 rx abort for band0/band1. |
| + * 0x304/0x314: trigger L3 tx abort for band0/band1. |
| + * 0x305/0x315: trigger L3 tx disable for band0/band1. |
| + * 0x306/0x316: trigger L3 bf recover for band0/band1. |
| + */ |
| + if (ser_set > 6) |
| + return -1; |
| + break; |
| + default: |
| + return -1; |
| + } |
| + |
| + return mt7915_mcu_set_ser(dev, ser_action, ser_set, ser_band); |
| +} |
| + |
| DEFINE_DEBUGFS_ATTRIBUTE(fops_ser_trigger, NULL, |
| mt7915_ser_trigger_set, "%lld\n"); |
| |
| +static int |
| +mt7915_ser_stats_show(struct seq_file *s, void *data) |
| +{ |
| +#define SER_ACTION_QUERY 0 |
| + struct mt7915_dev *dev = dev_get_drvdata(s->private); |
| + int ret = 0; |
| + |
| + /* get more info from firmware */ |
| + ret = mt7915_mcu_set_ser(dev, SER_ACTION_QUERY, 0, 0); |
| + msleep(100); |
| + |
| + seq_printf(s, "::E R , SER_STATUS = 0x%08X\n", |
| + mt76_rr(dev, MT_SWDEF_SER_STATUS)); |
| + seq_printf(s, "::E R , SER_PLE_ERR = 0x%08X\n", |
| + mt76_rr(dev, MT_SWDEF_PLE_STATUS)); |
| + seq_printf(s, "::E R , SER_PLE_ERR_1 = 0x%08X\n", |
| + mt76_rr(dev, MT_SWDEF_PLE1_STATUS)); |
| + seq_printf(s, "::E R , SER_PLE_ERR_AMSDU = 0x%08X\n", |
| + mt76_rr(dev, MT_SWDEF_PLE_AMSDU_STATUS)); |
| + seq_printf(s, "::E R , SER_PSE_ERR = 0x%08X\n", |
| + mt76_rr(dev, MT_SWDEF_PSE_STATUS)); |
| + seq_printf(s, "::E R , SER_PSE_ERR_1 = 0x%08X\n", |
| + mt76_rr(dev, MT_SWDEF_PSE1_STATUS)); |
| + seq_printf(s, "::E R , SER_LMAC_WISR6_B0 = 0x%08X\n", |
| + mt76_rr(dev, MT_SWDEF_LAMC_WISR6_BN0_STATUS)); |
| + seq_printf(s, "::E R , SER_LMAC_WISR6_B1 = 0x%08X\n", |
| + mt76_rr(dev, MT_SWDEF_LAMC_WISR6_BN1_STATUS)); |
| + seq_printf(s, "::E R , SER_LMAC_WISR7_B0 = 0x%08X\n", |
| + mt76_rr(dev, MT_SWDEF_LAMC_WISR7_BN0_STATUS)); |
| + seq_printf(s, "::E R , SER_LMAC_WISR7_B1 = 0x%08X\n", |
| + mt76_rr(dev, MT_SWDEF_LAMC_WISR7_BN1_STATUS)); |
| + |
| + return ret; |
| +} |
| + |
| static int |
| mt7915_radar_trigger(void *data, u64 val) |
| { |
| @@ -943,6 +1042,8 @@ int mt7915_init_debugfs(struct mt7915_phy *phy) |
| debugfs_create_file("xmit-queues", 0400, dir, phy, |
| &mt7915_xmit_queues_fops); |
| debugfs_create_file("tx_stats", 0400, dir, phy, &mt7915_tx_stats_fops); |
| + debugfs_create_devm_seqfile(dev->mt76.dev, "ser_show", dir, |
| + mt7915_ser_stats_show); |
| debugfs_create_file("fw_debug_wm", 0600, dir, dev, &fops_fw_debug_wm); |
| debugfs_create_file("fw_debug_wa", 0600, dir, dev, &fops_fw_debug_wa); |
| debugfs_create_file("fw_debug_bin", 0600, dir, dev, &fops_fw_debug_bin); |
| diff --git a/mt7915/mcu.c b/mt7915/mcu.c |
| index 681ede23..10450bd7 100755 |
| --- a/mt7915/mcu.c |
| +++ b/mt7915/mcu.c |
| @@ -2487,10 +2487,7 @@ int mt7915_mcu_init(struct mt7915_dev *dev) |
| /* force firmware operation mode into normal state, |
| * which should be set before firmware download stage. |
| */ |
| - if (is_mt7915(&dev->mt76)) |
| - mt76_wr(dev, MT_SWDEF_MODE, MT_SWDEF_NORMAL_MODE); |
| - else |
| - mt76_wr(dev, MT_SWDEF_MODE_MT7916, MT_SWDEF_NORMAL_MODE); |
| + mt76_wr(dev, MT_SWDEF_MODE, MT_SWDEF_NORMAL_MODE); |
| |
| ret = mt7915_driver_own(dev, 0); |
| if (ret) |
| diff --git a/mt7915/mmio.c b/mt7915/mmio.c |
| index 0bd32daa..2d733d32 100644 |
| --- a/mt7915/mmio.c |
| +++ b/mt7915/mmio.c |
| @@ -22,6 +22,7 @@ static const u32 mt7915_reg[] = { |
| [WFDMA_EXT_CSR_ADDR] = 0xd7000, |
| [CBTOP1_PHY_END] = 0x77ffffff, |
| [INFRA_MCU_ADDR_END] = 0x7c3fffff, |
| + [SWDEF_BASE_ADDR] = 0x41f200, |
| }; |
| |
| static const u32 mt7916_reg[] = { |
| @@ -36,6 +37,7 @@ static const u32 mt7916_reg[] = { |
| [WFDMA_EXT_CSR_ADDR] = 0xd7000, |
| [CBTOP1_PHY_END] = 0x7fffffff, |
| [INFRA_MCU_ADDR_END] = 0x7c085fff, |
| + [SWDEF_BASE_ADDR] = 0x411400, |
| }; |
| |
| static const u32 mt7986_reg[] = { |
| @@ -50,6 +52,7 @@ static const u32 mt7986_reg[] = { |
| [WFDMA_EXT_CSR_ADDR] = 0x27000, |
| [CBTOP1_PHY_END] = 0x7fffffff, |
| [INFRA_MCU_ADDR_END] = 0x7c085fff, |
| + [SWDEF_BASE_ADDR] = 0x411400, |
| }; |
| |
| static const u32 mt7915_offs[] = { |
| diff --git a/mt7915/regs.h b/mt7915/regs.h |
| index 97984aaf..ee212c99 100644 |
| --- a/mt7915/regs.h |
| +++ b/mt7915/regs.h |
| @@ -30,6 +30,7 @@ enum reg_rev { |
| WFDMA_EXT_CSR_ADDR, |
| CBTOP1_PHY_END, |
| INFRA_MCU_ADDR_END, |
| + SWDEF_BASE_ADDR, |
| __MT_REG_MAX, |
| }; |
| |
| @@ -942,12 +943,25 @@ enum offs_rev { |
| #define MT_ADIE_TYPE_MASK BIT(1) |
| |
| /* FW MODE SYNC */ |
| -#define MT_SWDEF_MODE 0x41f23c |
| -#define MT_SWDEF_MODE_MT7916 0x41143c |
| +#define MT_SWDEF_BASE __REG(SWDEF_BASE_ADDR) |
| + |
| +#define MT_SWDEF(ofs) (MT_SWDEF_BASE + (ofs)) |
| +#define MT_SWDEF_MODE MT_SWDEF(0x3c) |
| #define MT_SWDEF_NORMAL_MODE 0 |
| #define MT_SWDEF_ICAP_MODE 1 |
| #define MT_SWDEF_SPECTRUM_MODE 2 |
| |
| +#define MT_SWDEF_SER_STATUS MT_SWDEF(0x040) |
| +#define MT_SWDEF_PLE_STATUS MT_SWDEF(0x044) |
| +#define MT_SWDEF_PLE1_STATUS MT_SWDEF(0x048) |
| +#define MT_SWDEF_PLE_AMSDU_STATUS MT_SWDEF(0x04C) |
| +#define MT_SWDEF_PSE_STATUS MT_SWDEF(0x050) |
| +#define MT_SWDEF_PSE1_STATUS MT_SWDEF(0x054) |
| +#define MT_SWDEF_LAMC_WISR6_BN0_STATUS MT_SWDEF(0x058) |
| +#define MT_SWDEF_LAMC_WISR6_BN1_STATUS MT_SWDEF(0x05C) |
| +#define MT_SWDEF_LAMC_WISR7_BN0_STATUS MT_SWDEF(0x060) |
| +#define MT_SWDEF_LAMC_WISR7_BN1_STATUS MT_SWDEF(0x064) |
| + |
| #define MT_DIC_CMD_REG_BASE 0x41f000 |
| #define MT_DIC_CMD_REG(ofs) (MT_DIC_CMD_REG_BASE + (ofs)) |
| #define MT_DIC_CMD_REG_CMD MT_DIC_CMD_REG(0x10) |
| -- |
| 2.18.0 |
| |