| Index: linux-5.4.260/drivers/mtd/nand/spi/gigadevice.c |
| =================================================================== |
| --- linux-5.4.260.orig/drivers/mtd/nand/spi/gigadevice.c |
| +++ linux-5.4.260/drivers/mtd/nand/spi/gigadevice.c |
| @@ -13,7 +13,10 @@ |
| #define GD5FXGQ4XA_STATUS_ECC_1_7_BITFLIPS (1 << 4) |
| #define GD5FXGQ4XA_STATUS_ECC_8_BITFLIPS (3 << 4) |
| |
| -#define GD5FXGQ4UEXXG_REG_STATUS2 0xf0 |
| +#define GD5FXGQ5XE_STATUS_ECC_1_4_BITFLIPS (1 << 4) |
| +#define GD5FXGQ5XE_STATUS_ECC_4_BITFLIPS (3 << 4) |
| + |
| +#define GD5FXGQXXEXXG_REG_STATUS2 0xf0 |
| |
| #define GD5FXGQ4UXFXXG_STATUS_ECC_MASK (7 << 4) |
| #define GD5FXGQ4UXFXXG_STATUS_ECC_NO_BITFLIPS (0 << 4) |
| @@ -36,6 +39,22 @@ static SPINAND_OP_VARIANTS(read_cache_va |
| SPINAND_PAGE_READ_FROM_CACHE_OP_3A(true, 0, 1, NULL, 0), |
| SPINAND_PAGE_READ_FROM_CACHE_OP_3A(false, 0, 0, NULL, 0)); |
| |
| +static SPINAND_OP_VARIANTS(read_cache_variants_1gq5, |
| + SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0), |
| + SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0), |
| + SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0), |
| + SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0), |
| + SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0), |
| + SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0)); |
| + |
| +static SPINAND_OP_VARIANTS(read_cache_variants_2gq5, |
| + SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 4, NULL, 0), |
| + SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0), |
| + SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 2, NULL, 0), |
| + SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0), |
| + SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0), |
| + SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0)); |
| + |
| static SPINAND_OP_VARIANTS(write_cache_variants, |
| SPINAND_PROG_LOAD_X4(true, 0, NULL, 0), |
| SPINAND_PROG_LOAD(true, 0, NULL, 0)); |
| @@ -102,7 +121,7 @@ static int gd5fxgq4xa_ecc_get_status(str |
| return -EINVAL; |
| } |
| |
| -static int gd5fxgq4_variant2_ooblayout_ecc(struct mtd_info *mtd, int section, |
| +static int gd5fxgqx_variant2_ooblayout_ecc(struct mtd_info *mtd, int section, |
| struct mtd_oob_region *region) |
| { |
| if (section) |
| @@ -114,7 +133,7 @@ static int gd5fxgq4_variant2_ooblayout_e |
| return 0; |
| } |
| |
| -static int gd5fxgq4_variant2_ooblayout_free(struct mtd_info *mtd, int section, |
| +static int gd5fxgqx_variant2_ooblayout_free(struct mtd_info *mtd, int section, |
| struct mtd_oob_region *region) |
| { |
| if (section) |
| @@ -127,16 +146,46 @@ static int gd5fxgq4_variant2_ooblayout_f |
| return 0; |
| } |
| |
| -static const struct mtd_ooblayout_ops gd5fxgq4_variant2_ooblayout = { |
| - .ecc = gd5fxgq4_variant2_ooblayout_ecc, |
| - .free = gd5fxgq4_variant2_ooblayout_free, |
| +/* Valid for Q4/Q5 and Q6 (untested) devices */ |
| +static const struct mtd_ooblayout_ops gd5fxgqx_variant2_ooblayout = { |
| + .ecc = gd5fxgqx_variant2_ooblayout_ecc, |
| + .free = gd5fxgqx_variant2_ooblayout_free, |
| +}; |
| + |
| +static int gd5fxgq4xc_ooblayout_256_ecc(struct mtd_info *mtd, int section, |
| + struct mtd_oob_region *oobregion) |
| +{ |
| + if (section) |
| + return -ERANGE; |
| + |
| + oobregion->offset = 128; |
| + oobregion->length = 128; |
| + |
| + return 0; |
| +} |
| + |
| +static int gd5fxgq4xc_ooblayout_256_free(struct mtd_info *mtd, int section, |
| + struct mtd_oob_region *oobregion) |
| +{ |
| + if (section) |
| + return -ERANGE; |
| + |
| + oobregion->offset = 1; |
| + oobregion->length = 127; |
| + |
| + return 0; |
| +} |
| + |
| +static const struct mtd_ooblayout_ops gd5fxgq4xc_oob_256_ops = { |
| + .ecc = gd5fxgq4xc_ooblayout_256_ecc, |
| + .free = gd5fxgq4xc_ooblayout_256_free, |
| }; |
| |
| static int gd5fxgq4uexxg_ecc_get_status(struct spinand_device *spinand, |
| u8 status) |
| { |
| u8 status2; |
| - struct spi_mem_op op = SPINAND_GET_FEATURE_OP(GD5FXGQ4UEXXG_REG_STATUS2, |
| + struct spi_mem_op op = SPINAND_GET_FEATURE_OP(GD5FXGQXXEXXG_REG_STATUS2, |
| &status2); |
| int ret; |
| |
| @@ -174,6 +223,43 @@ static int gd5fxgq4uexxg_ecc_get_status( |
| return -EINVAL; |
| } |
| |
| +static int gd5fxgq5xexxg_ecc_get_status(struct spinand_device *spinand, |
| + u8 status) |
| +{ |
| + u8 status2; |
| + struct spi_mem_op op = SPINAND_GET_FEATURE_OP(GD5FXGQXXEXXG_REG_STATUS2, |
| + &status2); |
| + int ret; |
| + |
| + switch (status & STATUS_ECC_MASK) { |
| + case STATUS_ECC_NO_BITFLIPS: |
| + return 0; |
| + |
| + case GD5FXGQ5XE_STATUS_ECC_1_4_BITFLIPS: |
| + /* |
| + * Read status2 register to determine a more fine grained |
| + * bit error status |
| + */ |
| + ret = spi_mem_exec_op(spinand->spimem, &op); |
| + if (ret) |
| + return ret; |
| + |
| + /* |
| + * 1 ... 4 bits are flipped (and corrected) |
| + */ |
| + /* bits sorted this way (1...0): ECCSE1, ECCSE0 */ |
| + return ((status2 & STATUS_ECC_MASK) >> 4) + 1; |
| + |
| + case STATUS_ECC_UNCOR_ERROR: |
| + return -EBADMSG; |
| + |
| + default: |
| + break; |
| + } |
| + |
| + return -EINVAL; |
| +} |
| + |
| static int gd5fxgq4ufxxg_ecc_get_status(struct spinand_device *spinand, |
| u8 status) |
| { |
| @@ -195,7 +281,8 @@ static int gd5fxgq4ufxxg_ecc_get_status( |
| } |
| |
| static const struct spinand_info gigadevice_spinand_table[] = { |
| - SPINAND_INFO("GD5F1GQ4xA", 0xF1, |
| + SPINAND_INFO("GD5F1GQ4xA", |
| + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xf1), |
| NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1), |
| NAND_ECCREQ(8, 512), |
| SPINAND_INFO_OP_VARIANTS(&read_cache_variants, |
| @@ -204,7 +291,8 @@ static const struct spinand_info gigadev |
| SPINAND_HAS_QE_BIT, |
| SPINAND_ECCINFO(&gd5fxgq4xa_ooblayout, |
| gd5fxgq4xa_ecc_get_status)), |
| - SPINAND_INFO("GD5F2GQ4xA", 0xF2, |
| + SPINAND_INFO("GD5F2GQ4xA", |
| + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xf2), |
| NAND_MEMORG(1, 2048, 64, 64, 2048, 40, 1, 1, 1), |
| NAND_ECCREQ(8, 512), |
| SPINAND_INFO_OP_VARIANTS(&read_cache_variants, |
| @@ -213,7 +301,8 @@ static const struct spinand_info gigadev |
| SPINAND_HAS_QE_BIT, |
| SPINAND_ECCINFO(&gd5fxgq4xa_ooblayout, |
| gd5fxgq4xa_ecc_get_status)), |
| - SPINAND_INFO("GD5F4GQ4xA", 0xF4, |
| + SPINAND_INFO("GD5F4GQ4xA", |
| + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xf4), |
| NAND_MEMORG(1, 2048, 64, 64, 4096, 80, 1, 1, 1), |
| NAND_ECCREQ(8, 512), |
| SPINAND_INFO_OP_VARIANTS(&read_cache_variants, |
| @@ -222,59 +311,205 @@ static const struct spinand_info gigadev |
| SPINAND_HAS_QE_BIT, |
| SPINAND_ECCINFO(&gd5fxgq4xa_ooblayout, |
| gd5fxgq4xa_ecc_get_status)), |
| - SPINAND_INFO("GD5F1GQ4UExxG", 0xd1, |
| + SPINAND_INFO("GD5F4GQ4RC", |
| + SPINAND_ID(SPINAND_READID_METHOD_OPCODE, 0xa4, 0x68), |
| + NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1), |
| + NAND_ECCREQ(8, 512), |
| + SPINAND_INFO_OP_VARIANTS(&read_cache_variants_f, |
| + &write_cache_variants, |
| + &update_cache_variants), |
| + SPINAND_HAS_QE_BIT, |
| + SPINAND_ECCINFO(&gd5fxgq4xc_oob_256_ops, |
| + gd5fxgq4ufxxg_ecc_get_status)), |
| + SPINAND_INFO("GD5F4GQ4UC", |
| + SPINAND_ID(SPINAND_READID_METHOD_OPCODE, 0xb4, 0x68), |
| + NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1), |
| + NAND_ECCREQ(8, 512), |
| + SPINAND_INFO_OP_VARIANTS(&read_cache_variants_f, |
| + &write_cache_variants, |
| + &update_cache_variants), |
| + SPINAND_HAS_QE_BIT, |
| + SPINAND_ECCINFO(&gd5fxgq4xc_oob_256_ops, |
| + gd5fxgq4ufxxg_ecc_get_status)), |
| + SPINAND_INFO("GD5F1GQ4UExxG", |
| + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xd1), |
| + NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1), |
| + NAND_ECCREQ(8, 512), |
| + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, |
| + &write_cache_variants, |
| + &update_cache_variants), |
| + SPINAND_HAS_QE_BIT, |
| + SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout, |
| + gd5fxgq4uexxg_ecc_get_status)), |
| + SPINAND_INFO("GD5F1GQ4RExxG", |
| + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xc1), |
| NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1), |
| NAND_ECCREQ(8, 512), |
| SPINAND_INFO_OP_VARIANTS(&read_cache_variants, |
| &write_cache_variants, |
| &update_cache_variants), |
| SPINAND_HAS_QE_BIT, |
| - SPINAND_ECCINFO(&gd5fxgq4_variant2_ooblayout, |
| + SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout, |
| + gd5fxgq4uexxg_ecc_get_status)), |
| + SPINAND_INFO("GD5F2GQ4UExxG", |
| + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xd2), |
| + NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1), |
| + NAND_ECCREQ(8, 512), |
| + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, |
| + &write_cache_variants, |
| + &update_cache_variants), |
| + SPINAND_HAS_QE_BIT, |
| + SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout, |
| gd5fxgq4uexxg_ecc_get_status)), |
| - SPINAND_INFO("GD5F1GQ4UFxxG", 0xb148, |
| + SPINAND_INFO("GD5F2GQ4RExxG", |
| + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xc2), |
| + NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1), |
| + NAND_ECCREQ(8, 512), |
| + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, |
| + &write_cache_variants, |
| + &update_cache_variants), |
| + SPINAND_HAS_QE_BIT, |
| + SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout, |
| + gd5fxgq4uexxg_ecc_get_status)), |
| + SPINAND_INFO("GD5F1GQ4UFxxG", |
| + SPINAND_ID(SPINAND_READID_METHOD_OPCODE, 0xb1, 0x48), |
| NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1), |
| NAND_ECCREQ(8, 512), |
| SPINAND_INFO_OP_VARIANTS(&read_cache_variants_f, |
| &write_cache_variants, |
| &update_cache_variants), |
| SPINAND_HAS_QE_BIT, |
| - SPINAND_ECCINFO(&gd5fxgq4_variant2_ooblayout, |
| + SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout, |
| gd5fxgq4ufxxg_ecc_get_status)), |
| + SPINAND_INFO("GD5F1GQ5UExxG", |
| + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x51), |
| + NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1), |
| + NAND_ECCREQ(4, 512), |
| + SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5, |
| + &write_cache_variants, |
| + &update_cache_variants), |
| + SPINAND_HAS_QE_BIT, |
| + SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout, |
| + gd5fxgq5xexxg_ecc_get_status)), |
| + SPINAND_INFO("GD5F1GQ5RExxG", |
| + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x41), |
| + NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1), |
| + NAND_ECCREQ(4, 512), |
| + SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5, |
| + &write_cache_variants, |
| + &update_cache_variants), |
| + SPINAND_HAS_QE_BIT, |
| + SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout, |
| + gd5fxgq5xexxg_ecc_get_status)), |
| + SPINAND_INFO("GD5F2GQ5UExxG", |
| + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x52), |
| + NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1), |
| + NAND_ECCREQ(4, 512), |
| + SPINAND_INFO_OP_VARIANTS(&read_cache_variants_2gq5, |
| + &write_cache_variants, |
| + &update_cache_variants), |
| + SPINAND_HAS_QE_BIT, |
| + SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout, |
| + gd5fxgq5xexxg_ecc_get_status)), |
| + SPINAND_INFO("GD5F2GQ5RExxG", |
| + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x42), |
| + NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1), |
| + NAND_ECCREQ(4, 512), |
| + SPINAND_INFO_OP_VARIANTS(&read_cache_variants_2gq5, |
| + &write_cache_variants, |
| + &update_cache_variants), |
| + SPINAND_HAS_QE_BIT, |
| + SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout, |
| + gd5fxgq5xexxg_ecc_get_status)), |
| + SPINAND_INFO("GD5F4GQ6UExxG", |
| + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x55), |
| + NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 2, 1), |
| + NAND_ECCREQ(4, 512), |
| + SPINAND_INFO_OP_VARIANTS(&read_cache_variants_2gq5, |
| + &write_cache_variants, |
| + &update_cache_variants), |
| + SPINAND_HAS_QE_BIT, |
| + SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout, |
| + gd5fxgq5xexxg_ecc_get_status)), |
| + SPINAND_INFO("GD5F4GQ6RExxG", |
| + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x45), |
| + NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 2, 1), |
| + NAND_ECCREQ(4, 512), |
| + SPINAND_INFO_OP_VARIANTS(&read_cache_variants_2gq5, |
| + &write_cache_variants, |
| + &update_cache_variants), |
| + SPINAND_HAS_QE_BIT, |
| + SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout, |
| + gd5fxgq5xexxg_ecc_get_status)), |
| + SPINAND_INFO("GD5F1GM7UExxG", |
| + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x91), |
| + NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1), |
| + NAND_ECCREQ(8, 512), |
| + SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5, |
| + &write_cache_variants, |
| + &update_cache_variants), |
| + SPINAND_HAS_QE_BIT, |
| + SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout, |
| + gd5fxgq4uexxg_ecc_get_status)), |
| + SPINAND_INFO("GD5F1GM7RExxG", |
| + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x81), |
| + NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1), |
| + NAND_ECCREQ(8, 512), |
| + SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5, |
| + &write_cache_variants, |
| + &update_cache_variants), |
| + SPINAND_HAS_QE_BIT, |
| + SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout, |
| + gd5fxgq4uexxg_ecc_get_status)), |
| + SPINAND_INFO("GD5F2GM7UExxG", |
| + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x92), |
| + NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1), |
| + NAND_ECCREQ(8, 512), |
| + SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5, |
| + &write_cache_variants, |
| + &update_cache_variants), |
| + SPINAND_HAS_QE_BIT, |
| + SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout, |
| + gd5fxgq4uexxg_ecc_get_status)), |
| + SPINAND_INFO("GD5F2GM7RExxG", |
| + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x82), |
| + NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1), |
| + NAND_ECCREQ(8, 512), |
| + SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5, |
| + &write_cache_variants, |
| + &update_cache_variants), |
| + SPINAND_HAS_QE_BIT, |
| + SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout, |
| + gd5fxgq4uexxg_ecc_get_status)), |
| + SPINAND_INFO("GD5F4GM8UExxG", |
| + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x95), |
| + NAND_MEMORG(1, 2048, 128, 64, 4096, 80, 1, 1, 1), |
| + NAND_ECCREQ(8, 512), |
| + SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5, |
| + &write_cache_variants, |
| + &update_cache_variants), |
| + SPINAND_HAS_QE_BIT, |
| + SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout, |
| + gd5fxgq4uexxg_ecc_get_status)), |
| + SPINAND_INFO("GD5F4GM8RExxG", |
| + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x85), |
| + NAND_MEMORG(1, 2048, 128, 64, 4096, 80, 1, 1, 1), |
| + NAND_ECCREQ(8, 512), |
| + SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5, |
| + &write_cache_variants, |
| + &update_cache_variants), |
| + SPINAND_HAS_QE_BIT, |
| + SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout, |
| + gd5fxgq4uexxg_ecc_get_status)), |
| }; |
| |
| -static int gigadevice_spinand_detect(struct spinand_device *spinand) |
| -{ |
| - u8 *id = spinand->id.data; |
| - u16 did; |
| - int ret; |
| - |
| - /* |
| - * Earlier GDF5-series devices (A,E) return [0][MID][DID] |
| - * Later (F) devices return [MID][DID1][DID2] |
| - */ |
| - |
| - if (id[0] == SPINAND_MFR_GIGADEVICE) |
| - did = (id[1] << 8) + id[2]; |
| - else if (id[0] == 0 && id[1] == SPINAND_MFR_GIGADEVICE) |
| - did = id[2]; |
| - else |
| - return 0; |
| - |
| - ret = spinand_match_and_init(spinand, gigadevice_spinand_table, |
| - ARRAY_SIZE(gigadevice_spinand_table), |
| - did); |
| - if (ret) |
| - return ret; |
| - |
| - return 1; |
| -} |
| - |
| static const struct spinand_manufacturer_ops gigadevice_spinand_manuf_ops = { |
| - .detect = gigadevice_spinand_detect, |
| }; |
| |
| const struct spinand_manufacturer gigadevice_spinand_manufacturer = { |
| .id = SPINAND_MFR_GIGADEVICE, |
| .name = "GigaDevice", |
| + .chips = gigadevice_spinand_table, |
| + .nchips = ARRAY_SIZE(gigadevice_spinand_table), |
| .ops = &gigadevice_spinand_manuf_ops, |
| }; |
| Index: linux-5.4.260/drivers/mtd/nand/spi/macronix.c |
| =================================================================== |
| --- linux-5.4.260.orig/drivers/mtd/nand/spi/macronix.c |
| +++ linux-5.4.260/drivers/mtd/nand/spi/macronix.c |
| @@ -99,7 +99,8 @@ static int mx35lf1ge4ab_ecc_get_status(s |
| } |
| |
| static const struct spinand_info macronix_spinand_table[] = { |
| - SPINAND_INFO("MX35LF1GE4AB", 0x12, |
| + SPINAND_INFO("MX35LF1GE4AB", |
| + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x12), |
| NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1), |
| NAND_ECCREQ(4, 512), |
| SPINAND_INFO_OP_VARIANTS(&read_cache_variants, |
| @@ -108,7 +109,8 @@ static const struct spinand_info macroni |
| SPINAND_HAS_QE_BIT, |
| SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, |
| mx35lf1ge4ab_ecc_get_status)), |
| - SPINAND_INFO("MX35LF2GE4AB", 0x22, |
| + SPINAND_INFO("MX35LF2GE4AB", |
| + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x22), |
| NAND_MEMORG(1, 2048, 64, 64, 2048, 40, 2, 1, 1), |
| NAND_ECCREQ(4, 512), |
| SPINAND_INFO_OP_VARIANTS(&read_cache_variants, |
| @@ -116,51 +118,194 @@ static const struct spinand_info macroni |
| &update_cache_variants), |
| SPINAND_HAS_QE_BIT, |
| SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, NULL)), |
| - SPINAND_INFO("MX35LF2GE4AD", 0x26, |
| + SPINAND_INFO("MX35LF2GE4AD", |
| + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x26), |
| NAND_MEMORG(1, 2048, 64, 64, 2048, 40, 1, 1, 1), |
| NAND_ECCREQ(8, 512), |
| SPINAND_INFO_OP_VARIANTS(&read_cache_variants, |
| &write_cache_variants, |
| &update_cache_variants), |
| SPINAND_HAS_QE_BIT, |
| + SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, |
| + mx35lf1ge4ab_ecc_get_status)), |
| + SPINAND_INFO("MX35LF4GE4AD", |
| + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x37), |
| + NAND_MEMORG(1, 4096, 128, 64, 2048, 40, 1, 1, 1), |
| + NAND_ECCREQ(8, 512), |
| + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, |
| + &write_cache_variants, |
| + &update_cache_variants), |
| + SPINAND_HAS_QE_BIT, |
| + SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, |
| + mx35lf1ge4ab_ecc_get_status)), |
| + SPINAND_INFO("MX35LF1G24AD", |
| + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x14), |
| + NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1), |
| + NAND_ECCREQ(8, 512), |
| + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, |
| + &write_cache_variants, |
| + &update_cache_variants), |
| + SPINAND_HAS_QE_BIT, |
| SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, NULL)), |
| - SPINAND_INFO("MX35LF4GE4AD", 0x37, |
| - NAND_MEMORG(1, 4096, 128, 64, 2048, 40, 1, 1, 1), |
| + SPINAND_INFO("MX35LF2G24AD", |
| + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x24), |
| + NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 2, 1, 1), |
| NAND_ECCREQ(8, 512), |
| SPINAND_INFO_OP_VARIANTS(&read_cache_variants, |
| &write_cache_variants, |
| &update_cache_variants), |
| SPINAND_HAS_QE_BIT, |
| SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, NULL)), |
| -}; |
| - |
| -static int macronix_spinand_detect(struct spinand_device *spinand) |
| -{ |
| - u8 *id = spinand->id.data; |
| - int ret; |
| - |
| - /* |
| - * Macronix SPI NAND read ID needs a dummy byte, so the first byte in |
| - * raw_id is garbage. |
| - */ |
| - if (id[1] != SPINAND_MFR_MACRONIX) |
| - return 0; |
| + SPINAND_INFO("MX35LF4G24AD", |
| + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x35), |
| + NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 2, 1, 1), |
| + NAND_ECCREQ(8, 512), |
| + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, |
| + &write_cache_variants, |
| + &update_cache_variants), |
| + SPINAND_HAS_QE_BIT, |
| + SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, NULL)), |
| + SPINAND_INFO("MX31LF1GE4BC", |
| + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x1e), |
| + NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1), |
| + NAND_ECCREQ(8, 512), |
| + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, |
| + &write_cache_variants, |
| + &update_cache_variants), |
| + SPINAND_HAS_QE_BIT, |
| + SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, |
| + mx35lf1ge4ab_ecc_get_status)), |
| + SPINAND_INFO("MX31UF1GE4BC", |
| + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x9e), |
| + NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1), |
| + NAND_ECCREQ(8, 512), |
| + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, |
| + &write_cache_variants, |
| + &update_cache_variants), |
| + SPINAND_HAS_QE_BIT, |
| + SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, |
| + mx35lf1ge4ab_ecc_get_status)), |
| |
| - ret = spinand_match_and_init(spinand, macronix_spinand_table, |
| - ARRAY_SIZE(macronix_spinand_table), |
| - id[2]); |
| - if (ret) |
| - return ret; |
| + SPINAND_INFO("MX35LF2G14AC", |
| + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x20), |
| + NAND_MEMORG(1, 2048, 64, 64, 2048, 40, 2, 1, 1), |
| + NAND_ECCREQ(4, 512), |
| + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, |
| + &write_cache_variants, |
| + &update_cache_variants), |
| + SPINAND_HAS_QE_BIT, |
| + SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, |
| + mx35lf1ge4ab_ecc_get_status)), |
| + SPINAND_INFO("MX35UF4G24AD", |
| + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xb5), |
| + NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 2, 1, 1), |
| + NAND_ECCREQ(8, 512), |
| + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, |
| + &write_cache_variants, |
| + &update_cache_variants), |
| + SPINAND_HAS_QE_BIT, |
| + SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, |
| + mx35lf1ge4ab_ecc_get_status)), |
| + SPINAND_INFO("MX35UF4GE4AD", |
| + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xb7), |
| + NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1), |
| + NAND_ECCREQ(8, 512), |
| + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, |
| + &write_cache_variants, |
| + &update_cache_variants), |
| + SPINAND_HAS_QE_BIT, |
| + SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, |
| + mx35lf1ge4ab_ecc_get_status)), |
| + SPINAND_INFO("MX35UF2G14AC", |
| + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xa0), |
| + NAND_MEMORG(1, 2048, 64, 64, 2048, 40, 2, 1, 1), |
| + NAND_ECCREQ(4, 512), |
| + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, |
| + &write_cache_variants, |
| + &update_cache_variants), |
| + SPINAND_HAS_QE_BIT, |
| + SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, |
| + mx35lf1ge4ab_ecc_get_status)), |
| + SPINAND_INFO("MX35UF2G24AD", |
| + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xa4), |
| + NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 2, 1, 1), |
| + NAND_ECCREQ(8, 512), |
| + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, |
| + &write_cache_variants, |
| + &update_cache_variants), |
| + SPINAND_HAS_QE_BIT, |
| + SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, |
| + mx35lf1ge4ab_ecc_get_status)), |
| + SPINAND_INFO("MX35UF2GE4AD", |
| + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xa6), |
| + NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1), |
| + NAND_ECCREQ(8, 512), |
| + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, |
| + &write_cache_variants, |
| + &update_cache_variants), |
| + SPINAND_HAS_QE_BIT, |
| + SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, |
| + mx35lf1ge4ab_ecc_get_status)), |
| + SPINAND_INFO("MX35UF2GE4AC", |
| + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xa2), |
| + NAND_MEMORG(1, 2048, 64, 64, 2048, 40, 1, 1, 1), |
| + NAND_ECCREQ(4, 512), |
| + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, |
| + &write_cache_variants, |
| + &update_cache_variants), |
| + SPINAND_HAS_QE_BIT, |
| + SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, |
| + mx35lf1ge4ab_ecc_get_status)), |
| + SPINAND_INFO("MX35UF1G14AC", |
| + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x90), |
| + NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1), |
| + NAND_ECCREQ(4, 512), |
| + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, |
| + &write_cache_variants, |
| + &update_cache_variants), |
| + SPINAND_HAS_QE_BIT, |
| + SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, |
| + mx35lf1ge4ab_ecc_get_status)), |
| + SPINAND_INFO("MX35UF1G24AD", |
| + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x94), |
| + NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1), |
| + NAND_ECCREQ(8, 512), |
| + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, |
| + &write_cache_variants, |
| + &update_cache_variants), |
| + SPINAND_HAS_QE_BIT, |
| + SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, |
| + mx35lf1ge4ab_ecc_get_status)), |
| + SPINAND_INFO("MX35UF1GE4AD", |
| + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x96), |
| + NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1), |
| + NAND_ECCREQ(8, 512), |
| + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, |
| + &write_cache_variants, |
| + &update_cache_variants), |
| + SPINAND_HAS_QE_BIT, |
| + SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, |
| + mx35lf1ge4ab_ecc_get_status)), |
| + SPINAND_INFO("MX35UF1GE4AC", |
| + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x92), |
| + NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1), |
| + NAND_ECCREQ(4, 512), |
| + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, |
| + &write_cache_variants, |
| + &update_cache_variants), |
| + SPINAND_HAS_QE_BIT, |
| + SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, |
| + mx35lf1ge4ab_ecc_get_status)), |
| |
| - return 1; |
| -} |
| +}; |
| |
| static const struct spinand_manufacturer_ops macronix_spinand_manuf_ops = { |
| - .detect = macronix_spinand_detect, |
| }; |
| |
| const struct spinand_manufacturer macronix_spinand_manufacturer = { |
| .id = SPINAND_MFR_MACRONIX, |
| .name = "Macronix", |
| + .chips = macronix_spinand_table, |
| + .nchips = ARRAY_SIZE(macronix_spinand_table), |
| .ops = ¯onix_spinand_manuf_ops, |
| }; |
| Index: linux-5.4.260/drivers/mtd/nand/spi/micron.c |
| =================================================================== |
| --- linux-5.4.260.orig/drivers/mtd/nand/spi/micron.c |
| +++ linux-5.4.260/drivers/mtd/nand/spi/micron.c |
| @@ -12,13 +12,23 @@ |
| |
| #define SPINAND_MFR_MICRON 0x2c |
| |
| -#define MICRON_STATUS_ECC_MASK GENMASK(6, 4) |
| +#define MICRON_STATUS_ECC_MASK GENMASK(7, 4) |
| #define MICRON_STATUS_ECC_NO_BITFLIPS (0 << 4) |
| #define MICRON_STATUS_ECC_1TO3_BITFLIPS (1 << 4) |
| #define MICRON_STATUS_ECC_4TO6_BITFLIPS (3 << 4) |
| #define MICRON_STATUS_ECC_7TO8_BITFLIPS (5 << 4) |
| |
| -static SPINAND_OP_VARIANTS(read_cache_variants, |
| +#define MICRON_CFG_CR BIT(0) |
| + |
| +/* |
| + * As per datasheet, die selection is done by the 6th bit of Die |
| + * Select Register (Address 0xD0). |
| + */ |
| +#define MICRON_DIE_SELECT_REG 0xD0 |
| + |
| +#define MICRON_SELECT_DIE(x) ((x) << 6) |
| + |
| +static SPINAND_OP_VARIANTS(quadio_read_cache_variants, |
| SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0), |
| SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0), |
| SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0), |
| @@ -26,46 +36,114 @@ static SPINAND_OP_VARIANTS(read_cache_va |
| SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0), |
| SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0)); |
| |
| -static SPINAND_OP_VARIANTS(write_cache_variants, |
| +static SPINAND_OP_VARIANTS(x4_write_cache_variants, |
| SPINAND_PROG_LOAD_X4(true, 0, NULL, 0), |
| SPINAND_PROG_LOAD(true, 0, NULL, 0)); |
| |
| -static SPINAND_OP_VARIANTS(update_cache_variants, |
| +static SPINAND_OP_VARIANTS(x4_update_cache_variants, |
| SPINAND_PROG_LOAD_X4(false, 0, NULL, 0), |
| SPINAND_PROG_LOAD(false, 0, NULL, 0)); |
| |
| -static int mt29f2g01abagd_ooblayout_ecc(struct mtd_info *mtd, int section, |
| - struct mtd_oob_region *region) |
| +/* Micron MT29F2G01AAAED Device */ |
| +static SPINAND_OP_VARIANTS(x4_read_cache_variants, |
| + SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0), |
| + SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0), |
| + SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0), |
| + SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0)); |
| + |
| +static SPINAND_OP_VARIANTS(x1_write_cache_variants, |
| + SPINAND_PROG_LOAD(true, 0, NULL, 0)); |
| + |
| +static SPINAND_OP_VARIANTS(x1_update_cache_variants, |
| + SPINAND_PROG_LOAD(false, 0, NULL, 0)); |
| + |
| +static int micron_8_ooblayout_ecc(struct mtd_info *mtd, int section, |
| + struct mtd_oob_region *region) |
| { |
| if (section) |
| return -ERANGE; |
| |
| - region->offset = 64; |
| - region->length = 64; |
| + region->offset = mtd->oobsize / 2; |
| + region->length = mtd->oobsize / 2; |
| |
| return 0; |
| } |
| |
| -static int mt29f2g01abagd_ooblayout_free(struct mtd_info *mtd, int section, |
| - struct mtd_oob_region *region) |
| +static int micron_8_ooblayout_free(struct mtd_info *mtd, int section, |
| + struct mtd_oob_region *region) |
| { |
| if (section) |
| return -ERANGE; |
| |
| /* Reserve 2 bytes for the BBM. */ |
| region->offset = 2; |
| - region->length = 62; |
| + region->length = (mtd->oobsize / 2) - 2; |
| + |
| + return 0; |
| +} |
| + |
| +static const struct mtd_ooblayout_ops micron_8_ooblayout = { |
| + .ecc = micron_8_ooblayout_ecc, |
| + .free = micron_8_ooblayout_free, |
| +}; |
| + |
| +static int micron_4_ooblayout_ecc(struct mtd_info *mtd, int section, |
| + struct mtd_oob_region *region) |
| +{ |
| + struct spinand_device *spinand = mtd_to_spinand(mtd); |
| + |
| + if (section >= spinand->base.memorg.pagesize / |
| + mtd->ecc_step_size) |
| + return -ERANGE; |
| + |
| + region->offset = (section * 16) + 8; |
| + region->length = 8; |
| + |
| + return 0; |
| +} |
| + |
| +static int micron_4_ooblayout_free(struct mtd_info *mtd, int section, |
| + struct mtd_oob_region *region) |
| +{ |
| + struct spinand_device *spinand = mtd_to_spinand(mtd); |
| + |
| + if (section >= spinand->base.memorg.pagesize / |
| + mtd->ecc_step_size) |
| + return -ERANGE; |
| + |
| + if (section) { |
| + region->offset = 16 * section; |
| + region->length = 8; |
| + } else { |
| + /* section 0 has two bytes reserved for the BBM */ |
| + region->offset = 2; |
| + region->length = 6; |
| + } |
| |
| return 0; |
| } |
| |
| -static const struct mtd_ooblayout_ops mt29f2g01abagd_ooblayout = { |
| - .ecc = mt29f2g01abagd_ooblayout_ecc, |
| - .free = mt29f2g01abagd_ooblayout_free, |
| +static const struct mtd_ooblayout_ops micron_4_ooblayout = { |
| + .ecc = micron_4_ooblayout_ecc, |
| + .free = micron_4_ooblayout_free, |
| }; |
| |
| -static int mt29f2g01abagd_ecc_get_status(struct spinand_device *spinand, |
| - u8 status) |
| +static int micron_select_target(struct spinand_device *spinand, |
| + unsigned int target) |
| +{ |
| + struct spi_mem_op op = SPINAND_SET_FEATURE_OP(MICRON_DIE_SELECT_REG, |
| + spinand->scratchbuf); |
| + |
| + if (target > 1) |
| + return -EINVAL; |
| + |
| + *spinand->scratchbuf = MICRON_SELECT_DIE(target); |
| + |
| + return spi_mem_exec_op(spinand->spimem, &op); |
| +} |
| + |
| +static int micron_8_ecc_get_status(struct spinand_device *spinand, |
| + u8 status) |
| { |
| switch (status & MICRON_STATUS_ECC_MASK) { |
| case STATUS_ECC_NO_BITFLIPS: |
| @@ -91,43 +169,141 @@ static int mt29f2g01abagd_ecc_get_status |
| } |
| |
| static const struct spinand_info micron_spinand_table[] = { |
| - SPINAND_INFO("MT29F2G01ABAGD", 0x24, |
| + /* M79A 2Gb 3.3V */ |
| + SPINAND_INFO("MT29F2G01ABAGD", |
| + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x24), |
| NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 2, 1, 1), |
| NAND_ECCREQ(8, 512), |
| - SPINAND_INFO_OP_VARIANTS(&read_cache_variants, |
| - &write_cache_variants, |
| - &update_cache_variants), |
| + SPINAND_INFO_OP_VARIANTS(&quadio_read_cache_variants, |
| + &x4_write_cache_variants, |
| + &x4_update_cache_variants), |
| + 0, |
| + SPINAND_ECCINFO(µn_8_ooblayout, |
| + micron_8_ecc_get_status)), |
| + /* M79A 2Gb 1.8V */ |
| + SPINAND_INFO("MT29F2G01ABBGD", |
| + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x25), |
| + NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 2, 1, 1), |
| + NAND_ECCREQ(8, 512), |
| + SPINAND_INFO_OP_VARIANTS(&quadio_read_cache_variants, |
| + &x4_write_cache_variants, |
| + &x4_update_cache_variants), |
| + 0, |
| + SPINAND_ECCINFO(µn_8_ooblayout, |
| + micron_8_ecc_get_status)), |
| + /* M78A 1Gb 3.3V */ |
| + SPINAND_INFO("MT29F1G01ABAFD", |
| + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x14), |
| + NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1), |
| + NAND_ECCREQ(8, 512), |
| + SPINAND_INFO_OP_VARIANTS(&quadio_read_cache_variants, |
| + &x4_write_cache_variants, |
| + &x4_update_cache_variants), |
| + 0, |
| + SPINAND_ECCINFO(µn_8_ooblayout, |
| + micron_8_ecc_get_status)), |
| + /* M78A 1Gb 1.8V */ |
| + SPINAND_INFO("MT29F1G01ABAFD", |
| + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x15), |
| + NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1), |
| + NAND_ECCREQ(8, 512), |
| + SPINAND_INFO_OP_VARIANTS(&quadio_read_cache_variants, |
| + &x4_write_cache_variants, |
| + &x4_update_cache_variants), |
| + 0, |
| + SPINAND_ECCINFO(µn_8_ooblayout, |
| + micron_8_ecc_get_status)), |
| + /* M79A 4Gb 3.3V */ |
| + SPINAND_INFO("MT29F4G01ADAGD", |
| + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x36), |
| + NAND_MEMORG(1, 2048, 128, 64, 2048, 80, 2, 1, 2), |
| + NAND_ECCREQ(8, 512), |
| + SPINAND_INFO_OP_VARIANTS(&quadio_read_cache_variants, |
| + &x4_write_cache_variants, |
| + &x4_update_cache_variants), |
| + 0, |
| + SPINAND_ECCINFO(µn_8_ooblayout, |
| + micron_8_ecc_get_status), |
| + SPINAND_SELECT_TARGET(micron_select_target)), |
| + /* M70A 4Gb 3.3V */ |
| + SPINAND_INFO("MT29F4G01ABAFD", |
| + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x34), |
| + NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1), |
| + NAND_ECCREQ(8, 512), |
| + SPINAND_INFO_OP_VARIANTS(&quadio_read_cache_variants, |
| + &x4_write_cache_variants, |
| + &x4_update_cache_variants), |
| + SPINAND_HAS_CR_FEAT_BIT, |
| + SPINAND_ECCINFO(µn_8_ooblayout, |
| + micron_8_ecc_get_status)), |
| + /* M70A 4Gb 1.8V */ |
| + SPINAND_INFO("MT29F4G01ABBFD", |
| + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x35), |
| + NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1), |
| + NAND_ECCREQ(8, 512), |
| + SPINAND_INFO_OP_VARIANTS(&quadio_read_cache_variants, |
| + &x4_write_cache_variants, |
| + &x4_update_cache_variants), |
| + SPINAND_HAS_CR_FEAT_BIT, |
| + SPINAND_ECCINFO(µn_8_ooblayout, |
| + micron_8_ecc_get_status)), |
| + /* M70A 8Gb 3.3V */ |
| + SPINAND_INFO("MT29F8G01ADAFD", |
| + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x46), |
| + NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 2), |
| + NAND_ECCREQ(8, 512), |
| + SPINAND_INFO_OP_VARIANTS(&quadio_read_cache_variants, |
| + &x4_write_cache_variants, |
| + &x4_update_cache_variants), |
| + SPINAND_HAS_CR_FEAT_BIT, |
| + SPINAND_ECCINFO(µn_8_ooblayout, |
| + micron_8_ecc_get_status), |
| + SPINAND_SELECT_TARGET(micron_select_target)), |
| + /* M70A 8Gb 1.8V */ |
| + SPINAND_INFO("MT29F8G01ADBFD", |
| + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x47), |
| + NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 2), |
| + NAND_ECCREQ(8, 512), |
| + SPINAND_INFO_OP_VARIANTS(&quadio_read_cache_variants, |
| + &x4_write_cache_variants, |
| + &x4_update_cache_variants), |
| + SPINAND_HAS_CR_FEAT_BIT, |
| + SPINAND_ECCINFO(µn_8_ooblayout, |
| + micron_8_ecc_get_status), |
| + SPINAND_SELECT_TARGET(micron_select_target)), |
| + /* M69A 2Gb 3.3V */ |
| + SPINAND_INFO("MT29F2G01AAAED", |
| + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x9F), |
| + NAND_MEMORG(1, 2048, 64, 64, 2048, 80, 2, 1, 1), |
| + NAND_ECCREQ(4, 512), |
| + SPINAND_INFO_OP_VARIANTS(&x4_read_cache_variants, |
| + &x1_write_cache_variants, |
| + &x1_update_cache_variants), |
| 0, |
| - SPINAND_ECCINFO(&mt29f2g01abagd_ooblayout, |
| - mt29f2g01abagd_ecc_get_status)), |
| + SPINAND_ECCINFO(µn_4_ooblayout, NULL)), |
| }; |
| |
| -static int micron_spinand_detect(struct spinand_device *spinand) |
| +static int micron_spinand_init(struct spinand_device *spinand) |
| { |
| - u8 *id = spinand->id.data; |
| - int ret; |
| - |
| /* |
| - * Micron SPI NAND read ID need a dummy byte, |
| - * so the first byte in raw_id is dummy. |
| + * M70A device series enable Continuous Read feature at Power-up, |
| + * which is not supported. Disable this bit to avoid any possible |
| + * failure. |
| */ |
| - if (id[1] != SPINAND_MFR_MICRON) |
| - return 0; |
| - |
| - ret = spinand_match_and_init(spinand, micron_spinand_table, |
| - ARRAY_SIZE(micron_spinand_table), id[2]); |
| - if (ret) |
| - return ret; |
| + if (spinand->flags & SPINAND_HAS_CR_FEAT_BIT) |
| + return spinand_upd_cfg(spinand, MICRON_CFG_CR, 0); |
| |
| - return 1; |
| + return 0; |
| } |
| |
| static const struct spinand_manufacturer_ops micron_spinand_manuf_ops = { |
| - .detect = micron_spinand_detect, |
| + .init = micron_spinand_init, |
| }; |
| |
| const struct spinand_manufacturer micron_spinand_manufacturer = { |
| .id = SPINAND_MFR_MICRON, |
| .name = "Micron", |
| + .chips = micron_spinand_table, |
| + .nchips = ARRAY_SIZE(micron_spinand_table), |
| .ops = µn_spinand_manuf_ops, |
| }; |
| Index: linux-5.4.260/drivers/mtd/nand/spi/paragon.c |
| =================================================================== |
| --- linux-5.4.260.orig/drivers/mtd/nand/spi/paragon.c |
| +++ linux-5.4.260/drivers/mtd/nand/spi/paragon.c |
| @@ -97,7 +97,8 @@ static const struct mtd_ooblayout_ops pn |
| |
| |
| static const struct spinand_info paragon_spinand_table[] = { |
| - SPINAND_INFO("PN26G01A", 0xe1, |
| + SPINAND_INFO("PN26G01A", |
| + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xe1), |
| NAND_MEMORG(1, 2048, 128, 64, 1024, 21, 1, 1, 1), |
| NAND_ECCREQ(8, 512), |
| SPINAND_INFO_OP_VARIANTS(&read_cache_variants, |
| @@ -106,7 +107,8 @@ static const struct spinand_info paragon |
| 0, |
| SPINAND_ECCINFO(&pn26g0xa_ooblayout, |
| pn26g0xa_ecc_get_status)), |
| - SPINAND_INFO("PN26G02A", 0xe2, |
| + SPINAND_INFO("PN26G02A", |
| + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xe2), |
| NAND_MEMORG(1, 2048, 128, 64, 2048, 41, 1, 1, 1), |
| NAND_ECCREQ(8, 512), |
| SPINAND_INFO_OP_VARIANTS(&read_cache_variants, |
| @@ -117,31 +119,13 @@ static const struct spinand_info paragon |
| pn26g0xa_ecc_get_status)), |
| }; |
| |
| -static int paragon_spinand_detect(struct spinand_device *spinand) |
| -{ |
| - u8 *id = spinand->id.data; |
| - int ret; |
| - |
| - /* Read ID returns [0][MID][DID] */ |
| - |
| - if (id[1] != SPINAND_MFR_PARAGON) |
| - return 0; |
| - |
| - ret = spinand_match_and_init(spinand, paragon_spinand_table, |
| - ARRAY_SIZE(paragon_spinand_table), |
| - id[2]); |
| - if (ret) |
| - return ret; |
| - |
| - return 1; |
| -} |
| - |
| static const struct spinand_manufacturer_ops paragon_spinand_manuf_ops = { |
| - .detect = paragon_spinand_detect, |
| }; |
| |
| const struct spinand_manufacturer paragon_spinand_manufacturer = { |
| .id = SPINAND_MFR_PARAGON, |
| .name = "Paragon", |
| + .chips = paragon_spinand_table, |
| + .nchips = ARRAY_SIZE(paragon_spinand_table), |
| .ops = ¶gon_spinand_manuf_ops, |
| }; |
| Index: linux-5.4.260/drivers/mtd/nand/spi/toshiba.c |
| =================================================================== |
| --- linux-5.4.260.orig/drivers/mtd/nand/spi/toshiba.c |
| +++ linux-5.4.260/drivers/mtd/nand/spi/toshiba.c |
| @@ -10,6 +10,7 @@ |
| #include <linux/kernel.h> |
| #include <linux/mtd/spinand.h> |
| |
| +/* Kioxia is new name of Toshiba memory. */ |
| #define SPINAND_MFR_TOSHIBA 0x98 |
| #define TOSH_STATUS_ECC_HAS_BITFLIPS_T (3 << 4) |
| |
| @@ -19,14 +20,26 @@ static SPINAND_OP_VARIANTS(read_cache_va |
| SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0), |
| SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0)); |
| |
| +static SPINAND_OP_VARIANTS(write_cache_x4_variants, |
| + SPINAND_PROG_LOAD_X4(true, 0, NULL, 0), |
| + SPINAND_PROG_LOAD(true, 0, NULL, 0)); |
| + |
| +static SPINAND_OP_VARIANTS(update_cache_x4_variants, |
| + SPINAND_PROG_LOAD_X4(false, 0, NULL, 0), |
| + SPINAND_PROG_LOAD(false, 0, NULL, 0)); |
| + |
| +/* |
| + * Backward compatibility for 1st generation Serial NAND devices |
| + * which don't support Quad Program Load operation. |
| + */ |
| static SPINAND_OP_VARIANTS(write_cache_variants, |
| SPINAND_PROG_LOAD(true, 0, NULL, 0)); |
| |
| static SPINAND_OP_VARIANTS(update_cache_variants, |
| SPINAND_PROG_LOAD(false, 0, NULL, 0)); |
| |
| -static int tc58cxgxsx_ooblayout_ecc(struct mtd_info *mtd, int section, |
| - struct mtd_oob_region *region) |
| +static int tx58cxgxsxraix_ooblayout_ecc(struct mtd_info *mtd, int section, |
| + struct mtd_oob_region *region) |
| { |
| if (section > 0) |
| return -ERANGE; |
| @@ -37,8 +50,8 @@ static int tc58cxgxsx_ooblayout_ecc(stru |
| return 0; |
| } |
| |
| -static int tc58cxgxsx_ooblayout_free(struct mtd_info *mtd, int section, |
| - struct mtd_oob_region *region) |
| +static int tx58cxgxsxraix_ooblayout_free(struct mtd_info *mtd, int section, |
| + struct mtd_oob_region *region) |
| { |
| if (section > 0) |
| return -ERANGE; |
| @@ -50,13 +63,13 @@ static int tc58cxgxsx_ooblayout_free(str |
| return 0; |
| } |
| |
| -static const struct mtd_ooblayout_ops tc58cxgxsx_ooblayout = { |
| - .ecc = tc58cxgxsx_ooblayout_ecc, |
| - .free = tc58cxgxsx_ooblayout_free, |
| +static const struct mtd_ooblayout_ops tx58cxgxsxraix_ooblayout = { |
| + .ecc = tx58cxgxsxraix_ooblayout_ecc, |
| + .free = tx58cxgxsxraix_ooblayout_free, |
| }; |
| |
| -static int tc58cxgxsx_ecc_get_status(struct spinand_device *spinand, |
| - u8 status) |
| +static int tx58cxgxsxraix_ecc_get_status(struct spinand_device *spinand, |
| + u8 status) |
| { |
| struct nand_device *nand = spinand_to_nand(spinand); |
| u8 mbf = 0; |
| @@ -94,95 +107,174 @@ static int tc58cxgxsx_ecc_get_status(str |
| } |
| |
| static const struct spinand_info toshiba_spinand_table[] = { |
| - /* 3.3V 1Gb */ |
| - SPINAND_INFO("TC58CVG0S3", 0xC2, |
| + /* 3.3V 1Gb (1st generation) */ |
| + SPINAND_INFO("TC58CVG0S3HRAIG", |
| + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xC2), |
| NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1), |
| NAND_ECCREQ(8, 512), |
| SPINAND_INFO_OP_VARIANTS(&read_cache_variants, |
| &write_cache_variants, |
| &update_cache_variants), |
| 0, |
| - SPINAND_ECCINFO(&tc58cxgxsx_ooblayout, |
| - tc58cxgxsx_ecc_get_status)), |
| - /* 3.3V 2Gb */ |
| - SPINAND_INFO("TC58CVG1S3", 0xCB, |
| + SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout, |
| + tx58cxgxsxraix_ecc_get_status)), |
| + /* 3.3V 2Gb (1st generation) */ |
| + SPINAND_INFO("TC58CVG1S3HRAIG", |
| + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xCB), |
| NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1), |
| NAND_ECCREQ(8, 512), |
| SPINAND_INFO_OP_VARIANTS(&read_cache_variants, |
| &write_cache_variants, |
| &update_cache_variants), |
| 0, |
| - SPINAND_ECCINFO(&tc58cxgxsx_ooblayout, |
| - tc58cxgxsx_ecc_get_status)), |
| - /* 3.3V 4Gb */ |
| - SPINAND_INFO("TC58CVG2S0", 0xCD, |
| + SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout, |
| + tx58cxgxsxraix_ecc_get_status)), |
| + /* 3.3V 4Gb (1st generation) */ |
| + SPINAND_INFO("TC58CVG2S0HRAIG", |
| + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xCD), |
| NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1), |
| NAND_ECCREQ(8, 512), |
| SPINAND_INFO_OP_VARIANTS(&read_cache_variants, |
| &write_cache_variants, |
| &update_cache_variants), |
| 0, |
| - SPINAND_ECCINFO(&tc58cxgxsx_ooblayout, |
| - tc58cxgxsx_ecc_get_status)), |
| - /* 1.8V 1Gb */ |
| - SPINAND_INFO("TC58CYG0S3", 0xB2, |
| + SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout, |
| + tx58cxgxsxraix_ecc_get_status)), |
| + /* 1.8V 1Gb (1st generation) */ |
| + SPINAND_INFO("TC58CYG0S3HRAIG", |
| + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xB2), |
| NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1), |
| NAND_ECCREQ(8, 512), |
| SPINAND_INFO_OP_VARIANTS(&read_cache_variants, |
| &write_cache_variants, |
| &update_cache_variants), |
| 0, |
| - SPINAND_ECCINFO(&tc58cxgxsx_ooblayout, |
| - tc58cxgxsx_ecc_get_status)), |
| - /* 1.8V 2Gb */ |
| - SPINAND_INFO("TC58CYG1S3", 0xBB, |
| + SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout, |
| + tx58cxgxsxraix_ecc_get_status)), |
| + /* 1.8V 2Gb (1st generation) */ |
| + SPINAND_INFO("TC58CYG1S3HRAIG", |
| + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xBB), |
| NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1), |
| NAND_ECCREQ(8, 512), |
| SPINAND_INFO_OP_VARIANTS(&read_cache_variants, |
| &write_cache_variants, |
| &update_cache_variants), |
| 0, |
| - SPINAND_ECCINFO(&tc58cxgxsx_ooblayout, |
| - tc58cxgxsx_ecc_get_status)), |
| - /* 1.8V 4Gb */ |
| - SPINAND_INFO("TC58CYG2S0", 0xBD, |
| + SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout, |
| + tx58cxgxsxraix_ecc_get_status)), |
| + /* 1.8V 4Gb (1st generation) */ |
| + SPINAND_INFO("TC58CYG2S0HRAIG", |
| + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xBD), |
| NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1), |
| NAND_ECCREQ(8, 512), |
| SPINAND_INFO_OP_VARIANTS(&read_cache_variants, |
| &write_cache_variants, |
| &update_cache_variants), |
| 0, |
| - SPINAND_ECCINFO(&tc58cxgxsx_ooblayout, |
| - tc58cxgxsx_ecc_get_status)), |
| -}; |
| - |
| -static int toshiba_spinand_detect(struct spinand_device *spinand) |
| -{ |
| - u8 *id = spinand->id.data; |
| - int ret; |
| + SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout, |
| + tx58cxgxsxraix_ecc_get_status)), |
| |
| /* |
| - * Toshiba SPI NAND read ID needs a dummy byte, |
| - * so the first byte in id is garbage. |
| + * 2nd generation serial nand has HOLD_D which is equivalent to |
| + * QE_BIT. |
| */ |
| - if (id[1] != SPINAND_MFR_TOSHIBA) |
| - return 0; |
| - |
| - ret = spinand_match_and_init(spinand, toshiba_spinand_table, |
| - ARRAY_SIZE(toshiba_spinand_table), |
| - id[2]); |
| - if (ret) |
| - return ret; |
| - |
| - return 1; |
| -} |
| + /* 3.3V 1Gb (2nd generation) */ |
| + SPINAND_INFO("TC58CVG0S3HRAIJ", |
| + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xE2), |
| + NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1), |
| + NAND_ECCREQ(8, 512), |
| + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, |
| + &write_cache_x4_variants, |
| + &update_cache_x4_variants), |
| + SPINAND_HAS_QE_BIT, |
| + SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout, |
| + tx58cxgxsxraix_ecc_get_status)), |
| + /* 3.3V 2Gb (2nd generation) */ |
| + SPINAND_INFO("TC58CVG1S3HRAIJ", |
| + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xEB), |
| + NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1), |
| + NAND_ECCREQ(8, 512), |
| + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, |
| + &write_cache_x4_variants, |
| + &update_cache_x4_variants), |
| + SPINAND_HAS_QE_BIT, |
| + SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout, |
| + tx58cxgxsxraix_ecc_get_status)), |
| + /* 3.3V 4Gb (2nd generation) */ |
| + SPINAND_INFO("TC58CVG2S0HRAIJ", |
| + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xED), |
| + NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1), |
| + NAND_ECCREQ(8, 512), |
| + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, |
| + &write_cache_x4_variants, |
| + &update_cache_x4_variants), |
| + SPINAND_HAS_QE_BIT, |
| + SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout, |
| + tx58cxgxsxraix_ecc_get_status)), |
| + /* 3.3V 8Gb (2nd generation) */ |
| + SPINAND_INFO("TH58CVG3S0HRAIJ", |
| + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xE4), |
| + NAND_MEMORG(1, 4096, 256, 64, 4096, 80, 1, 1, 1), |
| + NAND_ECCREQ(8, 512), |
| + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, |
| + &write_cache_x4_variants, |
| + &update_cache_x4_variants), |
| + SPINAND_HAS_QE_BIT, |
| + SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout, |
| + tx58cxgxsxraix_ecc_get_status)), |
| + /* 1.8V 1Gb (2nd generation) */ |
| + SPINAND_INFO("TC58CYG0S3HRAIJ", |
| + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xD2), |
| + NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1), |
| + NAND_ECCREQ(8, 512), |
| + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, |
| + &write_cache_x4_variants, |
| + &update_cache_x4_variants), |
| + SPINAND_HAS_QE_BIT, |
| + SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout, |
| + tx58cxgxsxraix_ecc_get_status)), |
| + /* 1.8V 2Gb (2nd generation) */ |
| + SPINAND_INFO("TC58CYG1S3HRAIJ", |
| + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xDB), |
| + NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1), |
| + NAND_ECCREQ(8, 512), |
| + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, |
| + &write_cache_x4_variants, |
| + &update_cache_x4_variants), |
| + SPINAND_HAS_QE_BIT, |
| + SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout, |
| + tx58cxgxsxraix_ecc_get_status)), |
| + /* 1.8V 4Gb (2nd generation) */ |
| + SPINAND_INFO("TC58CYG2S0HRAIJ", |
| + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xDD), |
| + NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1), |
| + NAND_ECCREQ(8, 512), |
| + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, |
| + &write_cache_x4_variants, |
| + &update_cache_x4_variants), |
| + SPINAND_HAS_QE_BIT, |
| + SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout, |
| + tx58cxgxsxraix_ecc_get_status)), |
| + /* 1.8V 8Gb (2nd generation) */ |
| + SPINAND_INFO("TH58CYG3S0HRAIJ", |
| + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xD4), |
| + NAND_MEMORG(1, 4096, 256, 64, 4096, 80, 1, 1, 1), |
| + NAND_ECCREQ(8, 512), |
| + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, |
| + &write_cache_x4_variants, |
| + &update_cache_x4_variants), |
| + SPINAND_HAS_QE_BIT, |
| + SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout, |
| + tx58cxgxsxraix_ecc_get_status)), |
| +}; |
| |
| static const struct spinand_manufacturer_ops toshiba_spinand_manuf_ops = { |
| - .detect = toshiba_spinand_detect, |
| }; |
| |
| const struct spinand_manufacturer toshiba_spinand_manufacturer = { |
| .id = SPINAND_MFR_TOSHIBA, |
| .name = "Toshiba", |
| + .chips = toshiba_spinand_table, |
| + .nchips = ARRAY_SIZE(toshiba_spinand_table), |
| .ops = &toshiba_spinand_manuf_ops, |
| }; |