[][kernel][common][eth][net: phy: mediatek-ge: Fix that calibration result mismatches register value]
[Description]
Fix that calibration result mismatches register value:
[ 2.227748] MediaTek MT7988 PHY mdio-bus@gsw:03: cal_val: 0x4444, ret: 1
[ 2.235345] MediaTek MT7988 PHY mdio-bus@gsw:03: cal_val: 0x2222, ret: 1
[ 2.242940] MediaTek MT7988 PHY mdio-bus@gsw:03: cal_val: 0x1111, ret: 0
--> cal_val==1 will remain in register, however, in this case, we need to
use cal_val==2
[ 2.250537] MediaTek MT7988 PHY mdio-bus@gsw:03: cal_val: 0x2222, ret: 1
--> cal again with cal_val==2
[ 2.257224] MediaTek MT7988 PHY mdio-bus@gsw:03: TX-VCM SW cal result: 0x2
[Release-log]
N/A
Change-Id: Ifac94f7f881d9736215c13afda7ca3decaa074c5
Reviewed-on: https://gerrit.mediatek.inc/c/openwrt/feeds/mtk_openwrt_feeds/+/6394769
diff --git a/target/linux/mediatek/files-5.4/drivers/net/phy/mediatek-ge.c b/target/linux/mediatek/files-5.4/drivers/net/phy/mediatek-ge.c
index c0abdc7..146f15f 100644
--- a/target/linux/mediatek/files-5.4/drivers/net/phy/mediatek-ge.c
+++ b/target/linux/mediatek/files-5.4/drivers/net/phy/mediatek-ge.c
@@ -725,6 +725,11 @@
ret = upper_ret-lower_ret;
if (ret == 1) {
ret = 0;
+ /* Make sure we use upper_idx in our calibration system */
+ cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG9,
+ MTK_PHY_DA_RX_PSBN_TBT_MASK | MTK_PHY_DA_RX_PSBN_HBT_MASK |
+ MTK_PHY_DA_RX_PSBN_GBE_MASK | MTK_PHY_DA_RX_PSBN_LP_MASK,
+ upper_idx << 12 | upper_idx << 8 | upper_idx << 4 | upper_idx);
dev_info(&phydev->mdio.dev, "TX-VCM SW cal result: 0x%x\n", upper_idx);
} else if (lower_idx == TXRESERVE_MIN && upper_ret == 1 && lower_ret == 1) {
ret = 0;