[][kernel][mt7988][eth][Update GMAC connection for the MT7988C]
[Description]
Refactor GMAC connection to meet latest HDK for the MT7988C.
If without this patch, the kernel images cannot run on the latest
MT7988C RFB.
[Release-log]
N/A
Change-Id: I36f970d54ce24939b70deb771d3ebe16576debd2
Reviewed-on: https://gerrit.mediatek.inc/c/openwrt/feeds/mtk_openwrt_feeds/+/7429939
diff --git a/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988c-dsa-10g-emmc.dts b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988c-dsa-10g-emmc.dts
index bbfd3c6..afd03bf 100644
--- a/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988c-dsa-10g-emmc.dts
+++ b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988c-dsa-10g-emmc.dts
@@ -113,6 +113,13 @@
};
};
+ i2p5gbe_led0_pins: 2p5gbe-pins {
+ mux {
+ function = "led";
+ groups = "2p5gbe_led0";
+ };
+ };
+
pcie0_pins: pcie0-pins {
mux {
function = "pcie";
@@ -193,19 +200,35 @@
compatible = "mediatek,eth-mac";
reg = <1>;
mac-type = "xgdm";
- phy-mode = "usxgmii";
+ phy-mode = "xgmii";
phy-handle = <&phy0>;
};
+ gmac2: mac@2 {
+ compatible = "mediatek,eth-mac";
+ reg = <2>;
+ mac-type = "xgdm";
+ phy-mode = "usxgmii";
+ phy-handle = <&phy1>;
+ };
+
mdio: mdio-bus {
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <10500000>;
phy0: ethernet-phy@0 {
- reg = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2p5gbe_led0_pins>;
+ reg = <15>;
+ compatible = "ethernet-phy-ieee802.3-c45";
+ phy-mode = "xgmii";
+ };
+
+ phy1: ethernet-phy@8 {
+ reg = <8>;
compatible = "ethernet-phy-ieee802.3-c45";
- reset-gpios = <&pio 72 1>;
+ reset-gpios = <&pio 3 1>;
reset-assert-us = <100000>;
reset-deassert-us = <221000>;
};
diff --git a/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988c-dsa-10g-sd.dts b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988c-dsa-10g-sd.dts
index 750d9f1..0714bff 100644
--- a/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988c-dsa-10g-sd.dts
+++ b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988c-dsa-10g-sd.dts
@@ -104,6 +104,13 @@
};
};
+ i2p5gbe_led0_pins: 2p5gbe-pins {
+ mux {
+ function = "led";
+ groups = "2p5gbe_led0";
+ };
+ };
+
pcie0_pins: pcie0-pins {
mux {
function = "pcie";
@@ -184,19 +191,35 @@
compatible = "mediatek,eth-mac";
reg = <1>;
mac-type = "xgdm";
- phy-mode = "usxgmii";
+ phy-mode = "xgmii";
phy-handle = <&phy0>;
};
+ gmac2: mac@2 {
+ compatible = "mediatek,eth-mac";
+ reg = <2>;
+ mac-type = "xgdm";
+ phy-mode = "usxgmii";
+ phy-handle = <&phy1>;
+ };
+
mdio: mdio-bus {
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <10500000>;
phy0: ethernet-phy@0 {
- reg = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2p5gbe_led0_pins>;
+ reg = <15>;
+ compatible = "ethernet-phy-ieee802.3-c45";
+ phy-mode = "xgmii";
+ };
+
+ phy1: ethernet-phy@8 {
+ reg = <8>;
compatible = "ethernet-phy-ieee802.3-c45";
- reset-gpios = <&pio 72 1>;
+ reset-gpios = <&pio 3 1>;
reset-assert-us = <100000>;
reset-deassert-us = <221000>;
};
diff --git a/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988c-dsa-10g-snfi-nand.dts b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988c-dsa-10g-snfi-nand.dts
index bdc5d9e..53b9668 100644
--- a/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988c-dsa-10g-snfi-nand.dts
+++ b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988c-dsa-10g-snfi-nand.dts
@@ -138,6 +138,13 @@
};
};
+ i2p5gbe_led0_pins: 2p5gbe-pins {
+ mux {
+ function = "led";
+ groups = "2p5gbe_led0";
+ };
+ };
+
pcie0_pins: pcie0-pins {
mux {
function = "pcie";
@@ -219,19 +226,35 @@
compatible = "mediatek,eth-mac";
reg = <1>;
mac-type = "xgdm";
- phy-mode = "usxgmii";
+ phy-mode = "xgmii";
phy-handle = <&phy0>;
};
+ gmac2: mac@2 {
+ compatible = "mediatek,eth-mac";
+ reg = <2>;
+ mac-type = "xgdm";
+ phy-mode = "usxgmii";
+ phy-handle = <&phy1>;
+ };
+
mdio: mdio-bus {
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <10500000>;
phy0: ethernet-phy@0 {
- reg = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2p5gbe_led0_pins>;
+ reg = <15>;
+ compatible = "ethernet-phy-ieee802.3-c45";
+ phy-mode = "xgmii";
+ };
+
+ phy1: ethernet-phy@8 {
+ reg = <8>;
compatible = "ethernet-phy-ieee802.3-c45";
- reset-gpios = <&pio 72 1>;
+ reset-gpios = <&pio 3 1>;
reset-assert-us = <100000>;
reset-deassert-us = <221000>;
};
diff --git a/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988c-dsa-10g-spim-nand.dts b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988c-dsa-10g-spim-nand.dts
index ba261f6..db03e0b 100644
--- a/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988c-dsa-10g-spim-nand.dts
+++ b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988c-dsa-10g-spim-nand.dts
@@ -258,6 +258,13 @@
};
};
+ i2p5gbe_led0_pins: 2p5gbe-pins {
+ mux {
+ function = "led";
+ groups = "2p5gbe_led0";
+ };
+ };
+
i2c0_pins: i2c0-pins-g0 {
mux {
function = "i2c";
@@ -359,17 +366,33 @@
compatible = "mediatek,eth-mac";
reg = <1>;
mac-type = "xgdm";
- phy-mode = "usxgmii";
+ phy-mode = "xgmii";
phy-handle = <&phy0>;
};
+ gmac2: mac@2 {
+ compatible = "mediatek,eth-mac";
+ reg = <2>;
+ mac-type = "xgdm";
+ phy-mode = "usxgmii";
+ phy-handle = <&phy1>;
+ };
+
mdio: mdio-bus {
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <10500000>;
phy0: ethernet-phy@0 {
- reg = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2p5gbe_led0_pins>;
+ reg = <15>;
+ compatible = "ethernet-phy-ieee802.3-c45";
+ phy-mode = "xgmii";
+ };
+
+ phy1: ethernet-phy@8 {
+ reg = <8>;
compatible = "ethernet-phy-ieee802.3-c45";
reset-gpios = <&pio 3 1>;
reset-assert-us = <100000>;
diff --git a/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988c-dsa-10g-spim-nor.dts b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988c-dsa-10g-spim-nor.dts
index 28c1f7e..c0b7c33 100644
--- a/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988c-dsa-10g-spim-nor.dts
+++ b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988c-dsa-10g-spim-nor.dts
@@ -138,6 +138,13 @@
};
};
+ i2p5gbe_led0_pins: 2p5gbe-pins {
+ mux {
+ function = "led";
+ groups = "2p5gbe_led0";
+ };
+ };
+
pcie0_pins: pcie0-pins {
mux {
function = "pcie";
@@ -211,19 +218,35 @@
compatible = "mediatek,eth-mac";
reg = <1>;
mac-type = "xgdm";
- phy-mode = "usxgmii";
+ phy-mode = "xgmii";
phy-handle = <&phy0>;
};
+ gmac2: mac@2 {
+ compatible = "mediatek,eth-mac";
+ reg = <2>;
+ mac-type = "xgdm";
+ phy-mode = "usxgmii";
+ phy-handle = <&phy1>;
+ };
+
mdio: mdio-bus {
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <10500000>;
phy0: ethernet-phy@0 {
- reg = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2p5gbe_led0_pins>;
+ reg = <15>;
+ compatible = "ethernet-phy-ieee802.3-c45";
+ phy-mode = "xgmii";
+ };
+
+ phy1: ethernet-phy@8 {
+ reg = <8>;
compatible = "ethernet-phy-ieee802.3-c45";
- reset-gpios = <&pio 72 1>;
+ reset-gpios = <&pio 3 1>;
reset-assert-us = <100000>;
reset-deassert-us = <221000>;
};
diff --git a/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988c-dsa-e2p5g-spim-nand.dts b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988c-dsa-e2p5g-spim-nand.dts
index 830b223..6c383fc 100644
--- a/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988c-dsa-e2p5g-spim-nand.dts
+++ b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988c-dsa-e2p5g-spim-nand.dts
@@ -205,6 +205,13 @@
};
};
+ i2p5gbe_led0_pins: 2p5gbe-pins {
+ mux {
+ function = "led";
+ groups = "2p5gbe_led0";
+ };
+ };
+
i2c0_pins: i2c0-pins-g0 {
mux {
function = "i2c";
@@ -289,19 +296,35 @@
gmac1: mac@1 {
compatible = "mediatek,eth-mac";
reg = <1>;
+ mac-type = "xgdm";
+ phy-mode = "xgmii";
+ phy-handle = <&phy0>;
+ };
+
+ gmac2: mac@2 {
+ compatible = "mediatek,eth-mac";
+ reg = <2>;
mac-type = "gdm";
phy-mode = "2500base-x";
- phy-handle = <&phy13>;
+ phy-handle = <&phy5>;
};
mdio: mdio-bus {
#address-cells = <1>;
#size-cells = <0>;
+ phy0: ethernet-phy@0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2p5gbe_led0_pins>;
+ reg = <15>;
+ compatible = "ethernet-phy-ieee802.3-c45";
+ phy-mode = "xgmii";
+ };
+
- phy13: phy@13 {
+ phy5: phy@5 {
compatible = "ethernet-phy-ieee802.3-c45";
- reg = <13>;
- reset-gpios = <&pio 1 1>;
+ reg = <5>;
+ reset-gpios = <&pio 3 1>;
reset-assert-us = <600>;
reset-deassert-us = <20000>;
};
diff --git a/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988c-dsa-i2p5g-spim-nand.dts b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988c-dsa-i2p5g-spim-nand.dts
deleted file mode 100644
index e8b6f14..0000000
--- a/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988c-dsa-i2p5g-spim-nand.dts
+++ /dev/null
@@ -1,340 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (C) 2021 MediaTek Inc.
- * Author: Sam.Shih <sam.shih@mediatek.com>
- */
-
-/dts-v1/;
-#include "mt7988.dtsi"
-
-/ {
- model = "MediaTek MT7988C DSA internal-2.5G SPIM-NAND RFB";
- compatible = "mediatek,mt7988c-dsa-i2p5g-spim-snand",
- /* Reserve this for DVFS if creating new dts */
- "mediatek,mt7988";
-
- chosen {
- bootargs = "console=ttyS0,115200n1 loglevel=8 \
- earlycon=uart8250,mmio32,0x11000000 \
- pci=pcie_bus_perf";
- };
-
- memory {
- reg = <0 0x40000000 0 0x10000000>;
- };
-
- nmbm_spim_nand {
- compatible = "generic,nmbm";
-
- #address-cells = <1>;
- #size-cells = <1>;
-
- lower-mtd-device = <&spi_nand>;
- forced-create;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "BL2";
- reg = <0x00000 0x0100000>;
- read-only;
- };
-
- partition@100000 {
- label = "u-boot-env";
- reg = <0x0100000 0x0080000>;
- };
-
- factory: partition@180000 {
- label = "Factory";
- reg = <0x180000 0x0400000>;
- };
-
- partition@580000 {
- label = "FIP";
- reg = <0x580000 0x0200000>;
- };
-
- partition@780000 {
- label = "ubi";
- reg = <0x780000 0x7080000>;
- };
- };
- };
-
- wsys_adie: wsys_adie@0 {
- // fpga cases need to manual change adie_id / sku_type for dvt only
- compatible = "mediatek,rebb-mt7988-adie";
- adie_id = <7976>;
- sku_type = <3000>;
- };
-};
-
-&uart0 {
- status = "okay";
-};
-
-&spi0 {
- pinctrl-names = "default";
- pinctrl-0 = <&spi0_flash_pins>;
- status = "okay";
-
- spi_nand: spi_nand@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "spi-nand";
- spi-cal-enable;
- spi-cal-mode = "read-data";
- spi-cal-datalen = <7>;
- spi-cal-data = /bits/ 8 <0x53 0x50 0x49 0x4E 0x41 0x4E 0x44>;
- spi-cal-addrlen = <5>;
- spi-cal-addr = /bits/ 32 <0x0 0x0 0x0 0x0 0x0>;
- reg = <0>;
- spi-max-frequency = <52000000>;
- spi-tx-buswidth = <4>;
- spi-rx-buswidth = <4>;
- };
-};
-
-&spi1 {
- pinctrl-names = "default";
- /* pin shared with snfi */
- pinctrl-0 = <&spic_pins>;
- status = "disabled";
-};
-
-&pcie0 {
- pinctrl-names = "default";
- pinctrl-0 = <&pcie0_pins>;
- status = "okay";
-};
-
-&pcie1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pcie1_pins>;
- status = "disabled";
-};
-
-&pcie2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pcie2_pins>;
- status = "disabled";
-};
-
-&pcie3 {
- pinctrl-names = "default";
- pinctrl-0 = <&pcie3_pins>;
- status = "okay";
-};
-
-&pio {
- gbe_led0_pins: gbe-pins {
- mux {
- function = "led";
- groups = "gbe_led0";
- };
- };
-
- i2p5gbe_led0_pins: 2p5gbe-pins {
- mux {
- function = "led";
- groups = "2p5gbe_led0";
- };
- };
-
- pcie0_pins: pcie0-pins {
- mux {
- function = "pcie";
- groups = "pcie_2l_0_pereset", "pcie_clk_req_n0_0",
- "pcie_wake_n0_0";
- };
- };
-
- pcie1_pins: pcie1-pins {
- mux {
- function = "pcie";
- groups = "pcie_2l_1_pereset", "pcie_clk_req_n1",
- "pcie_wake_n1_0";
- };
- };
-
- pcie2_pins: pcie2-pins {
- mux {
- function = "pcie";
- groups = "pcie_1l_0_pereset", "pcie_clk_req_n2_0",
- "pcie_wake_n2_0";
- };
- };
-
- pcie3_pins: pcie3-pins {
- mux {
- function = "pcie";
- groups = "pcie_1l_1_pereset", "pcie_clk_req_n3",
- "pcie_wake_n3_0";
- };
- };
-
- spi0_flash_pins: spi0-pins {
- mux {
- function = "spi";
- groups = "spi0", "spi0_wp_hold";
- };
- };
-
- spic_pins: spi1-pins {
- mux {
- function = "spi";
- groups = "spi1";
- };
- };
-};
-
-&watchdog {
- status = "disabled";
-};
-
-ð {
- status = "okay";
-
- gmac0: mac@0 {
- compatible = "mediatek,eth-mac";
- reg = <0>;
- mac-type = "xgdm";
- phy-mode = "10gbase-kr";
-
- fixed-link {
- speed = <10000>;
- full-duplex;
- pause;
- };
- };
-
- gmac1: mac@1 {
- compatible = "mediatek,eth-mac";
- reg = <1>;
- mac-type = "xgdm";
- phy-mode = "xgmii";
- phy-handle = <&phy0>;
- };
-
- mdio: mdio-bus {
- #address-cells = <1>;
- #size-cells = <0>;
- phy0: ethernet-phy@0 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2p5gbe_led0_pins>;
- reg = <15>;
- compatible = "ethernet-phy-ieee802.3-c45";
- phy-mode = "xgmii";
- };
-
- switch@0 {
- compatible = "mediatek,mt7988";
- reg = <31>;
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- label = "lan0";
- phy-mode = "gmii";
- phy-handle = <&sphy0>;
- };
-
- port@1 {
- reg = <1>;
- label = "lan1";
- phy-mode = "gmii";
- phy-handle = <&sphy1>;
- };
-
- port@2 {
- reg = <2>;
- label = "lan2";
- phy-mode = "gmii";
- phy-handle = <&sphy2>;
- };
-
- port@3 {
- reg = <3>;
- label = "lan3";
- phy-mode = "gmii";
- phy-handle = <&sphy3>;
- };
-
- port@6 {
- reg = <6>;
- label = "cpu";
- ethernet = <&gmac0>;
- phy-mode = "10gbase-kr";
-
- fixed-link {
- speed = <10000>;
- full-duplex;
- pause;
- };
- };
- };
-
- mdio {
- compatible = "mediatek,dsa-slave-mdio";
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&gbe_led0_pins>;
-
- sphy0: switch_phy0@0 {
- compatible = "ethernet-phy-id03a2.9481";
- reg = <0>;
- phy-mode = "gmii";
- rext = "efuse";
- tx_r50 = "efuse";
- nvmem-cells = <&phy_calibration_p0>;
- nvmem-cell-names = "phy-cal-data";
- };
-
- sphy1: switch_phy1@1 {
- compatible = "ethernet-phy-id03a2.9481";
- reg = <1>;
- phy-mode = "gmii";
- rext = "efuse";
- tx_r50 = "efuse";
- nvmem-cells = <&phy_calibration_p1>;
- nvmem-cell-names = "phy-cal-data";
- };
-
- sphy2: switch_phy2@2 {
- compatible = "ethernet-phy-id03a2.9481";
- reg = <2>;
- phy-mode = "gmii";
- rext = "efuse";
- tx_r50 = "efuse";
- nvmem-cells = <&phy_calibration_p2>;
- nvmem-cell-names = "phy-cal-data";
- };
-
- sphy3: switch_phy3@3 {
- compatible = "ethernet-phy-id03a2.9481";
- reg = <3>;
- phy-mode = "gmii";
- rext = "efuse";
- tx_r50 = "efuse";
- nvmem-cells = <&phy_calibration_p3>;
- nvmem-cell-names = "phy-cal-data";
- };
- };
- };
- };
-};
-
-&hnat {
- mtketh-wan = "eth1";
- mtketh-lan = "lan";
- mtketh-lan2 = "eth2";
- mtketh-max-gmac = <3>;
- status = "okay";
-};
diff --git a/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988c-gsw-10g-sfp-spim-nand.dts b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988c-gsw-10g-sfp-spim-nand.dts
index 8c0436c..2185239 100644
--- a/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988c-gsw-10g-sfp-spim-nand.dts
+++ b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988c-gsw-10g-sfp-spim-nand.dts
@@ -219,6 +219,13 @@
};
};
+ i2p5gbe_led0_pins: 2p5gbe-pins {
+ mux {
+ function = "led";
+ groups = "2p5gbe_led0";
+ };
+ };
+
i2c0_pins: i2c0-pins-g0 {
mux {
function = "i2c";
@@ -304,6 +311,14 @@
compatible = "mediatek,eth-mac";
reg = <1>;
mac-type = "xgdm";
+ phy-mode = "xgmii";
+ phy-handle = <&phy0>;
+ };
+
+ gmac2: mac@2 {
+ compatible = "mediatek,eth-mac";
+ reg = <2>;
+ mac-type = "xgdm";
phy-mode = "10gbase-kr";
managed = "in-band-status";
sfp = <&sfp_esp0>;
@@ -312,6 +327,15 @@
mdio: mdio-bus {
#address-cells = <1>;
#size-cells = <0>;
+
+ phy0: ethernet-phy@0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2p5gbe_led0_pins>;
+ reg = <15>;
+ compatible = "ethernet-phy-ieee802.3-c45";
+ phy-mode = "xgmii";
+ };
+
};
};
diff --git a/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988c-gsw-10g-spim-nand.dts b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988c-gsw-10g-spim-nand.dts
index af63d6c..301d1ea 100644
--- a/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988c-gsw-10g-spim-nand.dts
+++ b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988c-gsw-10g-spim-nand.dts
@@ -234,6 +234,13 @@
};
};
+ i2p5gbe_led0_pins: 2p5gbe-pins {
+ mux {
+ function = "led";
+ groups = "2p5gbe_led0";
+ };
+ };
+
i2c0_pins: i2c0-pins-g0 {
mux {
function = "i2c";
@@ -335,19 +342,35 @@
compatible = "mediatek,eth-mac";
reg = <1>;
mac-type = "xgdm";
- phy-mode = "usxgmii";
+ phy-mode = "xgmii";
phy-handle = <&phy0>;
};
+ gmac2: mac@2 {
+ compatible = "mediatek,eth-mac";
+ reg = <2>;
+ mac-type = "xgdm";
+ phy-mode = "usxgmii";
+ phy-handle = <&phy1>;
+ };
+
mdio: mdio-bus {
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <10500000>;
phy0: ethernet-phy@0 {
- reg = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2p5gbe_led0_pins>;
+ reg = <15>;
+ compatible = "ethernet-phy-ieee802.3-c45";
+ phy-mode = "xgmii";
+ };
+
+ phy1: ethernet-phy@8 {
+ reg = <8>;
compatible = "ethernet-phy-ieee802.3-c45";
- reset-gpios = <&pio 72 1>;
+ reset-gpios = <&pio 3 1>;
reset-assert-us = <100000>;
reset-deassert-us = <221000>;
};
diff --git a/target/linux/mediatek/image/mt7988.mk b/target/linux/mediatek/image/mt7988.mk
index e3b73a2..82402da 100644
--- a/target/linux/mediatek/image/mt7988.mk
+++ b/target/linux/mediatek/image/mt7988.mk
@@ -276,23 +276,6 @@
endef
TARGET_DEVICES += mediatek_mt7988c-dsa-e2p5g-spim-nand
-define Device/mediatek_mt7988c-dsa-i2p5g-spim-nand
- DEVICE_VENDOR := MediaTek
- DEVICE_MODEL := mt7988c-dsa-i2p5g-spim-nand
- DEVICE_DTS := mt7988c-dsa-i2p5g-spim-nand
- DEVICE_DTS_DIR := $(DTS_DIR)/mediatek
- SUPPORTED_DEVICES := mediatek,mt7988c-dsa-i2p5g-spim-nand
- UBINIZE_OPTS := -E 5
- BLOCKSIZE := 128k
- PAGESIZE := 2048
- IMAGE_SIZE := 65536k
- KERNEL_IN_UBI := 1
- IMAGES += factory.bin
- IMAGE/factory.bin := append-ubi | check-size $$$$(IMAGE_SIZE)
- IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata
-endef
-TARGET_DEVICES += mediatek_mt7988c-dsa-i2p5g-spim-nand
-
define Device/mediatek_mt7988c-dsa-10g-snfi-nand
DEVICE_VENDOR := MediaTek
DEVICE_MODEL := mt7988c-dsa-10g-snfi-nand