| /* |
| * Copyright (c) 2020 MediaTek Inc. |
| * Author: Sam.Shih <sam.shih@mediatek.com> |
| * |
| * This program is free software; you can redistribute it and/or modify |
| * it under the terms of the GNU General Public License version 2 as |
| * published by the Free Software Foundation. |
| * |
| * This program is distributed in the hope that it will be useful, |
| * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| * GNU General Public License for more details. |
| */ |
| |
| #include <dt-bindings/interrupt-controller/irq.h> |
| #include <dt-bindings/interrupt-controller/arm-gic.h> |
| #include <dt-bindings/phy/phy.h> |
| #include <dt-bindings/reset/ti-syscon.h> |
| #include <dt-bindings/clock/mt7981-clk.h> |
| #include <dt-bindings/pinctrl/mt65xx.h> |
| #include <dt-bindings/input/linux-event-codes.h> |
| #include <dt-bindings/gpio/gpio.h> |
| |
| / { |
| compatible = "mediatek,mt7981-rfb"; |
| interrupt-parent = <&gic>; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| cpus { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| cpu@0 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a53"; |
| enable-method = "psci"; |
| reg = <0x0>; |
| }; |
| |
| cpu@1 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a53"; |
| enable-method = "psci"; |
| reg = <0x1>; |
| }; |
| }; |
| |
| pwm: pwm@10048000 { |
| compatible = "mediatek,mt7981-pwm"; |
| reg = <0 0x10048000 0 0x1000>; |
| #pwm-cells = <2>; |
| clocks = <&infracfg_ao CK_INFRA_PWM_STA>, |
| <&infracfg_ao CK_INFRA_PWM_HCK>, |
| <&infracfg_ao CK_INFRA_PWM1_CK>, |
| <&infracfg_ao CK_INFRA_PWM2_CK>, |
| <&infracfg_ao CK_INFRA_PWM3_CK>; |
| clock-names = "top", "main", "pwm1", "pwm2", "pwm3"; |
| }; |
| |
| thermal-zones { |
| cpu_thermal: cpu-thermal { |
| polling-delay-passive = <1000>; |
| polling-delay = <1000>; |
| thermal-sensors = <&thermal 0>; |
| }; |
| }; |
| |
| thermal: thermal@1100c800 { |
| #thermal-sensor-cells = <1>; |
| compatible = "mediatek,mt7981-thermal"; |
| reg = <0 0x1100c800 0 0x800>; |
| interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&infracfg_ao CK_INFRA_THERM_CK>, |
| <&infracfg_ao CK_INFRA_ADC_26M_CK>, |
| <&infracfg_ao CK_INFRA_ADC_FRC_CK>; |
| clock-names = "therm", "auxadc", "adc_32k"; |
| mediatek,auxadc = <&auxadc>; |
| mediatek,apmixedsys = <&apmixedsys>; |
| nvmem-cells = <&thermal_calibration>; |
| nvmem-cell-names = "calibration-data"; |
| }; |
| |
| auxadc: adc@1100d000 { |
| compatible = "mediatek,mt7981-auxadc", |
| "mediatek,mt7622-auxadc"; |
| reg = <0 0x1100d000 0 0x1000>; |
| clocks = <&infracfg_ao CK_INFRA_ADC_26M_CK>, |
| <&infracfg_ao CK_INFRA_ADC_FRC_CK>; |
| clock-names = "main", "32k"; |
| #io-channel-cells = <1>; |
| }; |
| |
| wed: wed@15010000 { |
| compatible = "mediatek,wed"; |
| wed_num = <2>; |
| /* add this property for wed get the pci slot number. */ |
| pci_slot_map = <0>, <1>; |
| reg = <0 0x15010000 0 0x1000>, |
| <0 0x15011000 0 0x1000>; |
| interrupt-parent = <&gic>; |
| interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| wdma: wdma@15104800 { |
| compatible = "mediatek,wed-wdma"; |
| reg = <0 0x15104800 0 0x400>, |
| <0 0x15104c00 0 0x400>; |
| }; |
| |
| ap2woccif: ap2woccif@151A5000 { |
| compatible = "mediatek,ap2woccif"; |
| reg = <0 0x151A5000 0 0x1000>, |
| <0 0x151AD000 0 0x1000>; |
| interrupt-parent = <&gic>; |
| interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| wocpu0_ilm: wocpu0_ilm@151E0000 { |
| compatible = "mediatek,wocpu0_ilm"; |
| reg = <0 0x151E0000 0 0x8000>; |
| }; |
| |
| wocpu_dlm: wocpu_dlm@151E8000 { |
| compatible = "mediatek,wocpu_dlm"; |
| reg = <0 0x151E8000 0 0x2000>, |
| <0 0x151F8000 0 0x2000>; |
| |
| resets = <ðsysrst 0>; |
| reset-names = "wocpu_rst"; |
| }; |
| |
| cpu_boot: wocpu_boot@15194000 { |
| compatible = "mediatek,wocpu_boot"; |
| reg = <0 0x15194000 0 0x1000>; |
| }; |
| |
| reserved-memory { |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| |
| /* 192 KiB reserved for ARM Trusted Firmware (BL31) */ |
| secmon_reserved: secmon@43000000 { |
| reg = <0 0x43000000 0 0x30000>; |
| no-map; |
| }; |
| |
| wmcpu_emi: wmcpu-reserved@47C80000 { |
| compatible = "mediatek,wmcpu-reserved"; |
| no-map; |
| reg = <0 0x47C80000 0 0x00100000>; |
| }; |
| |
| wocpu0_emi: wocpu0_emi@47D80000 { |
| compatible = "mediatek,wocpu0_emi"; |
| no-map; |
| reg = <0 0x47D80000 0 0x40000>; |
| shared = <0>; |
| }; |
| |
| wocpu_data: wocpu_data@47DC0000 { |
| compatible = "mediatek,wocpu_data"; |
| no-map; |
| reg = <0 0x47DC0000 0 0x240000>; |
| shared = <1>; |
| }; |
| }; |
| |
| psci { |
| compatible = "arm,psci-0.2"; |
| method = "smc"; |
| }; |
| |
| clk40m: oscillator@0 { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <40000000>; |
| clock-output-names = "clkxtal"; |
| }; |
| |
| infracfg_ao: infracfg_ao@10001000 { |
| compatible = "mediatek,mt7981-infracfg_ao", "syscon"; |
| reg = <0 0x10001000 0 0x68>; |
| #clock-cells = <1>; |
| }; |
| |
| infracfg: infracfg@10001040 { |
| compatible = "mediatek,mt7981-infracfg", "syscon"; |
| reg = <0 0x10001068 0 0x1000>; |
| #clock-cells = <1>; |
| }; |
| |
| topckgen: topckgen@1001B000 { |
| compatible = "mediatek,mt7981-topckgen", "syscon"; |
| reg = <0 0x1001B000 0 0x1000>; |
| #clock-cells = <1>; |
| }; |
| |
| apmixedsys: apmixedsys@1001E000 { |
| compatible = "mediatek,mt7981-apmixedsys", "syscon"; |
| reg = <0 0x1001E000 0 0x1000>; |
| #clock-cells = <1>; |
| }; |
| |
| system_clk: dummy_system_clk { |
| compatible = "fixed-clock"; |
| clock-frequency = <40000000>; |
| #clock-cells = <0>; |
| }; |
| |
| gpt_clk: dummy_gpt_clk { |
| compatible = "fixed-clock"; |
| clock-frequency = <20000000>; |
| #clock-cells = <0>; |
| }; |
| |
| timer { |
| compatible = "arm,armv8-timer"; |
| interrupt-parent = <&gic>; |
| clock-frequency = <13000000>; |
| interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, |
| <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, |
| <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, |
| <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; |
| |
| }; |
| |
| watchdog: watchdog@1001c000 { |
| compatible = "mediatek,mt7622-wdt", |
| "mediatek,mt6589-wdt"; |
| reg = <0 0x1001c000 0 0x1000>; |
| interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; |
| #reset-cells = <1>; |
| }; |
| |
| gic: interrupt-controller@c000000 { |
| compatible = "arm,gic-v3"; |
| #interrupt-cells = <3>; |
| interrupt-parent = <&gic>; |
| interrupt-controller; |
| reg = <0 0x0c000000 0 0x40000>, /* GICD */ |
| <0 0x0c080000 0 0x200000>; /* GICR */ |
| |
| interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| trng: trng@1020f000 { |
| compatible = "mediatek,mt7981-rng"; |
| }; |
| |
| uart0: serial@11002000 { |
| compatible = "mediatek,mt6577-uart"; |
| reg = <0 0x11002000 0 0x400>; |
| interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&infracfg_ao CK_INFRA_UART0_CK>; |
| assigned-clocks = <&topckgen CK_TOP_UART_SEL>, |
| <&infracfg_ao CK_INFRA_UART0_SEL>; |
| assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>, |
| <&infracfg CK_INFRA_UART>; |
| status = "disabled"; |
| }; |
| |
| uart1: serial@11003000 { |
| compatible = "mediatek,mt6577-uart"; |
| reg = <0 0x11003000 0 0x400>; |
| interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&infracfg_ao CK_INFRA_UART1_CK>; |
| assigned-clocks = <&topckgen CK_TOP_UART_SEL>, |
| <&infracfg_ao CK_INFRA_UART1_SEL>; |
| assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>, |
| <&infracfg CK_INFRA_UART>; |
| status = "disabled"; |
| }; |
| |
| uart2: serial@11004000 { |
| compatible = "mediatek,mt6577-uart"; |
| reg = <0 0x11004000 0 0x400>; |
| interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&infracfg_ao CK_INFRA_UART2_CK>; |
| assigned-clocks = <&topckgen CK_TOP_UART_SEL>, |
| <&infracfg_ao CK_INFRA_UART2_SEL>; |
| assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>, |
| <&infracfg CK_INFRA_UART>; |
| status = "disabled"; |
| }; |
| |
| i2c0: i2c@11007000 { |
| compatible = "mediatek,mt7981-i2c"; |
| reg = <0 0x11007000 0 0x1000>, |
| <0 0x10217080 0 0x80>; |
| interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; |
| clock-div = <1>; |
| clocks = <&infracfg_ao CK_INFRA_I2CO_CK>, |
| <&infracfg_ao CK_INFRA_AP_DMA_CK>; |
| clock-names = "main", "dma"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| pcie: pcie@11280000 { |
| compatible = "mediatek,mt7981-pcie", |
| "mediatek,mt7986-pcie"; |
| device_type = "pci"; |
| reg = <0 0x11280000 0 0x4000>; |
| reg-names = "pcie-mac"; |
| #address-cells = <3>; |
| #size-cells = <2>; |
| interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; |
| bus-range = <0x00 0xff>; |
| ranges = <0x82000000 0 0x20000000 |
| 0x0 0x20000000 0 0x10000000>; |
| status = "disabled"; |
| |
| clocks = <&infracfg_ao CK_INFRA_IPCIE_CK>, |
| <&infracfg_ao CK_INFRA_IPCIE_PIPE_CK>, |
| <&infracfg_ao CK_INFRA_IPCIER_CK>, |
| <&infracfg_ao CK_INFRA_IPCIEB_CK>; |
| |
| phys = <&u3port0 PHY_TYPE_PCIE>; |
| phy-names = "pcie-phy"; |
| |
| #interrupt-cells = <1>; |
| interrupt-map-mask = <0 0 0 7>; |
| interrupt-map = <0 0 0 1 &pcie_intc 0>, |
| <0 0 0 2 &pcie_intc 1>, |
| <0 0 0 3 &pcie_intc 2>, |
| <0 0 0 4 &pcie_intc 3>; |
| pcie_intc: interrupt-controller { |
| interrupt-controller; |
| #address-cells = <0>; |
| #interrupt-cells = <1>; |
| }; |
| }; |
| |
| crypto: crypto@10320000 { |
| compatible = "inside-secure,safexcel-eip97"; |
| reg = <0 0x10320000 0 0x40000>; |
| interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "ring0", "ring1", "ring2", "ring3"; |
| clocks = <&topckgen CK_TOP_EIP97B>; |
| clock-names = "top_eip97_ck"; |
| assigned-clocks = <&topckgen CK_TOP_EIP97B_SEL>; |
| assigned-clock-parents = <&topckgen CK_TOP_CB_NET1_D5>; |
| }; |
| |
| pio: pinctrl@11d00000 { |
| compatible = "mediatek,mt7981-pinctrl"; |
| reg = <0 0x11d00000 0 0x1000>, |
| <0 0x11c00000 0 0x1000>, |
| <0 0x11c10000 0 0x1000>, |
| <0 0x11d20000 0 0x1000>, |
| <0 0x11e00000 0 0x1000>, |
| <0 0x11e20000 0 0x1000>, |
| <0 0x11f00000 0 0x1000>, |
| <0 0x11f10000 0 0x1000>, |
| <0 0x1000b000 0 0x1000>; |
| reg-names = "gpio_base", "iocfg_rt_base", "iocfg_rm_base", |
| "iocfg_rb_base", "iocfg_lb_base", "iocfg_bl_base", |
| "iocfg_tm_base", "iocfg_tl_base", "eint"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| gpio-ranges = <&pio 0 0 56>; |
| interrupt-controller; |
| interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-parent = <&gic>; |
| #interrupt-cells = <2>; |
| }; |
| |
| ethsys: syscon@15000000 { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| compatible = "mediatek,mt7981-ethsys", |
| "syscon"; |
| reg = <0 0x15000000 0 0x1000>; |
| #clock-cells = <1>; |
| #reset-cells = <1>; |
| |
| ethsysrst: reset-controller { |
| compatible = "ti,syscon-reset"; |
| #reset-cells = <1>; |
| ti,reset-bits = <0x34 4 0x34 4 0x34 4 (ASSERT_SET | DEASSERT_CLEAR | STATUS_SET)>; |
| }; |
| }; |
| |
| eth: ethernet@15100000 { |
| compatible = "mediatek,mt7981-eth"; |
| reg = <0 0x15100000 0 0x80000>; |
| interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <ðsys CK_ETH_FE_EN>, |
| <ðsys CK_ETH_GP2_EN>, |
| <ðsys CK_ETH_GP1_EN>, |
| <ðsys CK_ETH_WOCPU0_EN>, |
| <&sgmiisys0 CK_SGM0_TX_EN>, |
| <&sgmiisys0 CK_SGM0_RX_EN>, |
| <&sgmiisys0 CK_SGM0_CK0_EN>, |
| <&sgmiisys0 CK_SGM0_CDR_CK0_EN>, |
| <&sgmiisys1 CK_SGM1_TX_EN>, |
| <&sgmiisys1 CK_SGM1_RX_EN>, |
| <&sgmiisys1 CK_SGM1_CK1_EN>, |
| <&sgmiisys1 CK_SGM1_CDR_CK1_EN>; |
| clock-names = "fe", "gp2", "gp1", "wocpu0", |
| "sgmii_tx250m", "sgmii_rx250m", |
| "sgmii_cdr_ref", "sgmii_cdr_fb", |
| "sgmii2_tx250m", "sgmii2_rx250m", |
| "sgmii2_cdr_ref", "sgmii2_cdr_fb"; |
| assigned-clocks = <&topckgen CK_TOP_NETSYS_2X_SEL>, |
| <&topckgen CK_TOP_SGM_325M_SEL>; |
| assigned-clock-parents = <&topckgen CK_TOP_CB_NET2_800M>, |
| <&topckgen CK_TOP_CB_SGM_325M>; |
| mediatek,ethsys = <ðsys>; |
| mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>; |
| mediatek,infracfg = <&topmisc>; |
| #reset-cells = <1>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| hnat: hnat@15000000 { |
| compatible = "mediatek,mtk-hnat_v4"; |
| reg = <0 0x15100000 0 0x80000>; |
| resets = <ðsys 0>; |
| reset-names = "mtketh"; |
| status = "disabled"; |
| }; |
| |
| sgmiisys0: syscon@10060000 { |
| compatible = "mediatek,mt7981-sgmiisys_0", "syscon"; |
| reg = <0 0x10060000 0 0x1000>; |
| pn_swap; |
| #clock-cells = <1>; |
| }; |
| |
| sgmiisys1: syscon@10070000 { |
| compatible = "mediatek,mt7981-sgmiisys_1", "syscon"; |
| reg = <0 0x10070000 0 0x1000>; |
| #clock-cells = <1>; |
| }; |
| |
| topmisc: topmisc@11d10000 { |
| compatible = "mediatek,mt7981-topmisc", "syscon"; |
| reg = <0 0x11d10000 0 0x10000>; |
| #clock-cells = <1>; |
| }; |
| |
| snand: snfi@11005000 { |
| compatible = "mediatek,mt7986-snand"; |
| reg = <0 0x11005000 0 0x1000>, <0 0x11006000 0 0x1000>; |
| reg-names = "nfi", "ecc"; |
| interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&infracfg_ao CK_INFRA_SPINFI1_CK>, |
| <&infracfg_ao CK_INFRA_NFI1_CK>, |
| <&infracfg_ao CK_INFRA_NFI_HCK_CK>; |
| clock-names = "pad_clk", "nfi_clk", "nfi_hclk"; |
| assigned-clocks = <&topckgen CK_TOP_SPINFI_SEL>, |
| <&topckgen CK_TOP_NFI1X_SEL>; |
| assigned-clock-parents = <&topckgen CK_TOP_CB_M_D8>, |
| <&topckgen CK_TOP_CB_M_D8>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| mmc0: mmc@11230000 { |
| compatible = "mediatek,mt7986-mmc", |
| "mediatek,mt7981-mmc"; |
| reg = <0 0x11230000 0 0x1000>, <0 0x11c20000 0 0x1000>; |
| interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&topckgen CK_TOP_EMMC_208M>, |
| <&topckgen CK_TOP_EMMC_400M>, |
| <&infracfg_ao CK_INFRA_MSDC_CK>; |
| assigned-clocks = <&topckgen CK_TOP_EMMC_208M_SEL>, |
| <&topckgen CK_TOP_EMMC_400M_SEL>; |
| assigned-clock-parents = <&topckgen CK_TOP_CB_M_D2>, |
| <&topckgen CK_TOP_CB_NET2_D2>; |
| clock-names = "source", "hclk", "source_cg"; |
| status = "disabled"; |
| }; |
| |
| wbsys: wbsys@18000000 { |
| compatible = "mediatek,wbsys"; |
| reg = <0 0x18000000 0 0x1000000>; |
| interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>; |
| chip_id = <0x7981>; |
| }; |
| |
| wed_pcie: wed_pcie@10003000 { |
| compatible = "mediatek,wed_pcie"; |
| reg = <0 0x10003000 0 0x10>; |
| }; |
| |
| spi0: spi@1100a000 { |
| compatible = "mediatek,ipm-spi-quad"; |
| reg = <0 0x1100a000 0 0x100>; |
| interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&topckgen CK_TOP_CB_M_D2>, |
| <&topckgen CK_TOP_SPI_SEL>, |
| <&infracfg_ao CK_INFRA_SPI0_CK>, |
| <&infracfg_ao CK_INFRA_SPI0_HCK_CK>; |
| clock-names = "parent-clk", "sel-clk", "spi-clk", "spi-hclk"; |
| status = "disabled"; |
| }; |
| |
| spi1: spi@1100b000 { |
| compatible = "mediatek,ipm-spi-single"; |
| reg = <0 0x1100b000 0 0x100>; |
| interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&topckgen CK_TOP_CB_M_D2>, |
| <&topckgen CK_TOP_SPIM_MST_SEL>, |
| <&infracfg_ao CK_INFRA_SPI1_CK>, |
| <&infracfg_ao CK_INFRA_SPI1_HCK_CK>; |
| clock-names = "parent-clk", "sel-clk", "spi-clk", "spi-hclk"; |
| status = "disabled"; |
| }; |
| |
| spi2: spi@11009000 { |
| compatible = "mediatek,ipm-spi-quad"; |
| reg = <0 0x11009000 0 0x100>; |
| interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&topckgen CK_TOP_CB_M_D2>, |
| <&topckgen CK_TOP_SPI_SEL>, |
| <&infracfg_ao CK_INFRA_SPI2_CK>, |
| <&infracfg_ao CK_INFRA_SPI2_HCK_CK>; |
| clock-names = "parent-clk", "sel-clk", "spi-clk", "spi-hclk"; |
| status = "disabled"; |
| }; |
| |
| |
| consys: consys@10000000 { |
| compatible = "mediatek,mt7981-consys"; |
| reg = <0 0x10000000 0 0x8600000>; |
| memory-region = <&wmcpu_emi>; |
| }; |
| |
| xhci: xhci@11200000 { |
| compatible = "mediatek,mt7986-xhci", |
| "mediatek,mtk-xhci"; |
| reg = <0 0x11200000 0 0x2e00>, |
| <0 0x11203e00 0 0x0100>; |
| reg-names = "mac", "ippc"; |
| interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; |
| phys = <&u2port0 PHY_TYPE_USB2>; |
| clocks = <&system_clk>, |
| <&system_clk>, |
| <&system_clk>, |
| <&system_clk>, |
| <&system_clk>; |
| clock-names = "sys_ck", |
| "xhci_ck", |
| "ref_ck", |
| "mcu_ck", |
| "dma_ck"; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| mediatek,u3p-dis-msk = <0x01>; |
| status = "disabled"; |
| }; |
| |
| usbtphy: usb-phy@11e10000 { |
| compatible = "mediatek,mt7986", |
| "mediatek,generic-tphy-v2"; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| status = "okay"; |
| |
| u2port0: usb-phy@11e10000 { |
| reg = <0 0x11e10000 0 0x700>; |
| clocks = <&system_clk>; |
| clock-names = "ref"; |
| #phy-cells = <1>; |
| status = "okay"; |
| }; |
| |
| u3port0: usb-phy@11e10700 { |
| reg = <0 0x11e10700 0 0x900>; |
| clocks = <&system_clk>; |
| clock-names = "ref"; |
| #phy-cells = <1>; |
| mediatek,syscon-type = <&topmisc 0x218 0>; |
| nvmem-cells = <&comb_intr_p0>, |
| <&comb_rx_imp_p0>, |
| <&comb_tx_imp_p0>; |
| nvmem-cell-names = "intr", "rx_imp", "tx_imp"; |
| status = "okay"; |
| }; |
| }; |
| |
| reg_3p3v: regulator-3p3v { |
| compatible = "regulator-fixed"; |
| regulator-name = "fixed-3.3V"; |
| regulator-min-microvolt = <3300000>; |
| regulator-max-microvolt = <3300000>; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| |
| clkitg: clkitg { |
| compatible = "simple-bus"; |
| }; |
| |
| efuse: efuse@11f20000 { |
| compatible = "mediatek,efuse"; |
| reg = <0 0x11f20000 0 0x1000>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| |
| thermal_calibration: calib@274 { |
| reg = <0x274 0xc>; |
| }; |
| |
| phy_calibration: calib@8dc { |
| reg = <0x8dc 0x10>; |
| }; |
| |
| comb_rx_imp_p0: usb3-rx-imp@8c8 { |
| reg = <0x8c8 1>; |
| bits = <0 5>; |
| }; |
| |
| comb_tx_imp_p0: usb3-tx-imp@8c8 { |
| reg = <0x8c8 2>; |
| bits = <5 5>; |
| }; |
| |
| comb_intr_p0: usb3-intr@8c9 { |
| reg = <0x8c9 1>; |
| bits = <2 6>; |
| }; |
| }; |
| |
| afe: audio-controller@11210000 { |
| compatible = "mediatek,mt79xx-audio"; |
| reg = <0 0x11210000 0 0x9000>; |
| interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&infracfg_ao CK_INFRA_AUD_BUS_CK>, |
| <&infracfg_ao CK_INFRA_AUD_26M_CK>, |
| <&infracfg_ao CK_INFRA_AUD_L_CK>, |
| <&infracfg_ao CK_INFRA_AUD_AUD_CK>, |
| <&infracfg_ao CK_INFRA_AUD_EG2_CK>, |
| <&topckgen CK_TOP_AUD_SEL>; |
| clock-names = "aud_bus_ck", |
| "aud_26m_ck", |
| "aud_l_ck", |
| "aud_aud_ck", |
| "aud_eg2_ck", |
| "aud_sel"; |
| assigned-clocks = <&topckgen CK_TOP_AUD_SEL>, |
| <&topckgen CK_TOP_A1SYS_SEL>, |
| <&topckgen CK_TOP_AUD_L_SEL>, |
| <&topckgen CK_TOP_A_TUNER_SEL>; |
| assigned-clock-parents = <&topckgen CK_TOP_CB_APLL2_196M>, |
| <&topckgen CK_TOP_APLL2_D4>, |
| <&topckgen CK_TOP_CB_APLL2_196M>, |
| <&topckgen CK_TOP_APLL2_D4>; |
| status = "disabled"; |
| }; |
| |
| ice: ice_debug { |
| compatible = "mediatek,mt7981-ice_debug", |
| "mediatek,mt2701-ice_debug"; |
| clocks = <&infracfg_ao CK_INFRA_DBG_CK>; |
| clock-names = "ice_dbg"; |
| }; |
| }; |
| #include "mt7981-clkitg.dtsi" |