[][kernel][mt7986/mt7981][eth][Add Ethernet RSS support for Panther and Cheetah]
[Description]
Add Ethernet RSS (receive side scaling) support for Panther and Cheetah.
The main purpose of RSS is to increase the utilization rate
of each CPU as much as possible to prevent the performance
from not being fully demonstrated.
In order to improve software path peak throughput, it's
necessary to enble RSS to hash Rx packets among multi-cores.
If without this patch, Panther and Cheetah software path can't meet peak
throughput requirement.
[Release-log]
N/A
Change-Id: Ib6b18a8ab6a5580a85a3c68964c2b41906e25cfb
Reviewed-on: https://gerrit.mediatek.inc/c/openwrt/feeds/mtk_openwrt_feeds/+/7986183
diff --git a/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.c
index b0cfc66..1b01406 100644
--- a/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.c
@@ -3141,9 +3141,6 @@
/* Enable RSS dly int supoort */
val |= MTK_LRO_DLY_INT_EN;
mtk_w32(eth, val, MTK_PDMA_LRO_CTRL_DW0);
-
- /* Set RSS delay config int ring1 */
- mtk_w32(eth, MTK_MAX_DELAY_INT, MTK_LRO_RX1_DLY_INT);
}
/* Hash Type */
@@ -3182,7 +3179,12 @@
mtk_w32(eth, 0x210FFFF2, MTK_FE_INT_GRP);
/* Enable RSS delay interrupt */
- mtk_w32(eth, 0x8f0f8f0f, MTK_PDMA_RSS_DELAY_INT);
+ if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_RX_V2)) {
+ mtk_w32(eth, MTK_MAX_DELAY_INT, MTK_LRO_RX1_DLY_INT);
+ mtk_w32(eth, MTK_MAX_DELAY_INT, MTK_LRO_RX2_DLY_INT);
+ mtk_w32(eth, MTK_MAX_DELAY_INT, MTK_LRO_RX3_DLY_INT);
+ } else
+ mtk_w32(eth, MTK_MAX_DELAY_INT_V2, MTK_PDMA_RSS_DELAY_INT);
return 0;
}
@@ -5339,7 +5341,7 @@
.required_clks = MT7986_CLKS_BITMAP,
.required_pctl = false,
.has_sram = false,
- .rss_num = 0,
+ .rss_num = 4,
.txrx = {
.txd_size = sizeof(struct mtk_tx_dma_v2),
.rxd_size = sizeof(struct mtk_rx_dma),
@@ -5357,7 +5359,7 @@
.required_clks = MT7981_CLKS_BITMAP,
.required_pctl = false,
.has_sram = false,
- .rss_num = 0,
+ .rss_num = 4,
.txrx = {
.txd_size = sizeof(struct mtk_tx_dma_v2),
.rxd_size = sizeof(struct mtk_rx_dma),
diff --git a/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.h
index 88df3b2..8a9b615 100644
--- a/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+++ b/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.h
@@ -263,11 +263,10 @@
/* PDMA RSS Control Registers */
#if defined(CONFIG_MEDIATEK_NETSYS_RX_V2) || defined(CONFIG_MEDIATEK_NETSYS_V3)
#define MTK_PDMA_RSS_GLO_CFG (PDMA_BASE + 0x800)
-#define MTK_RX_NAPI_NUM (4)
#else
#define MTK_PDMA_RSS_GLO_CFG 0x2800
-#define MTK_RX_NAPI_NUM (1)
#endif
+#define MTK_RX_NAPI_NUM (4)
#define MTK_RSS_RING(x) (x)
#define MTK_RSS_EN BIT(0)
#define MTK_RSS_CFG_REQ BIT(2)
@@ -326,8 +325,11 @@
#else
#define MTK_PDMA_INT_GRP3 (PDMA_BASE + 0x22c)
#endif
-#define MTK_LRO_RX1_DLY_INT 0xa70
-#define MTK_MAX_DELAY_INT 0x8f0f8f0f
+#define MTK_LRO_RX1_DLY_INT (PDMA_BASE + 0x270)
+#define MTK_LRO_RX2_DLY_INT (PDMA_BASE + 0x274)
+#define MTK_LRO_RX3_DLY_INT (PDMA_BASE + 0x278)
+#define MTK_MAX_DELAY_INT 0x8f0f
+#define MTK_MAX_DELAY_INT_V2 0x8f0f8f0f
/* PDMA HW LRO IP Setting Registers */
#if defined(CONFIG_MEDIATEK_NETSYS_RX_V2) || defined(CONFIG_MEDIATEK_NETSYS_V3)
@@ -1553,12 +1555,12 @@
#define MT7986_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | \
MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA | \
- MTK_NETSYS_V2)
+ MTK_NETSYS_V2 | MTK_RSS)
#define MT7981_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | MTK_GMAC2_GEPHY | \
MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA | \
MTK_MUX_U3_GMAC2_TO_QPHY | MTK_U3_COPHY_V2 | \
- MTK_NETSYS_V2)
+ MTK_NETSYS_V2 | MTK_RSS)
#define MT7988_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | MTK_GMAC3_SGMII | \
MTK_MUX_GMAC123_TO_GEPHY_SGMII | MTK_QDMA | \