[][kernel][MT7988][dsa][phy][coverity scan fix]
[Description]
Fix Converity scan error.
[Release-log]
N/A
Change-Id: I755ce2ea040b093a993a1859ff3a009c64ae6bed
Reviewed-on: https://gerrit.mediatek.inc/c/openwrt/feeds/mtk_openwrt_feeds/+/6838042
diff --git a/target/linux/mediatek/patches-5.4/752-net-dsa-phy-coverity-scan.patch b/target/linux/mediatek/patches-5.4/752-net-dsa-phy-coverity-scan.patch
new file mode 100644
index 0000000..e2c731f
--- /dev/null
+++ b/target/linux/mediatek/patches-5.4/752-net-dsa-phy-coverity-scan.patch
@@ -0,0 +1,380 @@
+diff -Naur a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c
+--- a/drivers/net/dsa/mt7530.c 2022-11-25 14:10:39.452491570 +0800
++++ b/drivers/net/dsa/mt7530.c 2022-11-28 09:47:11.157096408 +0800
+@@ -2476,7 +2476,7 @@
+ mt7531_cpu_port_config(struct dsa_switch *ds, int port)
+ {
+ struct mt7530_priv *priv = ds->priv;
+- phy_interface_t interface;
++ phy_interface_t interface = PHY_INTERFACE_MODE_NA;
+ int speed;
+
+ switch (port) {
+@@ -2496,6 +2496,8 @@
+ priv->p6_interface = interface;
+ break;
+ };
++ if (interface == PHY_INTERFACE_MODE_NA)
++ dev_err(priv->dev, "invalid interface\n");
+
+ if (interface == PHY_INTERFACE_MODE_2500BASEX)
+ speed = SPEED_2500;
+diff -Naur a/drivers/net/dsa/mt7531_phy.c b/drivers/net/dsa/mt7531_phy.c
+--- a/drivers/net/dsa/mt7531_phy.c 2022-11-25 14:10:47.032465430 +0800
++++ b/drivers/net/dsa/mt7531_phy.c 2022-11-29 09:56:05.024665073 +0800
+@@ -252,7 +252,7 @@
+ u16 dev1e_17a_tmp, dev1e_e0_tmp;
+
+ /* *** Iext/Rext Cal start ************ */
+- all_ana_cal_status = ANACAL_INIT;
++ //all_ana_cal_status = ANACAL_INIT;
+ /* analog calibration enable, Rext calibration enable */
+ /* 1e_db[12]:rg_cal_ckinv, [8]:rg_ana_calen, [4]:rg_rext_calen, [0]:rg_zcalen_a */
+ /* 1e_dc[0]:rg_txvos_calen */
+@@ -296,7 +296,7 @@
+ all_ana_cal_status = ANACAL_FINISH;
+ //printk(" GE Rext AnaCal Done! (%d)(0x%x) \r\n", cnt, rg_zcal_ctrl);
+ } else {
+- dev1e_17a_tmp = tc_phy_read_dev_reg(ds, PHY0, 0x1e, 0x017a);
++ //dev1e_17a_tmp = tc_phy_read_dev_reg(ds, PHY0, 0x1e, 0x017a);
+ dev1e_e0_tmp = tc_phy_read_dev_reg(ds, PHY0, 0x1e, 0xe0);
+ if ((rg_zcal_ctrl == 0x3F) || (rg_zcal_ctrl == 0x00)) {
+ all_ana_cal_status = ANACAL_SATURATION; /* need to FT(IC fail?) */
+@@ -718,32 +718,34 @@
+ } else if (phyaddr == 1) {
+ if (calibration_pair == ANACAL_PAIR_A)
+ tx_amp_temp = tx_amp_temp - 1;
+- else if(calibration_pair == ANACAL_PAIR_B)
+- tx_amp_temp = tx_amp_temp ;
++ //else if(calibration_pair == ANACAL_PAIR_B)
++ // tx_amp_temp = tx_amp_temp;
+ else if(calibration_pair == ANACAL_PAIR_C)
+ tx_amp_temp = tx_amp_temp - 1;
+ else if(calibration_pair == ANACAL_PAIR_D)
+ tx_amp_temp = tx_amp_temp - 1;
+ } else if (phyaddr == 2) {
+- if (calibration_pair == ANACAL_PAIR_A)
+- tx_amp_temp = tx_amp_temp;
+- else if(calibration_pair == ANACAL_PAIR_B)
++ //if (calibration_pair == ANACAL_PAIR_A)
++ // tx_amp_temp = tx_amp_temp;
++ //else if(calibration_pair == ANACAL_PAIR_B)
++ if(calibration_pair == ANACAL_PAIR_B)
+ tx_amp_temp = tx_amp_temp - 1;
+- else if(calibration_pair == ANACAL_PAIR_C)
+- tx_amp_temp = tx_amp_temp;
++ //else if(calibration_pair == ANACAL_PAIR_C)
++ // tx_amp_temp = tx_amp_temp;
+ else if(calibration_pair == ANACAL_PAIR_D)
+ tx_amp_temp = tx_amp_temp - 1;
+- } else if (phyaddr == 3) {
+- tx_amp_temp = tx_amp_temp;
++ //} else if (phyaddr == 3) {
++ // tx_amp_temp = tx_amp_temp;
+ } else if (phyaddr == 4) {
+- if (calibration_pair == ANACAL_PAIR_A)
+- tx_amp_temp = tx_amp_temp;
+- else if(calibration_pair == ANACAL_PAIR_B)
++ //if (calibration_pair == ANACAL_PAIR_A)
++ // tx_amp_temp = tx_amp_temp;
++ //else if(calibration_pair == ANACAL_PAIR_B)
++ if(calibration_pair == ANACAL_PAIR_B)
+ tx_amp_temp = tx_amp_temp - 1;
+- else if(calibration_pair == ANACAL_PAIR_C)
+- tx_amp_temp = tx_amp_temp;
+- else if(calibration_pair == ANACAL_PAIR_D)
+- tx_amp_temp = tx_amp_temp;
++ //else if(calibration_pair == ANACAL_PAIR_C)
++ // tx_amp_temp = tx_amp_temp;
++ //else if(calibration_pair == ANACAL_PAIR_D)
++ // tx_amp_temp = tx_amp_temp;
+ }
+ reg_temp = tc_phy_read_dev_reg(ds, phyaddr, 0x1e, tx_amp_reg)&(~0xff00);
+ tc_phy_write_dev_reg(ds, phyaddr, 0x1e, tx_amp_reg_100,(tx_amp_temp|((tx_amp_temp)<<tx_amp_reg_shift)));
+@@ -858,7 +860,7 @@
+ reg_backup = 0x0000;
+ reg_backup |= ((tx_amp_temp << 10) | (tx_amp_temp << 0));
+ tc_phy_write_dev_reg(ds, phyaddr, 0x1e, 0x12, reg_backup);
+- reg_backup = tc_phy_read_dev_reg(ds, phyaddr, 0x1e, 0x12);
++ //reg_backup = tc_phy_read_dev_reg(ds, phyaddr, 0x1e, 0x12);
+ //printk("PORT[%d] 1e.012 = %x (OFFSET_1000M_PAIR_A)\n", phyaddr, reg_backup);
+ reg_backup = tc_phy_read_dev_reg(ds, phyaddr, 0x1e, 0x16);
+ reg_tmp = ((reg_backup & 0x3f) >> 0);
+@@ -866,7 +868,7 @@
+ reg_backup = (reg_backup & (~0x3f));
+ reg_backup |= (tx_amp_temp << 0);
+ tc_phy_write_dev_reg(ds, phyaddr, 0x1e, 0x16, reg_backup);
+- reg_backup = tc_phy_read_dev_reg(ds, phyaddr, 0x1e, 0x16);
++ //reg_backup = tc_phy_read_dev_reg(ds, phyaddr, 0x1e, 0x16);
+ //printk("PORT[%d] 1e.016 = %x (OFFSET_TESTMODE_1000M_PAIR_A)\n", phyaddr, reg_backup);
+ }
+ else if(calibration_pair == ANACAL_PAIR_B){
+@@ -876,7 +878,7 @@
+ reg_backup = 0x0000;
+ reg_backup |= ((tx_amp_temp << 8) | (tx_amp_temp << 0));
+ tc_phy_write_dev_reg(ds, phyaddr, 0x1e, 0x17, reg_backup);
+- reg_backup = tc_phy_read_dev_reg(ds, phyaddr, 0x1e, 0x17);
++ //reg_backup = tc_phy_read_dev_reg(ds, phyaddr, 0x1e, 0x17);
+ //printk("PORT[%d] 1e.017 = %x (OFFSET_1000M_PAIR_B)\n", phyaddr, reg_backup);
+ reg_backup = tc_phy_read_dev_reg(ds, phyaddr, 0x1e, 0x18);
+ reg_tmp = ((reg_backup & 0x3f) >> 0);
+@@ -884,7 +886,7 @@
+ reg_backup = (reg_backup & (~0x3f));
+ reg_backup |= (tx_amp_temp << 0);
+ tc_phy_write_dev_reg(ds, phyaddr, 0x1e, 0x18, reg_backup);
+- reg_backup = tc_phy_read_dev_reg(ds, phyaddr, 0x1e, 0x18);
++ //reg_backup = tc_phy_read_dev_reg(ds, phyaddr, 0x1e, 0x18);
+ //printk("PORT[%d] 1e.018 = %x (OFFSET_TESTMODE_1000M_PAIR_B)\n", phyaddr, reg_backup);
+ }
+ else if(calibration_pair == ANACAL_PAIR_C){
+@@ -894,7 +896,7 @@
+ reg_backup = (reg_backup & (~0x3f00));
+ reg_backup |= (tx_amp_temp << 8);
+ tc_phy_write_dev_reg(ds, phyaddr, 0x1e, 0x19, reg_backup);
+- reg_backup = tc_phy_read_dev_reg(ds, phyaddr, 0x1e, 0x19);
++ //reg_backup = tc_phy_read_dev_reg(ds, phyaddr, 0x1e, 0x19);
+ //printk("PORT[%d] 1e.019 = %x (OFFSET_1000M_PAIR_C)\n", phyaddr, reg_backup);
+ reg_backup = tc_phy_read_dev_reg(ds, phyaddr, 0x1e, 0x20);
+ reg_tmp = ((reg_backup & 0x3f) >> 0);
+@@ -902,7 +904,7 @@
+ reg_backup = (reg_backup & (~0x3f));
+ reg_backup |= (tx_amp_temp << 0);
+ tc_phy_write_dev_reg(ds, phyaddr, 0x1e, 0x20, reg_backup);
+- reg_backup = tc_phy_read_dev_reg(ds, phyaddr, 0x1e, 0x20);
++ //reg_backup = tc_phy_read_dev_reg(ds, phyaddr, 0x1e, 0x20);
+ //printk("PORT[%d] 1e.020 = %x (OFFSET_TESTMODE_1000M_PAIR_C)\n", phyaddr, reg_backup);
+ }
+ else if(calibration_pair == ANACAL_PAIR_D){
+@@ -912,7 +914,7 @@
+ reg_backup = (reg_backup & (~0x3f00));
+ reg_backup |= (tx_amp_temp << 8);
+ tc_phy_write_dev_reg(ds, phyaddr, 0x1e, 0x21, reg_backup);
+- reg_backup = tc_phy_read_dev_reg(ds, phyaddr, 0x1e, 0x21);
++ //reg_backup = tc_phy_read_dev_reg(ds, phyaddr, 0x1e, 0x21);
+ //printk("PORT[%d] 1e.021 = %x (OFFSET_1000M_PAIR_D)\n", phyaddr, reg_backup);
+ reg_backup = tc_phy_read_dev_reg(ds, phyaddr, 0x1e, 0x22);
+ reg_tmp = ((reg_backup & 0x3f) >> 0);
+@@ -920,7 +922,7 @@
+ reg_backup = (reg_backup & (~0x3f));
+ reg_backup |= (tx_amp_temp << 0);
+ tc_phy_write_dev_reg(ds, phyaddr, 0x1e, 0x22, reg_backup);
+- reg_backup = tc_phy_read_dev_reg(ds, phyaddr, 0x1e, 0x22);
++ //reg_backup = tc_phy_read_dev_reg(ds, phyaddr, 0x1e, 0x22);
+ //printk("PORT[%d] 1e.022 = %x (OFFSET_TESTMODE_1000M_PAIR_D)\n", phyaddr, reg_backup);
+ }
+
+@@ -1352,7 +1354,7 @@
+
+ int mt7531_phy_setup(struct dsa_switch *ds)
+ {
+- int ret;
++ int ret = 0;
+ int i;
+
+ mt7531_phy_setting(ds);
+diff -Naur a/drivers/net/phy/mtk/mt753x/mt7531.c b/drivers/net/phy/mtk/mt753x/mt7531.c
+--- a/drivers/net/phy/mtk/mt753x/mt7531.c 2022-11-25 14:11:51.944272549 +0800
++++ b/drivers/net/phy/mtk/mt753x/mt7531.c 2022-11-25 14:19:49.970820719 +0800
+@@ -1062,6 +1062,7 @@
+ u32 pmcr;
+ u32 speed;
+
++ pdev = container_of(gsw->dev, struct platform_device, dev);
+ switch_node = of_find_node_by_name(NULL, "switch0");
+ if (switch_node == NULL) {
+ dev_err(&pdev->dev, "switch node invaild\n");
+@@ -1074,7 +1075,6 @@
+ return -EIO;
+ }
+
+- pdev = container_of(gsw->dev, struct platform_device, dev);
+ gsw->sysctrl_base = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
+ "mediatek,sysctrl");
+ if (IS_ERR(gsw->sysctrl_base)) {
+diff -Naur a/drivers/net/phy/mtk/mt753x/mt753x_common.c b/drivers/net/phy/mtk/mt753x/mt753x_common.c
+--- a/drivers/net/phy/mtk/mt753x/mt753x_common.c 2022-11-25 14:12:06.308223474 +0800
++++ b/drivers/net/phy/mtk/mt753x/mt753x_common.c 2022-11-25 14:21:52.038450276 +0800
+@@ -49,6 +49,9 @@
+ case MAC_SPD_2500:
+ speed = "2.5Gbps";
+ break;
++ default:
++ dev_info(gsw->dev, "Invalid speed\n");
++ return;
+ }
+
+ if (pmsr & MAC_LNK_STS) {
+diff -Naur a/drivers/net/phy/mtk/mt753x/mt753x_mdio.c b/drivers/net/phy/mtk/mt753x/mt753x_mdio.c
+--- a/drivers/net/phy/mtk/mt753x/mt753x_mdio.c 2022-11-25 14:12:29.064162894 +0800
++++ b/drivers/net/phy/mtk/mt753x/mt753x_mdio.c 2022-11-25 17:04:01.973949052 +0800
+@@ -495,7 +495,7 @@
+ struct device_node *np = gsw->dev->of_node;
+ struct reset_control *rstc;
+ int mcm;
+- int ret = -EINVAL;
++ int ret;
+
+ mcm = of_property_read_bool(np, "mediatek,mcm");
+ if (mcm) {
+diff -Naur a/drivers/net/phy/mtk/mt753x/mt753x_nl.c b/drivers/net/phy/mtk/mt753x/mt753x_nl.c
+--- a/drivers/net/phy/mtk/mt753x/mt753x_nl.c 2022-11-25 14:12:12.292202033 +0800
++++ b/drivers/net/phy/mtk/mt753x/mt753x_nl.c 2022-11-25 17:01:26.881930912 +0800
+@@ -75,8 +75,10 @@
+ len = snprintf(buf, sizeof(buf),
+ "id: %d, model: %s, node: %s\n",
+ gsw->id, gsw->name, gsw->dev->of_node->name);
+- strncat(buff, buf, size - total);
+- total += len;
++ if (len == strlen(buf)) {
++ strncat(buff, buf, size - total);
++ total += len;
++ }
+ }
+
+ mt753x_put_gsw();
+diff -Naur a/drivers/net/phy/mtk/mt753x/mt753x_phy.c b/drivers/net/phy/mtk/mt753x/mt753x_phy.c
+--- a/drivers/net/phy/mtk/mt753x/mt753x_phy.c 2022-11-25 14:12:34.160149995 +0800
++++ b/drivers/net/phy/mtk/mt753x/mt753x_phy.c 2022-11-29 14:12:28.261884707 +0800
+@@ -141,7 +141,7 @@
+ u16 dev1e_17a_tmp, dev1e_e0_tmp;
+
+ /* *** Iext/Rext Cal start ************ */
+- all_ana_cal_status = ANACAL_INIT;
++ //all_ana_cal_status = ANACAL_INIT;
+ /* analog calibration enable, Rext calibration enable */
+ /* 1e_db[12]:rg_cal_ckinv, [8]:rg_ana_calen, [4]:rg_rext_calen, [0]:rg_zcalen_a */
+ /* 1e_dc[0]:rg_txvos_calen */
+@@ -185,7 +185,7 @@
+ all_ana_cal_status = ANACAL_FINISH;
+ //printk(" GE Rext AnaCal Done! (%d)(0x%x) \r\n", cnt, rg_zcal_ctrl);
+ } else {
+- dev1e_17a_tmp = tc_phy_read_dev_reg(gsw, PHY0, 0x1e, 0x017a);
++ //dev1e_17a_tmp = tc_phy_read_dev_reg(gsw, PHY0, 0x1e, 0x017a);
+ dev1e_e0_tmp = tc_phy_read_dev_reg(gsw, PHY0, 0x1e, 0xe0);
+ if ((rg_zcal_ctrl == 0x3F) || (rg_zcal_ctrl == 0x00)) {
+ all_ana_cal_status = ANACAL_SATURATION; /* need to FT(IC fail?) */
+@@ -580,33 +580,35 @@
+ } else if (phyaddr == 1) {
+ if (calibration_pair == ANACAL_PAIR_A)
+ tx_amp_temp = tx_amp_temp - 1;
+- else if(calibration_pair == ANACAL_PAIR_B)
+- tx_amp_temp = tx_amp_temp ;
++ //else if(calibration_pair == ANACAL_PAIR_B)
++ // tx_amp_temp = tx_amp_temp;
+ else if(calibration_pair == ANACAL_PAIR_C)
+ tx_amp_temp = tx_amp_temp - 1;
+ else if(calibration_pair == ANACAL_PAIR_D)
+ tx_amp_temp = tx_amp_temp - 1;
+ } else if (phyaddr == 2) {
+- if (calibration_pair == ANACAL_PAIR_A)
+- tx_amp_temp = tx_amp_temp;
+- else if(calibration_pair == ANACAL_PAIR_B)
++ //if (calibration_pair == ANACAL_PAIR_A)
++ // tx_amp_temp = tx_amp_temp;
++ //else if(calibration_pair == ANACAL_PAIR_B)
++ if(calibration_pair == ANACAL_PAIR_B)
+ tx_amp_temp = tx_amp_temp - 1;
+- else if(calibration_pair == ANACAL_PAIR_C)
+- tx_amp_temp = tx_amp_temp;
++ //else if(calibration_pair == ANACAL_PAIR_C)
++ // tx_amp_temp = tx_amp_temp;
+ else if(calibration_pair == ANACAL_PAIR_D)
+ tx_amp_temp = tx_amp_temp - 1;
+- } else if (phyaddr == 3) {
+- tx_amp_temp = tx_amp_temp;
++ //} else if (phyaddr == 3) {
++ // tx_amp_temp = tx_amp_temp;
+ } else if (phyaddr == 4) {
+- if (calibration_pair == ANACAL_PAIR_A)
+- tx_amp_temp = tx_amp_temp;
+- else if(calibration_pair == ANACAL_PAIR_B)
++ //if (calibration_pair == ANACAL_PAIR_A)
++ // tx_amp_temp = tx_amp_temp;
++ //else if(calibration_pair == ANACAL_PAIR_B)
++ if(calibration_pair == ANACAL_PAIR_B)
+ tx_amp_temp = tx_amp_temp - 1;
+- else if(calibration_pair == ANACAL_PAIR_C)
+- tx_amp_temp = tx_amp_temp;
+- else if(calibration_pair == ANACAL_PAIR_D)
+- tx_amp_temp = tx_amp_temp;
+- }
++ //else if(calibration_pair == ANACAL_PAIR_C)
++ // tx_amp_temp = tx_amp_temp;
++ //else if(calibration_pair == ANACAL_PAIR_D)
++ // tx_amp_temp = tx_amp_temp;
++ }
+ reg_temp = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg)&(~0xff00);
+ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100,(tx_amp_temp|((tx_amp_temp)<<tx_amp_reg_shift)));
+ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg, (tx_amp_temp|((tx_amp_temp)<<tx_amp_reg_shift)));
+@@ -704,7 +706,7 @@
+ reg_backup = 0x0000;
+ reg_backup |= ((reg_tmp << 10) | (reg_tmp << 0));
+ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x12, reg_backup);
+- reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x12);
++ //reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x12);
+ //printk("PORT[%d] 1e.012 = %x (OFFSET_1000M_PAIR_A)\n", phyaddr, reg_backup);
+ reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x16);
+ reg_tmp = ((reg_backup & 0x3f) >> 0);
+@@ -712,7 +714,7 @@
+ reg_backup = (reg_backup & (~0x3f));
+ reg_backup |= (reg_tmp << 0);
+ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x16, reg_backup);
+- reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x16);
++ //reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x16);
+ //printk("PORT[%d] 1e.016 = %x (OFFSET_TESTMODE_1000M_PAIR_A)\n", phyaddr, reg_backup);
+ }
+ else if(calibration_pair == ANACAL_PAIR_B){
+@@ -722,7 +724,7 @@
+ reg_backup = 0x0000;
+ reg_backup |= ((reg_tmp << 8) | (reg_tmp << 0));
+ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x17, reg_backup);
+- reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x17);
++ //reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x17);
+ //printk("PORT[%d] 1e.017 = %x (OFFSET_1000M_PAIR_B)\n", phyaddr, reg_backup);
+ reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x18);
+ reg_tmp = ((reg_backup & 0x3f) >> 0);
+@@ -730,7 +732,7 @@
+ reg_backup = (reg_backup & (~0x3f));
+ reg_backup |= (reg_tmp << 0);
+ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x18, reg_backup);
+- reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x18);
++ //reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x18);
+ //printk("PORT[%d] 1e.018 = %x (OFFSET_TESTMODE_1000M_PAIR_B)\n", phyaddr, reg_backup);
+ }
+ else if(calibration_pair == ANACAL_PAIR_C){
+@@ -740,7 +742,7 @@
+ reg_backup = (reg_backup & (~0x3f00));
+ reg_backup |= (reg_tmp << 8);
+ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x19, reg_backup);
+- reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x19);
++ //reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x19);
+ //printk("PORT[%d] 1e.019 = %x (OFFSET_1000M_PAIR_C)\n", phyaddr, reg_backup);
+ reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x20);
+ reg_tmp = ((reg_backup & 0x3f) >> 0);
+@@ -748,7 +750,7 @@
+ reg_backup = (reg_backup & (~0x3f));
+ reg_backup |= (reg_tmp << 0);
+ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x20, reg_backup);
+- reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x20);
++ //reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x20);
+ //printk("PORT[%d] 1e.020 = %x (OFFSET_TESTMODE_1000M_PAIR_C)\n", phyaddr, reg_backup);
+ }
+ else if(calibration_pair == ANACAL_PAIR_D){
+@@ -758,7 +760,7 @@
+ reg_backup = (reg_backup & (~0x3f00));
+ reg_backup |= (reg_tmp << 8);
+ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x21, reg_backup);
+- reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x21);
++ //reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x21);
+ //printk("PORT[%d] 1e.021 = %x (OFFSET_1000M_PAIR_D)\n", phyaddr, reg_backup);
+ reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x22);
+ reg_tmp = ((reg_backup & 0x3f) >> 0);
+@@ -766,7 +768,7 @@
+ reg_backup = (reg_backup & (~0x3f));
+ reg_backup |= (reg_tmp << 0);
+ tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x22, reg_backup);
+- reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x22);
++ //reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x22);
+ //printk("PORT[%d] 1e.022 = %x (OFFSET_TESTMODE_1000M_PAIR_D)\n", phyaddr, reg_backup);
+ }
+