[][Kernel][Common][eth][update debug info and reset condition]
[Description]
Change dump more correct QDMA info and reset condition
- dump all QDMA page info
- don't reset if pause frame cause timeout
- add reset when GMAC RX path error
[Release-log]
N/A
Change-Id: Ife2569284eb4a3bee84d5b3ebdc6f0a9b296d8d9
Reviewed-on: https://gerrit.mediatek.inc/c/openwrt/feeds/mtk_openwrt_feeds/+/6309535
diff --git a/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_reset.c b/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_reset.c
index 4c4f631..9327f0c 100644
--- a/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_reset.c
+++ b/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_reset.c
@@ -177,10 +177,17 @@
void mtk_dump_netsys_info(void *_eth)
{
struct mtk_eth *eth = _eth;
+ u32 id = 0;
mtk_dump_reg(eth, "FE", 0x0, 0x500);
mtk_dump_reg(eth, "ADMA", PDMA_BASE, 0x300);
- mtk_dump_reg(eth, "QDMA", QDMA_BASE, 0x400);
+ for (id = 0; id < MTK_QDMA_PAGE_NUM; id++){
+ mtk_w32(eth, id, MTK_QDMA_PAGE);
+ pr_info("\nQDMA PAGE:%x ",mtk_r32(eth, MTK_QDMA_PAGE));
+ mtk_dump_reg(eth, "QDMA", QDMA_BASE, 0x100);
+ mtk_w32(eth, 0, MTK_QDMA_PAGE);
+ }
+ mtk_dump_reg(eth, "QDMA", MTK_QRX_BASE_PTR0, 0x300);
mtk_dump_reg(eth, "WDMA", WDMA_BASE(0), 0x600);
mtk_dump_reg(eth, "PPE", 0x2200, 0x200);
mtk_dump_reg(eth, "GMAC", 0x10000, 0x300);
@@ -192,6 +199,10 @@
static u32 timestamp = 0;
static u32 err_cnt1 = 0, err_cnt2 = 0, err_cnt3 = 0;
static u32 prev_wdidx = 0;
+ unsigned int mib_base = MTK_GDM1_TX_GBCNT;
+ static u32 prev_gdm2rx = 0;
+
+ /*wdma tx path*/
u32 cur_wdidx = mtk_r32(eth, MTK_WDMA_DTX_PTR(0));
u32 is_wtx_busy = mtk_r32(eth, MTK_WDMA_GLO_CFG(0)) & MTK_TX_DMA_BUSY;
u32 is_oq_free = ((mtk_r32(eth, MTK_PSE_OQ_STA(0)) & 0x01FF0000) == 0) &&
@@ -199,20 +210,31 @@
((mtk_r32(eth, MTK_PSE_OQ_STA(4)) & 0x01FF0000) == 0);
u32 is_cdm_full =
!(mtk_r32(eth, MTK_WDMA_TX_DBG_MON0(0)) & MTK_CDM_TXFIFO_RDY);
+ /*qdma tx path*/
u32 is_qfsm_hang = mtk_r32(eth, MTK_QDMA_FSM) != 0;
u32 is_qfwd_hang = mtk_r32(eth, MTK_QDMA_FWD_CNT) == 0;
u32 is_qfq_hang = mtk_r32(eth, MTK_QDMA_FQ_CNT) !=
((MTK_DMA_SIZE << 16) | MTK_DMA_SIZE);
+ u32 is_gdm1_tx = (mtk_r32(eth, MTK_FE_GDM1_FSM) & 0xFFFF0000) > 0;
+ u32 is_gdm2_tx = (mtk_r32(eth, MTK_FE_GDM2_FSM) & 0xFFFF0000) > 0;
+ u32 is_gmac1_tx = (mtk_r32(eth, MTK_MAC_FSM(0)) & 0xFF000000) != 0x1000000;
+ u32 is_gmac2_tx = (mtk_r32(eth, MTK_MAC_FSM(1)) & 0xFF000000) != 0x1000000;
+ u32 gdm1_fc = mtk_r32(eth, mib_base+0x24);
+ u32 gdm2_fc = mtk_r32(eth, mib_base+0x64);
+ /*adma rx path*/
u32 is_oq0_stuck = (mtk_r32(eth, MTK_PSE_OQ_STA(0)) & 0x1FF) != 0;
u32 is_cdm1_busy = (mtk_r32(eth, MTK_FE_CDM1_FSM) & 0xFFFF0000) != 0;
u32 is_adma_busy = ((mtk_r32(eth, MTK_ADMA_RX_DBG0) & 0x1F) == 0) &&
((mtk_r32(eth, MTK_ADMA_RX_DBG0) & 0x40) == 0);
+ /*gmac2 rx path*/
+ u32 gmac2_rx = (mtk_r32(eth, MTK_MAC_FSM(1)) & 0xFF0000 != 0x10000);
+ u32 gdm2_rx_cnt = mtk_r32(eth, mib_base+0x48);
if (cur_wdidx == prev_wdidx && is_wtx_busy &&
is_oq_free && is_cdm_full) {
err_cnt1++;
if (err_cnt1 >= 3) {
- pr_info("WDMA CDM Hang !\n");
+ pr_info("WDMA CDM Info\n");
pr_info("============== Time: %d ================\n",
timestamp);
pr_info("err_cnt1 = %d", err_cnt1);
@@ -242,10 +264,11 @@
schedule_work(ð->pending_work);
}
}
- } else if (is_qfsm_hang && is_qfwd_hang) {
+ } else if (is_qfsm_hang && is_qfwd_hang &&
+ ((is_gdm1_tx && is_gmac1_tx && (gdm1_fc < 1)) || (is_gdm2_tx && is_gmac2_tx && (gdm2_fc < 1)))) {
err_cnt2++;
if (err_cnt2 >= 3) {
- pr_info("QDMA Tx Hang !\n");
+ pr_info("QDMA Tx Info\n");
pr_info("============== Time: %d ================\n",
timestamp);
pr_info("err_cnt2 = %d", err_cnt2);
@@ -259,6 +282,8 @@
mtk_r32(eth, MTK_QDMA_FWD_CNT));
pr_info("MTK_QDMA_FQ_CNT = 0x%x\n",
mtk_r32(eth, MTK_QDMA_FQ_CNT));
+ pr_info("GDM1 FC = 0x%x\n",gdm1_fc);
+ pr_info("GDM2 FC = 0x%x\n",gdm2_fc);
pr_info("==============================\n");
if ((atomic_read(&reset_lock) == 0) &&
@@ -270,7 +295,7 @@
} else if (is_oq0_stuck && is_cdm1_busy && is_adma_busy) {
err_cnt3++;
if (err_cnt3 >= 3) {
- pr_info("ADMA Rx Hang !\n");
+ pr_info("ADMA Rx Info\n");
pr_info("============== Time: %d ================\n",
timestamp);
pr_info("err_cnt3 = %d", err_cnt3);
@@ -291,6 +316,22 @@
schedule_work(ð->pending_work);
}
}
+ }else if ((gdm2_rx_cnt == prev_gdm2rx) && gmac2_rx) {
+ err_cnt3++;
+ if (err_cnt3 >= 3) {
+ pr_info("GMAC Rx Info\n");
+ pr_info("============== Time: %d ================\n",
+ timestamp);
+ pr_info("err_cnt3 = %d", err_cnt3);
+ pr_info("gmac2_rx = %d\n", gmac2_rx);
+ pr_info("gdm2_rx_cnt = %d\n", gdm2_rx_cnt);
+ pr_info("==============================\n");
+ if ((atomic_read(&reset_lock) == 0) &&
+ (atomic_read(&force) == 0)){
+ atomic_inc(&force);
+ schedule_work(ð->pending_work);
+ }
+ }
} else {
err_cnt1 = 0;
err_cnt2 = 0;
@@ -298,6 +339,7 @@
}
prev_wdidx = cur_wdidx;
+ prev_gdm2rx = gdm2_rx_cnt;
mod_timer(ð->mtk_dma_monitor_timer, jiffies + 1 * HZ);
}
diff --git a/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.h
index 7fa0db8..d75c28f 100755
--- a/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+++ b/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.h
@@ -475,6 +475,7 @@
/* QDMA TX NUM */
#define MTK_QDMA_TX_NUM 16
+#define MTK_QDMA_PAGE_NUM 8
#define MTK_QDMA_TX_MASK ((MTK_QDMA_TX_NUM) - 1)
#define QID_LOW_BITS(x) ((x) & 0xf)
#define QID_HIGH_BITS(x) ((((x) >> 4) & 0x3) << 20)