| From 650cb1ed09a37bcb426ec5f27ae0e65f1d65df94 Mon Sep 17 00:00:00 2001 |
| From: Shayne Chen <shayne.chen@mediatek.com> |
| Date: Mon, 9 May 2022 15:12:22 +0800 |
| Subject: [PATCH] mt76: besra: add internal debug patch |
| |
| --- |
| besra/Makefile | 5 +- |
| besra/besra.h | 35 + |
| besra/debugfs.c | 25 +- |
| besra/mac.c | 18 + |
| besra/mcu.c | 4 + |
| besra/mtk_debug.h | 3716 +++++++++++++++++++++++++++++++++++++++++++ |
| besra/mtk_debugfs.c | 3576 +++++++++++++++++++++++++++++++++++++++++ |
| tools/fwlog.c | 25 +- |
| 8 files changed, 7393 insertions(+), 11 deletions(-) |
| mode change 100755 => 100644 besra/Makefile |
| create mode 100644 besra/mtk_debug.h |
| create mode 100644 besra/mtk_debugfs.c |
| |
| diff --git a/besra/Makefile b/besra/Makefile |
| old mode 100755 |
| new mode 100644 |
| index a51abe0c..edb7800a |
| --- a/besra/Makefile |
| +++ b/besra/Makefile |
| @@ -1,8 +1,11 @@ |
| # SPDX-License-Identifier: ISC |
| +EXTRA_CFLAGS += -DCONFIG_MTK_DEBUG |
| |
| obj-$(CONFIG_BESRA) += besra.o |
| |
| besra-y := pci.o init.o dma.o eeprom.o main.o mcu.o mac.o \ |
| debugfs.o mmio.o |
| |
| -besra-$(CONFIG_NL80211_TESTMODE) += testmode.o |
| \ No newline at end of file |
| +besra-$(CONFIG_NL80211_TESTMODE) += testmode.o |
| + |
| +besra-y += mtk_debugfs.o |
| diff --git a/besra/besra.h b/besra/besra.h |
| index 63a97363..30c3a79b 100644 |
| --- a/besra/besra.h |
| +++ b/besra/besra.h |
| @@ -301,6 +301,23 @@ struct besra_dev { |
| u8 table_mask; |
| u8 n_agrt; |
| } twt; |
| + |
| +#ifdef CONFIG_MTK_DEBUG |
| + u16 wlan_idx; |
| + struct { |
| + bool dump_mcu_pkt; |
| + bool dump_txd; |
| + bool dump_tx_pkt; |
| + bool dump_rx_pkt; |
| + bool dump_rx_raw; |
| + u32 fw_dbg_module; |
| + u8 fw_dbg_lv; |
| + u32 bcn_total_cnt[__MT_MAX_BAND]; |
| + u32 token_idx; |
| + u32 rxd_read_cnt; |
| + u32 txd_read_cnt; |
| + } dbg; |
| +#endif |
| }; |
| |
| enum { |
| @@ -571,4 +588,22 @@ void besra_sta_add_debugfs(struct ieee80211_hw *hw, struct ieee80211_vif *vif, |
| struct ieee80211_sta *sta, struct dentry *dir); |
| #endif |
| |
| +#ifdef CONFIG_MTK_DEBUG |
| +void besra_packet_log_to_host(struct besra_dev *dev, const void *data, int len, int type, int des_len); |
| + |
| +#define PKT_BIN_DEBUG_MAGIC 0xc8763123 |
| +enum { |
| + PKT_BIN_DEBUG_MCU, |
| + PKT_BIN_DEBUG_TXD, |
| + PKT_BIN_DEBUG_TX, |
| + PKT_BIN_DEBUG_RX, |
| + PKT_BIN_DEBUG_RX_RAW, |
| +}; |
| + |
| +int besra_mtk_init_debugfs(struct besra_phy *phy, struct dentry *dir); |
| +void besra_dump_bmac_rxd_info(struct besra_dev *dev, __le32 *rxd); |
| +void besra_dump_bmac_txd_info(struct besra_dev *dev, __le32 *txd, bool dump_txp); |
| +void besra_dump_bmac_txp_info(struct besra_dev *dev, __le32 *txp); |
| +#endif |
| + |
| #endif |
| diff --git a/besra/debugfs.c b/besra/debugfs.c |
| index 4be253ea..9f3e11a8 100644 |
| --- a/besra/debugfs.c |
| +++ b/besra/debugfs.c |
| @@ -371,6 +371,9 @@ besra_fw_debug_wm_set(void *data, u64 val) |
| int ret; |
| |
| dev->fw_debug_wm = val ? MCU_FW_LOG_TO_HOST : 0; |
| +#ifdef CONFIG_MTK_DEBUG |
| + dev->fw_debug_wm = val; |
| +#endif |
| |
| if (dev->fw_debug_bin) |
| val = MCU_FW_LOG_RELAY; |
| @@ -494,6 +497,16 @@ besra_fw_debug_bin_set(void *data, u64 val) |
| |
| relay_reset(dev->relay_fwlog); |
| |
| +#ifdef CONFIG_MTK_DEBUG |
| + dev->dbg.dump_mcu_pkt = val & BIT(4) ? true : false; |
| + dev->dbg.dump_txd = val & BIT(5) ? true : false; |
| + dev->dbg.dump_tx_pkt = val & BIT(6) ? true : false; |
| + dev->dbg.dump_rx_pkt = val & BIT(7) ? true : false; |
| + dev->dbg.dump_rx_raw = val & BIT(8) ? true : false; |
| + if (!(val & GENMASK(3, 0))) |
| + return 0; |
| +#endif |
| + |
| return besra_fw_debug_wm_set(dev, dev->fw_debug_wm); |
| } |
| |
| @@ -942,8 +955,13 @@ int besra_init_debugfs(struct besra_phy *phy) |
| besra_rdd_monitor); |
| } |
| |
| - if (phy == &dev->phy) |
| + if (phy == &dev->phy) { |
| dev->debugfs_dir = dir; |
| +#ifdef CONFIG_MTK_DEBUG |
| + debugfs_create_u16("wlan_idx", 0600, dir, &dev->wlan_idx); |
| + besra_mtk_init_debugfs(phy, dir); |
| +#endif |
| + } |
| |
| return 0; |
| } |
| @@ -1000,7 +1018,12 @@ void besra_debugfs_rx_fw_monitor(struct besra_dev *dev, const void *data, int le |
| |
| bool besra_debugfs_rx_log(struct besra_dev *dev, const void *data, int len) |
| { |
| +#ifdef CONFIG_MTK_DEBUG |
| + if (get_unaligned_le32(data) != FW_BIN_LOG_MAGIC && |
| + get_unaligned_le32(data) != PKT_BIN_DEBUG_MAGIC) |
| +#else |
| if (get_unaligned_le32(data) != FW_BIN_LOG_MAGIC) |
| +#endif |
| return false; |
| |
| if (dev->relay_fwlog) |
| diff --git a/besra/mac.c b/besra/mac.c |
| index 2d48a1a4..b726e2d8 100644 |
| --- a/besra/mac.c |
| +++ b/besra/mac.c |
| @@ -589,6 +589,11 @@ besra_mac_fill_rx(struct besra_dev *dev, struct sk_buff *skb) |
| int idx; |
| u8 band_idx; |
| |
| +#ifdef CONFIG_MTK_DEBUG |
| + if (dev->dbg.dump_rx_raw) |
| + besra_packet_log_to_host(dev, skb->data, skb->len, PKT_BIN_DEBUG_RX_RAW, 0); |
| + besra_dump_bmac_rxd_info(dev, rxd); |
| +#endif |
| memset(status, 0, sizeof(*status)); |
| |
| band_idx = FIELD_GET(MT_RXD1_NORMAL_BAND_IDX, rxd1); |
| @@ -763,6 +768,10 @@ besra_mac_fill_rx(struct besra_dev *dev, struct sk_buff *skb) |
| } |
| |
| hdr_gap = (u8 *)rxd - skb->data + 2 * remove_pad; |
| +#ifdef CONFIG_MTK_DEBUG |
| + if (dev->dbg.dump_rx_pkt) |
| + besra_packet_log_to_host(dev, skb->data, skb->len, PKT_BIN_DEBUG_RX, hdr_gap); |
| +#endif |
| if (hdr_trans && ieee80211_has_morefrags(fc)) { |
| if (besra_reverse_frag0_hdr_trans(skb, hdr_gap)) |
| return -EINVAL; |
| @@ -1330,6 +1339,15 @@ int besra_tx_prepare_skb(struct mt76_dev *mdev, void *txwi_ptr, |
| tx_info->buf[1].skip_unmap = true; |
| tx_info->nbuf = MT_CT_DMA_BUF_NUM; |
| |
| +#ifdef CONFIG_MTK_DEBUG |
| + besra_dump_bmac_txd_info(dev, (__le32 *)txwi, true); |
| + |
| + if (dev->dbg.dump_txd) |
| + besra_packet_log_to_host(dev, txwi, MT_TXD_SIZE, PKT_BIN_DEBUG_TXD, 0); |
| + if (dev->dbg.dump_tx_pkt) |
| + besra_packet_log_to_host(dev, t->skb->data, t->skb->len, PKT_BIN_DEBUG_TX, 0); |
| +#endif |
| + |
| return 0; |
| } |
| |
| diff --git a/besra/mcu.c b/besra/mcu.c |
| index 5276552c..6fc175c6 100644 |
| --- a/besra/mcu.c |
| +++ b/besra/mcu.c |
| @@ -299,6 +299,10 @@ besra_mcu_send_message(struct mt76_dev *mdev, struct sk_buff *skb, |
| mcu_txd->s2d_index = MCU_S2D_H2N; |
| |
| exit: |
| +#ifdef CONFIG_MTK_DEBUG |
| + if (dev->dbg.dump_mcu_pkt) |
| + besra_packet_log_to_host(dev, skb->data, skb->len, PKT_BIN_DEBUG_MCU, 0); |
| +#endif |
| if (wait_seq) |
| *wait_seq = seq; |
| |
| diff --git a/besra/mtk_debug.h b/besra/mtk_debug.h |
| new file mode 100644 |
| index 00000000..1a797c81 |
| --- /dev/null |
| +++ b/besra/mtk_debug.h |
| @@ -0,0 +1,3716 @@ |
| +#ifndef __MTK_DEBUG_H |
| +#define __MTK_DEBUG_H |
| + |
| +#ifdef CONFIG_MTK_DEBUG |
| + |
| +struct bin_debug_hdr { |
| + __le32 magic_num; |
| + __le16 serial_id; |
| + __le16 msg_type; |
| + __le16 len; |
| + __le16 des_len; /* descriptor len for rxd */ |
| +} __packed; |
| + |
| +#define NO_SHIFT_DEFINE 0xFFFFFFFF |
| +#define BITS(m, n) (~(BIT(m)-1) & ((BIT(n) - 1) | BIT(n))) |
| + |
| +#define GET_FIELD(_field, _reg) \ |
| + ({ \ |
| + (((_reg) & (_field##_MASK)) >> (_field##_SHIFT)); \ |
| + }) |
| + |
| +struct queue_desc { |
| + u32 hw_desc_base; |
| + u16 ring_size; |
| + char *const ring_info; |
| +}; |
| + |
| +enum umac_port { |
| + ENUM_UMAC_HIF_PORT_0 = 0, |
| + ENUM_UMAC_CPU_PORT_1 = 1, |
| + ENUM_UMAC_LMAC_PORT_2 = 2, |
| + ENUM_PLE_CTRL_PSE_PORT_3 = 3, |
| + ENUM_UMAC_PSE_PLE_PORT_TOTAL_NUM = 4 |
| +}; |
| + |
| +/* N9 MCU QUEUE LIST */ |
| +enum umac_cpu_port_queue_idx { |
| + ENUM_UMAC_CTX_Q_0 = 0, |
| + ENUM_UMAC_CTX_Q_1 = 1, |
| + ENUM_UMAC_CTX_Q_2 = 2, |
| + ENUM_UMAC_CTX_Q_3 = 3, |
| + ENUM_UMAC_CRX = 0, |
| + ENUM_UMAC_CIF_QUEUE_TOTAL_NUM = 4 |
| +}; |
| + |
| +/* LMAC PLE For PSE Control P3 */ |
| +enum umac_ple_ctrl_port3_queue_idx { |
| + ENUM_UMAC_PLE_CTRL_P3_Q_0X1E = 0x1e, |
| + ENUM_UMAC_PLE_CTRL_P3_Q_0X1F = 0x1f, |
| + ENUM_UMAC_PLE_CTRL_P3_TOTAL_NUM = 2 |
| +}; |
| + |
| +/* PSE PLE QUEUE */ |
| +#define CR_NUM_OF_AC 9 |
| +#define ALL_CR_NUM_OF_ALL_AC (CR_NUM_OF_AC * 4) |
| +struct bmac_queue_info { |
| + char *QueueName; |
| + u32 Portid; |
| + u32 Queueid; |
| + u32 tgid; |
| +}; |
| + |
| +struct bmac_queue_info_t { |
| + char *QueueName; |
| + u32 Portid; |
| + u32 Queueid; |
| +}; |
| + |
| +/* WTBL */ |
| +enum besra_wtbl_type { |
| + WTBL_TYPE_LMAC, /* WTBL in LMAC */ |
| + WTBL_TYPE_UMAC, /* WTBL in UMAC */ |
| + WTBL_TYPE_KEY, /* Key Table */ |
| + MAX_NUM_WTBL_TYPE |
| +}; |
| + |
| +struct berse_wtbl_parse { |
| + u8 *name; |
| + u32 mask; |
| + u32 shift; |
| + u8 new_line; |
| +}; |
| + |
| +enum muar_idx { |
| + MUAR_INDEX_OWN_MAC_ADDR_0 = 0, |
| + MUAR_INDEX_OWN_MAC_ADDR_1, |
| + MUAR_INDEX_OWN_MAC_ADDR_2, |
| + MUAR_INDEX_OWN_MAC_ADDR_3, |
| + MUAR_INDEX_OWN_MAC_ADDR_4, |
| + MUAR_INDEX_OWN_MAC_ADDR_BC_MC = 0xE, |
| + MUAR_INDEX_UNMATCHED = 0xF, |
| + MUAR_INDEX_OWN_MAC_ADDR_11 = 0x11, |
| + MUAR_INDEX_OWN_MAC_ADDR_12, |
| + MUAR_INDEX_OWN_MAC_ADDR_13, |
| + MUAR_INDEX_OWN_MAC_ADDR_14, |
| + MUAR_INDEX_OWN_MAC_ADDR_15, |
| + MUAR_INDEX_OWN_MAC_ADDR_16, |
| + MUAR_INDEX_OWN_MAC_ADDR_17, |
| + MUAR_INDEX_OWN_MAC_ADDR_18, |
| + MUAR_INDEX_OWN_MAC_ADDR_19, |
| + MUAR_INDEX_OWN_MAC_ADDR_1A, |
| + MUAR_INDEX_OWN_MAC_ADDR_1B, |
| + MUAR_INDEX_OWN_MAC_ADDR_1C, |
| + MUAR_INDEX_OWN_MAC_ADDR_1D, |
| + MUAR_INDEX_OWN_MAC_ADDR_1E, |
| + MUAR_INDEX_OWN_MAC_ADDR_1F, |
| + MUAR_INDEX_OWN_MAC_ADDR_20, |
| + MUAR_INDEX_OWN_MAC_ADDR_21, |
| + MUAR_INDEX_OWN_MAC_ADDR_22, |
| + MUAR_INDEX_OWN_MAC_ADDR_23, |
| + MUAR_INDEX_OWN_MAC_ADDR_24, |
| + MUAR_INDEX_OWN_MAC_ADDR_25, |
| + MUAR_INDEX_OWN_MAC_ADDR_26, |
| + MUAR_INDEX_OWN_MAC_ADDR_27, |
| + MUAR_INDEX_OWN_MAC_ADDR_28, |
| + MUAR_INDEX_OWN_MAC_ADDR_29, |
| + MUAR_INDEX_OWN_MAC_ADDR_2A, |
| + MUAR_INDEX_OWN_MAC_ADDR_2B, |
| + MUAR_INDEX_OWN_MAC_ADDR_2C, |
| + MUAR_INDEX_OWN_MAC_ADDR_2D, |
| + MUAR_INDEX_OWN_MAC_ADDR_2E, |
| + MUAR_INDEX_OWN_MAC_ADDR_2F |
| +}; |
| + |
| +enum cipher_suit { |
| + IGTK_CIPHER_SUIT_NONE = 0, |
| + IGTK_CIPHER_SUIT_BIP, |
| + IGTK_CIPHER_SUIT_BIP_256 |
| +}; |
| + |
| +#define LWTBL_LEN_IN_DW 36 |
| +#define UWTBL_LEN_IN_DW 10 |
| + |
| +#define MT_DBG_WTBL_BASE 0x820D8000 |
| + |
| +#define MT_DBG_WTBLON_TOP_BASE 0x820d4000 |
| +#define MT_DBG_WTBLON_TOP_WDUCR_ADDR (MT_DBG_WTBLON_TOP_BASE + 0x0370) // 4370 |
| +#define MT_DBG_WTBLON_TOP_WDUCR_GROUP GENMASK(4, 0) |
| + |
| +#define MT_DBG_UWTBL_TOP_BASE 0x820c4000 |
| +#define MT_DBG_UWTBL_TOP_WDUCR_ADDR (MT_DBG_UWTBL_TOP_BASE + 0x0104) // 4104 |
| +#define MT_DBG_UWTBL_TOP_WDUCR_GROUP GENMASK(5, 0) |
| +#define MT_DBG_UWTBL_TOP_WDUCR_TARGET BIT(31) |
| + |
| +#define LWTBL_IDX2BASE_ID GENMASK(14, 8) |
| +#define LWTBL_IDX2BASE_DW GENMASK(7, 2) |
| +#define LWTBL_IDX2BASE(_id, _dw) (MT_DBG_WTBL_BASE | \ |
| + FIELD_PREP(LWTBL_IDX2BASE_ID, _id) | \ |
| + FIELD_PREP(LWTBL_IDX2BASE_DW, _dw)) |
| + |
| +#define UWTBL_IDX2BASE_ID GENMASK(12, 6) |
| +#define UWTBL_IDX2BASE_DW GENMASK(5, 2) |
| +#define UWTBL_IDX2BASE(_id, _dw) (MT_DBG_UWTBL_TOP_BASE | 0x2000 | \ |
| + FIELD_PREP(UWTBL_IDX2BASE_ID, _id) | \ |
| + FIELD_PREP(UWTBL_IDX2BASE_DW, _dw)) |
| + |
| +#define KEYTBL_IDX2BASE_KEY GENMASK(12, 6) |
| +#define KEYTBL_IDX2BASE_DW GENMASK(5, 2) |
| +#define KEYTBL_IDX2BASE(_key, _dw) (MT_DBG_UWTBL_TOP_BASE | 0x2000 | \ |
| + FIELD_PREP(KEYTBL_IDX2BASE_KEY, _key) | \ |
| + FIELD_PREP(KEYTBL_IDX2BASE_DW, _dw)) |
| + |
| +// UMAC WTBL |
| +// DW0 |
| +#define WF_UWTBL_PEER_MLD_ADDRESS_47_32__DW 0 |
| +#define WF_UWTBL_PEER_MLD_ADDRESS_47_32__ADDR 0 |
| +#define WF_UWTBL_PEER_MLD_ADDRESS_47_32__MASK 0x0000ffff // 15- 0 |
| +#define WF_UWTBL_PEER_MLD_ADDRESS_47_32__SHIFT 0 |
| +#define WF_UWTBL_OWN_MLD_ID_DW 0 |
| +#define WF_UWTBL_OWN_MLD_ID_ADDR 0 |
| +#define WF_UWTBL_OWN_MLD_ID_MASK 0x003f0000 // 21-16 |
| +#define WF_UWTBL_OWN_MLD_ID_SHIFT 16 |
| +// DW1 |
| +#define WF_UWTBL_PEER_MLD_ADDRESS_31_0__DW 1 |
| +#define WF_UWTBL_PEER_MLD_ADDRESS_31_0__ADDR 4 |
| +#define WF_UWTBL_PEER_MLD_ADDRESS_31_0__MASK 0xffffffff // 31- 0 |
| +#define WF_UWTBL_PEER_MLD_ADDRESS_31_0__SHIFT 0 |
| +// DW2 |
| +#define WF_UWTBL_PN_31_0__DW 2 |
| +#define WF_UWTBL_PN_31_0__ADDR 8 |
| +#define WF_UWTBL_PN_31_0__MASK 0xffffffff // 31- 0 |
| +#define WF_UWTBL_PN_31_0__SHIFT 0 |
| +// DW3 |
| +#define WF_UWTBL_PN_47_32__DW 3 |
| +#define WF_UWTBL_PN_47_32__ADDR 12 |
| +#define WF_UWTBL_PN_47_32__MASK 0x0000ffff // 15- 0 |
| +#define WF_UWTBL_PN_47_32__SHIFT 0 |
| +#define WF_UWTBL_COM_SN_DW 3 |
| +#define WF_UWTBL_COM_SN_ADDR 12 |
| +#define WF_UWTBL_COM_SN_MASK 0x0fff0000 // 27-16 |
| +#define WF_UWTBL_COM_SN_SHIFT 16 |
| +// DW4 |
| +#define WF_UWTBL_TID0_SN_DW 4 |
| +#define WF_UWTBL_TID0_SN_ADDR 16 |
| +#define WF_UWTBL_TID0_SN_MASK 0x00000fff // 11- 0 |
| +#define WF_UWTBL_TID0_SN_SHIFT 0 |
| +#define WF_UWTBL_RX_BIPN_31_0__DW 4 |
| +#define WF_UWTBL_RX_BIPN_31_0__ADDR 16 |
| +#define WF_UWTBL_RX_BIPN_31_0__MASK 0xffffffff // 31- 0 |
| +#define WF_UWTBL_RX_BIPN_31_0__SHIFT 0 |
| +#define WF_UWTBL_TID1_SN_DW 4 |
| +#define WF_UWTBL_TID1_SN_ADDR 16 |
| +#define WF_UWTBL_TID1_SN_MASK 0x00fff000 // 23-12 |
| +#define WF_UWTBL_TID1_SN_SHIFT 12 |
| +#define WF_UWTBL_TID2_SN_7_0__DW 4 |
| +#define WF_UWTBL_TID2_SN_7_0__ADDR 16 |
| +#define WF_UWTBL_TID2_SN_7_0__MASK 0xff000000 // 31-24 |
| +#define WF_UWTBL_TID2_SN_7_0__SHIFT 24 |
| +// DW5 |
| +#define WF_UWTBL_TID2_SN_11_8__DW 5 |
| +#define WF_UWTBL_TID2_SN_11_8__ADDR 20 |
| +#define WF_UWTBL_TID2_SN_11_8__MASK 0x0000000f // 3- 0 |
| +#define WF_UWTBL_TID2_SN_11_8__SHIFT 0 |
| +#define WF_UWTBL_RX_BIPN_47_32__DW 5 |
| +#define WF_UWTBL_RX_BIPN_47_32__ADDR 20 |
| +#define WF_UWTBL_RX_BIPN_47_32__MASK 0x0000ffff // 15- 0 |
| +#define WF_UWTBL_RX_BIPN_47_32__SHIFT 0 |
| +#define WF_UWTBL_TID3_SN_DW 5 |
| +#define WF_UWTBL_TID3_SN_ADDR 20 |
| +#define WF_UWTBL_TID3_SN_MASK 0x0000fff0 // 15- 4 |
| +#define WF_UWTBL_TID3_SN_SHIFT 4 |
| +#define WF_UWTBL_TID4_SN_DW 5 |
| +#define WF_UWTBL_TID4_SN_ADDR 20 |
| +#define WF_UWTBL_TID4_SN_MASK 0x0fff0000 // 27-16 |
| +#define WF_UWTBL_TID4_SN_SHIFT 16 |
| +#define WF_UWTBL_TID5_SN_3_0__DW 5 |
| +#define WF_UWTBL_TID5_SN_3_0__ADDR 20 |
| +#define WF_UWTBL_TID5_SN_3_0__MASK 0xf0000000 // 31-28 |
| +#define WF_UWTBL_TID5_SN_3_0__SHIFT 28 |
| +// DW6 |
| +#define WF_UWTBL_TID5_SN_11_4__DW 6 |
| +#define WF_UWTBL_TID5_SN_11_4__ADDR 24 |
| +#define WF_UWTBL_TID5_SN_11_4__MASK 0x000000ff // 7- 0 |
| +#define WF_UWTBL_TID5_SN_11_4__SHIFT 0 |
| +#define WF_UWTBL_KEY_LOC2_DW 6 |
| +#define WF_UWTBL_KEY_LOC2_ADDR 24 |
| +#define WF_UWTBL_KEY_LOC2_MASK 0x00001fff // 12- 0 |
| +#define WF_UWTBL_KEY_LOC2_SHIFT 0 |
| +#define WF_UWTBL_TID6_SN_DW 6 |
| +#define WF_UWTBL_TID6_SN_ADDR 24 |
| +#define WF_UWTBL_TID6_SN_MASK 0x000fff00 // 19- 8 |
| +#define WF_UWTBL_TID6_SN_SHIFT 8 |
| +#define WF_UWTBL_TID7_SN_DW 6 |
| +#define WF_UWTBL_TID7_SN_ADDR 24 |
| +#define WF_UWTBL_TID7_SN_MASK 0xfff00000 // 31-20 |
| +#define WF_UWTBL_TID7_SN_SHIFT 20 |
| +// DW7 |
| +#define WF_UWTBL_KEY_LOC0_DW 7 |
| +#define WF_UWTBL_KEY_LOC0_ADDR 28 |
| +#define WF_UWTBL_KEY_LOC0_MASK 0x00001fff // 12- 0 |
| +#define WF_UWTBL_KEY_LOC0_SHIFT 0 |
| +#define WF_UWTBL_KEY_LOC1_DW 7 |
| +#define WF_UWTBL_KEY_LOC1_ADDR 28 |
| +#define WF_UWTBL_KEY_LOC1_MASK 0x1fff0000 // 28-16 |
| +#define WF_UWTBL_KEY_LOC1_SHIFT 16 |
| +// DW8 |
| +#define WF_UWTBL_AMSDU_CFG_DW 8 |
| +#define WF_UWTBL_AMSDU_CFG_ADDR 32 |
| +#define WF_UWTBL_AMSDU_CFG_MASK 0x00000fff // 11- 0 |
| +#define WF_UWTBL_AMSDU_CFG_SHIFT 0 |
| +#define WF_UWTBL_WMM_Q_DW 8 |
| +#define WF_UWTBL_WMM_Q_ADDR 32 |
| +#define WF_UWTBL_WMM_Q_MASK 0x06000000 // 26-25 |
| +#define WF_UWTBL_WMM_Q_SHIFT 25 |
| +#define WF_UWTBL_QOS_DW 8 |
| +#define WF_UWTBL_QOS_ADDR 32 |
| +#define WF_UWTBL_QOS_MASK 0x08000000 // 27-27 |
| +#define WF_UWTBL_QOS_SHIFT 27 |
| +#define WF_UWTBL_HT_DW 8 |
| +#define WF_UWTBL_HT_ADDR 32 |
| +#define WF_UWTBL_HT_MASK 0x10000000 // 28-28 |
| +#define WF_UWTBL_HT_SHIFT 28 |
| +#define WF_UWTBL_HDRT_MODE_DW 8 |
| +#define WF_UWTBL_HDRT_MODE_ADDR 32 |
| +#define WF_UWTBL_HDRT_MODE_MASK 0x20000000 // 29-29 |
| +#define WF_UWTBL_HDRT_MODE_SHIFT 29 |
| +// DW9 |
| +#define WF_UWTBL_RELATED_IDX0_DW 9 |
| +#define WF_UWTBL_RELATED_IDX0_ADDR 36 |
| +#define WF_UWTBL_RELATED_IDX0_MASK 0x00000fff // 11- 0 |
| +#define WF_UWTBL_RELATED_IDX0_SHIFT 0 |
| +#define WF_UWTBL_RELATED_BAND0_DW 9 |
| +#define WF_UWTBL_RELATED_BAND0_ADDR 36 |
| +#define WF_UWTBL_RELATED_BAND0_MASK 0x00003000 // 13-12 |
| +#define WF_UWTBL_RELATED_BAND0_SHIFT 12 |
| +#define WF_UWTBL_PRIMARY_MLD_BAND_DW 9 |
| +#define WF_UWTBL_PRIMARY_MLD_BAND_ADDR 36 |
| +#define WF_UWTBL_PRIMARY_MLD_BAND_MASK 0x0000c000 // 15-14 |
| +#define WF_UWTBL_PRIMARY_MLD_BAND_SHIFT 14 |
| +#define WF_UWTBL_RELATED_IDX1_DW 9 |
| +#define WF_UWTBL_RELATED_IDX1_ADDR 36 |
| +#define WF_UWTBL_RELATED_IDX1_MASK 0x0fff0000 // 27-16 |
| +#define WF_UWTBL_RELATED_IDX1_SHIFT 16 |
| +#define WF_UWTBL_RELATED_BAND1_DW 9 |
| +#define WF_UWTBL_RELATED_BAND1_ADDR 36 |
| +#define WF_UWTBL_RELATED_BAND1_MASK 0x30000000 // 29-28 |
| +#define WF_UWTBL_RELATED_BAND1_SHIFT 28 |
| +#define WF_UWTBL_SECONDARY_MLD_BAND_DW 9 |
| +#define WF_UWTBL_SECONDARY_MLD_BAND_ADDR 36 |
| +#define WF_UWTBL_SECONDARY_MLD_BAND_MASK 0xc0000000 // 31-30 |
| +#define WF_UWTBL_SECONDARY_MLD_BAND_SHIFT 30 |
| + |
| +/* LMAC WTBL */ |
| +// DW0 |
| +#define WF_LWTBL_PEER_LINK_ADDRESS_47_32__DW 0 |
| +#define WF_LWTBL_PEER_LINK_ADDRESS_47_32__ADDR 0 |
| +#define WF_LWTBL_PEER_LINK_ADDRESS_47_32__MASK \ |
| + 0x0000ffff // 15- 0 |
| +#define WF_LWTBL_PEER_LINK_ADDRESS_47_32__SHIFT 0 |
| +#define WF_LWTBL_MUAR_DW 0 |
| +#define WF_LWTBL_MUAR_ADDR 0 |
| +#define WF_LWTBL_MUAR_MASK \ |
| + 0x003f0000 // 21-16 |
| +#define WF_LWTBL_MUAR_SHIFT 16 |
| +#define WF_LWTBL_RCA1_DW 0 |
| +#define WF_LWTBL_RCA1_ADDR 0 |
| +#define WF_LWTBL_RCA1_MASK \ |
| + 0x00400000 // 22-22 |
| +#define WF_LWTBL_RCA1_SHIFT 22 |
| +#define WF_LWTBL_KID_DW 0 |
| +#define WF_LWTBL_KID_ADDR 0 |
| +#define WF_LWTBL_KID_MASK \ |
| + 0x01800000 // 24-23 |
| +#define WF_LWTBL_KID_SHIFT 23 |
| +#define WF_LWTBL_RCID_DW 0 |
| +#define WF_LWTBL_RCID_ADDR 0 |
| +#define WF_LWTBL_RCID_MASK \ |
| + 0x02000000 // 25-25 |
| +#define WF_LWTBL_RCID_SHIFT 25 |
| +#define WF_LWTBL_BAND_DW 0 |
| +#define WF_LWTBL_BAND_ADDR 0 |
| +#define WF_LWTBL_BAND_MASK \ |
| + 0x0c000000 // 27-26 |
| +#define WF_LWTBL_BAND_SHIFT 26 |
| +#define WF_LWTBL_RV_DW 0 |
| +#define WF_LWTBL_RV_ADDR 0 |
| +#define WF_LWTBL_RV_MASK \ |
| + 0x10000000 // 28-28 |
| +#define WF_LWTBL_RV_SHIFT 28 |
| +#define WF_LWTBL_RCA2_DW 0 |
| +#define WF_LWTBL_RCA2_ADDR 0 |
| +#define WF_LWTBL_RCA2_MASK \ |
| + 0x20000000 // 29-29 |
| +#define WF_LWTBL_RCA2_SHIFT 29 |
| +#define WF_LWTBL_WPI_FLAG_DW 0 |
| +#define WF_LWTBL_WPI_FLAG_ADDR 0 |
| +#define WF_LWTBL_WPI_FLAG_MASK \ |
| + 0x40000000 // 30-30 |
| +#define WF_LWTBL_WPI_FLAG_SHIFT 30 |
| +// DW1 |
| +#define WF_LWTBL_PEER_LINK_ADDRESS_31_0__DW 1 |
| +#define WF_LWTBL_PEER_LINK_ADDRESS_31_0__ADDR 4 |
| +#define WF_LWTBL_PEER_LINK_ADDRESS_31_0__MASK \ |
| + 0xffffffff // 31- 0 |
| +#define WF_LWTBL_PEER_LINK_ADDRESS_31_0__SHIFT 0 |
| +// DW2 |
| +#define WF_LWTBL_AID_DW 2 |
| +#define WF_LWTBL_AID_ADDR 8 |
| +#define WF_LWTBL_AID_MASK \ |
| + 0x00000fff // 11- 0 |
| +#define WF_LWTBL_AID_SHIFT 0 |
| +#define WF_LWTBL_GID_SU_DW 2 |
| +#define WF_LWTBL_GID_SU_ADDR 8 |
| +#define WF_LWTBL_GID_SU_MASK \ |
| + 0x00001000 // 12-12 |
| +#define WF_LWTBL_GID_SU_SHIFT 12 |
| +#define WF_LWTBL_SPP_EN_DW 2 |
| +#define WF_LWTBL_SPP_EN_ADDR 8 |
| +#define WF_LWTBL_SPP_EN_MASK \ |
| + 0x00002000 // 13-13 |
| +#define WF_LWTBL_SPP_EN_SHIFT 13 |
| +#define WF_LWTBL_WPI_EVEN_DW 2 |
| +#define WF_LWTBL_WPI_EVEN_ADDR 8 |
| +#define WF_LWTBL_WPI_EVEN_MASK \ |
| + 0x00004000 // 14-14 |
| +#define WF_LWTBL_WPI_EVEN_SHIFT 14 |
| +#define WF_LWTBL_AAD_OM_DW 2 |
| +#define WF_LWTBL_AAD_OM_ADDR 8 |
| +#define WF_LWTBL_AAD_OM_MASK \ |
| + 0x00008000 // 15-15 |
| +#define WF_LWTBL_AAD_OM_SHIFT 15 |
| +#define WF_LWTBL_CIPHER_SUIT_PGTK_DW 2 |
| +#define WF_LWTBL_CIPHER_SUIT_PGTK_ADDR 8 |
| +#define WF_LWTBL_CIPHER_SUIT_PGTK_MASK \ |
| + 0x001f0000 // 20-16 |
| +#define WF_LWTBL_CIPHER_SUIT_PGTK_SHIFT 16 |
| +#define WF_LWTBL_FD_DW 2 |
| +#define WF_LWTBL_FD_ADDR 8 |
| +#define WF_LWTBL_FD_MASK \ |
| + 0x00200000 // 21-21 |
| +#define WF_LWTBL_FD_SHIFT 21 |
| +#define WF_LWTBL_TD_DW 2 |
| +#define WF_LWTBL_TD_ADDR 8 |
| +#define WF_LWTBL_TD_MASK \ |
| + 0x00400000 // 22-22 |
| +#define WF_LWTBL_TD_SHIFT 22 |
| +#define WF_LWTBL_SW_DW 2 |
| +#define WF_LWTBL_SW_ADDR 8 |
| +#define WF_LWTBL_SW_MASK \ |
| + 0x00800000 // 23-23 |
| +#define WF_LWTBL_SW_SHIFT 23 |
| +#define WF_LWTBL_UL_DW 2 |
| +#define WF_LWTBL_UL_ADDR 8 |
| +#define WF_LWTBL_UL_MASK \ |
| + 0x01000000 // 24-24 |
| +#define WF_LWTBL_UL_SHIFT 24 |
| +#define WF_LWTBL_TX_PS_DW 2 |
| +#define WF_LWTBL_TX_PS_ADDR 8 |
| +#define WF_LWTBL_TX_PS_MASK \ |
| + 0x02000000 // 25-25 |
| +#define WF_LWTBL_TX_PS_SHIFT 25 |
| +#define WF_LWTBL_QOS_DW 2 |
| +#define WF_LWTBL_QOS_ADDR 8 |
| +#define WF_LWTBL_QOS_MASK \ |
| + 0x04000000 // 26-26 |
| +#define WF_LWTBL_QOS_SHIFT 26 |
| +#define WF_LWTBL_HT_DW 2 |
| +#define WF_LWTBL_HT_ADDR 8 |
| +#define WF_LWTBL_HT_MASK \ |
| + 0x08000000 // 27-27 |
| +#define WF_LWTBL_HT_SHIFT 27 |
| +#define WF_LWTBL_VHT_DW 2 |
| +#define WF_LWTBL_VHT_ADDR 8 |
| +#define WF_LWTBL_VHT_MASK \ |
| + 0x10000000 // 28-28 |
| +#define WF_LWTBL_VHT_SHIFT 28 |
| +#define WF_LWTBL_HE_DW 2 |
| +#define WF_LWTBL_HE_ADDR 8 |
| +#define WF_LWTBL_HE_MASK \ |
| + 0x20000000 // 29-29 |
| +#define WF_LWTBL_HE_SHIFT 29 |
| +#define WF_LWTBL_EHT_DW 2 |
| +#define WF_LWTBL_EHT_ADDR 8 |
| +#define WF_LWTBL_EHT_MASK \ |
| + 0x40000000 // 30-30 |
| +#define WF_LWTBL_EHT_SHIFT 30 |
| +#define WF_LWTBL_MESH_DW 2 |
| +#define WF_LWTBL_MESH_ADDR 8 |
| +#define WF_LWTBL_MESH_MASK \ |
| + 0x80000000 // 31-31 |
| +#define WF_LWTBL_MESH_SHIFT 31 |
| +// DW3 |
| +#define WF_LWTBL_WMM_Q_DW 3 |
| +#define WF_LWTBL_WMM_Q_ADDR 12 |
| +#define WF_LWTBL_WMM_Q_MASK \ |
| + 0x00000003 // 1- 0 |
| +#define WF_LWTBL_WMM_Q_SHIFT 0 |
| +#define WF_LWTBL_EHT_SIG_MCS_DW 3 |
| +#define WF_LWTBL_EHT_SIG_MCS_ADDR 12 |
| +#define WF_LWTBL_EHT_SIG_MCS_MASK \ |
| + 0x0000000c // 3- 2 |
| +#define WF_LWTBL_EHT_SIG_MCS_SHIFT 2 |
| +#define WF_LWTBL_HDRT_MODE_DW 3 |
| +#define WF_LWTBL_HDRT_MODE_ADDR 12 |
| +#define WF_LWTBL_HDRT_MODE_MASK \ |
| + 0x00000010 // 4- 4 |
| +#define WF_LWTBL_HDRT_MODE_SHIFT 4 |
| +#define WF_LWTBL_BEAM_CHG_DW 3 |
| +#define WF_LWTBL_BEAM_CHG_ADDR 12 |
| +#define WF_LWTBL_BEAM_CHG_MASK \ |
| + 0x00000020 // 5- 5 |
| +#define WF_LWTBL_BEAM_CHG_SHIFT 5 |
| +#define WF_LWTBL_EHT_LTF_SYM_NUM_OPT_DW 3 |
| +#define WF_LWTBL_EHT_LTF_SYM_NUM_OPT_ADDR 12 |
| +#define WF_LWTBL_EHT_LTF_SYM_NUM_OPT_MASK \ |
| + 0x000000c0 // 7- 6 |
| +#define WF_LWTBL_EHT_LTF_SYM_NUM_OPT_SHIFT 6 |
| +#define WF_LWTBL_PFMU_IDX_DW 3 |
| +#define WF_LWTBL_PFMU_IDX_ADDR 12 |
| +#define WF_LWTBL_PFMU_IDX_MASK \ |
| + 0x0000ff00 // 15- 8 |
| +#define WF_LWTBL_PFMU_IDX_SHIFT 8 |
| +#define WF_LWTBL_ULPF_IDX_DW 3 |
| +#define WF_LWTBL_ULPF_IDX_ADDR 12 |
| +#define WF_LWTBL_ULPF_IDX_MASK \ |
| + 0x00ff0000 // 23-16 |
| +#define WF_LWTBL_ULPF_IDX_SHIFT 16 |
| +#define WF_LWTBL_RIBF_DW 3 |
| +#define WF_LWTBL_RIBF_ADDR 12 |
| +#define WF_LWTBL_RIBF_MASK \ |
| + 0x01000000 // 24-24 |
| +#define WF_LWTBL_RIBF_SHIFT 24 |
| +#define WF_LWTBL_ULPF_DW 3 |
| +#define WF_LWTBL_ULPF_ADDR 12 |
| +#define WF_LWTBL_ULPF_MASK \ |
| + 0x02000000 // 25-25 |
| +#define WF_LWTBL_ULPF_SHIFT 25 |
| +#define WF_LWTBL_TBF_HT_DW 3 |
| +#define WF_LWTBL_TBF_HT_ADDR 12 |
| +#define WF_LWTBL_TBF_HT_MASK \ |
| + 0x08000000 // 27-27 |
| +#define WF_LWTBL_TBF_HT_SHIFT 27 |
| +#define WF_LWTBL_TBF_VHT_DW 3 |
| +#define WF_LWTBL_TBF_VHT_ADDR 12 |
| +#define WF_LWTBL_TBF_VHT_MASK \ |
| + 0x10000000 // 28-28 |
| +#define WF_LWTBL_TBF_VHT_SHIFT 28 |
| +#define WF_LWTBL_TBF_HE_DW 3 |
| +#define WF_LWTBL_TBF_HE_ADDR 12 |
| +#define WF_LWTBL_TBF_HE_MASK \ |
| + 0x20000000 // 29-29 |
| +#define WF_LWTBL_TBF_HE_SHIFT 29 |
| +#define WF_LWTBL_TBF_EHT_DW 3 |
| +#define WF_LWTBL_TBF_EHT_ADDR 12 |
| +#define WF_LWTBL_TBF_EHT_MASK \ |
| + 0x40000000 // 30-30 |
| +#define WF_LWTBL_TBF_EHT_SHIFT 30 |
| +#define WF_LWTBL_IGN_FBK_DW 3 |
| +#define WF_LWTBL_IGN_FBK_ADDR 12 |
| +#define WF_LWTBL_IGN_FBK_MASK \ |
| + 0x80000000 // 31-31 |
| +#define WF_LWTBL_IGN_FBK_SHIFT 31 |
| +// DW4 |
| +#define WF_LWTBL_ANT_ID0_DW 4 |
| +#define WF_LWTBL_ANT_ID0_ADDR 16 |
| +#define WF_LWTBL_ANT_ID0_MASK \ |
| + 0x00000007 // 2- 0 |
| +#define WF_LWTBL_ANT_ID0_SHIFT 0 |
| +#define WF_LWTBL_ANT_ID1_DW 4 |
| +#define WF_LWTBL_ANT_ID1_ADDR 16 |
| +#define WF_LWTBL_ANT_ID1_MASK \ |
| + 0x00000038 // 5- 3 |
| +#define WF_LWTBL_ANT_ID1_SHIFT 3 |
| +#define WF_LWTBL_ANT_ID2_DW 4 |
| +#define WF_LWTBL_ANT_ID2_ADDR 16 |
| +#define WF_LWTBL_ANT_ID2_MASK \ |
| + 0x000001c0 // 8- 6 |
| +#define WF_LWTBL_ANT_ID2_SHIFT 6 |
| +#define WF_LWTBL_ANT_ID3_DW 4 |
| +#define WF_LWTBL_ANT_ID3_ADDR 16 |
| +#define WF_LWTBL_ANT_ID3_MASK \ |
| + 0x00000e00 // 11- 9 |
| +#define WF_LWTBL_ANT_ID3_SHIFT 9 |
| +#define WF_LWTBL_ANT_ID4_DW 4 |
| +#define WF_LWTBL_ANT_ID4_ADDR 16 |
| +#define WF_LWTBL_ANT_ID4_MASK \ |
| + 0x00007000 // 14-12 |
| +#define WF_LWTBL_ANT_ID4_SHIFT 12 |
| +#define WF_LWTBL_ANT_ID5_DW 4 |
| +#define WF_LWTBL_ANT_ID5_ADDR 16 |
| +#define WF_LWTBL_ANT_ID5_MASK \ |
| + 0x00038000 // 17-15 |
| +#define WF_LWTBL_ANT_ID5_SHIFT 15 |
| +#define WF_LWTBL_ANT_ID6_DW 4 |
| +#define WF_LWTBL_ANT_ID6_ADDR 16 |
| +#define WF_LWTBL_ANT_ID6_MASK \ |
| + 0x001c0000 // 20-18 |
| +#define WF_LWTBL_ANT_ID6_SHIFT 18 |
| +#define WF_LWTBL_ANT_ID7_DW 4 |
| +#define WF_LWTBL_ANT_ID7_ADDR 16 |
| +#define WF_LWTBL_ANT_ID7_MASK \ |
| + 0x00e00000 // 23-21 |
| +#define WF_LWTBL_ANT_ID7_SHIFT 21 |
| +#define WF_LWTBL_PE_DW 4 |
| +#define WF_LWTBL_PE_ADDR 16 |
| +#define WF_LWTBL_PE_MASK \ |
| + 0x03000000 // 25-24 |
| +#define WF_LWTBL_PE_SHIFT 24 |
| +#define WF_LWTBL_DIS_RHTR_DW 4 |
| +#define WF_LWTBL_DIS_RHTR_ADDR 16 |
| +#define WF_LWTBL_DIS_RHTR_MASK \ |
| + 0x04000000 // 26-26 |
| +#define WF_LWTBL_DIS_RHTR_SHIFT 26 |
| +#define WF_LWTBL_LDPC_HT_DW 4 |
| +#define WF_LWTBL_LDPC_HT_ADDR 16 |
| +#define WF_LWTBL_LDPC_HT_MASK \ |
| + 0x08000000 // 27-27 |
| +#define WF_LWTBL_LDPC_HT_SHIFT 27 |
| +#define WF_LWTBL_LDPC_VHT_DW 4 |
| +#define WF_LWTBL_LDPC_VHT_ADDR 16 |
| +#define WF_LWTBL_LDPC_VHT_MASK \ |
| + 0x10000000 // 28-28 |
| +#define WF_LWTBL_LDPC_VHT_SHIFT 28 |
| +#define WF_LWTBL_LDPC_HE_DW 4 |
| +#define WF_LWTBL_LDPC_HE_ADDR 16 |
| +#define WF_LWTBL_LDPC_HE_MASK \ |
| + 0x20000000 // 29-29 |
| +#define WF_LWTBL_LDPC_HE_SHIFT 29 |
| +#define WF_LWTBL_LDPC_EHT_DW 4 |
| +#define WF_LWTBL_LDPC_EHT_ADDR 16 |
| +#define WF_LWTBL_LDPC_EHT_MASK \ |
| + 0x40000000 // 30-30 |
| +#define WF_LWTBL_LDPC_EHT_SHIFT 30 |
| +// DW5 |
| +#define WF_LWTBL_AF_DW 5 |
| +#define WF_LWTBL_AF_ADDR 20 |
| +#define WF_LWTBL_AF_MASK \ |
| + 0x00000007 // 2- 0 |
| +#define WF_LWTBL_AF_SHIFT 0 |
| +#define WF_LWTBL_AF_HE_DW 5 |
| +#define WF_LWTBL_AF_HE_ADDR 20 |
| +#define WF_LWTBL_AF_HE_MASK \ |
| + 0x00000018 // 4- 3 |
| +#define WF_LWTBL_AF_HE_SHIFT 3 |
| +#define WF_LWTBL_RTS_DW 5 |
| +#define WF_LWTBL_RTS_ADDR 20 |
| +#define WF_LWTBL_RTS_MASK \ |
| + 0x00000020 // 5- 5 |
| +#define WF_LWTBL_RTS_SHIFT 5 |
| +#define WF_LWTBL_SMPS_DW 5 |
| +#define WF_LWTBL_SMPS_ADDR 20 |
| +#define WF_LWTBL_SMPS_MASK \ |
| + 0x00000040 // 6- 6 |
| +#define WF_LWTBL_SMPS_SHIFT 6 |
| +#define WF_LWTBL_DYN_BW_DW 5 |
| +#define WF_LWTBL_DYN_BW_ADDR 20 |
| +#define WF_LWTBL_DYN_BW_MASK \ |
| + 0x00000080 // 7- 7 |
| +#define WF_LWTBL_DYN_BW_SHIFT 7 |
| +#define WF_LWTBL_MMSS_DW 5 |
| +#define WF_LWTBL_MMSS_ADDR 20 |
| +#define WF_LWTBL_MMSS_MASK \ |
| + 0x00000700 // 10- 8 |
| +#define WF_LWTBL_MMSS_SHIFT 8 |
| +#define WF_LWTBL_USR_DW 5 |
| +#define WF_LWTBL_USR_ADDR 20 |
| +#define WF_LWTBL_USR_MASK \ |
| + 0x00000800 // 11-11 |
| +#define WF_LWTBL_USR_SHIFT 11 |
| +#define WF_LWTBL_SR_R_DW 5 |
| +#define WF_LWTBL_SR_R_ADDR 20 |
| +#define WF_LWTBL_SR_R_MASK \ |
| + 0x00007000 // 14-12 |
| +#define WF_LWTBL_SR_R_SHIFT 12 |
| +#define WF_LWTBL_SR_ABORT_DW 5 |
| +#define WF_LWTBL_SR_ABORT_ADDR 20 |
| +#define WF_LWTBL_SR_ABORT_MASK \ |
| + 0x00008000 // 15-15 |
| +#define WF_LWTBL_SR_ABORT_SHIFT 15 |
| +#define WF_LWTBL_TX_POWER_OFFSET_DW 5 |
| +#define WF_LWTBL_TX_POWER_OFFSET_ADDR 20 |
| +#define WF_LWTBL_TX_POWER_OFFSET_MASK \ |
| + 0x003f0000 // 21-16 |
| +#define WF_LWTBL_TX_POWER_OFFSET_SHIFT 16 |
| +#define WF_LWTBL_LTF_EHT_DW 5 |
| +#define WF_LWTBL_LTF_EHT_ADDR 20 |
| +#define WF_LWTBL_LTF_EHT_MASK \ |
| + 0x00c00000 // 23-22 |
| +#define WF_LWTBL_LTF_EHT_SHIFT 22 |
| +#define WF_LWTBL_GI_EHT_DW 5 |
| +#define WF_LWTBL_GI_EHT_ADDR 20 |
| +#define WF_LWTBL_GI_EHT_MASK \ |
| + 0x03000000 // 25-24 |
| +#define WF_LWTBL_GI_EHT_SHIFT 24 |
| +#define WF_LWTBL_DOPPL_DW 5 |
| +#define WF_LWTBL_DOPPL_ADDR 20 |
| +#define WF_LWTBL_DOPPL_MASK \ |
| + 0x04000000 // 26-26 |
| +#define WF_LWTBL_DOPPL_SHIFT 26 |
| +#define WF_LWTBL_TXOP_PS_CAP_DW 5 |
| +#define WF_LWTBL_TXOP_PS_CAP_ADDR 20 |
| +#define WF_LWTBL_TXOP_PS_CAP_MASK \ |
| + 0x08000000 // 27-27 |
| +#define WF_LWTBL_TXOP_PS_CAP_SHIFT 27 |
| +#define WF_LWTBL_DU_I_PSM_DW 5 |
| +#define WF_LWTBL_DU_I_PSM_ADDR 20 |
| +#define WF_LWTBL_DU_I_PSM_MASK \ |
| + 0x10000000 // 28-28 |
| +#define WF_LWTBL_DU_I_PSM_SHIFT 28 |
| +#define WF_LWTBL_I_PSM_DW 5 |
| +#define WF_LWTBL_I_PSM_ADDR 20 |
| +#define WF_LWTBL_I_PSM_MASK \ |
| + 0x20000000 // 29-29 |
| +#define WF_LWTBL_I_PSM_SHIFT 29 |
| +#define WF_LWTBL_PSM_DW 5 |
| +#define WF_LWTBL_PSM_ADDR 20 |
| +#define WF_LWTBL_PSM_MASK \ |
| + 0x40000000 // 30-30 |
| +#define WF_LWTBL_PSM_SHIFT 30 |
| +#define WF_LWTBL_SKIP_TX_DW 5 |
| +#define WF_LWTBL_SKIP_TX_ADDR 20 |
| +#define WF_LWTBL_SKIP_TX_MASK \ |
| + 0x80000000 // 31-31 |
| +#define WF_LWTBL_SKIP_TX_SHIFT 31 |
| +// DW6 |
| +#define WF_LWTBL_CBRN_DW 6 |
| +#define WF_LWTBL_CBRN_ADDR 24 |
| +#define WF_LWTBL_CBRN_MASK \ |
| + 0x00000007 // 2- 0 |
| +#define WF_LWTBL_CBRN_SHIFT 0 |
| +#define WF_LWTBL_DBNSS_EN_DW 6 |
| +#define WF_LWTBL_DBNSS_EN_ADDR 24 |
| +#define WF_LWTBL_DBNSS_EN_MASK \ |
| + 0x00000008 // 3- 3 |
| +#define WF_LWTBL_DBNSS_EN_SHIFT 3 |
| +#define WF_LWTBL_BAF_EN_DW 6 |
| +#define WF_LWTBL_BAF_EN_ADDR 24 |
| +#define WF_LWTBL_BAF_EN_MASK \ |
| + 0x00000010 // 4- 4 |
| +#define WF_LWTBL_BAF_EN_SHIFT 4 |
| +#define WF_LWTBL_RDGBA_DW 6 |
| +#define WF_LWTBL_RDGBA_ADDR 24 |
| +#define WF_LWTBL_RDGBA_MASK \ |
| + 0x00000020 // 5- 5 |
| +#define WF_LWTBL_RDGBA_SHIFT 5 |
| +#define WF_LWTBL_R_DW 6 |
| +#define WF_LWTBL_R_ADDR 24 |
| +#define WF_LWTBL_R_MASK \ |
| + 0x00000040 // 6- 6 |
| +#define WF_LWTBL_R_SHIFT 6 |
| +#define WF_LWTBL_SPE_IDX_DW 6 |
| +#define WF_LWTBL_SPE_IDX_ADDR 24 |
| +#define WF_LWTBL_SPE_IDX_MASK \ |
| + 0x00000f80 // 11- 7 |
| +#define WF_LWTBL_SPE_IDX_SHIFT 7 |
| +#define WF_LWTBL_G2_DW 6 |
| +#define WF_LWTBL_G2_ADDR 24 |
| +#define WF_LWTBL_G2_MASK \ |
| + 0x00001000 // 12-12 |
| +#define WF_LWTBL_G2_SHIFT 12 |
| +#define WF_LWTBL_G4_DW 6 |
| +#define WF_LWTBL_G4_ADDR 24 |
| +#define WF_LWTBL_G4_MASK \ |
| + 0x00002000 // 13-13 |
| +#define WF_LWTBL_G4_SHIFT 13 |
| +#define WF_LWTBL_G8_DW 6 |
| +#define WF_LWTBL_G8_ADDR 24 |
| +#define WF_LWTBL_G8_MASK \ |
| + 0x00004000 // 14-14 |
| +#define WF_LWTBL_G8_SHIFT 14 |
| +#define WF_LWTBL_G16_DW 6 |
| +#define WF_LWTBL_G16_ADDR 24 |
| +#define WF_LWTBL_G16_MASK \ |
| + 0x00008000 // 15-15 |
| +#define WF_LWTBL_G16_SHIFT 15 |
| +#define WF_LWTBL_G2_LTF_DW 6 |
| +#define WF_LWTBL_G2_LTF_ADDR 24 |
| +#define WF_LWTBL_G2_LTF_MASK \ |
| + 0x00030000 // 17-16 |
| +#define WF_LWTBL_G2_LTF_SHIFT 16 |
| +#define WF_LWTBL_G4_LTF_DW 6 |
| +#define WF_LWTBL_G4_LTF_ADDR 24 |
| +#define WF_LWTBL_G4_LTF_MASK \ |
| + 0x000c0000 // 19-18 |
| +#define WF_LWTBL_G4_LTF_SHIFT 18 |
| +#define WF_LWTBL_G8_LTF_DW 6 |
| +#define WF_LWTBL_G8_LTF_ADDR 24 |
| +#define WF_LWTBL_G8_LTF_MASK \ |
| + 0x00300000 // 21-20 |
| +#define WF_LWTBL_G8_LTF_SHIFT 20 |
| +#define WF_LWTBL_G16_LTF_DW 6 |
| +#define WF_LWTBL_G16_LTF_ADDR 24 |
| +#define WF_LWTBL_G16_LTF_MASK \ |
| + 0x00c00000 // 23-22 |
| +#define WF_LWTBL_G16_LTF_SHIFT 22 |
| +#define WF_LWTBL_G2_HE_DW 6 |
| +#define WF_LWTBL_G2_HE_ADDR 24 |
| +#define WF_LWTBL_G2_HE_MASK \ |
| + 0x03000000 // 25-24 |
| +#define WF_LWTBL_G2_HE_SHIFT 24 |
| +#define WF_LWTBL_G4_HE_DW 6 |
| +#define WF_LWTBL_G4_HE_ADDR 24 |
| +#define WF_LWTBL_G4_HE_MASK \ |
| + 0x0c000000 // 27-26 |
| +#define WF_LWTBL_G4_HE_SHIFT 26 |
| +#define WF_LWTBL_G8_HE_DW 6 |
| +#define WF_LWTBL_G8_HE_ADDR 24 |
| +#define WF_LWTBL_G8_HE_MASK \ |
| + 0x30000000 // 29-28 |
| +#define WF_LWTBL_G8_HE_SHIFT 28 |
| +#define WF_LWTBL_G16_HE_DW 6 |
| +#define WF_LWTBL_G16_HE_ADDR 24 |
| +#define WF_LWTBL_G16_HE_MASK \ |
| + 0xc0000000 // 31-30 |
| +#define WF_LWTBL_G16_HE_SHIFT 30 |
| +// DW7 |
| +#define WF_LWTBL_BA_WIN_SIZE0_DW 7 |
| +#define WF_LWTBL_BA_WIN_SIZE0_ADDR 28 |
| +#define WF_LWTBL_BA_WIN_SIZE0_MASK \ |
| + 0x0000000f // 3- 0 |
| +#define WF_LWTBL_BA_WIN_SIZE0_SHIFT 0 |
| +#define WF_LWTBL_BA_WIN_SIZE1_DW 7 |
| +#define WF_LWTBL_BA_WIN_SIZE1_ADDR 28 |
| +#define WF_LWTBL_BA_WIN_SIZE1_MASK \ |
| + 0x000000f0 // 7- 4 |
| +#define WF_LWTBL_BA_WIN_SIZE1_SHIFT 4 |
| +#define WF_LWTBL_BA_WIN_SIZE2_DW 7 |
| +#define WF_LWTBL_BA_WIN_SIZE2_ADDR 28 |
| +#define WF_LWTBL_BA_WIN_SIZE2_MASK \ |
| + 0x00000f00 // 11- 8 |
| +#define WF_LWTBL_BA_WIN_SIZE2_SHIFT 8 |
| +#define WF_LWTBL_BA_WIN_SIZE3_DW 7 |
| +#define WF_LWTBL_BA_WIN_SIZE3_ADDR 28 |
| +#define WF_LWTBL_BA_WIN_SIZE3_MASK \ |
| + 0x0000f000 // 15-12 |
| +#define WF_LWTBL_BA_WIN_SIZE3_SHIFT 12 |
| +#define WF_LWTBL_BA_WIN_SIZE4_DW 7 |
| +#define WF_LWTBL_BA_WIN_SIZE4_ADDR 28 |
| +#define WF_LWTBL_BA_WIN_SIZE4_MASK \ |
| + 0x000f0000 // 19-16 |
| +#define WF_LWTBL_BA_WIN_SIZE4_SHIFT 16 |
| +#define WF_LWTBL_BA_WIN_SIZE5_DW 7 |
| +#define WF_LWTBL_BA_WIN_SIZE5_ADDR 28 |
| +#define WF_LWTBL_BA_WIN_SIZE5_MASK \ |
| + 0x00f00000 // 23-20 |
| +#define WF_LWTBL_BA_WIN_SIZE5_SHIFT 20 |
| +#define WF_LWTBL_BA_WIN_SIZE6_DW 7 |
| +#define WF_LWTBL_BA_WIN_SIZE6_ADDR 28 |
| +#define WF_LWTBL_BA_WIN_SIZE6_MASK \ |
| + 0x0f000000 // 27-24 |
| +#define WF_LWTBL_BA_WIN_SIZE6_SHIFT 24 |
| +#define WF_LWTBL_BA_WIN_SIZE7_DW 7 |
| +#define WF_LWTBL_BA_WIN_SIZE7_ADDR 28 |
| +#define WF_LWTBL_BA_WIN_SIZE7_MASK \ |
| + 0xf0000000 // 31-28 |
| +#define WF_LWTBL_BA_WIN_SIZE7_SHIFT 28 |
| +// DW8 |
| +#define WF_LWTBL_AC0_RTS_FAIL_CNT_DW 8 |
| +#define WF_LWTBL_AC0_RTS_FAIL_CNT_ADDR 32 |
| +#define WF_LWTBL_AC0_RTS_FAIL_CNT_MASK \ |
| + 0x0000001f // 4- 0 |
| +#define WF_LWTBL_AC0_RTS_FAIL_CNT_SHIFT 0 |
| +#define WF_LWTBL_AC1_RTS_FAIL_CNT_DW 8 |
| +#define WF_LWTBL_AC1_RTS_FAIL_CNT_ADDR 32 |
| +#define WF_LWTBL_AC1_RTS_FAIL_CNT_MASK \ |
| + 0x000003e0 // 9- 5 |
| +#define WF_LWTBL_AC1_RTS_FAIL_CNT_SHIFT 5 |
| +#define WF_LWTBL_AC2_RTS_FAIL_CNT_DW 8 |
| +#define WF_LWTBL_AC2_RTS_FAIL_CNT_ADDR 32 |
| +#define WF_LWTBL_AC2_RTS_FAIL_CNT_MASK \ |
| + 0x00007c00 // 14-10 |
| +#define WF_LWTBL_AC2_RTS_FAIL_CNT_SHIFT 10 |
| +#define WF_LWTBL_AC3_RTS_FAIL_CNT_DW 8 |
| +#define WF_LWTBL_AC3_RTS_FAIL_CNT_ADDR 32 |
| +#define WF_LWTBL_AC3_RTS_FAIL_CNT_MASK \ |
| + 0x000f8000 // 19-15 |
| +#define WF_LWTBL_AC3_RTS_FAIL_CNT_SHIFT 15 |
| +#define WF_LWTBL_PARTIAL_AID_DW 8 |
| +#define WF_LWTBL_PARTIAL_AID_ADDR 32 |
| +#define WF_LWTBL_PARTIAL_AID_MASK \ |
| + 0x1ff00000 // 28-20 |
| +#define WF_LWTBL_PARTIAL_AID_SHIFT 20 |
| +#define WF_LWTBL_CHK_PER_DW 8 |
| +#define WF_LWTBL_CHK_PER_ADDR 32 |
| +#define WF_LWTBL_CHK_PER_MASK \ |
| + 0x80000000 // 31-31 |
| +#define WF_LWTBL_CHK_PER_SHIFT 31 |
| +// DW9 |
| +#define WF_LWTBL_RX_AVG_MPDU_SIZE_DW 9 |
| +#define WF_LWTBL_RX_AVG_MPDU_SIZE_ADDR 36 |
| +#define WF_LWTBL_RX_AVG_MPDU_SIZE_MASK \ |
| + 0x00003fff // 13- 0 |
| +#define WF_LWTBL_RX_AVG_MPDU_SIZE_SHIFT 0 |
| +#define WF_LWTBL_PRITX_SW_MODE_DW 9 |
| +#define WF_LWTBL_PRITX_SW_MODE_ADDR 36 |
| +#define WF_LWTBL_PRITX_SW_MODE_MASK \ |
| + 0x00008000 // 15-15 |
| +#define WF_LWTBL_PRITX_SW_MODE_SHIFT 15 |
| +#define WF_LWTBL_PRITX_ERSU_DW 9 |
| +#define WF_LWTBL_PRITX_ERSU_ADDR 36 |
| +#define WF_LWTBL_PRITX_ERSU_MASK \ |
| + 0x00010000 // 16-16 |
| +#define WF_LWTBL_PRITX_ERSU_SHIFT 16 |
| +#define WF_LWTBL_PRITX_PLR_DW 9 |
| +#define WF_LWTBL_PRITX_PLR_ADDR 36 |
| +#define WF_LWTBL_PRITX_PLR_MASK \ |
| + 0x00020000 // 17-17 |
| +#define WF_LWTBL_PRITX_PLR_SHIFT 17 |
| +#define WF_LWTBL_PRITX_DCM_DW 9 |
| +#define WF_LWTBL_PRITX_DCM_ADDR 36 |
| +#define WF_LWTBL_PRITX_DCM_MASK \ |
| + 0x00040000 // 18-18 |
| +#define WF_LWTBL_PRITX_DCM_SHIFT 18 |
| +#define WF_LWTBL_PRITX_ER106T_DW 9 |
| +#define WF_LWTBL_PRITX_ER106T_ADDR 36 |
| +#define WF_LWTBL_PRITX_ER106T_MASK \ |
| + 0x00080000 // 19-19 |
| +#define WF_LWTBL_PRITX_ER106T_SHIFT 19 |
| +#define WF_LWTBL_FCAP_DW 9 |
| +#define WF_LWTBL_FCAP_ADDR 36 |
| +#define WF_LWTBL_FCAP_MASK \ |
| + 0x00700000 // 22-20 |
| +#define WF_LWTBL_FCAP_SHIFT 20 |
| +#define WF_LWTBL_MPDU_FAIL_CNT_DW 9 |
| +#define WF_LWTBL_MPDU_FAIL_CNT_ADDR 36 |
| +#define WF_LWTBL_MPDU_FAIL_CNT_MASK \ |
| + 0x03800000 // 25-23 |
| +#define WF_LWTBL_MPDU_FAIL_CNT_SHIFT 23 |
| +#define WF_LWTBL_MPDU_OK_CNT_DW 9 |
| +#define WF_LWTBL_MPDU_OK_CNT_ADDR 36 |
| +#define WF_LWTBL_MPDU_OK_CNT_MASK \ |
| + 0x1c000000 // 28-26 |
| +#define WF_LWTBL_MPDU_OK_CNT_SHIFT 26 |
| +#define WF_LWTBL_RATE_IDX_DW 9 |
| +#define WF_LWTBL_RATE_IDX_ADDR 36 |
| +#define WF_LWTBL_RATE_IDX_MASK \ |
| + 0xe0000000 // 31-29 |
| +#define WF_LWTBL_RATE_IDX_SHIFT 29 |
| +// DW10 |
| +#define WF_LWTBL_RATE1_DW 10 |
| +#define WF_LWTBL_RATE1_ADDR 40 |
| +#define WF_LWTBL_RATE1_MASK \ |
| + 0x00007fff // 14- 0 |
| +#define WF_LWTBL_RATE1_SHIFT 0 |
| +#define WF_LWTBL_RATE2_DW 10 |
| +#define WF_LWTBL_RATE2_ADDR 40 |
| +#define WF_LWTBL_RATE2_MASK \ |
| + 0x7fff0000 // 30-16 |
| +#define WF_LWTBL_RATE2_SHIFT 16 |
| +// DW11 |
| +#define WF_LWTBL_RATE3_DW 11 |
| +#define WF_LWTBL_RATE3_ADDR 44 |
| +#define WF_LWTBL_RATE3_MASK \ |
| + 0x00007fff // 14- 0 |
| +#define WF_LWTBL_RATE3_SHIFT 0 |
| +#define WF_LWTBL_RATE4_DW 11 |
| +#define WF_LWTBL_RATE4_ADDR 44 |
| +#define WF_LWTBL_RATE4_MASK \ |
| + 0x7fff0000 // 30-16 |
| +#define WF_LWTBL_RATE4_SHIFT 16 |
| +// DW12 |
| +#define WF_LWTBL_RATE5_DW 12 |
| +#define WF_LWTBL_RATE5_ADDR 48 |
| +#define WF_LWTBL_RATE5_MASK \ |
| + 0x00007fff // 14- 0 |
| +#define WF_LWTBL_RATE5_SHIFT 0 |
| +#define WF_LWTBL_RATE6_DW 12 |
| +#define WF_LWTBL_RATE6_ADDR 48 |
| +#define WF_LWTBL_RATE6_MASK \ |
| + 0x7fff0000 // 30-16 |
| +#define WF_LWTBL_RATE6_SHIFT 16 |
| +// DW13 |
| +#define WF_LWTBL_RATE7_DW 13 |
| +#define WF_LWTBL_RATE7_ADDR 52 |
| +#define WF_LWTBL_RATE7_MASK \ |
| + 0x00007fff // 14- 0 |
| +#define WF_LWTBL_RATE7_SHIFT 0 |
| +#define WF_LWTBL_RATE8_DW 13 |
| +#define WF_LWTBL_RATE8_ADDR 52 |
| +#define WF_LWTBL_RATE8_MASK \ |
| + 0x7fff0000 // 30-16 |
| +#define WF_LWTBL_RATE8_SHIFT 16 |
| +// DW14 |
| +#define WF_LWTBL_RATE1_TX_CNT_DW 14 |
| +#define WF_LWTBL_RATE1_TX_CNT_ADDR 56 |
| +#define WF_LWTBL_RATE1_TX_CNT_MASK \ |
| + 0x0000ffff // 15- 0 |
| +#define WF_LWTBL_RATE1_TX_CNT_SHIFT 0 |
| +#define WF_LWTBL_CIPHER_SUIT_IGTK_DW 14 |
| +#define WF_LWTBL_CIPHER_SUIT_IGTK_ADDR 56 |
| +#define WF_LWTBL_CIPHER_SUIT_IGTK_MASK \ |
| + 0x00003000 // 13-12 |
| +#define WF_LWTBL_CIPHER_SUIT_IGTK_SHIFT 12 |
| +#define WF_LWTBL_CIPHER_SUIT_BIGTK_DW 14 |
| +#define WF_LWTBL_CIPHER_SUIT_BIGTK_ADDR 56 |
| +#define WF_LWTBL_CIPHER_SUIT_BIGTK_MASK \ |
| + 0x0000c000 // 15-14 |
| +#define WF_LWTBL_CIPHER_SUIT_BIGTK_SHIFT 14 |
| +#define WF_LWTBL_RATE1_FAIL_CNT_DW 14 |
| +#define WF_LWTBL_RATE1_FAIL_CNT_ADDR 56 |
| +#define WF_LWTBL_RATE1_FAIL_CNT_MASK \ |
| + 0xffff0000 // 31-16 |
| +#define WF_LWTBL_RATE1_FAIL_CNT_SHIFT 16 |
| +// DW15 |
| +#define WF_LWTBL_RATE2_OK_CNT_DW 15 |
| +#define WF_LWTBL_RATE2_OK_CNT_ADDR 60 |
| +#define WF_LWTBL_RATE2_OK_CNT_MASK \ |
| + 0x0000ffff // 15- 0 |
| +#define WF_LWTBL_RATE2_OK_CNT_SHIFT 0 |
| +#define WF_LWTBL_RATE3_OK_CNT_DW 15 |
| +#define WF_LWTBL_RATE3_OK_CNT_ADDR 60 |
| +#define WF_LWTBL_RATE3_OK_CNT_MASK \ |
| + 0xffff0000 // 31-16 |
| +#define WF_LWTBL_RATE3_OK_CNT_SHIFT 16 |
| +// DW16 |
| +#define WF_LWTBL_CURRENT_BW_TX_CNT_DW 16 |
| +#define WF_LWTBL_CURRENT_BW_TX_CNT_ADDR 64 |
| +#define WF_LWTBL_CURRENT_BW_TX_CNT_MASK \ |
| + 0x0000ffff // 15- 0 |
| +#define WF_LWTBL_CURRENT_BW_TX_CNT_SHIFT 0 |
| +#define WF_LWTBL_CURRENT_BW_FAIL_CNT_DW 16 |
| +#define WF_LWTBL_CURRENT_BW_FAIL_CNT_ADDR 64 |
| +#define WF_LWTBL_CURRENT_BW_FAIL_CNT_MASK \ |
| + 0xffff0000 // 31-16 |
| +#define WF_LWTBL_CURRENT_BW_FAIL_CNT_SHIFT 16 |
| +// DW17 |
| +#define WF_LWTBL_OTHER_BW_TX_CNT_DW 17 |
| +#define WF_LWTBL_OTHER_BW_TX_CNT_ADDR 68 |
| +#define WF_LWTBL_OTHER_BW_TX_CNT_MASK \ |
| + 0x0000ffff // 15- 0 |
| +#define WF_LWTBL_OTHER_BW_TX_CNT_SHIFT 0 |
| +#define WF_LWTBL_OTHER_BW_FAIL_CNT_DW 17 |
| +#define WF_LWTBL_OTHER_BW_FAIL_CNT_ADDR 68 |
| +#define WF_LWTBL_OTHER_BW_FAIL_CNT_MASK \ |
| + 0xffff0000 // 31-16 |
| +#define WF_LWTBL_OTHER_BW_FAIL_CNT_SHIFT 16 |
| +// DW18 |
| +#define WF_LWTBL_RTS_OK_CNT_DW 18 |
| +#define WF_LWTBL_RTS_OK_CNT_ADDR 72 |
| +#define WF_LWTBL_RTS_OK_CNT_MASK \ |
| + 0x0000ffff // 15- 0 |
| +#define WF_LWTBL_RTS_OK_CNT_SHIFT 0 |
| +#define WF_LWTBL_RTS_FAIL_CNT_DW 18 |
| +#define WF_LWTBL_RTS_FAIL_CNT_ADDR 72 |
| +#define WF_LWTBL_RTS_FAIL_CNT_MASK \ |
| + 0xffff0000 // 31-16 |
| +#define WF_LWTBL_RTS_FAIL_CNT_SHIFT 16 |
| +// DW19 |
| +#define WF_LWTBL_DATA_RETRY_CNT_DW 19 |
| +#define WF_LWTBL_DATA_RETRY_CNT_ADDR 76 |
| +#define WF_LWTBL_DATA_RETRY_CNT_MASK \ |
| + 0x0000ffff // 15- 0 |
| +#define WF_LWTBL_DATA_RETRY_CNT_SHIFT 0 |
| +#define WF_LWTBL_MGNT_RETRY_CNT_DW 19 |
| +#define WF_LWTBL_MGNT_RETRY_CNT_ADDR 76 |
| +#define WF_LWTBL_MGNT_RETRY_CNT_MASK \ |
| + 0xffff0000 // 31-16 |
| +#define WF_LWTBL_MGNT_RETRY_CNT_SHIFT 16 |
| +// DW20 |
| +#define WF_LWTBL_AC0_CTT_CDT_CRB_DW 20 |
| +#define WF_LWTBL_AC0_CTT_CDT_CRB_ADDR 80 |
| +#define WF_LWTBL_AC0_CTT_CDT_CRB_MASK \ |
| + 0xffffffff // 31- 0 |
| +#define WF_LWTBL_AC0_CTT_CDT_CRB_SHIFT 0 |
| +// DW21 |
| +// DO NOT process repeat field(adm[0]) |
| +// DW22 |
| +#define WF_LWTBL_AC1_CTT_CDT_CRB_DW 22 |
| +#define WF_LWTBL_AC1_CTT_CDT_CRB_ADDR 88 |
| +#define WF_LWTBL_AC1_CTT_CDT_CRB_MASK \ |
| + 0xffffffff // 31- 0 |
| +#define WF_LWTBL_AC1_CTT_CDT_CRB_SHIFT 0 |
| +// DW23 |
| +// DO NOT process repeat field(adm[1]) |
| +// DW24 |
| +#define WF_LWTBL_AC2_CTT_CDT_CRB_DW 24 |
| +#define WF_LWTBL_AC2_CTT_CDT_CRB_ADDR 96 |
| +#define WF_LWTBL_AC2_CTT_CDT_CRB_MASK \ |
| + 0xffffffff // 31- 0 |
| +#define WF_LWTBL_AC2_CTT_CDT_CRB_SHIFT 0 |
| +// DW25 |
| +// DO NOT process repeat field(adm[2]) |
| +// DW26 |
| +#define WF_LWTBL_AC3_CTT_CDT_CRB_DW 26 |
| +#define WF_LWTBL_AC3_CTT_CDT_CRB_ADDR 104 |
| +#define WF_LWTBL_AC3_CTT_CDT_CRB_MASK \ |
| + 0xffffffff // 31- 0 |
| +#define WF_LWTBL_AC3_CTT_CDT_CRB_SHIFT 0 |
| +// DW27 |
| +// DO NOT process repeat field(adm[3]) |
| +// DW28 |
| +#define WF_LWTBL_RELATED_IDX0_DW 28 |
| +#define WF_LWTBL_RELATED_IDX0_ADDR 112 |
| +#define WF_LWTBL_RELATED_IDX0_MASK \ |
| + 0x00000fff // 11- 0 |
| +#define WF_LWTBL_RELATED_IDX0_SHIFT 0 |
| +#define WF_LWTBL_RELATED_BAND0_DW 28 |
| +#define WF_LWTBL_RELATED_BAND0_ADDR 112 |
| +#define WF_LWTBL_RELATED_BAND0_MASK \ |
| + 0x00003000 // 13-12 |
| +#define WF_LWTBL_RELATED_BAND0_SHIFT 12 |
| +#define WF_LWTBL_PRIMARY_MLD_BAND_DW 28 |
| +#define WF_LWTBL_PRIMARY_MLD_BAND_ADDR 112 |
| +#define WF_LWTBL_PRIMARY_MLD_BAND_MASK \ |
| + 0x0000c000 // 15-14 |
| +#define WF_LWTBL_PRIMARY_MLD_BAND_SHIFT 14 |
| +#define WF_LWTBL_RELATED_IDX1_DW 28 |
| +#define WF_LWTBL_RELATED_IDX1_ADDR 112 |
| +#define WF_LWTBL_RELATED_IDX1_MASK \ |
| + 0x0fff0000 // 27-16 |
| +#define WF_LWTBL_RELATED_IDX1_SHIFT 16 |
| +#define WF_LWTBL_RELATED_BAND1_DW 28 |
| +#define WF_LWTBL_RELATED_BAND1_ADDR 112 |
| +#define WF_LWTBL_RELATED_BAND1_MASK \ |
| + 0x30000000 // 29-28 |
| +#define WF_LWTBL_RELATED_BAND1_SHIFT 28 |
| +#define WF_LWTBL_SECONDARY_MLD_BAND_DW 28 |
| +#define WF_LWTBL_SECONDARY_MLD_BAND_ADDR 112 |
| +#define WF_LWTBL_SECONDARY_MLD_BAND_MASK \ |
| + 0xc0000000 // 31-30 |
| +#define WF_LWTBL_SECONDARY_MLD_BAND_SHIFT 30 |
| +// DW29 |
| +#define WF_LWTBL_DISPATCH_POLICY0_DW 29 |
| +#define WF_LWTBL_DISPATCH_POLICY0_ADDR 116 |
| +#define WF_LWTBL_DISPATCH_POLICY0_MASK \ |
| + 0x00000003 // 1- 0 |
| +#define WF_LWTBL_DISPATCH_POLICY0_SHIFT 0 |
| +#define WF_LWTBL_DISPATCH_POLICY1_DW 29 |
| +#define WF_LWTBL_DISPATCH_POLICY1_ADDR 116 |
| +#define WF_LWTBL_DISPATCH_POLICY1_MASK \ |
| + 0x0000000c // 3- 2 |
| +#define WF_LWTBL_DISPATCH_POLICY1_SHIFT 2 |
| +#define WF_LWTBL_DISPATCH_POLICY2_DW 29 |
| +#define WF_LWTBL_DISPATCH_POLICY2_ADDR 116 |
| +#define WF_LWTBL_DISPATCH_POLICY2_MASK \ |
| + 0x00000030 // 5- 4 |
| +#define WF_LWTBL_DISPATCH_POLICY2_SHIFT 4 |
| +#define WF_LWTBL_DISPATCH_POLICY3_DW 29 |
| +#define WF_LWTBL_DISPATCH_POLICY3_ADDR 116 |
| +#define WF_LWTBL_DISPATCH_POLICY3_MASK \ |
| + 0x000000c0 // 7- 6 |
| +#define WF_LWTBL_DISPATCH_POLICY3_SHIFT 6 |
| +#define WF_LWTBL_DISPATCH_POLICY4_DW 29 |
| +#define WF_LWTBL_DISPATCH_POLICY4_ADDR 116 |
| +#define WF_LWTBL_DISPATCH_POLICY4_MASK \ |
| + 0x00000300 // 9- 8 |
| +#define WF_LWTBL_DISPATCH_POLICY4_SHIFT 8 |
| +#define WF_LWTBL_DISPATCH_POLICY5_DW 29 |
| +#define WF_LWTBL_DISPATCH_POLICY5_ADDR 116 |
| +#define WF_LWTBL_DISPATCH_POLICY5_MASK \ |
| + 0x00000c00 // 11-10 |
| +#define WF_LWTBL_DISPATCH_POLICY5_SHIFT 10 |
| +#define WF_LWTBL_DISPATCH_POLICY6_DW 29 |
| +#define WF_LWTBL_DISPATCH_POLICY6_ADDR 116 |
| +#define WF_LWTBL_DISPATCH_POLICY6_MASK \ |
| + 0x00003000 // 13-12 |
| +#define WF_LWTBL_DISPATCH_POLICY6_SHIFT 12 |
| +#define WF_LWTBL_DISPATCH_POLICY7_DW 29 |
| +#define WF_LWTBL_DISPATCH_POLICY7_ADDR 116 |
| +#define WF_LWTBL_DISPATCH_POLICY7_MASK \ |
| + 0x0000c000 // 15-14 |
| +#define WF_LWTBL_DISPATCH_POLICY7_SHIFT 14 |
| +#define WF_LWTBL_OWN_MLD_ID_DW 29 |
| +#define WF_LWTBL_OWN_MLD_ID_ADDR 116 |
| +#define WF_LWTBL_OWN_MLD_ID_MASK \ |
| + 0x003f0000 // 21-16 |
| +#define WF_LWTBL_OWN_MLD_ID_SHIFT 16 |
| +#define WF_LWTBL_EMLSR0_DW 29 |
| +#define WF_LWTBL_EMLSR0_ADDR 116 |
| +#define WF_LWTBL_EMLSR0_MASK \ |
| + 0x00400000 // 22-22 |
| +#define WF_LWTBL_EMLSR0_SHIFT 22 |
| +#define WF_LWTBL_EMLMR0_DW 29 |
| +#define WF_LWTBL_EMLMR0_ADDR 116 |
| +#define WF_LWTBL_EMLMR0_MASK \ |
| + 0x00800000 // 23-23 |
| +#define WF_LWTBL_EMLMR0_SHIFT 23 |
| +#define WF_LWTBL_EMLSR1_DW 29 |
| +#define WF_LWTBL_EMLSR1_ADDR 116 |
| +#define WF_LWTBL_EMLSR1_MASK \ |
| + 0x01000000 // 24-24 |
| +#define WF_LWTBL_EMLSR1_SHIFT 24 |
| +#define WF_LWTBL_EMLMR1_DW 29 |
| +#define WF_LWTBL_EMLMR1_ADDR 116 |
| +#define WF_LWTBL_EMLMR1_MASK \ |
| + 0x02000000 // 25-25 |
| +#define WF_LWTBL_EMLMR1_SHIFT 25 |
| +#define WF_LWTBL_EMLSR2_DW 29 |
| +#define WF_LWTBL_EMLSR2_ADDR 116 |
| +#define WF_LWTBL_EMLSR2_MASK \ |
| + 0x04000000 // 26-26 |
| +#define WF_LWTBL_EMLSR2_SHIFT 26 |
| +#define WF_LWTBL_EMLMR2_DW 29 |
| +#define WF_LWTBL_EMLMR2_ADDR 116 |
| +#define WF_LWTBL_EMLMR2_MASK \ |
| + 0x08000000 // 27-27 |
| +#define WF_LWTBL_EMLMR2_SHIFT 27 |
| +#define WF_LWTBL_STR_BITMAP_DW 29 |
| +#define WF_LWTBL_STR_BITMAP_ADDR 116 |
| +#define WF_LWTBL_STR_BITMAP_MASK \ |
| + 0xe0000000 // 31-29 |
| +#define WF_LWTBL_STR_BITMAP_SHIFT 29 |
| +// DW30 |
| +#define WF_LWTBL_DISPATCH_ORDER_DW 30 |
| +#define WF_LWTBL_DISPATCH_ORDER_ADDR 120 |
| +#define WF_LWTBL_DISPATCH_ORDER_MASK \ |
| + 0x0000007f // 6- 0 |
| +#define WF_LWTBL_DISPATCH_ORDER_SHIFT 0 |
| +#define WF_LWTBL_DISPATCH_RATIO_DW 30 |
| +#define WF_LWTBL_DISPATCH_RATIO_ADDR 120 |
| +#define WF_LWTBL_DISPATCH_RATIO_MASK \ |
| + 0x00003f80 // 13- 7 |
| +#define WF_LWTBL_DISPATCH_RATIO_SHIFT 7 |
| +#define WF_LWTBL_LINK_MGF_DW 30 |
| +#define WF_LWTBL_LINK_MGF_ADDR 120 |
| +#define WF_LWTBL_LINK_MGF_MASK \ |
| + 0xffff0000 // 31-16 |
| +#define WF_LWTBL_LINK_MGF_SHIFT 16 |
| +// DW31 |
| +#define WF_LWTBL_NEGOTIATED_WINSIZE0_DW 31 |
| +#define WF_LWTBL_NEGOTIATED_WINSIZE0_ADDR 124 |
| +#define WF_LWTBL_NEGOTIATED_WINSIZE0_MASK \ |
| + 0x00000007 // 2- 0 |
| +#define WF_LWTBL_NEGOTIATED_WINSIZE0_SHIFT 0 |
| +#define WF_LWTBL_NEGOTIATED_WINSIZE1_DW 31 |
| +#define WF_LWTBL_NEGOTIATED_WINSIZE1_ADDR 124 |
| +#define WF_LWTBL_NEGOTIATED_WINSIZE1_MASK \ |
| + 0x00000038 // 5- 3 |
| +#define WF_LWTBL_NEGOTIATED_WINSIZE1_SHIFT 3 |
| +#define WF_LWTBL_NEGOTIATED_WINSIZE2_DW 31 |
| +#define WF_LWTBL_NEGOTIATED_WINSIZE2_ADDR 124 |
| +#define WF_LWTBL_NEGOTIATED_WINSIZE2_MASK \ |
| + 0x000001c0 // 8- 6 |
| +#define WF_LWTBL_NEGOTIATED_WINSIZE2_SHIFT 6 |
| +#define WF_LWTBL_NEGOTIATED_WINSIZE3_DW 31 |
| +#define WF_LWTBL_NEGOTIATED_WINSIZE3_ADDR 124 |
| +#define WF_LWTBL_NEGOTIATED_WINSIZE3_MASK \ |
| + 0x00000e00 // 11- 9 |
| +#define WF_LWTBL_NEGOTIATED_WINSIZE3_SHIFT 9 |
| +#define WF_LWTBL_NEGOTIATED_WINSIZE4_DW 31 |
| +#define WF_LWTBL_NEGOTIATED_WINSIZE4_ADDR 124 |
| +#define WF_LWTBL_NEGOTIATED_WINSIZE4_MASK \ |
| + 0x00007000 // 14-12 |
| +#define WF_LWTBL_NEGOTIATED_WINSIZE4_SHIFT 12 |
| +#define WF_LWTBL_NEGOTIATED_WINSIZE5_DW 31 |
| +#define WF_LWTBL_NEGOTIATED_WINSIZE5_ADDR 124 |
| +#define WF_LWTBL_NEGOTIATED_WINSIZE5_MASK \ |
| + 0x00038000 // 17-15 |
| +#define WF_LWTBL_NEGOTIATED_WINSIZE5_SHIFT 15 |
| +#define WF_LWTBL_NEGOTIATED_WINSIZE6_DW 31 |
| +#define WF_LWTBL_NEGOTIATED_WINSIZE6_ADDR 124 |
| +#define WF_LWTBL_NEGOTIATED_WINSIZE6_MASK \ |
| + 0x001c0000 // 20-18 |
| +#define WF_LWTBL_NEGOTIATED_WINSIZE6_SHIFT 18 |
| +#define WF_LWTBL_NEGOTIATED_WINSIZE7_DW 31 |
| +#define WF_LWTBL_NEGOTIATED_WINSIZE7_ADDR 124 |
| +#define WF_LWTBL_NEGOTIATED_WINSIZE7_MASK \ |
| + 0x00e00000 // 23-21 |
| +#define WF_LWTBL_NEGOTIATED_WINSIZE7_SHIFT 21 |
| +#define WF_LWTBL_CASCAD_DW 31 |
| +#define WF_LWTBL_CASCAD_ADDR 124 |
| +#define WF_LWTBL_CASCAD_MASK \ |
| + 0x02000000 // 25-25 |
| +#define WF_LWTBL_CASCAD_SHIFT 25 |
| +#define WF_LWTBL_ALL_ACK_DW 31 |
| +#define WF_LWTBL_ALL_ACK_ADDR 124 |
| +#define WF_LWTBL_ALL_ACK_MASK \ |
| + 0x04000000 // 26-26 |
| +#define WF_LWTBL_ALL_ACK_SHIFT 26 |
| +#define WF_LWTBL_MPDU_SIZE_DW 31 |
| +#define WF_LWTBL_MPDU_SIZE_ADDR 124 |
| +#define WF_LWTBL_MPDU_SIZE_MASK \ |
| + 0x18000000 // 28-27 |
| +#define WF_LWTBL_MPDU_SIZE_SHIFT 27 |
| +#define WF_LWTBL_BA_MODE_DW 31 |
| +#define WF_LWTBL_BA_MODE_ADDR 124 |
| +#define WF_LWTBL_BA_MODE_MASK \ |
| + 0xe0000000 // 31-29 |
| +#define WF_LWTBL_BA_MODE_SHIFT 29 |
| +// DW32 |
| +#define WF_LWTBL_OM_INFO_DW 32 |
| +#define WF_LWTBL_OM_INFO_ADDR 128 |
| +#define WF_LWTBL_OM_INFO_MASK \ |
| + 0x00000fff // 11- 0 |
| +#define WF_LWTBL_OM_INFO_SHIFT 0 |
| +#define WF_LWTBL_RXD_DUP_FOR_OM_CHG_DW 32 |
| +#define WF_LWTBL_RXD_DUP_FOR_OM_CHG_ADDR 128 |
| +#define WF_LWTBL_RXD_DUP_FOR_OM_CHG_MASK \ |
| + 0x00001000 // 12-12 |
| +#define WF_LWTBL_RXD_DUP_FOR_OM_CHG_SHIFT 12 |
| +#define WF_LWTBL_RXD_DUP_WHITE_LIST_DW 32 |
| +#define WF_LWTBL_RXD_DUP_WHITE_LIST_ADDR 128 |
| +#define WF_LWTBL_RXD_DUP_WHITE_LIST_MASK \ |
| + 0x01ffe000 // 24-13 |
| +#define WF_LWTBL_RXD_DUP_WHITE_LIST_SHIFT 13 |
| +#define WF_LWTBL_RXD_DUP_MODE_DW 32 |
| +#define WF_LWTBL_RXD_DUP_MODE_ADDR 128 |
| +#define WF_LWTBL_RXD_DUP_MODE_MASK \ |
| + 0x06000000 // 26-25 |
| +#define WF_LWTBL_RXD_DUP_MODE_SHIFT 25 |
| +#define WF_LWTBL_DROP_DW 32 |
| +#define WF_LWTBL_DROP_ADDR 128 |
| +#define WF_LWTBL_DROP_MASK \ |
| + 0x40000000 // 30-30 |
| +#define WF_LWTBL_DROP_SHIFT 30 |
| +#define WF_LWTBL_ACK_EN_DW 32 |
| +#define WF_LWTBL_ACK_EN_ADDR 128 |
| +#define WF_LWTBL_ACK_EN_MASK \ |
| + 0x80000000 // 31-31 |
| +#define WF_LWTBL_ACK_EN_SHIFT 31 |
| +// DW33 |
| +#define WF_LWTBL_USER_RSSI_DW 33 |
| +#define WF_LWTBL_USER_RSSI_ADDR 132 |
| +#define WF_LWTBL_USER_RSSI_MASK \ |
| + 0x000001ff // 8- 0 |
| +#define WF_LWTBL_USER_RSSI_SHIFT 0 |
| +#define WF_LWTBL_USER_SNR_DW 33 |
| +#define WF_LWTBL_USER_SNR_ADDR 132 |
| +#define WF_LWTBL_USER_SNR_MASK \ |
| + 0x00007e00 // 14- 9 |
| +#define WF_LWTBL_USER_SNR_SHIFT 9 |
| +#define WF_LWTBL_RAPID_REACTION_RATE_DW 33 |
| +#define WF_LWTBL_RAPID_REACTION_RATE_ADDR 132 |
| +#define WF_LWTBL_RAPID_REACTION_RATE_MASK \ |
| + 0x0fff0000 // 27-16 |
| +#define WF_LWTBL_RAPID_REACTION_RATE_SHIFT 16 |
| +#define WF_LWTBL_HT_AMSDU_DW 33 |
| +#define WF_LWTBL_HT_AMSDU_ADDR 132 |
| +#define WF_LWTBL_HT_AMSDU_MASK \ |
| + 0x40000000 // 30-30 |
| +#define WF_LWTBL_HT_AMSDU_SHIFT 30 |
| +#define WF_LWTBL_AMSDU_CROSS_LG_DW 33 |
| +#define WF_LWTBL_AMSDU_CROSS_LG_ADDR 132 |
| +#define WF_LWTBL_AMSDU_CROSS_LG_MASK \ |
| + 0x80000000 // 31-31 |
| +#define WF_LWTBL_AMSDU_CROSS_LG_SHIFT 31 |
| +// DW34 |
| +#define WF_LWTBL_RESP_RCPI0_DW 34 |
| +#define WF_LWTBL_RESP_RCPI0_ADDR 136 |
| +#define WF_LWTBL_RESP_RCPI0_MASK \ |
| + 0x000000ff // 7- 0 |
| +#define WF_LWTBL_RESP_RCPI0_SHIFT 0 |
| +#define WF_LWTBL_RESP_RCPI1_DW 34 |
| +#define WF_LWTBL_RESP_RCPI1_ADDR 136 |
| +#define WF_LWTBL_RESP_RCPI1_MASK \ |
| + 0x0000ff00 // 15- 8 |
| +#define WF_LWTBL_RESP_RCPI1_SHIFT 8 |
| +#define WF_LWTBL_RESP_RCPI2_DW 34 |
| +#define WF_LWTBL_RESP_RCPI2_ADDR 136 |
| +#define WF_LWTBL_RESP_RCPI2_MASK \ |
| + 0x00ff0000 // 23-16 |
| +#define WF_LWTBL_RESP_RCPI2_SHIFT 16 |
| +#define WF_LWTBL_RESP_RCPI3_DW 34 |
| +#define WF_LWTBL_RESP_RCPI3_ADDR 136 |
| +#define WF_LWTBL_RESP_RCPI3_MASK \ |
| + 0xff000000 // 31-24 |
| +#define WF_LWTBL_RESP_RCPI3_SHIFT 24 |
| +// DW35 |
| +#define WF_LWTBL_SNR_RX0_DW 35 |
| +#define WF_LWTBL_SNR_RX0_ADDR 140 |
| +#define WF_LWTBL_SNR_RX0_MASK \ |
| + 0x0000003f // 5- 0 |
| +#define WF_LWTBL_SNR_RX0_SHIFT 0 |
| +#define WF_LWTBL_SNR_RX1_DW 35 |
| +#define WF_LWTBL_SNR_RX1_ADDR 140 |
| +#define WF_LWTBL_SNR_RX1_MASK \ |
| + 0x00000fc0 // 11- 6 |
| +#define WF_LWTBL_SNR_RX1_SHIFT 6 |
| +#define WF_LWTBL_SNR_RX2_DW 35 |
| +#define WF_LWTBL_SNR_RX2_ADDR 140 |
| +#define WF_LWTBL_SNR_RX2_MASK \ |
| + 0x0003f000 // 17-12 |
| +#define WF_LWTBL_SNR_RX2_SHIFT 12 |
| +#define WF_LWTBL_SNR_RX3_DW 35 |
| +#define WF_LWTBL_SNR_RX3_ADDR 140 |
| +#define WF_LWTBL_SNR_RX3_MASK \ |
| + 0x00fc0000 // 23-18 |
| +#define WF_LWTBL_SNR_RX3_SHIFT 18 |
| + |
| +/* WTBL Group - Packet Number */ |
| +/* DW 2 */ |
| +#define WTBL_PN0_MASK BITS(0, 7) |
| +#define WTBL_PN0_OFFSET 0 |
| +#define WTBL_PN1_MASK BITS(8, 15) |
| +#define WTBL_PN1_OFFSET 8 |
| +#define WTBL_PN2_MASK BITS(16, 23) |
| +#define WTBL_PN2_OFFSET 16 |
| +#define WTBL_PN3_MASK BITS(24, 31) |
| +#define WTBL_PN3_OFFSET 24 |
| + |
| +/* DW 3 */ |
| +#define WTBL_PN4_MASK BITS(0, 7) |
| +#define WTBL_PN4_OFFSET 0 |
| +#define WTBL_PN5_MASK BITS(8, 15) |
| +#define WTBL_PN5_OFFSET 8 |
| + |
| +/* DW 4 */ |
| +#define WTBL_BIPN0_MASK BITS(0, 7) |
| +#define WTBL_BIPN0_OFFSET 0 |
| +#define WTBL_BIPN1_MASK BITS(8, 15) |
| +#define WTBL_BIPN1_OFFSET 8 |
| +#define WTBL_BIPN2_MASK BITS(16, 23) |
| +#define WTBL_BIPN2_OFFSET 16 |
| +#define WTBL_BIPN3_MASK BITS(24, 31) |
| +#define WTBL_BIPN3_OFFSET 24 |
| + |
| +/* DW 5 */ |
| +#define WTBL_BIPN4_MASK BITS(0, 7) |
| +#define WTBL_BIPN4_OFFSET 0 |
| +#define WTBL_BIPN5_MASK BITS(8, 15) |
| +#define WTBL_BIPN5_OFFSET 8 |
| + |
| +/* UWTBL DW 6 */ |
| +#define WTBL_AMSDU_LEN_MASK BITS(0, 5) |
| +#define WTBL_AMSDU_LEN_OFFSET 0 |
| +#define WTBL_AMSDU_NUM_MASK BITS(6, 10) |
| +#define WTBL_AMSDU_NUM_OFFSET 6 |
| +#define WTBL_AMSDU_EN_MASK BIT(11) |
| +#define WTBL_AMSDU_EN_OFFSET 11 |
| + |
| +/* LWTBL Rate field */ |
| +#define WTBL_RATE_TX_RATE_MASK BITS(0, 5) |
| +#define WTBL_RATE_TX_RATE_OFFSET 0 |
| +#define WTBL_RATE_TX_MODE_MASK BITS(6, 9) |
| +#define WTBL_RATE_TX_MODE_OFFSET 6 |
| +#define WTBL_RATE_NSTS_MASK BITS(10, 13) |
| +#define WTBL_RATE_NSTS_OFFSET 10 |
| +#define WTBL_RATE_STBC_MASK BIT(14) |
| +#define WTBL_RATE_STBC_OFFSET 14 |
| + |
| +/***** WTBL(LMAC) DW Offset *****/ |
| +/* LMAC WTBL Group - Peer Unique Information */ |
| +#define WTBL_GROUP_PEER_INFO_DW_0 0 |
| +#define WTBL_GROUP_PEER_INFO_DW_1 1 |
| + |
| +/* WTBL Group - TxRx Capability/Information */ |
| +#define WTBL_GROUP_TRX_CAP_DW_2 2 |
| +#define WTBL_GROUP_TRX_CAP_DW_3 3 |
| +#define WTBL_GROUP_TRX_CAP_DW_4 4 |
| +#define WTBL_GROUP_TRX_CAP_DW_5 5 |
| +#define WTBL_GROUP_TRX_CAP_DW_6 6 |
| +#define WTBL_GROUP_TRX_CAP_DW_7 7 |
| +#define WTBL_GROUP_TRX_CAP_DW_8 8 |
| +#define WTBL_GROUP_TRX_CAP_DW_9 9 |
| + |
| +/* WTBL Group - Auto Rate Table*/ |
| +#define WTBL_GROUP_AUTO_RATE_1_2 10 |
| +#define WTBL_GROUP_AUTO_RATE_3_4 11 |
| +#define WTBL_GROUP_AUTO_RATE_5_6 12 |
| +#define WTBL_GROUP_AUTO_RATE_7_8 13 |
| + |
| +/* WTBL Group - Tx Counter */ |
| +#define WTBL_GROUP_TX_CNT_LINE_1 14 |
| +#define WTBL_GROUP_TX_CNT_LINE_2 15 |
| +#define WTBL_GROUP_TX_CNT_LINE_3 16 |
| +#define WTBL_GROUP_TX_CNT_LINE_4 17 |
| +#define WTBL_GROUP_TX_CNT_LINE_5 18 |
| +#define WTBL_GROUP_TX_CNT_LINE_6 19 |
| + |
| +/* WTBL Group - Admission Control Counter */ |
| +#define WTBL_GROUP_ADM_CNT_LINE_1 20 |
| +#define WTBL_GROUP_ADM_CNT_LINE_2 21 |
| +#define WTBL_GROUP_ADM_CNT_LINE_3 22 |
| +#define WTBL_GROUP_ADM_CNT_LINE_4 23 |
| +#define WTBL_GROUP_ADM_CNT_LINE_5 24 |
| +#define WTBL_GROUP_ADM_CNT_LINE_6 25 |
| +#define WTBL_GROUP_ADM_CNT_LINE_7 26 |
| +#define WTBL_GROUP_ADM_CNT_LINE_8 27 |
| + |
| +/* WTBL Group -MLO Info */ |
| +#define WTBL_GROUP_MLO_INFO_LINE_1 28 |
| +#define WTBL_GROUP_MLO_INFO_LINE_2 29 |
| +#define WTBL_GROUP_MLO_INFO_LINE_3 30 |
| + |
| +/* WTBL Group -RESP Info */ |
| +#define WTBL_GROUP_RESP_INFO_DW_31 31 |
| + |
| +/* WTBL Group -RX DUP Info */ |
| +#define WTBL_GROUP_RX_DUP_INFO_DW_32 32 |
| + |
| +/* WTBL Group - Rx Statistics Counter */ |
| +#define WTBL_GROUP_RX_STAT_CNT_LINE_1 33 |
| +#define WTBL_GROUP_RX_STAT_CNT_LINE_2 34 |
| +#define WTBL_GROUP_RX_STAT_CNT_LINE_3 35 |
| + |
| +/* UWTBL Group - HW AMSDU */ |
| +#define UWTBL_HW_AMSDU_DW WF_UWTBL_AMSDU_CFG_DW |
| + |
| +/* LWTBL DW 4 */ |
| +#define WTBL_DIS_RHTR WF_LWTBL_DIS_RHTR_MASK |
| + |
| +/* UWTBL DW 5 */ |
| +#define WTBL_KEY_LINK_DW_KEY_LOC0_MASK BITS(0, 10) |
| +#define WTBL_PSM WF_LWTBL_PSM_MASK |
| + |
| +/* Need to sync with FW define */ |
| +#define INVALID_KEY_ENTRY WTBL_KEY_LINK_DW_KEY_LOC0_MASK |
| + |
| +// RATE |
| +#define WTBL_RATE_TX_RATE_MASK BITS(0, 5) |
| +#define WTBL_RATE_TX_RATE_OFFSET 0 |
| +#define WTBL_RATE_TX_MODE_MASK BITS(6, 9) |
| +#define WTBL_RATE_TX_MODE_OFFSET 6 |
| +#define WTBL_RATE_NSTS_MASK BITS(10, 13) |
| +#define WTBL_RATE_NSTS_OFFSET 10 |
| +#define WTBL_RATE_STBC_MASK BIT(14) |
| +#define WTBL_RATE_STBC_OFFSET 14 |
| + |
| +/* DMA */ |
| +// HOST DMA |
| +//#define CONN_INFRA_REMAPPING_OFFSET 0x64000000 |
| +//#define WF_WFDMA_HOST_DMA0_BASE (0x18024000 + CONN_INFRA_REMAPPING_OFFSET) |
| +#define WF_WFDMA_HOST_DMA0_BASE 0xd4000 |
| + |
| +#define WF_WFDMA_HOST_DMA0_HOST_INT_STA_ADDR \ |
| + (WF_WFDMA_HOST_DMA0_BASE + 0x200) /* 4200 */ |
| +#define WF_WFDMA_HOST_DMA0_HOST_INT_ENA_ADDR \ |
| + (WF_WFDMA_HOST_DMA0_BASE + 0X204) /* 4204 */ |
| +#define WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_ADDR \ |
| + (WF_WFDMA_HOST_DMA0_BASE + 0x208) /* 4208 */ |
| + |
| +#define WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_RX_DMA_BUSY_ADDR \ |
| + WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_ADDR |
| +#define WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK \ |
| + 0x00000008 /* RX_DMA_BUSY[3] */ |
| +#define WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT 3 |
| +#define WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_RX_DMA_EN_ADDR \ |
| + WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_ADDR |
| +#define WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_RX_DMA_EN_MASK \ |
| + 0x00000004 /* RX_DMA_EN[2] */ |
| +#define WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_RX_DMA_EN_SHFT 2 |
| +#define WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_TX_DMA_BUSY_ADDR \ |
| + WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_ADDR |
| +#define WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK \ |
| + 0x00000002 /* TX_DMA_BUSY[1] */ |
| +#define WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT 1 |
| +#define WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_TX_DMA_EN_ADDR \ |
| + WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_ADDR |
| +#define WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_TX_DMA_EN_MASK \ |
| + 0x00000001 /* TX_DMA_EN[0] */ |
| +#define WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_TX_DMA_EN_SHFT 0 |
| + |
| + |
| +#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING0_CTRL0_ADDR \ |
| + (WF_WFDMA_HOST_DMA0_BASE + 0x300) /* 4300 */ |
| +#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING0_CTRL1_ADDR \ |
| + (WF_WFDMA_HOST_DMA0_BASE + 0x304) /* 4304 */ |
| +#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING0_CTRL2_ADDR \ |
| + (WF_WFDMA_HOST_DMA0_BASE + 0x308) /* 4308 */ |
| +#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING0_CTRL3_ADDR \ |
| + (WF_WFDMA_HOST_DMA0_BASE + 0x30c) /* 430C */ |
| +#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING1_CTRL0_ADDR \ |
| + (WF_WFDMA_HOST_DMA0_BASE + 0x310) /* 4310 */ |
| +#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING1_CTRL1_ADDR \ |
| + (WF_WFDMA_HOST_DMA0_BASE + 0x314) /* 4314 */ |
| +#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING1_CTRL2_ADDR \ |
| + (WF_WFDMA_HOST_DMA0_BASE + 0x318) /* 4318 */ |
| +#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING1_CTRL3_ADDR \ |
| + (WF_WFDMA_HOST_DMA0_BASE + 0x31c) /* 431C */ |
| +#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING2_CTRL0_ADDR \ |
| + (WF_WFDMA_HOST_DMA0_BASE + 0x320) /* 4320 */ |
| +#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING2_CTRL1_ADDR \ |
| + (WF_WFDMA_HOST_DMA0_BASE + 0x324) /* 4324 */ |
| +#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING2_CTRL2_ADDR \ |
| + (WF_WFDMA_HOST_DMA0_BASE + 0x328) /* 4328 */ |
| +#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING2_CTRL3_ADDR \ |
| + (WF_WFDMA_HOST_DMA0_BASE + 0x32c) /* 432C */ |
| +#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING3_CTRL0_ADDR \ |
| + (WF_WFDMA_HOST_DMA0_BASE + 0x330) /* 4330 */ |
| +#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING3_CTRL1_ADDR \ |
| + (WF_WFDMA_HOST_DMA0_BASE + 0x334) /* 4334 */ |
| +#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING3_CTRL2_ADDR \ |
| + (WF_WFDMA_HOST_DMA0_BASE + 0x338) /* 4338 */ |
| +#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING3_CTRL3_ADDR \ |
| + (WF_WFDMA_HOST_DMA0_BASE + 0x33c) /* 433C */ |
| +#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING4_CTRL0_ADDR \ |
| + (WF_WFDMA_HOST_DMA0_BASE + 0x340) /* 4340 */ |
| +#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING4_CTRL1_ADDR \ |
| + (WF_WFDMA_HOST_DMA0_BASE + 0x344) /* 4344 */ |
| +#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING4_CTRL2_ADDR \ |
| + (WF_WFDMA_HOST_DMA0_BASE + 0x348) /* 4348 */ |
| +#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING4_CTRL3_ADDR \ |
| + (WF_WFDMA_HOST_DMA0_BASE + 0x34c) /* 434C */ |
| +#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING5_CTRL0_ADDR \ |
| + (WF_WFDMA_HOST_DMA0_BASE + 0x350) /* 4350 */ |
| +#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING5_CTRL1_ADDR \ |
| + (WF_WFDMA_HOST_DMA0_BASE + 0x354) /* 4354 */ |
| +#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING5_CTRL2_ADDR \ |
| + (WF_WFDMA_HOST_DMA0_BASE + 0x358) /* 4358 */ |
| +#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING5_CTRL3_ADDR \ |
| + (WF_WFDMA_HOST_DMA0_BASE + 0x35c) /* 435C */ |
| +#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING6_CTRL0_ADDR \ |
| + (WF_WFDMA_HOST_DMA0_BASE + 0x360) /* 4360 */ |
| +#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING6_CTRL1_ADDR \ |
| + (WF_WFDMA_HOST_DMA0_BASE + 0x364) /* 4364 */ |
| +#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING6_CTRL2_ADDR \ |
| + (WF_WFDMA_HOST_DMA0_BASE + 0x368) /* 4368 */ |
| +#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING6_CTRL3_ADDR \ |
| + (WF_WFDMA_HOST_DMA0_BASE + 0x36c) /* 436C */ |
| +#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING16_CTRL0_ADDR \ |
| + (WF_WFDMA_HOST_DMA0_BASE + 0x400) /* 4400 */ |
| +#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING16_CTRL1_ADDR \ |
| + (WF_WFDMA_HOST_DMA0_BASE + 0x404) /* 4404 */ |
| +#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING16_CTRL2_ADDR \ |
| + (WF_WFDMA_HOST_DMA0_BASE + 0x408) /* 4408 */ |
| +#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING16_CTRL3_ADDR \ |
| + (WF_WFDMA_HOST_DMA0_BASE + 0x40c) /* 440C */ |
| +#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING17_CTRL0_ADDR \ |
| + (WF_WFDMA_HOST_DMA0_BASE + 0x410) /* 4410 */ |
| +#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING17_CTRL1_ADDR \ |
| + (WF_WFDMA_HOST_DMA0_BASE + 0x414) /* 4414 */ |
| +#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING17_CTRL2_ADDR \ |
| + (WF_WFDMA_HOST_DMA0_BASE + 0x418) /* 4418 */ |
| +#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING17_CTRL3_ADDR \ |
| + (WF_WFDMA_HOST_DMA0_BASE + 0x41c) /* 441C */ |
| +#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING18_CTRL0_ADDR \ |
| + (WF_WFDMA_HOST_DMA0_BASE + 0x420) /* 4420 */ |
| +#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING18_CTRL1_ADDR \ |
| + (WF_WFDMA_HOST_DMA0_BASE + 0x424) /* 4424 */ |
| +#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING18_CTRL2_ADDR \ |
| + (WF_WFDMA_HOST_DMA0_BASE + 0x428) /* 4428 */ |
| +#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING18_CTRL3_ADDR \ |
| + (WF_WFDMA_HOST_DMA0_BASE + 0x42c) /* 442C */ |
| +#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING19_CTRL0_ADDR \ |
| + (WF_WFDMA_HOST_DMA0_BASE + 0x430) /* 4430 */ |
| +#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING19_CTRL1_ADDR \ |
| + (WF_WFDMA_HOST_DMA0_BASE + 0x434) /* 4434 */ |
| +#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING19_CTRL2_ADDR \ |
| + (WF_WFDMA_HOST_DMA0_BASE + 0x438) /* 4438 */ |
| +#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING19_CTRL3_ADDR \ |
| + (WF_WFDMA_HOST_DMA0_BASE + 0x43c) /* 443C */ |
| +#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING20_CTRL0_ADDR \ |
| + (WF_WFDMA_HOST_DMA0_BASE + 0x440) /* 4440 */ |
| +#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING20_CTRL1_ADDR \ |
| + (WF_WFDMA_HOST_DMA0_BASE + 0x444) /* 4444 */ |
| +#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING20_CTRL2_ADDR \ |
| + (WF_WFDMA_HOST_DMA0_BASE + 0x448) /* 4448 */ |
| +#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING20_CTRL3_ADDR \ |
| + (WF_WFDMA_HOST_DMA0_BASE + 0x44c) /* 444C */ |
| +#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING21_CTRL0_ADDR \ |
| + (WF_WFDMA_HOST_DMA0_BASE + 0x450) /* 4450 */ |
| +#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING21_CTRL1_ADDR \ |
| + (WF_WFDMA_HOST_DMA0_BASE + 0x454) /* 4454 */ |
| +#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING21_CTRL2_ADDR \ |
| + (WF_WFDMA_HOST_DMA0_BASE + 0x458) /* 4458 */ |
| +#define WF_WFDMA_HOST_DMA0_WPDMA_TX_RING21_CTRL3_ADDR \ |
| + |
| +#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING0_CTRL0_ADDR \ |
| + (WF_WFDMA_HOST_DMA0_BASE + 0x500) /* 4500 */ |
| +#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING0_CTRL1_ADDR \ |
| + (WF_WFDMA_HOST_DMA0_BASE + 0x504) /* 4504 */ |
| +#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING0_CTRL2_ADDR \ |
| + (WF_WFDMA_HOST_DMA0_BASE + 0x508) /* 4508 */ |
| +#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING0_CTRL3_ADDR \ |
| + (WF_WFDMA_HOST_DMA0_BASE + 0x50c) /* 450C */ |
| +#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING1_CTRL0_ADDR \ |
| + (WF_WFDMA_HOST_DMA0_BASE + 0x510) /* 4510 */ |
| +#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING1_CTRL1_ADDR \ |
| + (WF_WFDMA_HOST_DMA0_BASE + 0x514) /* 4514 */ |
| +#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING1_CTRL2_ADDR \ |
| + (WF_WFDMA_HOST_DMA0_BASE + 0x518) /* 4518 */ |
| +#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING1_CTRL3_ADDR \ |
| + (WF_WFDMA_HOST_DMA0_BASE + 0x51c) /* 451C */ |
| +#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING2_CTRL0_ADDR \ |
| + (WF_WFDMA_HOST_DMA0_BASE + 0x520) /* 4520 */ |
| +#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING2_CTRL1_ADDR \ |
| + (WF_WFDMA_HOST_DMA0_BASE + 0x524) /* 4524 */ |
| +#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING2_CTRL2_ADDR \ |
| + (WF_WFDMA_HOST_DMA0_BASE + 0x528) /* 4528 */ |
| +#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING2_CTRL3_ADDR \ |
| + (WF_WFDMA_HOST_DMA0_BASE + 0x52C) /* 452C */ |
| +#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING3_CTRL0_ADDR \ |
| + (WF_WFDMA_HOST_DMA0_BASE + 0x530) /* 4530 */ |
| +#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING3_CTRL1_ADDR \ |
| + (WF_WFDMA_HOST_DMA0_BASE + 0x534) /* 4534 */ |
| +#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING3_CTRL2_ADDR \ |
| + (WF_WFDMA_HOST_DMA0_BASE + 0x538) /* 4538 */ |
| +#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING3_CTRL3_ADDR \ |
| + (WF_WFDMA_HOST_DMA0_BASE + 0x53C) /* 453C */ |
| +#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING4_CTRL0_ADDR \ |
| + (WF_WFDMA_HOST_DMA0_BASE + 0x540) /* 4540 */ |
| +#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING4_CTRL1_ADDR \ |
| + (WF_WFDMA_HOST_DMA0_BASE + 0x544) /* 4544 */ |
| +#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING4_CTRL2_ADDR \ |
| + (WF_WFDMA_HOST_DMA0_BASE + 0x548) /* 4548 */ |
| +#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING4_CTRL3_ADDR \ |
| + (WF_WFDMA_HOST_DMA0_BASE + 0x54c) /* 454C */ |
| +#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING5_CTRL0_ADDR \ |
| + (WF_WFDMA_HOST_DMA0_BASE + 0x550) /* 4550 */ |
| +#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING5_CTRL1_ADDR \ |
| + (WF_WFDMA_HOST_DMA0_BASE + 0x554) /* 4554 */ |
| +#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING5_CTRL2_ADDR \ |
| + (WF_WFDMA_HOST_DMA0_BASE + 0x558) /* 4558 */ |
| +#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING5_CTRL3_ADDR \ |
| + (WF_WFDMA_HOST_DMA0_BASE + 0x55c) /* 455C */ |
| +#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING6_CTRL0_ADDR \ |
| + (WF_WFDMA_HOST_DMA0_BASE + 0x560) /* 4560 */ |
| +#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING6_CTRL1_ADDR \ |
| + (WF_WFDMA_HOST_DMA0_BASE + 0x564) /* 4564 */ |
| +#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING6_CTRL2_ADDR \ |
| + (WF_WFDMA_HOST_DMA0_BASE + 0x568) /* 4568 */ |
| +#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING6_CTRL3_ADDR \ |
| + (WF_WFDMA_HOST_DMA0_BASE + 0x56c) /* 456C */ |
| +#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING7_CTRL0_ADDR \ |
| + (WF_WFDMA_HOST_DMA0_BASE + 0x570) /* 4570 */ |
| +#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING7_CTRL1_ADDR \ |
| + (WF_WFDMA_HOST_DMA0_BASE + 0x574) /* 4574 */ |
| +#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING7_CTRL2_ADDR \ |
| + (WF_WFDMA_HOST_DMA0_BASE + 0x578) /* 4578 */ |
| +#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING7_CTRL3_ADDR \ |
| + (WF_WFDMA_HOST_DMA0_BASE + 0x57c) /* 457C */ |
| +#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING8_CTRL0_ADDR \ |
| + (WF_WFDMA_HOST_DMA0_BASE + 0x580) /* 4580 */ |
| +#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING8_CTRL1_ADDR \ |
| + (WF_WFDMA_HOST_DMA0_BASE + 0x584) /* 4584 */ |
| +#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING8_CTRL2_ADDR \ |
| + (WF_WFDMA_HOST_DMA0_BASE + 0x588) /* 4588 */ |
| +#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING8_CTRL3_ADDR \ |
| + (WF_WFDMA_HOST_DMA0_BASE + 0x58c) /* 458C */ |
| +#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING9_CTRL0_ADDR \ |
| + (WF_WFDMA_HOST_DMA0_BASE + 0x590) /* 4590 */ |
| +#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING9_CTRL1_ADDR \ |
| + (WF_WFDMA_HOST_DMA0_BASE + 0x594) /* 4594 */ |
| +#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING9_CTRL2_ADDR \ |
| + (WF_WFDMA_HOST_DMA0_BASE + 0x598) /* 4598 */ |
| +#define WF_WFDMA_HOST_DMA0_WPDMA_RX_RING9_CTRL3_ADDR \ |
| + (WF_WFDMA_HOST_DMA0_BASE + 0x59c) /* 459C */ |
| + |
| +//MCU DMA |
| +//#define WF_WFDMA_MCU_DMA0_BASE 0x02000 |
| +#define WF_WFDMA_MCU_DMA0_BASE 0x54000000 |
| + |
| +#define WF_WFDMA_MCU_DMA0_HOST_INT_STA_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x200) // 0200 |
| +#define WF_WFDMA_MCU_DMA0_HOST_INT_ENA_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0X204) // 0204 |
| +#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x208) // 0208 |
| + |
| +#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_BUSY_ADDR WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_ADDR |
| +#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK 0x00000008 // RX_DMA_BUSY[3] |
| +#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT 3 |
| +#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_EN_ADDR WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_ADDR |
| +#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_EN_MASK 0x00000004 // RX_DMA_EN[2] |
| +#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_EN_SHFT 2 |
| +#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_BUSY_ADDR WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_ADDR |
| +#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK 0x00000002 // TX_DMA_BUSY[1] |
| +#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT 1 |
| +#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_EN_ADDR WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_ADDR |
| +#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_EN_MASK 0x00000001 // TX_DMA_EN[0] |
| +#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_EN_SHFT 0 |
| + |
| +#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING0_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x300) // 0300 |
| +#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING0_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x304) // 0304 |
| +#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING0_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x308) // 0308 |
| +#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING0_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x30c) // 030C |
| +#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING1_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x310) // 0310 |
| +#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING1_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x314) // 0314 |
| +#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING1_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x318) // 0318 |
| +#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING1_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x31c) // 031C |
| +#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING2_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x320) // 0320 |
| +#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING2_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x324) // 0324 |
| +#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING2_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x328) // 0328 |
| +#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING2_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x32c) // 032C |
| +#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING3_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x330) // 0330 |
| +#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING3_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x334) // 0334 |
| +#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING3_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x338) // 0338 |
| +#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING3_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x33c) // 033C |
| +#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING4_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x340) // 0340 |
| +#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING4_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x344) // 0344 |
| +#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING4_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x348) // 0348 |
| +#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING4_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x34c) // 034C |
| +#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING5_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x350) // 0350 |
| +#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING5_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x354) // 0354 |
| +#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING5_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x358) // 0358 |
| +#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING5_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x35c) // 035C |
| +#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING6_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x360) // 0360 |
| +#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING6_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x364) // 0364 |
| +#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING6_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x368) // 0368 |
| +#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING6_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x36c) // 036C |
| +#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING7_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x370) // 0370 |
| +#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING7_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x374) // 0374 |
| +#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING7_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x378) // 0378 |
| +#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING7_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x37c) // 037C |
| + |
| +#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING0_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x500) // 0500 |
| +#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING0_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x504) // 0504 |
| +#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING0_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x508) // 0508 |
| +#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING0_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x50c) // 050C |
| +#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING1_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x510) // 0510 |
| +#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING1_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x514) // 0514 |
| +#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING1_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x518) // 0518 |
| +#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING1_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x51c) // 051C |
| +#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING2_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x520) // 0520 |
| +#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING2_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x524) // 0524 |
| +#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING2_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x528) // 0528 |
| +#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING2_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x52C) // 052C |
| +#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING3_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x530) // 0530 |
| +#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING3_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x534) // 0534 |
| +#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING3_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x538) // 0538 |
| +#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING3_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x53C) // 053C |
| +#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING4_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x540) // 0540 |
| +#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING4_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x544) // 0544 |
| +#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING4_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x548) // 0548 |
| +#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING4_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x54C) // 054C |
| +#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING5_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x550) // 0550 |
| +#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING5_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x554) // 0554 |
| +#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING5_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x558) // 0558 |
| +#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING5_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x55C) // 055C |
| +#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING6_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x560) // 0560 |
| +#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING6_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x564) // 0564 |
| +#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING6_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x568) // 0568 |
| +#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING6_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x56c) // 056C |
| +#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING7_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x570) // 0570 |
| +#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING7_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x574) // 0574 |
| +#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING7_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x578) // 0578 |
| +#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING7_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x57c) // 057C |
| +#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING8_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x580) // 0580 |
| +#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING8_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x584) // 0584 |
| +#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING8_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x588) // 0588 |
| +#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING8_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x58c) // 058C |
| +#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING9_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x590) // 0590 |
| +#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING9_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x594) // 0594 |
| +#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING9_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x598) // 0598 |
| +#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING9_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x59c) // 059C |
| +#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING10_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x5A0) // 05A0 |
| +#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING10_CTRL1_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x5A4) // 05A4 |
| +#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING10_CTRL2_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x5A8) // 05A8 |
| +#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING10_CTRL3_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x5Ac) // 05AC |
| + |
| +// MEM DMA |
| +#define WF_WFDMA_MEM_DMA_BASE 0x58000000 |
| + |
| +#define WF_WFDMA_MEM_DMA_HOST_INT_STA_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x200) // 0200 |
| +#define WF_WFDMA_MEM_DMA_HOST_INT_ENA_ADDR (WF_WFDMA_MEM_DMA_BASE + 0X204) // 0204 |
| +#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x208) // 0208 |
| + |
| +#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_BUSY_ADDR WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_ADDR |
| +#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK 0x00000008 // RX_DMA_BUSY[3] |
| +#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT 3 |
| +#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_EN_ADDR WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_ADDR |
| +#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_EN_MASK 0x00000004 // RX_DMA_EN[2] |
| +#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_EN_SHFT 2 |
| +#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_BUSY_ADDR WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_ADDR |
| +#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK 0x00000002 // TX_DMA_BUSY[1] |
| +#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT 1 |
| +#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_EN_ADDR WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_ADDR |
| +#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_EN_MASK 0x00000001 // TX_DMA_EN[0] |
| +#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_EN_SHFT 0 |
| + |
| +#define WF_WFDMA_MEM_DMA_WPDMA_TX_RING0_CTRL0_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x300) // 0300 |
| +#define WF_WFDMA_MEM_DMA_WPDMA_TX_RING0_CTRL1_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x304) // 0304 |
| +#define WF_WFDMA_MEM_DMA_WPDMA_TX_RING0_CTRL2_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x308) // 0308 |
| +#define WF_WFDMA_MEM_DMA_WPDMA_TX_RING0_CTRL3_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x30c) // 030C |
| +#define WF_WFDMA_MEM_DMA_WPDMA_TX_RING1_CTRL0_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x310) // 0310 |
| +#define WF_WFDMA_MEM_DMA_WPDMA_TX_RING1_CTRL1_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x314) // 0314 |
| +#define WF_WFDMA_MEM_DMA_WPDMA_TX_RING1_CTRL2_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x318) // 0318 |
| +#define WF_WFDMA_MEM_DMA_WPDMA_TX_RING1_CTRL3_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x31c) // 031C |
| +#define WF_WFDMA_MEM_DMA_WPDMA_TX_RING2_CTRL0_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x320) // 0320 |
| +#define WF_WFDMA_MEM_DMA_WPDMA_TX_RING2_CTRL1_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x324) // 0324 |
| +#define WF_WFDMA_MEM_DMA_WPDMA_TX_RING2_CTRL2_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x328) // 0328 |
| +#define WF_WFDMA_MEM_DMA_WPDMA_TX_RING2_CTRL3_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x32c) // 032C |
| + |
| +#define WF_WFDMA_MEM_DMA_WPDMA_RX_RING0_CTRL0_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x500) // 0500 |
| +#define WF_WFDMA_MEM_DMA_WPDMA_RX_RING0_CTRL1_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x504) // 0504 |
| +#define WF_WFDMA_MEM_DMA_WPDMA_RX_RING0_CTRL2_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x508) // 0508 |
| +#define WF_WFDMA_MEM_DMA_WPDMA_RX_RING0_CTRL3_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x50c) // 050C |
| +#define WF_WFDMA_MEM_DMA_WPDMA_RX_RING1_CTRL0_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x510) // 0510 |
| +#define WF_WFDMA_MEM_DMA_WPDMA_RX_RING1_CTRL1_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x514) // 0514 |
| +#define WF_WFDMA_MEM_DMA_WPDMA_RX_RING1_CTRL2_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x518) // 0518 |
| +#define WF_WFDMA_MEM_DMA_WPDMA_RX_RING1_CTRL3_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x51c) // 051C |
| +#define WF_WFDMA_MEM_DMA_WPDMA_RX_RING2_CTRL0_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x520) // 0520 |
| +#define WF_WFDMA_MEM_DMA_WPDMA_RX_RING2_CTRL1_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x524) // 0524 |
| +#define WF_WFDMA_MEM_DMA_WPDMA_RX_RING2_CTRL2_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x528) // 0528 |
| +#define WF_WFDMA_MEM_DMA_WPDMA_RX_RING2_CTRL3_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x52C) // 052C |
| + |
| +/* MIB INFO */ |
| +#define WF_UMIB_TOP_BASE 0x820cd000 |
| +#define BN0_WF_MIB_TOP_BASE 0x820ed000 |
| +#define BN1_WF_MIB_TOP_BASE 0x820fd000 |
| +#define IP1_BN0_WF_MIB_TOP_BASE 0x830ed000 |
| + |
| +#define WF_UMIB_TOP_B0BROCR_ADDR (WF_UMIB_TOP_BASE + 0x480) // D480 |
| +#define WF_UMIB_TOP_B0BRBCR_ADDR (WF_UMIB_TOP_BASE + 0x4D0) // D4D0 |
| +#define WF_UMIB_TOP_B0BRDCR_ADDR (WF_UMIB_TOP_BASE + 0x520) // D520 |
| +#define WF_UMIB_TOP_B1BROCR_ADDR (WF_UMIB_TOP_BASE + 0x5B4) // D5B4 |
| +#define WF_UMIB_TOP_B2BROCR_ADDR (WF_UMIB_TOP_BASE + 0x6E8) // D6E8 |
| + |
| +#define BN0_WF_MIB_TOP_M0SCR0_ADDR (BN0_WF_MIB_TOP_BASE + 0x000) // D000 |
| +#define BN0_WF_MIB_TOP_M0SDR6_ADDR (BN0_WF_MIB_TOP_BASE + 0x020) // D020 |
| +#define BN0_WF_MIB_TOP_M0SDR9_ADDR (BN0_WF_MIB_TOP_BASE + 0x024) // D024 |
| +#define BN0_WF_MIB_TOP_M0SDR18_ADDR (BN0_WF_MIB_TOP_BASE + 0x030) // D030 |
| +#define BN0_WF_MIB_TOP_BTOCR_ADDR (BN0_WF_MIB_TOP_BASE + 0x400) // D400 |
| +#define BN0_WF_MIB_TOP_BTBCR_ADDR (BN0_WF_MIB_TOP_BASE + 0x428) // D428 |
| +#define BN0_WF_MIB_TOP_BTDCR_ADDR (BN0_WF_MIB_TOP_BASE + 0x4F0) // D4F0 |
| +#define BN0_WF_MIB_TOP_BTCR_ADDR (BN0_WF_MIB_TOP_BASE + 0x4F8) // D4F8 |
| +#define BN0_WF_MIB_TOP_RVSR0_ADDR (BN0_WF_MIB_TOP_BASE + 0x6D4) // D6D4 |
| + |
| +#define BN0_WF_MIB_TOP_TSCR0_ADDR (BN0_WF_MIB_TOP_BASE + 0x670) // D670 |
| +#define BN0_WF_MIB_TOP_TSCR3_ADDR (BN0_WF_MIB_TOP_BASE + 0x67C) // D67C |
| +#define BN0_WF_MIB_TOP_TSCR4_ADDR (BN0_WF_MIB_TOP_BASE + 0x680) // D680 |
| +#define BN0_WF_MIB_TOP_TSCR5_ADDR (BN0_WF_MIB_TOP_BASE + 0x684) // D684 |
| +#define BN0_WF_MIB_TOP_TSCR6_ADDR (BN0_WF_MIB_TOP_BASE + 0x688) // D688 |
| +#define BN0_WF_MIB_TOP_TSCR7_ADDR (BN0_WF_MIB_TOP_BASE + 0x68C) // D68C |
| +#define BN0_WF_MIB_TOP_TSCR8_ADDR (BN0_WF_MIB_TOP_BASE + 0x690) // D690 |
| + |
| +#define BN0_WF_MIB_TOP_TBCR0_ADDR (BN0_WF_MIB_TOP_BASE + 0x6AC) // D6AC |
| +#define BN0_WF_MIB_TOP_TBCR1_ADDR (BN0_WF_MIB_TOP_BASE + 0x6B0) // D6B0 |
| +#define BN0_WF_MIB_TOP_TBCR2_ADDR (BN0_WF_MIB_TOP_BASE + 0x6B4) // D6B4 |
| +#define BN0_WF_MIB_TOP_TBCR3_ADDR (BN0_WF_MIB_TOP_BASE + 0x6B8) // D6B8 |
| +#define BN0_WF_MIB_TOP_TBCR4_ADDR (BN0_WF_MIB_TOP_BASE + 0x6BC) // D6BC |
| + |
| +#define BN0_WF_MIB_TOP_TDRCR0_ADDR (BN0_WF_MIB_TOP_BASE + 0x6DC) // D6DC |
| +#define BN0_WF_MIB_TOP_TDRCR1_ADDR (BN0_WF_MIB_TOP_BASE + 0x6E0) // D6E0 |
| +#define BN0_WF_MIB_TOP_TDRCR2_ADDR (BN0_WF_MIB_TOP_BASE + 0x6E4) // D6E4 |
| +#define BN0_WF_MIB_TOP_TDRCR3_ADDR (BN0_WF_MIB_TOP_BASE + 0x6E8) // D6E8 |
| +#define BN0_WF_MIB_TOP_TDRCR4_ADDR (BN0_WF_MIB_TOP_BASE + 0x6EC) // D6EC |
| + |
| +#define BN0_WF_MIB_TOP_BTSCR0_ADDR (BN0_WF_MIB_TOP_BASE + 0x5E0) // D5E0 |
| +#define BN0_WF_MIB_TOP_BTSCR1_ADDR (BN0_WF_MIB_TOP_BASE + 0x5F0) // D5F0 |
| +#define BN0_WF_MIB_TOP_BTSCR2_ADDR (BN0_WF_MIB_TOP_BASE + 0x600) // D600 |
| +#define BN0_WF_MIB_TOP_BTSCR3_ADDR (BN0_WF_MIB_TOP_BASE + 0x610) // D610 |
| +#define BN0_WF_MIB_TOP_BTSCR4_ADDR (BN0_WF_MIB_TOP_BASE + 0x620) // D620 |
| +#define BN0_WF_MIB_TOP_BTSCR5_ADDR (BN0_WF_MIB_TOP_BASE + 0x73C) // D73C |
| +#define BN0_WF_MIB_TOP_BTSCR6_ADDR (BN0_WF_MIB_TOP_BASE + 0x74C) // D74C |
| + |
| +#define BN0_WF_MIB_TOP_RSCR1_ADDR (BN0_WF_MIB_TOP_BASE + 0x760) // D760 |
| +#define BN0_WF_MIB_TOP_BSCR2_ADDR (BN0_WF_MIB_TOP_BASE + 0x964) // D964 |
| +#define BN0_WF_MIB_TOP_TSCR18_ADDR (BN0_WF_MIB_TOP_BASE + 0x9AC) // D9AC |
| + |
| +#define BN0_WF_MIB_TOP_MSR0_ADDR (BN0_WF_MIB_TOP_BASE + 0x9F4) // D9F4 |
| +#define BN0_WF_MIB_TOP_MSR1_ADDR (BN0_WF_MIB_TOP_BASE + 0x9F8) // D9F8 |
| +#define BN0_WF_MIB_TOP_MSR2_ADDR (BN0_WF_MIB_TOP_BASE + 0x9FC) // D9FC |
| +#define BN0_WF_MIB_TOP_MCTR5_ADDR (BN0_WF_MIB_TOP_BASE + 0xA00) // DA00 |
| +#define BN0_WF_MIB_TOP_MCTR6_ADDR (BN0_WF_MIB_TOP_BASE + 0xA04) // DA04 |
| + |
| +#define BN0_WF_MIB_TOP_RSCR26_ADDR (BN0_WF_MIB_TOP_BASE + 0x904) // D904 |
| +#define BN0_WF_MIB_TOP_RSCR27_ADDR (BN0_WF_MIB_TOP_BASE + 0x908) // D908 |
| +#define BN0_WF_MIB_TOP_RSCR28_ADDR (BN0_WF_MIB_TOP_BASE + 0x90C) // D90C |
| +#define BN0_WF_MIB_TOP_RSCR31_ADDR (BN0_WF_MIB_TOP_BASE + 0x918) // D918 |
| +#define BN0_WF_MIB_TOP_RSCR33_ADDR (BN0_WF_MIB_TOP_BASE + 0x920) // D920 |
| +#define BN0_WF_MIB_TOP_RSCR35_ADDR (BN0_WF_MIB_TOP_BASE + 0x928) // D928 |
| +#define BN0_WF_MIB_TOP_RSCR36_ADDR (BN0_WF_MIB_TOP_BASE + 0x92C) // D92C |
| + |
| +#define BN0_WF_MIB_TOP_TSCR3_AMPDU_MPDU_COUNT_MASK 0xFFFFFFFF // AMPDU_MPDU_COUNT[31..0] |
| +#define BN0_WF_MIB_TOP_TSCR4_AMPDU_ACKED_COUNT_MASK 0xFFFFFFFF // AMPDU_ACKED_COUNT[31..0] |
| +#define BN0_WF_MIB_TOP_M0SDR6_CHANNEL_IDLE_COUNT_MASK 0x0000FFFF // CHANNEL_IDLE_COUNT[15..0] |
| +#define BN0_WF_MIB_TOP_M0SDR9_CCA_NAV_TX_TIME_MASK 0x00FFFFFF // CCA_NAV_TX_TIME[23..0] |
| +#define BN0_WF_MIB_TOP_RSCR26_RX_MDRDY_COUNT_MASK 0xFFFFFFFF // RX_MDRDY_COUNT[31..0] |
| +#define BN0_WF_MIB_TOP_MSR0_CCK_MDRDY_TIME_MASK 0xFFFFFFFF // CCK_MDRDY_TIME[31..0] |
| +#define BN0_WF_MIB_TOP_MSR1_OFDM_LG_MIXED_VHT_MDRDY_TIME_MASK 0xFFFFFFFF // OFDM_LG_MIXED_VHT_MDRDY_TIME[31..0] |
| +#define BN0_WF_MIB_TOP_MSR2_OFDM_GREEN_MDRDY_TIME_MASK 0xFFFFFFFF // OFDM_GREEN_MDRDY_TIME[31..0] |
| +#define BN0_WF_MIB_TOP_MCTR5_P_CCA_TIME_MASK 0xFFFFFFFF // P_CCA_TIME[31..0] |
| +#define BN0_WF_MIB_TOP_MCTR6_S_CCA_TIME_MASK 0xFFFFFFFF // S_CCA_TIME[31..0] |
| +#define BN0_WF_MIB_TOP_M0SDR18_P_ED_TIME_MASK 0x00FFFFFF // P_ED_TIME[23..0] |
| +#define BN0_WF_MIB_TOP_TSCR18_BEACONTXCOUNT_MASK 0xFFFFFFFF // BEACONTXCOUNT[31..0] |
| +#define BN0_WF_MIB_TOP_TBCR0_TX_20MHZ_CNT_MASK 0xFFFFFFFF // TX_20MHZ_CNT[31..0] |
| +#define BN0_WF_MIB_TOP_TBCR1_TX_40MHZ_CNT_MASK 0xFFFFFFFF // TX_40MHZ_CNT[31..0] |
| +#define BN0_WF_MIB_TOP_TBCR2_TX_80MHZ_CNT_MASK 0xFFFFFFFF // TX_80MHZ_CNT[31..0] |
| +#define BN0_WF_MIB_TOP_TBCR3_TX_160MHZ_CNT_MASK 0xFFFFFFFF // TX_160MHZ_CNT[31..0] |
| +#define BN0_WF_MIB_TOP_TBCR4_TX_320MHZ_CNT_MASK 0xFFFFFFFF // TX_320MHZ_CNT[31..0] |
| +#define BN0_WF_MIB_TOP_BSCR2_MUBF_TX_COUNT_MASK 0xFFFFFFFF // MUBF_TX_COUNT[31..0] |
| +#define BN0_WF_MIB_TOP_RVSR0_VEC_MISS_COUNT_MASK 0xFFFFFFFF // VEC_MISS_COUNT[31..0] |
| +#define BN0_WF_MIB_TOP_RSCR35_DELIMITER_FAIL_COUNT_MASK 0xFFFFFFFF // DELIMITER_FAIL_COUNT[31..0] |
| +#define BN0_WF_MIB_TOP_RSCR1_RX_FCS_ERROR_COUNT_MASK 0xFFFFFFFF // RX_FCS_ERROR_COUNT[31..0] |
| +#define BN0_WF_MIB_TOP_RSCR33_RX_FIFO_FULL_COUNT_MASK 0xFFFFFFFF // RX_FIFO_FULL_COUNT[31..0] |
| +#define BN0_WF_MIB_TOP_RSCR36_RX_LEN_MISMATCH_MASK 0xFFFFFFFF // RX_LEN_MISMATCH[31..0] |
| +#define BN0_WF_MIB_TOP_RSCR31_RX_MPDU_COUNT_MASK 0xFFFFFFFF // RX_MPDU_COUNT[31..0] |
| +#define BN0_WF_MIB_TOP_BTSCR5_RTSTXCOUNTn_MASK 0xFFFFFFFF // RTSTXCOUNTn[31..0] |
| +#define BN0_WF_MIB_TOP_BTSCR6_RTSRETRYCOUNTn_MASK 0xFFFFFFFF // RTSRETRYCOUNTn[31..0] |
| +#define BN0_WF_MIB_TOP_BTSCR0_BAMISSCOUNTn_MASK 0xFFFFFFFF // BAMISSCOUNTn[31..0] |
| +#define BN0_WF_MIB_TOP_BTSCR1_ACKFAILCOUNTn_MASK 0xFFFFFFFF // ACKFAILCOUNTn[31..0] |
| +#define BN0_WF_MIB_TOP_BTSCR2_FRAMERETRYCOUNTn_MASK 0xFFFFFFFF // FRAMERETRYCOUNTn[31..0] |
| +#define BN0_WF_MIB_TOP_BTSCR3_FRAMERETRY2COUNTn_MASK 0xFFFFFFFF // FRAMERETRY2COUNTn[31..0] |
| +#define BN0_WF_MIB_TOP_BTSCR4_FRAMERETRY3COUNTn_MASK 0xFFFFFFFF // FRAMERETRY3COUNTn[31..0] |
| + |
| +/* PLE AMSDU */ |
| +#define WF_PLE_TOP_BASE 0x820c0000 |
| + |
| +#define WF_PLE_TOP_AMSDU_PACK_1_MSDU_CNT_ADDR (WF_PLE_TOP_BASE + 0x10e0) // 10E0 |
| +#define WF_PLE_TOP_AMSDU_PACK_2_MSDU_CNT_ADDR (WF_PLE_TOP_BASE + 0x10e4) // 10E4 |
| +#define WF_PLE_TOP_AMSDU_PACK_3_MSDU_CNT_ADDR (WF_PLE_TOP_BASE + 0x10e8) // 10E8 |
| +#define WF_PLE_TOP_AMSDU_PACK_4_MSDU_CNT_ADDR (WF_PLE_TOP_BASE + 0x10ec) // 10EC |
| +#define WF_PLE_TOP_AMSDU_PACK_5_MSDU_CNT_ADDR (WF_PLE_TOP_BASE + 0x10f0) // 10F0 |
| +#define WF_PLE_TOP_AMSDU_PACK_6_MSDU_CNT_ADDR (WF_PLE_TOP_BASE + 0x10f4) // 10F4 |
| +#define WF_PLE_TOP_AMSDU_PACK_7_MSDU_CNT_ADDR (WF_PLE_TOP_BASE + 0x10f8) // 10F8 |
| +#define WF_PLE_TOP_AMSDU_PACK_8_MSDU_CNT_ADDR (WF_PLE_TOP_BASE + 0x10fc) // 10FC |
| + |
| +/* PLE */ |
| +#define WF_PLE_TOP_PBUF_CTRL_ADDR (WF_PLE_TOP_BASE + 0x04) // 0004 |
| + |
| +#define WF_PLE_TOP_PG_HIF_GROUP_ADDR (WF_PLE_TOP_BASE + 0x0c) // 000C |
| +#define WF_PLE_TOP_PG_HIF_WMTXD_GROUP_ADDR (WF_PLE_TOP_BASE + 0x10) // 0010 |
| +#define WF_PLE_TOP_PG_HIF_TXCMD_GROUP_ADDR (WF_PLE_TOP_BASE + 0x14) // 0014 |
| +#define WF_PLE_TOP_PG_CPU_GROUP_ADDR (WF_PLE_TOP_BASE + 0x18) // 0018 |
| +#define WF_PLE_TOP_QUEUE_EMPTY_ADDR (WF_PLE_TOP_BASE + 0x360) // 0360 |
| + |
| +#define WF_PLE_TOP_DIS_STA_MAP0_ADDR (WF_PLE_TOP_BASE + 0x100) // 0100 |
| +#define WF_PLE_TOP_DIS_STA_MAP1_ADDR (WF_PLE_TOP_BASE + 0x104) // 0104 |
| +#define WF_PLE_TOP_DIS_STA_MAP2_ADDR (WF_PLE_TOP_BASE + 0x108) // 0108 |
| +#define WF_PLE_TOP_DIS_STA_MAP3_ADDR (WF_PLE_TOP_BASE + 0x10c) // 010C |
| +#define WF_PLE_TOP_DIS_STA_MAP4_ADDR (WF_PLE_TOP_BASE + 0x110) // 0110 |
| +#define WF_PLE_TOP_DIS_STA_MAP5_ADDR (WF_PLE_TOP_BASE + 0x114) // 0114 |
| +#define WF_PLE_TOP_DIS_STA_MAP6_ADDR (WF_PLE_TOP_BASE + 0x118) // 0118 |
| +#define WF_PLE_TOP_DIS_STA_MAP7_ADDR (WF_PLE_TOP_BASE + 0x11c) // 011C |
| +#define WF_PLE_TOP_DIS_STA_MAP8_ADDR (WF_PLE_TOP_BASE + 0x120) // 0120 |
| + |
| +#define WF_PLE_TOP_TXCMD_QUEUE_EMPTY_ADDR (WF_PLE_TOP_BASE + 0x378) // 0378 |
| +#define WF_PLE_TOP_NATIVE_TXCMD_QUEUE_EMPTY_ADDR (WF_PLE_TOP_BASE + 0x37c) // 037C |
| + |
| +#define WF_PLE_TOP_FREEPG_CNT_ADDR (WF_PLE_TOP_BASE + 0x3a0) // 03A0 |
| +#define WF_PLE_TOP_FREEPG_HEAD_TAIL_ADDR (WF_PLE_TOP_BASE + 0x3a4) // 03A4 |
| +#define WF_PLE_TOP_HIF_PG_INFO_ADDR (WF_PLE_TOP_BASE + 0x3a8) // 03A8 |
| +#define WF_PLE_TOP_HIF_WMTXD_PG_INFO_ADDR (WF_PLE_TOP_BASE + 0x3ac) // 03AC |
| +#define WF_PLE_TOP_HIF_TXCMD_PG_INFO_ADDR (WF_PLE_TOP_BASE + 0x3b0) // 03B0 |
| +#define WF_PLE_TOP_CPU_PG_INFO_ADDR (WF_PLE_TOP_BASE + 0x3b4) // 03B4 |
| + |
| +#define WF_PLE_TOP_FL_QUE_CTRL_0_ADDR (WF_PLE_TOP_BASE + 0x3e0) // 03E0 |
| +#define WF_PLE_TOP_FL_QUE_CTRL_1_ADDR (WF_PLE_TOP_BASE + 0x3e4) // 03E4 |
| +#define WF_PLE_TOP_FL_QUE_CTRL_2_ADDR (WF_PLE_TOP_BASE + 0x3e8) // 03E8 |
| +#define WF_PLE_TOP_FL_QUE_CTRL_3_ADDR (WF_PLE_TOP_BASE + 0x3ec) // 03EC |
| + |
| +#define WF_PLE_TOP_AC0_QUEUE_EMPTY0_ADDR (WF_PLE_TOP_BASE + 0x600) // 0600 |
| +#define WF_PLE_TOP_AC0_QUEUE_EMPTY1_ADDR (WF_PLE_TOP_BASE + 0x604) // 0604 |
| +#define WF_PLE_TOP_AC0_QUEUE_EMPTY2_ADDR (WF_PLE_TOP_BASE + 0x608) // 0608 |
| +#define WF_PLE_TOP_AC0_QUEUE_EMPTY3_ADDR (WF_PLE_TOP_BASE + 0x60c) // 060C |
| +#define WF_PLE_TOP_AC0_QUEUE_EMPTY4_ADDR (WF_PLE_TOP_BASE + 0x610) // 0610 |
| +#define WF_PLE_TOP_AC0_QUEUE_EMPTY5_ADDR (WF_PLE_TOP_BASE + 0x614) // 0614 |
| +#define WF_PLE_TOP_AC0_QUEUE_EMPTY6_ADDR (WF_PLE_TOP_BASE + 0x618) // 0618 |
| +#define WF_PLE_TOP_AC0_QUEUE_EMPTY7_ADDR (WF_PLE_TOP_BASE + 0x61c) // 061C |
| +#define WF_PLE_TOP_AC0_QUEUE_EMPTY8_ADDR (WF_PLE_TOP_BASE + 0x620) // 0620 |
| + |
| +#define WF_PLE_TOP_AC1_QUEUE_EMPTY0_ADDR (WF_PLE_TOP_BASE + 0x700) // 0700 |
| +#define WF_PLE_TOP_AC1_QUEUE_EMPTY1_ADDR (WF_PLE_TOP_BASE + 0x704) // 0704 |
| +#define WF_PLE_TOP_AC1_QUEUE_EMPTY2_ADDR (WF_PLE_TOP_BASE + 0x708) // 0708 |
| +#define WF_PLE_TOP_AC1_QUEUE_EMPTY3_ADDR (WF_PLE_TOP_BASE + 0x70c) // 070C |
| +#define WF_PLE_TOP_AC1_QUEUE_EMPTY4_ADDR (WF_PLE_TOP_BASE + 0x710) // 0710 |
| +#define WF_PLE_TOP_AC1_QUEUE_EMPTY5_ADDR (WF_PLE_TOP_BASE + 0x714) // 0714 |
| +#define WF_PLE_TOP_AC1_QUEUE_EMPTY6_ADDR (WF_PLE_TOP_BASE + 0x718) // 0718 |
| +#define WF_PLE_TOP_AC1_QUEUE_EMPTY7_ADDR (WF_PLE_TOP_BASE + 0x71c) // 071C |
| +#define WF_PLE_TOP_AC1_QUEUE_EMPTY8_ADDR (WF_PLE_TOP_BASE + 0x720) // 0720 |
| + |
| +#define WF_PLE_TOP_AC2_QUEUE_EMPTY0_ADDR (WF_PLE_TOP_BASE + 0x800) // 0800 |
| +#define WF_PLE_TOP_AC2_QUEUE_EMPTY1_ADDR (WF_PLE_TOP_BASE + 0x804) // 0804 |
| +#define WF_PLE_TOP_AC2_QUEUE_EMPTY2_ADDR (WF_PLE_TOP_BASE + 0x808) // 0808 |
| +#define WF_PLE_TOP_AC2_QUEUE_EMPTY3_ADDR (WF_PLE_TOP_BASE + 0x80c) // 080C |
| +#define WF_PLE_TOP_AC2_QUEUE_EMPTY4_ADDR (WF_PLE_TOP_BASE + 0x810) // 0810 |
| +#define WF_PLE_TOP_AC2_QUEUE_EMPTY5_ADDR (WF_PLE_TOP_BASE + 0x814) // 0814 |
| +#define WF_PLE_TOP_AC2_QUEUE_EMPTY6_ADDR (WF_PLE_TOP_BASE + 0x818) // 0818 |
| +#define WF_PLE_TOP_AC2_QUEUE_EMPTY7_ADDR (WF_PLE_TOP_BASE + 0x81c) // 081C |
| +#define WF_PLE_TOP_AC2_QUEUE_EMPTY8_ADDR (WF_PLE_TOP_BASE + 0x820) // 0820 |
| + |
| +#define WF_PLE_TOP_AC3_QUEUE_EMPTY0_ADDR (WF_PLE_TOP_BASE + 0x900) // 0900 |
| +#define WF_PLE_TOP_AC3_QUEUE_EMPTY1_ADDR (WF_PLE_TOP_BASE + 0x904) // 0904 |
| +#define WF_PLE_TOP_AC3_QUEUE_EMPTY2_ADDR (WF_PLE_TOP_BASE + 0x908) // 0908 |
| +#define WF_PLE_TOP_AC3_QUEUE_EMPTY3_ADDR (WF_PLE_TOP_BASE + 0x90c) // 090C |
| +#define WF_PLE_TOP_AC3_QUEUE_EMPTY4_ADDR (WF_PLE_TOP_BASE + 0x910) // 0910 |
| +#define WF_PLE_TOP_AC3_QUEUE_EMPTY5_ADDR (WF_PLE_TOP_BASE + 0x914) // 0914 |
| +#define WF_PLE_TOP_AC3_QUEUE_EMPTY6_ADDR (WF_PLE_TOP_BASE + 0x918) // 0918 |
| +#define WF_PLE_TOP_AC3_QUEUE_EMPTY7_ADDR (WF_PLE_TOP_BASE + 0x91c) // 091C |
| +#define WF_PLE_TOP_AC3_QUEUE_EMPTY8_ADDR (WF_PLE_TOP_BASE + 0x920) // 0920 |
| + |
| +#define WF_PLE_TOP_QUEUE_EMPTY_ALL_AC_EMPTY_ADDR WF_PLE_TOP_QUEUE_EMPTY_ADDR |
| +#define WF_PLE_TOP_QUEUE_EMPTY_ALL_AC_EMPTY_MASK 0x01000000 // ALL_AC_EMPTY[24] |
| +#define WF_PLE_TOP_QUEUE_EMPTY_ALL_AC_EMPTY_SHFT 24 |
| + |
| +#define WF_PLE_TOP_PBUF_CTRL_PAGE_SIZE_CFG_ADDR WF_PLE_TOP_PBUF_CTRL_ADDR |
| +#define WF_PLE_TOP_PBUF_CTRL_PAGE_SIZE_CFG_MASK 0x80000000 // PAGE_SIZE_CFG[31] |
| +#define WF_PLE_TOP_PBUF_CTRL_PAGE_SIZE_CFG_SHFT 31 |
| +#define WF_PLE_TOP_PBUF_CTRL_PBUF_OFFSET_ADDR WF_PLE_TOP_PBUF_CTRL_ADDR |
| +#define WF_PLE_TOP_PBUF_CTRL_PBUF_OFFSET_MASK 0x03FE0000 // PBUF_OFFSET[25..17] |
| +#define WF_PLE_TOP_PBUF_CTRL_PBUF_OFFSET_SHFT 17 |
| +#define WF_PLE_TOP_PBUF_CTRL_TOTAL_PAGE_NUM_ADDR WF_PLE_TOP_PBUF_CTRL_ADDR |
| +#define WF_PLE_TOP_PBUF_CTRL_TOTAL_PAGE_NUM_MASK 0x00000FFF // TOTAL_PAGE_NUM[11..0] |
| +#define WF_PLE_TOP_PBUF_CTRL_TOTAL_PAGE_NUM_SHFT 0 |
| + |
| +#define WF_PLE_TOP_FREEPG_CNT_FFA_CNT_ADDR WF_PLE_TOP_FREEPG_CNT_ADDR |
| +#define WF_PLE_TOP_FREEPG_CNT_FFA_CNT_MASK 0x0FFF0000 // FFA_CNT[27..16] |
| +#define WF_PLE_TOP_FREEPG_CNT_FFA_CNT_SHFT 16 |
| +#define WF_PLE_TOP_FREEPG_CNT_FREEPG_CNT_ADDR WF_PLE_TOP_FREEPG_CNT_ADDR |
| +#define WF_PLE_TOP_FREEPG_CNT_FREEPG_CNT_MASK 0x00000FFF // FREEPG_CNT[11..0] |
| +#define WF_PLE_TOP_FREEPG_CNT_FREEPG_CNT_SHFT 0 |
| + |
| +#define WF_PLE_TOP_FREEPG_HEAD_TAIL_FREEPG_TAIL_ADDR WF_PLE_TOP_FREEPG_HEAD_TAIL_ADDR |
| +#define WF_PLE_TOP_FREEPG_HEAD_TAIL_FREEPG_TAIL_MASK 0x0FFF0000 // FREEPG_TAIL[27..16] |
| +#define WF_PLE_TOP_FREEPG_HEAD_TAIL_FREEPG_TAIL_SHFT 16 |
| +#define WF_PLE_TOP_FREEPG_HEAD_TAIL_FREEPG_HEAD_ADDR WF_PLE_TOP_FREEPG_HEAD_TAIL_ADDR |
| +#define WF_PLE_TOP_FREEPG_HEAD_TAIL_FREEPG_HEAD_MASK 0x00000FFF // FREEPG_HEAD[11..0] |
| +#define WF_PLE_TOP_FREEPG_HEAD_TAIL_FREEPG_HEAD_SHFT 0 |
| + |
| +#define WF_PLE_TOP_PG_HIF_GROUP_HIF_MAX_QUOTA_ADDR WF_PLE_TOP_PG_HIF_GROUP_ADDR |
| +#define WF_PLE_TOP_PG_HIF_GROUP_HIF_MAX_QUOTA_MASK 0x0FFF0000 // HIF_MAX_QUOTA[27..16] |
| +#define WF_PLE_TOP_PG_HIF_GROUP_HIF_MAX_QUOTA_SHFT 16 |
| +#define WF_PLE_TOP_PG_HIF_GROUP_HIF_MIN_QUOTA_ADDR WF_PLE_TOP_PG_HIF_GROUP_ADDR |
| +#define WF_PLE_TOP_PG_HIF_GROUP_HIF_MIN_QUOTA_MASK 0x00000FFF // HIF_MIN_QUOTA[11..0] |
| +#define WF_PLE_TOP_PG_HIF_GROUP_HIF_MIN_QUOTA_SHFT 0 |
| + |
| +#define WF_PLE_TOP_HIF_PG_INFO_HIF_SRC_CNT_ADDR WF_PLE_TOP_HIF_PG_INFO_ADDR |
| +#define WF_PLE_TOP_HIF_PG_INFO_HIF_SRC_CNT_MASK 0x0FFF0000 // HIF_SRC_CNT[27..16] |
| +#define WF_PLE_TOP_HIF_PG_INFO_HIF_SRC_CNT_SHFT 16 |
| +#define WF_PLE_TOP_HIF_PG_INFO_HIF_RSV_CNT_ADDR WF_PLE_TOP_HIF_PG_INFO_ADDR |
| +#define WF_PLE_TOP_HIF_PG_INFO_HIF_RSV_CNT_MASK 0x00000FFF // HIF_RSV_CNT[11..0] |
| +#define WF_PLE_TOP_HIF_PG_INFO_HIF_RSV_CNT_SHFT 0 |
| + |
| +#define WF_PLE_TOP_PG_HIF_WMTXD_GROUP_HIF_WMTXD_MAX_QUOTA_ADDR WF_PLE_TOP_PG_HIF_WMTXD_GROUP_ADDR |
| +#define WF_PLE_TOP_PG_HIF_WMTXD_GROUP_HIF_WMTXD_MAX_QUOTA_MASK 0x0FFF0000 // HIF_WMTXD_MAX_QUOTA[27..16] |
| +#define WF_PLE_TOP_PG_HIF_WMTXD_GROUP_HIF_WMTXD_MAX_QUOTA_SHFT 16 |
| +#define WF_PLE_TOP_PG_HIF_WMTXD_GROUP_HIF_WMTXD_MIN_QUOTA_ADDR WF_PLE_TOP_PG_HIF_WMTXD_GROUP_ADDR |
| +#define WF_PLE_TOP_PG_HIF_WMTXD_GROUP_HIF_WMTXD_MIN_QUOTA_MASK 0x00000FFF // HIF_WMTXD_MIN_QUOTA[11..0] |
| +#define WF_PLE_TOP_PG_HIF_WMTXD_GROUP_HIF_WMTXD_MIN_QUOTA_SHFT 0 |
| + |
| +#define WF_PLE_TOP_HIF_WMTXD_PG_INFO_HIF_WMTXD_SRC_CNT_ADDR WF_PLE_TOP_HIF_WMTXD_PG_INFO_ADDR |
| +#define WF_PLE_TOP_HIF_WMTXD_PG_INFO_HIF_WMTXD_SRC_CNT_MASK 0x0FFF0000 // HIF_WMTXD_SRC_CNT[27..16] |
| +#define WF_PLE_TOP_HIF_WMTXD_PG_INFO_HIF_WMTXD_SRC_CNT_SHFT 16 |
| +#define WF_PLE_TOP_HIF_WMTXD_PG_INFO_HIF_WMTXD_RSV_CNT_ADDR WF_PLE_TOP_HIF_WMTXD_PG_INFO_ADDR |
| +#define WF_PLE_TOP_HIF_WMTXD_PG_INFO_HIF_WMTXD_RSV_CNT_MASK 0x00000FFF // HIF_WMTXD_RSV_CNT[11..0] |
| +#define WF_PLE_TOP_HIF_WMTXD_PG_INFO_HIF_WMTXD_RSV_CNT_SHFT 0 |
| + |
| +#define WF_PLE_TOP_PG_HIF_TXCMD_GROUP_HIF_TXCMD_MAX_QUOTA_ADDR WF_PLE_TOP_PG_HIF_TXCMD_GROUP_ADDR |
| +#define WF_PLE_TOP_PG_HIF_TXCMD_GROUP_HIF_TXCMD_MAX_QUOTA_MASK 0x0FFF0000 // HIF_TXCMD_MAX_QUOTA[27..16] |
| +#define WF_PLE_TOP_PG_HIF_TXCMD_GROUP_HIF_TXCMD_MAX_QUOTA_SHFT 16 |
| +#define WF_PLE_TOP_PG_HIF_TXCMD_GROUP_HIF_TXCMD_MIN_QUOTA_ADDR WF_PLE_TOP_PG_HIF_TXCMD_GROUP_ADDR |
| +#define WF_PLE_TOP_PG_HIF_TXCMD_GROUP_HIF_TXCMD_MIN_QUOTA_MASK 0x00000FFF // HIF_TXCMD_MIN_QUOTA[11..0] |
| +#define WF_PLE_TOP_PG_HIF_TXCMD_GROUP_HIF_TXCMD_MIN_QUOTA_SHFT 0 |
| + |
| +#define WF_PLE_TOP_HIF_TXCMD_PG_INFO_HIF_TXCMD_SRC_CNT_ADDR WF_PLE_TOP_HIF_TXCMD_PG_INFO_ADDR |
| +#define WF_PLE_TOP_HIF_TXCMD_PG_INFO_HIF_TXCMD_SRC_CNT_MASK 0x0FFF0000 // HIF_TXCMD_SRC_CNT[27..16] |
| +#define WF_PLE_TOP_HIF_TXCMD_PG_INFO_HIF_TXCMD_SRC_CNT_SHFT 16 |
| +#define WF_PLE_TOP_HIF_TXCMD_PG_INFO_HIF_TXCMD_RSV_CNT_ADDR WF_PLE_TOP_HIF_TXCMD_PG_INFO_ADDR |
| +#define WF_PLE_TOP_HIF_TXCMD_PG_INFO_HIF_TXCMD_RSV_CNT_MASK 0x00000FFF // HIF_TXCMD_RSV_CNT[11..0] |
| +#define WF_PLE_TOP_HIF_TXCMD_PG_INFO_HIF_TXCMD_RSV_CNT_SHFT 0 |
| + |
| +#define WF_PLE_TOP_PG_CPU_GROUP_CPU_MAX_QUOTA_ADDR WF_PLE_TOP_PG_CPU_GROUP_ADDR |
| +#define WF_PLE_TOP_PG_CPU_GROUP_CPU_MAX_QUOTA_MASK 0x0FFF0000 // CPU_MAX_QUOTA[27..16] |
| +#define WF_PLE_TOP_PG_CPU_GROUP_CPU_MAX_QUOTA_SHFT 16 |
| +#define WF_PLE_TOP_PG_CPU_GROUP_CPU_MIN_QUOTA_ADDR WF_PLE_TOP_PG_CPU_GROUP_ADDR |
| +#define WF_PLE_TOP_PG_CPU_GROUP_CPU_MIN_QUOTA_MASK 0x00000FFF // CPU_MIN_QUOTA[11..0] |
| +#define WF_PLE_TOP_PG_CPU_GROUP_CPU_MIN_QUOTA_SHFT 0 |
| + |
| +#define WF_PLE_TOP_CPU_PG_INFO_CPU_SRC_CNT_ADDR WF_PLE_TOP_CPU_PG_INFO_ADDR |
| +#define WF_PLE_TOP_CPU_PG_INFO_CPU_SRC_CNT_MASK 0x0FFF0000 // CPU_SRC_CNT[27..16] |
| +#define WF_PLE_TOP_CPU_PG_INFO_CPU_SRC_CNT_SHFT 16 |
| +#define WF_PLE_TOP_CPU_PG_INFO_CPU_RSV_CNT_ADDR WF_PLE_TOP_CPU_PG_INFO_ADDR |
| +#define WF_PLE_TOP_CPU_PG_INFO_CPU_RSV_CNT_MASK 0x00000FFF // CPU_RSV_CNT[11..0] |
| +#define WF_PLE_TOP_CPU_PG_INFO_CPU_RSV_CNT_SHFT 0 |
| + |
| +#define WF_PLE_TOP_FL_QUE_CTRL_0_EXECUTE_ADDR WF_PLE_TOP_FL_QUE_CTRL_0_ADDR |
| +#define WF_PLE_TOP_FL_QUE_CTRL_0_EXECUTE_MASK 0x80000000 // EXECUTE[31] |
| +#define WF_PLE_TOP_FL_QUE_CTRL_0_EXECUTE_SHFT 31 |
| +#define WF_PLE_TOP_FL_QUE_CTRL_0_Q_BUF_QID_ADDR WF_PLE_TOP_FL_QUE_CTRL_0_ADDR |
| +#define WF_PLE_TOP_FL_QUE_CTRL_0_Q_BUF_QID_MASK 0x7F000000 // Q_BUF_QID[30..24] |
| +#define WF_PLE_TOP_FL_QUE_CTRL_0_Q_BUF_QID_SHFT 24 |
| +#define WF_PLE_TOP_FL_QUE_CTRL_0_FL_BUFFER_ADDR_ADDR WF_PLE_TOP_FL_QUE_CTRL_0_ADDR |
| +#define WF_PLE_TOP_FL_QUE_CTRL_0_FL_BUFFER_ADDR_MASK 0x00FFF000 // FL_BUFFER_ADDR[23..12] |
| +#define WF_PLE_TOP_FL_QUE_CTRL_0_FL_BUFFER_ADDR_SHFT 12 |
| +#define WF_PLE_TOP_FL_QUE_CTRL_0_Q_BUF_WLANID_ADDR WF_PLE_TOP_FL_QUE_CTRL_0_ADDR |
| +#define WF_PLE_TOP_FL_QUE_CTRL_0_Q_BUF_WLANID_MASK 0x00000FFF // Q_BUF_WLANID[11..0] |
| +#define WF_PLE_TOP_FL_QUE_CTRL_0_Q_BUF_WLANID_SHFT 0 |
| + |
| +#define WF_PLE_TOP_FL_QUE_CTRL_1_Q_BUF_TGID_ADDR WF_PLE_TOP_FL_QUE_CTRL_1_ADDR |
| +#define WF_PLE_TOP_FL_QUE_CTRL_1_Q_BUF_TGID_MASK 0xC0000000 // Q_BUF_TGID[31..30] |
| +#define WF_PLE_TOP_FL_QUE_CTRL_1_Q_BUF_TGID_SHFT 30 |
| +#define WF_PLE_TOP_FL_QUE_CTRL_1_Q_BUF_PID_ADDR WF_PLE_TOP_FL_QUE_CTRL_1_ADDR |
| +#define WF_PLE_TOP_FL_QUE_CTRL_1_Q_BUF_PID_MASK 0x30000000 // Q_BUF_PID[29..28] |
| +#define WF_PLE_TOP_FL_QUE_CTRL_1_Q_BUF_PID_SHFT 28 |
| + |
| +#define WF_PLE_TOP_FL_QUE_CTRL_2_QUEUE_TAIL_FID_ADDR WF_PLE_TOP_FL_QUE_CTRL_2_ADDR |
| +#define WF_PLE_TOP_FL_QUE_CTRL_2_QUEUE_TAIL_FID_MASK 0x0FFF0000 // QUEUE_TAIL_FID[27..16] |
| +#define WF_PLE_TOP_FL_QUE_CTRL_2_QUEUE_TAIL_FID_SHFT 16 |
| +#define WF_PLE_TOP_FL_QUE_CTRL_2_QUEUE_HEAD_FID_ADDR WF_PLE_TOP_FL_QUE_CTRL_2_ADDR |
| +#define WF_PLE_TOP_FL_QUE_CTRL_2_QUEUE_HEAD_FID_MASK 0x00000FFF // QUEUE_HEAD_FID[11..0] |
| +#define WF_PLE_TOP_FL_QUE_CTRL_2_QUEUE_HEAD_FID_SHFT 0 |
| + |
| +#define WF_PLE_TOP_FL_QUE_CTRL_3_QUEUE_PKT_NUM_ADDR WF_PLE_TOP_FL_QUE_CTRL_3_ADDR |
| +#define WF_PLE_TOP_FL_QUE_CTRL_3_QUEUE_PKT_NUM_MASK 0x00000FFF // QUEUE_PKT_NUM[11..0] |
| +#define WF_PLE_TOP_FL_QUE_CTRL_3_QUEUE_PKT_NUM_SHFT 0 |
| + |
| +/* PSE */ |
| +#define WF_PSE_TOP_BASE 0x820c8000 |
| + |
| +#define WF_PSE_TOP_PBUF_CTRL_ADDR (WF_PSE_TOP_BASE + 0x04) // 8004 |
| +#define WF_PSE_TOP_QUEUE_EMPTY_ADDR (WF_PSE_TOP_BASE + 0xB0) // 80B0 |
| +#define WF_PSE_TOP_QUEUE_EMPTY_1_ADDR (WF_PSE_TOP_BASE + 0xBC) // 80BC |
| +#define WF_PSE_TOP_PG_HIF0_GROUP_ADDR (WF_PSE_TOP_BASE + 0x110) // 8110 |
| +#define WF_PSE_TOP_PG_HIF1_GROUP_ADDR (WF_PSE_TOP_BASE + 0x114) // 8114 |
| +#define WF_PSE_TOP_PG_CPU_GROUP_ADDR (WF_PSE_TOP_BASE + 0x118) // 8118 |
| +#define WF_PSE_TOP_PG_PLE_GROUP_ADDR (WF_PSE_TOP_BASE + 0x11C) // 811C |
| +#define WF_PSE_TOP_PG_PLE1_GROUP_ADDR (WF_PSE_TOP_BASE + 0x120) // 8120 |
| +#define WF_PSE_TOP_PG_LMAC0_GROUP_ADDR (WF_PSE_TOP_BASE + 0x124) // 8124 |
| +#define WF_PSE_TOP_PG_LMAC1_GROUP_ADDR (WF_PSE_TOP_BASE + 0x128) // 8128 |
| +#define WF_PSE_TOP_PG_LMAC2_GROUP_ADDR (WF_PSE_TOP_BASE + 0x12C) // 812C |
| +#define WF_PSE_TOP_PG_LMAC3_GROUP_ADDR (WF_PSE_TOP_BASE + 0x130) // 8130 |
| +#define WF_PSE_TOP_PG_MDP_GROUP_ADDR (WF_PSE_TOP_BASE + 0x134) // 8134 |
| +#define WF_PSE_TOP_PG_MDP2_GROUP_ADDR (WF_PSE_TOP_BASE + 0x13C) // 813C |
| +#define WF_PSE_TOP_PG_HIF2_GROUP_ADDR (WF_PSE_TOP_BASE + 0x140) // 8140 |
| +#define WF_PSE_TOP_PG_MDP3_GROUP_ADDR (WF_PSE_TOP_BASE + 0x144) // 8144 |
| +#define WF_PSE_TOP_HIF0_PG_INFO_ADDR (WF_PSE_TOP_BASE + 0x150) // 8150 |
| +#define WF_PSE_TOP_HIF1_PG_INFO_ADDR (WF_PSE_TOP_BASE + 0x154) // 8154 |
| +#define WF_PSE_TOP_CPU_PG_INFO_ADDR (WF_PSE_TOP_BASE + 0x158) // 8158 |
| +#define WF_PSE_TOP_PLE_PG_INFO_ADDR (WF_PSE_TOP_BASE + 0x15C) // 815C |
| +#define WF_PSE_TOP_PLE1_PG_INFO_ADDR (WF_PSE_TOP_BASE + 0x160) // 8160 |
| +#define WF_PSE_TOP_LMAC0_PG_INFO_ADDR (WF_PSE_TOP_BASE + 0x164) // 8164 |
| +#define WF_PSE_TOP_LMAC1_PG_INFO_ADDR (WF_PSE_TOP_BASE + 0x168) // 8168 |
| +#define WF_PSE_TOP_LMAC2_PG_INFO_ADDR (WF_PSE_TOP_BASE + 0x16C) // 816C |
| +#define WF_PSE_TOP_LMAC3_PG_INFO_ADDR (WF_PSE_TOP_BASE + 0x170) // 8170 |
| +#define WF_PSE_TOP_MDP_PG_INFO_ADDR (WF_PSE_TOP_BASE + 0x174) // 8174 |
| +#define WF_PSE_TOP_MDP2_PG_INFO_ADDR (WF_PSE_TOP_BASE + 0x17C) // 817C |
| +#define WF_PSE_TOP_HIF2_PG_INFO_ADDR (WF_PSE_TOP_BASE + 0x180) // 8180 |
| +#define WF_PSE_TOP_MDP3_PG_INFO_ADDR (WF_PSE_TOP_BASE + 0x184) // 8184 |
| +#define WF_PSE_TOP_FL_QUE_CTRL_0_ADDR (WF_PSE_TOP_BASE + 0x1B0) // 81B0 |
| +#define WF_PSE_TOP_FL_QUE_CTRL_1_ADDR (WF_PSE_TOP_BASE + 0x1B4) // 81B4 |
| +#define WF_PSE_TOP_FL_QUE_CTRL_2_ADDR (WF_PSE_TOP_BASE + 0x1B8) // 81B8 |
| +#define WF_PSE_TOP_FL_QUE_CTRL_3_ADDR (WF_PSE_TOP_BASE + 0x1BC) // 81BC |
| +#define WF_PSE_TOP_FREEPG_CNT_ADDR (WF_PSE_TOP_BASE + 0x380) // 8380 |
| +#define WF_PSE_TOP_FREEPG_HEAD_TAIL_ADDR (WF_PSE_TOP_BASE + 0x384) // 8384 |
| + |
| +#define WF_PSE_TOP_PBUF_CTRL_PAGE_SIZE_CFG_ADDR WF_PSE_TOP_PBUF_CTRL_ADDR |
| +#define WF_PSE_TOP_PBUF_CTRL_PAGE_SIZE_CFG_MASK 0x80000000 // PAGE_SIZE_CFG[31] |
| +#define WF_PSE_TOP_PBUF_CTRL_PAGE_SIZE_CFG_SHFT 31 |
| +#define WF_PSE_TOP_PBUF_CTRL_PBUF_OFFSET_ADDR WF_PSE_TOP_PBUF_CTRL_ADDR |
| +#define WF_PSE_TOP_PBUF_CTRL_PBUF_OFFSET_MASK 0x03FE0000 // PBUF_OFFSET[25..17] |
| +#define WF_PSE_TOP_PBUF_CTRL_PBUF_OFFSET_SHFT 17 |
| +#define WF_PSE_TOP_PBUF_CTRL_TOTAL_PAGE_NUM_ADDR WF_PSE_TOP_PBUF_CTRL_ADDR |
| +#define WF_PSE_TOP_PBUF_CTRL_TOTAL_PAGE_NUM_MASK 0x00000FFF // TOTAL_PAGE_NUM[11..0] |
| +#define WF_PSE_TOP_PBUF_CTRL_TOTAL_PAGE_NUM_SHFT 0 |
| + |
| +#define WF_PSE_TOP_QUEUE_EMPTY_RLS_Q_EMTPY_ADDR WF_PSE_TOP_QUEUE_EMPTY_ADDR |
| +#define WF_PSE_TOP_QUEUE_EMPTY_RLS_Q_EMTPY_MASK 0x80000000 // RLS_Q_EMTPY[31] |
| +#define WF_PSE_TOP_QUEUE_EMPTY_RLS_Q_EMTPY_SHFT 31 |
| +#define WF_PSE_TOP_QUEUE_EMPTY_CPU_Q4_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_ADDR |
| +#define WF_PSE_TOP_QUEUE_EMPTY_CPU_Q4_EMPTY_MASK 0x10000000 // CPU_Q4_EMPTY[28] |
| +#define WF_PSE_TOP_QUEUE_EMPTY_CPU_Q4_EMPTY_SHFT 28 |
| +#define WF_PSE_TOP_QUEUE_EMPTY_MDP_RXIOC1_QUEUE_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_ADDR |
| +#define WF_PSE_TOP_QUEUE_EMPTY_MDP_RXIOC1_QUEUE_EMPTY_MASK 0x08000000 // MDP_RXIOC1_QUEUE_EMPTY[27] |
| +#define WF_PSE_TOP_QUEUE_EMPTY_MDP_RXIOC1_QUEUE_EMPTY_SHFT 27 |
| +#define WF_PSE_TOP_QUEUE_EMPTY_MDP_TXIOC1_QUEUE_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_ADDR |
| +#define WF_PSE_TOP_QUEUE_EMPTY_MDP_TXIOC1_QUEUE_EMPTY_MASK 0x04000000 // MDP_TXIOC1_QUEUE_EMPTY[26] |
| +#define WF_PSE_TOP_QUEUE_EMPTY_MDP_TXIOC1_QUEUE_EMPTY_SHFT 26 |
| +#define WF_PSE_TOP_QUEUE_EMPTY_SEC_TX1_QUEUE_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_ADDR |
| +#define WF_PSE_TOP_QUEUE_EMPTY_SEC_TX1_QUEUE_EMPTY_MASK 0x02000000 // SEC_TX1_QUEUE_EMPTY[25] |
| +#define WF_PSE_TOP_QUEUE_EMPTY_SEC_TX1_QUEUE_EMPTY_SHFT 25 |
| +#define WF_PSE_TOP_QUEUE_EMPTY_MDP_TX1_QUEUE_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_ADDR |
| +#define WF_PSE_TOP_QUEUE_EMPTY_MDP_TX1_QUEUE_EMPTY_MASK 0x01000000 // MDP_TX1_QUEUE_EMPTY[24] |
| +#define WF_PSE_TOP_QUEUE_EMPTY_MDP_TX1_QUEUE_EMPTY_SHFT 24 |
| +#define WF_PSE_TOP_QUEUE_EMPTY_MDP_RXIOC_QUEUE_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_ADDR |
| +#define WF_PSE_TOP_QUEUE_EMPTY_MDP_RXIOC_QUEUE_EMPTY_MASK 0x00800000 // MDP_RXIOC_QUEUE_EMPTY[23] |
| +#define WF_PSE_TOP_QUEUE_EMPTY_MDP_RXIOC_QUEUE_EMPTY_SHFT 23 |
| +#define WF_PSE_TOP_QUEUE_EMPTY_MDP_TXIOC_QUEUE_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_ADDR |
| +#define WF_PSE_TOP_QUEUE_EMPTY_MDP_TXIOC_QUEUE_EMPTY_MASK 0x00400000 // MDP_TXIOC_QUEUE_EMPTY[22] |
| +#define WF_PSE_TOP_QUEUE_EMPTY_MDP_TXIOC_QUEUE_EMPTY_SHFT 22 |
| +#define WF_PSE_TOP_QUEUE_EMPTY_SFD_PARK_QUEUE_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_ADDR |
| +#define WF_PSE_TOP_QUEUE_EMPTY_SFD_PARK_QUEUE_EMPTY_MASK 0x00200000 // SFD_PARK_QUEUE_EMPTY[21] |
| +#define WF_PSE_TOP_QUEUE_EMPTY_SFD_PARK_QUEUE_EMPTY_SHFT 21 |
| +#define WF_PSE_TOP_QUEUE_EMPTY_SEC_RX_QUEUE_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_ADDR |
| +#define WF_PSE_TOP_QUEUE_EMPTY_SEC_RX_QUEUE_EMPTY_MASK 0x00100000 // SEC_RX_QUEUE_EMPTY[20] |
| +#define WF_PSE_TOP_QUEUE_EMPTY_SEC_RX_QUEUE_EMPTY_SHFT 20 |
| +#define WF_PSE_TOP_QUEUE_EMPTY_SEC_TX_QUEUE_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_ADDR |
| +#define WF_PSE_TOP_QUEUE_EMPTY_SEC_TX_QUEUE_EMPTY_MASK 0x00080000 // SEC_TX_QUEUE_EMPTY[19] |
| +#define WF_PSE_TOP_QUEUE_EMPTY_SEC_TX_QUEUE_EMPTY_SHFT 19 |
| +#define WF_PSE_TOP_QUEUE_EMPTY_MDP_RX_QUEUE_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_ADDR |
| +#define WF_PSE_TOP_QUEUE_EMPTY_MDP_RX_QUEUE_EMPTY_MASK 0x00040000 // MDP_RX_QUEUE_EMPTY[18] |
| +#define WF_PSE_TOP_QUEUE_EMPTY_MDP_RX_QUEUE_EMPTY_SHFT 18 |
| +#define WF_PSE_TOP_QUEUE_EMPTY_MDP_TX_QUEUE_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_ADDR |
| +#define WF_PSE_TOP_QUEUE_EMPTY_MDP_TX_QUEUE_EMPTY_MASK 0x00020000 // MDP_TX_QUEUE_EMPTY[17] |
| +#define WF_PSE_TOP_QUEUE_EMPTY_MDP_TX_QUEUE_EMPTY_SHFT 17 |
| +#define WF_PSE_TOP_QUEUE_EMPTY_LMAC_TX_QUEUE_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_ADDR |
| +#define WF_PSE_TOP_QUEUE_EMPTY_LMAC_TX_QUEUE_EMPTY_MASK 0x00010000 // LMAC_TX_QUEUE_EMPTY[16] |
| +#define WF_PSE_TOP_QUEUE_EMPTY_LMAC_TX_QUEUE_EMPTY_SHFT 16 |
| + |
| +#define WF_PSE_TOP_QUEUE_EMPTY_CPU_Q3_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_ADDR |
| +#define WF_PSE_TOP_QUEUE_EMPTY_CPU_Q3_EMPTY_MASK 0x00000008 // CPU_Q3_EMPTY[3] |
| +#define WF_PSE_TOP_QUEUE_EMPTY_CPU_Q3_EMPTY_SHFT 3 |
| +#define WF_PSE_TOP_QUEUE_EMPTY_CPU_Q2_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_ADDR |
| +#define WF_PSE_TOP_QUEUE_EMPTY_CPU_Q2_EMPTY_MASK 0x00000004 // CPU_Q2_EMPTY[2] |
| +#define WF_PSE_TOP_QUEUE_EMPTY_CPU_Q2_EMPTY_SHFT 2 |
| +#define WF_PSE_TOP_QUEUE_EMPTY_CPU_Q1_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_ADDR |
| +#define WF_PSE_TOP_QUEUE_EMPTY_CPU_Q1_EMPTY_MASK 0x00000002 // CPU_Q1_EMPTY[1] |
| +#define WF_PSE_TOP_QUEUE_EMPTY_CPU_Q1_EMPTY_SHFT 1 |
| +#define WF_PSE_TOP_QUEUE_EMPTY_CPU_Q0_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_ADDR |
| +#define WF_PSE_TOP_QUEUE_EMPTY_CPU_Q0_EMPTY_MASK 0x00000001 // CPU_Q0_EMPTY[0] |
| +#define WF_PSE_TOP_QUEUE_EMPTY_CPU_Q0_EMPTY_SHFT 0 |
| + |
| +#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_13_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_1_ADDR |
| +#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_13_EMPTY_MASK 0x20000000 // HIF_13_EMPTY[29] |
| +#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_13_EMPTY_SHFT 29 |
| +#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_12_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_1_ADDR |
| +#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_12_EMPTY_MASK 0x10000000 // HIF_12_EMPTY[28] |
| +#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_12_EMPTY_SHFT 28 |
| +#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_11_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_1_ADDR |
| +#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_11_EMPTY_MASK 0x08000000 // HIF_11_EMPTY[27] |
| +#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_11_EMPTY_SHFT 27 |
| +#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_10_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_1_ADDR |
| +#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_10_EMPTY_MASK 0x04000000 // HIF_10_EMPTY[26] |
| +#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_10_EMPTY_SHFT 26 |
| +#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_9_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_1_ADDR |
| +#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_9_EMPTY_MASK 0x02000000 // HIF_9_EMPTY[25] |
| +#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_9_EMPTY_SHFT 25 |
| +#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_8_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_1_ADDR |
| +#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_8_EMPTY_MASK 0x01000000 // HIF_8_EMPTY[24] |
| +#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_8_EMPTY_SHFT 24 |
| +#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_7_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_1_ADDR |
| +#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_7_EMPTY_MASK 0x00800000 // HIF_7_EMPTY[23] |
| +#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_7_EMPTY_SHFT 23 |
| +#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_6_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_1_ADDR |
| +#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_6_EMPTY_MASK 0x00400000 // HIF_6_EMPTY[22] |
| +#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_6_EMPTY_SHFT 22 |
| +#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_5_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_1_ADDR |
| +#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_5_EMPTY_MASK 0x00200000 // HIF_5_EMPTY[21] |
| +#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_5_EMPTY_SHFT 21 |
| +#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_4_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_1_ADDR |
| +#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_4_EMPTY_MASK 0x00100000 // HIF_4_EMPTY[20] |
| +#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_4_EMPTY_SHFT 20 |
| +#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_3_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_1_ADDR |
| +#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_3_EMPTY_MASK 0x00080000 // HIF_3_EMPTY[19] |
| +#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_3_EMPTY_SHFT 19 |
| +#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_2_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_1_ADDR |
| +#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_2_EMPTY_MASK 0x00040000 // HIF_2_EMPTY[18] |
| +#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_2_EMPTY_SHFT 18 |
| +#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_1_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_1_ADDR |
| +#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_1_EMPTY_MASK 0x00020000 // HIF_1_EMPTY[17] |
| +#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_1_EMPTY_SHFT 17 |
| +#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_0_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_1_ADDR |
| +#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_0_EMPTY_MASK 0x00010000 // HIF_0_EMPTY[16] |
| +#define WF_PSE_TOP_QUEUE_EMPTY_1_HIF_0_EMPTY_SHFT 16 |
| +#define WF_PSE_TOP_QUEUE_EMPTY_1_MDP_RXIOC3_QUEUE_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_1_ADDR |
| +#define WF_PSE_TOP_QUEUE_EMPTY_1_MDP_RXIOC3_QUEUE_EMPTY_MASK 0x00008000 // MDP_RXIOC3_QUEUE_EMPTY[15] |
| +#define WF_PSE_TOP_QUEUE_EMPTY_1_MDP_RXIOC3_QUEUE_EMPTY_SHFT 15 |
| +#define WF_PSE_TOP_QUEUE_EMPTY_1_MDP_RXIOC2_QUEUE_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_1_ADDR |
| +#define WF_PSE_TOP_QUEUE_EMPTY_1_MDP_RXIOC2_QUEUE_EMPTY_MASK 0x00000800 // MDP_RXIOC2_QUEUE_EMPTY[11] |
| +#define WF_PSE_TOP_QUEUE_EMPTY_1_MDP_RXIOC2_QUEUE_EMPTY_SHFT 11 |
| +#define WF_PSE_TOP_QUEUE_EMPTY_1_MDP_TXIOC2_QUEUE_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_1_ADDR |
| +#define WF_PSE_TOP_QUEUE_EMPTY_1_MDP_TXIOC2_QUEUE_EMPTY_MASK 0x00000400 // MDP_TXIOC2_QUEUE_EMPTY[10] |
| +#define WF_PSE_TOP_QUEUE_EMPTY_1_MDP_TXIOC2_QUEUE_EMPTY_SHFT 10 |
| +#define WF_PSE_TOP_QUEUE_EMPTY_1_SEC_TX2_QUEUE_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_1_ADDR |
| +#define WF_PSE_TOP_QUEUE_EMPTY_1_SEC_TX2_QUEUE_EMPTY_MASK 0x00000200 // SEC_TX2_QUEUE_EMPTY[9] |
| +#define WF_PSE_TOP_QUEUE_EMPTY_1_SEC_TX2_QUEUE_EMPTY_SHFT 9 |
| +#define WF_PSE_TOP_QUEUE_EMPTY_1_MDP_TX2_QUEUE_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_1_ADDR |
| +#define WF_PSE_TOP_QUEUE_EMPTY_1_MDP_TX2_QUEUE_EMPTY_MASK 0x00000100 // MDP_TX2_QUEUE_EMPTY[8] |
| +#define WF_PSE_TOP_QUEUE_EMPTY_1_MDP_TX2_QUEUE_EMPTY_SHFT 8 |
| + |
| +#define WF_PSE_TOP_PG_HIF0_GROUP_HIF0_MAX_QUOTA_ADDR WF_PSE_TOP_PG_HIF0_GROUP_ADDR |
| +#define WF_PSE_TOP_PG_HIF0_GROUP_HIF0_MAX_QUOTA_MASK 0x0FFF0000 // HIF0_MAX_QUOTA[27..16] |
| +#define WF_PSE_TOP_PG_HIF0_GROUP_HIF0_MAX_QUOTA_SHFT 16 |
| +#define WF_PSE_TOP_PG_HIF0_GROUP_HIF0_MIN_QUOTA_ADDR WF_PSE_TOP_PG_HIF0_GROUP_ADDR |
| +#define WF_PSE_TOP_PG_HIF0_GROUP_HIF0_MIN_QUOTA_MASK 0x00000FFF // HIF0_MIN_QUOTA[11..0] |
| +#define WF_PSE_TOP_PG_HIF0_GROUP_HIF0_MIN_QUOTA_SHFT 0 |
| + |
| + |
| +#define WF_PSE_TOP_PG_HIF1_GROUP_HIF1_MAX_QUOTA_ADDR WF_PSE_TOP_PG_HIF1_GROUP_ADDR |
| +#define WF_PSE_TOP_PG_HIF1_GROUP_HIF1_MAX_QUOTA_MASK 0x0FFF0000 // HIF1_MAX_QUOTA[27..16] |
| +#define WF_PSE_TOP_PG_HIF1_GROUP_HIF1_MAX_QUOTA_SHFT 16 |
| +#define WF_PSE_TOP_PG_HIF1_GROUP_HIF1_MIN_QUOTA_ADDR WF_PSE_TOP_PG_HIF1_GROUP_ADDR |
| +#define WF_PSE_TOP_PG_HIF1_GROUP_HIF1_MIN_QUOTA_MASK 0x00000FFF // HIF1_MIN_QUOTA[11..0] |
| +#define WF_PSE_TOP_PG_HIF1_GROUP_HIF1_MIN_QUOTA_SHFT 0 |
| + |
| +#define WF_PSE_TOP_PG_CPU_GROUP_CPU_MAX_QUOTA_ADDR WF_PSE_TOP_PG_CPU_GROUP_ADDR |
| +#define WF_PSE_TOP_PG_CPU_GROUP_CPU_MAX_QUOTA_MASK 0x0FFF0000 // CPU_MAX_QUOTA[27..16] |
| +#define WF_PSE_TOP_PG_CPU_GROUP_CPU_MAX_QUOTA_SHFT 16 |
| +#define WF_PSE_TOP_PG_CPU_GROUP_CPU_MIN_QUOTA_ADDR WF_PSE_TOP_PG_CPU_GROUP_ADDR |
| +#define WF_PSE_TOP_PG_CPU_GROUP_CPU_MIN_QUOTA_MASK 0x00000FFF // CPU_MIN_QUOTA[11..0] |
| +#define WF_PSE_TOP_PG_CPU_GROUP_CPU_MIN_QUOTA_SHFT 0 |
| + |
| +#define WF_PSE_TOP_PG_PLE_GROUP_PLE_MAX_QUOTA_ADDR WF_PSE_TOP_PG_PLE_GROUP_ADDR |
| +#define WF_PSE_TOP_PG_PLE_GROUP_PLE_MAX_QUOTA_MASK 0x0FFF0000 // PLE_MAX_QUOTA[27..16] |
| +#define WF_PSE_TOP_PG_PLE_GROUP_PLE_MAX_QUOTA_SHFT 16 |
| +#define WF_PSE_TOP_PG_PLE_GROUP_PLE_MIN_QUOTA_ADDR WF_PSE_TOP_PG_PLE_GROUP_ADDR |
| +#define WF_PSE_TOP_PG_PLE_GROUP_PLE_MIN_QUOTA_MASK 0x00000FFF // PLE_MIN_QUOTA[11..0] |
| +#define WF_PSE_TOP_PG_PLE_GROUP_PLE_MIN_QUOTA_SHFT 0 |
| + |
| +#define WF_PSE_TOP_PG_LMAC0_GROUP_LMAC0_MAX_QUOTA_ADDR WF_PSE_TOP_PG_LMAC0_GROUP_ADDR |
| +#define WF_PSE_TOP_PG_LMAC0_GROUP_LMAC0_MAX_QUOTA_MASK 0x0FFF0000 // LMAC0_MAX_QUOTA[27..16] |
| +#define WF_PSE_TOP_PG_LMAC0_GROUP_LMAC0_MAX_QUOTA_SHFT 16 |
| +#define WF_PSE_TOP_PG_LMAC0_GROUP_LMAC0_MIN_QUOTA_ADDR WF_PSE_TOP_PG_LMAC0_GROUP_ADDR |
| +#define WF_PSE_TOP_PG_LMAC0_GROUP_LMAC0_MIN_QUOTA_MASK 0x00000FFF // LMAC0_MIN_QUOTA[11..0] |
| +#define WF_PSE_TOP_PG_LMAC0_GROUP_LMAC0_MIN_QUOTA_SHFT 0 |
| + |
| +#define WF_PSE_TOP_PG_LMAC1_GROUP_LMAC1_MAX_QUOTA_ADDR WF_PSE_TOP_PG_LMAC1_GROUP_ADDR |
| +#define WF_PSE_TOP_PG_LMAC1_GROUP_LMAC1_MAX_QUOTA_MASK 0x0FFF0000 // LMAC1_MAX_QUOTA[27..16] |
| +#define WF_PSE_TOP_PG_LMAC1_GROUP_LMAC1_MAX_QUOTA_SHFT 16 |
| +#define WF_PSE_TOP_PG_LMAC1_GROUP_LMAC1_MIN_QUOTA_ADDR WF_PSE_TOP_PG_LMAC1_GROUP_ADDR |
| +#define WF_PSE_TOP_PG_LMAC1_GROUP_LMAC1_MIN_QUOTA_MASK 0x00000FFF // LMAC1_MIN_QUOTA[11..0] |
| +#define WF_PSE_TOP_PG_LMAC1_GROUP_LMAC1_MIN_QUOTA_SHFT 0 |
| + |
| +#define WF_PSE_TOP_PG_LMAC2_GROUP_LMAC2_MAX_QUOTA_ADDR WF_PSE_TOP_PG_LMAC2_GROUP_ADDR |
| +#define WF_PSE_TOP_PG_LMAC2_GROUP_LMAC2_MAX_QUOTA_MASK 0x0FFF0000 // LMAC2_MAX_QUOTA[27..16] |
| +#define WF_PSE_TOP_PG_LMAC2_GROUP_LMAC2_MAX_QUOTA_SHFT 16 |
| +#define WF_PSE_TOP_PG_LMAC2_GROUP_LMAC2_MIN_QUOTA_ADDR WF_PSE_TOP_PG_LMAC2_GROUP_ADDR |
| +#define WF_PSE_TOP_PG_LMAC2_GROUP_LMAC2_MIN_QUOTA_MASK 0x00000FFF // LMAC2_MIN_QUOTA[11..0] |
| +#define WF_PSE_TOP_PG_LMAC2_GROUP_LMAC2_MIN_QUOTA_SHFT 0 |
| + |
| +#define WF_PSE_TOP_PG_LMAC3_GROUP_LMAC3_MAX_QUOTA_ADDR WF_PSE_TOP_PG_LMAC3_GROUP_ADDR |
| +#define WF_PSE_TOP_PG_LMAC3_GROUP_LMAC3_MAX_QUOTA_MASK 0x0FFF0000 // LMAC3_MAX_QUOTA[27..16] |
| +#define WF_PSE_TOP_PG_LMAC3_GROUP_LMAC3_MAX_QUOTA_SHFT 16 |
| +#define WF_PSE_TOP_PG_LMAC3_GROUP_LMAC3_MIN_QUOTA_ADDR WF_PSE_TOP_PG_LMAC3_GROUP_ADDR |
| +#define WF_PSE_TOP_PG_LMAC3_GROUP_LMAC3_MIN_QUOTA_MASK 0x00000FFF // LMAC3_MIN_QUOTA[11..0] |
| +#define WF_PSE_TOP_PG_LMAC3_GROUP_LMAC3_MIN_QUOTA_SHFT 0 |
| + |
| +#define WF_PSE_TOP_PG_MDP_GROUP_MDP_MAX_QUOTA_ADDR WF_PSE_TOP_PG_MDP_GROUP_ADDR |
| +#define WF_PSE_TOP_PG_MDP_GROUP_MDP_MAX_QUOTA_MASK 0x0FFF0000 // MDP_MAX_QUOTA[27..16] |
| +#define WF_PSE_TOP_PG_MDP_GROUP_MDP_MAX_QUOTA_SHFT 16 |
| +#define WF_PSE_TOP_PG_MDP_GROUP_MDP_MIN_QUOTA_ADDR WF_PSE_TOP_PG_MDP_GROUP_ADDR |
| +#define WF_PSE_TOP_PG_MDP_GROUP_MDP_MIN_QUOTA_MASK 0x00000FFF // MDP_MIN_QUOTA[11..0] |
| +#define WF_PSE_TOP_PG_MDP_GROUP_MDP_MIN_QUOTA_SHFT 0 |
| + |
| +#define WF_PSE_TOP_PG_MDP2_GROUP_MDP2_MAX_QUOTA_ADDR WF_PSE_TOP_PG_MDP2_GROUP_ADDR |
| +#define WF_PSE_TOP_PG_MDP2_GROUP_MDP2_MAX_QUOTA_MASK 0x0FFF0000 // MDP2_MAX_QUOTA[27..16] |
| +#define WF_PSE_TOP_PG_MDP2_GROUP_MDP2_MAX_QUOTA_SHFT 16 |
| +#define WF_PSE_TOP_PG_MDP2_GROUP_MDP2_MIN_QUOTA_ADDR WF_PSE_TOP_PG_MDP2_GROUP_ADDR |
| +#define WF_PSE_TOP_PG_MDP2_GROUP_MDP2_MIN_QUOTA_MASK 0x00000FFF // MDP2_MIN_QUOTA[11..0] |
| +#define WF_PSE_TOP_PG_MDP2_GROUP_MDP2_MIN_QUOTA_SHFT 0 |
| + |
| +#define WF_PSE_TOP_PG_HIF2_GROUP_HIF2_MAX_QUOTA_ADDR WF_PSE_TOP_PG_HIF2_GROUP_ADDR |
| +#define WF_PSE_TOP_PG_HIF2_GROUP_HIF2_MAX_QUOTA_MASK 0x0FFF0000 // HIF2_MAX_QUOTA[27..16] |
| +#define WF_PSE_TOP_PG_HIF2_GROUP_HIF2_MAX_QUOTA_SHFT 16 |
| +#define WF_PSE_TOP_PG_HIF2_GROUP_HIF2_MIN_QUOTA_ADDR WF_PSE_TOP_PG_HIF2_GROUP_ADDR |
| +#define WF_PSE_TOP_PG_HIF2_GROUP_HIF2_MIN_QUOTA_MASK 0x00000FFF // HIF2_MIN_QUOTA[11..0] |
| +#define WF_PSE_TOP_PG_HIF2_GROUP_HIF2_MIN_QUOTA_SHFT 0 |
| + |
| +#define WF_PSE_TOP_PG_MDP3_GROUP_MDP3_MAX_QUOTA_ADDR WF_PSE_TOP_PG_MDP3_GROUP_ADDR |
| +#define WF_PSE_TOP_PG_MDP3_GROUP_MDP3_MAX_QUOTA_MASK 0x0FFF0000 // MDP3_MAX_QUOTA[27..16] |
| +#define WF_PSE_TOP_PG_MDP3_GROUP_MDP3_MAX_QUOTA_SHFT 16 |
| +#define WF_PSE_TOP_PG_MDP3_GROUP_MDP3_MIN_QUOTA_ADDR WF_PSE_TOP_PG_MDP3_GROUP_ADDR |
| +#define WF_PSE_TOP_PG_MDP3_GROUP_MDP3_MIN_QUOTA_MASK 0x00000FFF // MDP3_MIN_QUOTA[11..0] |
| +#define WF_PSE_TOP_PG_MDP3_GROUP_MDP3_MIN_QUOTA_SHFT 0 |
| + |
| +#define WF_PSE_TOP_HIF0_PG_INFO_HIF0_SRC_CNT_ADDR WF_PSE_TOP_HIF0_PG_INFO_ADDR |
| +#define WF_PSE_TOP_HIF0_PG_INFO_HIF0_SRC_CNT_MASK 0x0FFF0000 // HIF0_SRC_CNT[27..16] |
| +#define WF_PSE_TOP_HIF0_PG_INFO_HIF0_SRC_CNT_SHFT 16 |
| +#define WF_PSE_TOP_HIF0_PG_INFO_HIF0_RSV_CNT_ADDR WF_PSE_TOP_HIF0_PG_INFO_ADDR |
| +#define WF_PSE_TOP_HIF0_PG_INFO_HIF0_RSV_CNT_MASK 0x00000FFF // HIF0_RSV_CNT[11..0] |
| +#define WF_PSE_TOP_HIF0_PG_INFO_HIF0_RSV_CNT_SHFT 0 |
| + |
| +#define WF_PSE_TOP_HIF1_PG_INFO_HIF1_SRC_CNT_ADDR WF_PSE_TOP_HIF1_PG_INFO_ADDR |
| +#define WF_PSE_TOP_HIF1_PG_INFO_HIF1_SRC_CNT_MASK 0x0FFF0000 // HIF1_SRC_CNT[27..16] |
| +#define WF_PSE_TOP_HIF1_PG_INFO_HIF1_SRC_CNT_SHFT 16 |
| +#define WF_PSE_TOP_HIF1_PG_INFO_HIF1_RSV_CNT_ADDR WF_PSE_TOP_HIF1_PG_INFO_ADDR |
| +#define WF_PSE_TOP_HIF1_PG_INFO_HIF1_RSV_CNT_MASK 0x00000FFF // HIF1_RSV_CNT[11..0] |
| +#define WF_PSE_TOP_HIF1_PG_INFO_HIF1_RSV_CNT_SHFT 0 |
| + |
| +#define WF_PSE_TOP_CPU_PG_INFO_CPU_SRC_CNT_ADDR WF_PSE_TOP_CPU_PG_INFO_ADDR |
| +#define WF_PSE_TOP_CPU_PG_INFO_CPU_SRC_CNT_MASK 0x0FFF0000 // CPU_SRC_CNT[27..16] |
| +#define WF_PSE_TOP_CPU_PG_INFO_CPU_SRC_CNT_SHFT 16 |
| +#define WF_PSE_TOP_CPU_PG_INFO_CPU_RSV_CNT_ADDR WF_PSE_TOP_CPU_PG_INFO_ADDR |
| +#define WF_PSE_TOP_CPU_PG_INFO_CPU_RSV_CNT_MASK 0x00000FFF // CPU_RSV_CNT[11..0] |
| +#define WF_PSE_TOP_CPU_PG_INFO_CPU_RSV_CNT_SHFT 0 |
| + |
| +#define WF_PSE_TOP_PLE_PG_INFO_PLE_SRC_CNT_ADDR WF_PSE_TOP_PLE_PG_INFO_ADDR |
| +#define WF_PSE_TOP_PLE_PG_INFO_PLE_SRC_CNT_MASK 0x0FFF0000 // PLE_SRC_CNT[27..16] |
| +#define WF_PSE_TOP_PLE_PG_INFO_PLE_SRC_CNT_SHFT 16 |
| +#define WF_PSE_TOP_PLE_PG_INFO_PLE_RSV_CNT_ADDR WF_PSE_TOP_PLE_PG_INFO_ADDR |
| +#define WF_PSE_TOP_PLE_PG_INFO_PLE_RSV_CNT_MASK 0x00000FFF // PLE_RSV_CNT[11..0] |
| +#define WF_PSE_TOP_PLE_PG_INFO_PLE_RSV_CNT_SHFT 0 |
| + |
| +#define WF_PSE_TOP_LMAC0_PG_INFO_LMAC0_SRC_CNT_ADDR WF_PSE_TOP_LMAC0_PG_INFO_ADDR |
| +#define WF_PSE_TOP_LMAC0_PG_INFO_LMAC0_SRC_CNT_MASK 0x0FFF0000 // LMAC0_SRC_CNT[27..16] |
| +#define WF_PSE_TOP_LMAC0_PG_INFO_LMAC0_SRC_CNT_SHFT 16 |
| +#define WF_PSE_TOP_LMAC0_PG_INFO_LMAC0_RSV_CNT_ADDR WF_PSE_TOP_LMAC0_PG_INFO_ADDR |
| +#define WF_PSE_TOP_LMAC0_PG_INFO_LMAC0_RSV_CNT_MASK 0x00000FFF // LMAC0_RSV_CNT[11..0] |
| +#define WF_PSE_TOP_LMAC0_PG_INFO_LMAC0_RSV_CNT_SHFT 0 |
| + |
| +#define WF_PSE_TOP_LMAC1_PG_INFO_LMAC1_SRC_CNT_ADDR WF_PSE_TOP_LMAC1_PG_INFO_ADDR |
| +#define WF_PSE_TOP_LMAC1_PG_INFO_LMAC1_SRC_CNT_MASK 0x0FFF0000 // LMAC1_SRC_CNT[27..16] |
| +#define WF_PSE_TOP_LMAC1_PG_INFO_LMAC1_SRC_CNT_SHFT 16 |
| +#define WF_PSE_TOP_LMAC1_PG_INFO_LMAC1_RSV_CNT_ADDR WF_PSE_TOP_LMAC1_PG_INFO_ADDR |
| +#define WF_PSE_TOP_LMAC1_PG_INFO_LMAC1_RSV_CNT_MASK 0x00000FFF // LMAC1_RSV_CNT[11..0] |
| +#define WF_PSE_TOP_LMAC1_PG_INFO_LMAC1_RSV_CNT_SHFT 0 |
| + |
| +#define WF_PSE_TOP_LMAC2_PG_INFO_LMAC2_SRC_CNT_ADDR WF_PSE_TOP_LMAC2_PG_INFO_ADDR |
| +#define WF_PSE_TOP_LMAC2_PG_INFO_LMAC2_SRC_CNT_MASK 0x0FFF0000 // LMAC2_SRC_CNT[27..16] |
| +#define WF_PSE_TOP_LMAC2_PG_INFO_LMAC2_SRC_CNT_SHFT 16 |
| +#define WF_PSE_TOP_LMAC2_PG_INFO_LMAC2_RSV_CNT_ADDR WF_PSE_TOP_LMAC2_PG_INFO_ADDR |
| +#define WF_PSE_TOP_LMAC2_PG_INFO_LMAC2_RSV_CNT_MASK 0x00000FFF // LMAC2_RSV_CNT[11..0] |
| +#define WF_PSE_TOP_LMAC2_PG_INFO_LMAC2_RSV_CNT_SHFT 0 |
| + |
| +#define WF_PSE_TOP_LMAC3_PG_INFO_LMAC3_SRC_CNT_ADDR WF_PSE_TOP_LMAC3_PG_INFO_ADDR |
| +#define WF_PSE_TOP_LMAC3_PG_INFO_LMAC3_SRC_CNT_MASK 0x0FFF0000 // LMAC3_SRC_CNT[27..16] |
| +#define WF_PSE_TOP_LMAC3_PG_INFO_LMAC3_SRC_CNT_SHFT 16 |
| +#define WF_PSE_TOP_LMAC3_PG_INFO_LMAC3_RSV_CNT_ADDR WF_PSE_TOP_LMAC3_PG_INFO_ADDR |
| +#define WF_PSE_TOP_LMAC3_PG_INFO_LMAC3_RSV_CNT_MASK 0x00000FFF // LMAC3_RSV_CNT[11..0] |
| +#define WF_PSE_TOP_LMAC3_PG_INFO_LMAC3_RSV_CNT_SHFT 0 |
| + |
| +#define WF_PSE_TOP_MDP_PG_INFO_MDP_SRC_CNT_ADDR WF_PSE_TOP_MDP_PG_INFO_ADDR |
| +#define WF_PSE_TOP_MDP_PG_INFO_MDP_SRC_CNT_MASK 0x0FFF0000 // MDP_SRC_CNT[27..16] |
| +#define WF_PSE_TOP_MDP_PG_INFO_MDP_SRC_CNT_SHFT 16 |
| +#define WF_PSE_TOP_MDP_PG_INFO_MDP_RSV_CNT_ADDR WF_PSE_TOP_MDP_PG_INFO_ADDR |
| +#define WF_PSE_TOP_MDP_PG_INFO_MDP_RSV_CNT_MASK 0x00000FFF // MDP_RSV_CNT[11..0] |
| +#define WF_PSE_TOP_MDP_PG_INFO_MDP_RSV_CNT_SHFT 0 |
| + |
| +#define WF_PSE_TOP_MDP2_PG_INFO_MDP2_SRC_CNT_ADDR WF_PSE_TOP_MDP2_PG_INFO_ADDR |
| +#define WF_PSE_TOP_MDP2_PG_INFO_MDP2_SRC_CNT_MASK 0x0FFF0000 // MDP2_SRC_CNT[27..16] |
| +#define WF_PSE_TOP_MDP2_PG_INFO_MDP2_SRC_CNT_SHFT 16 |
| +#define WF_PSE_TOP_MDP2_PG_INFO_MDP2_RSV_CNT_ADDR WF_PSE_TOP_MDP2_PG_INFO_ADDR |
| +#define WF_PSE_TOP_MDP2_PG_INFO_MDP2_RSV_CNT_MASK 0x00000FFF // MDP2_RSV_CNT[11..0] |
| +#define WF_PSE_TOP_MDP2_PG_INFO_MDP2_RSV_CNT_SHFT 0 |
| + |
| +#define WF_PSE_TOP_HIF2_PG_INFO_HIF2_SRC_CNT_ADDR WF_PSE_TOP_HIF2_PG_INFO_ADDR |
| +#define WF_PSE_TOP_HIF2_PG_INFO_HIF2_SRC_CNT_MASK 0x0FFF0000 // HIF2_SRC_CNT[27..16] |
| +#define WF_PSE_TOP_HIF2_PG_INFO_HIF2_SRC_CNT_SHFT 16 |
| +#define WF_PSE_TOP_HIF2_PG_INFO_HIF2_RSV_CNT_ADDR WF_PSE_TOP_HIF2_PG_INFO_ADDR |
| +#define WF_PSE_TOP_HIF2_PG_INFO_HIF2_RSV_CNT_MASK 0x00000FFF // HIF2_RSV_CNT[11..0] |
| +#define WF_PSE_TOP_HIF2_PG_INFO_HIF2_RSV_CNT_SHFT 0 |
| + |
| +#define WF_PSE_TOP_MDP3_PG_INFO_MDP3_SRC_CNT_ADDR WF_PSE_TOP_MDP3_PG_INFO_ADDR |
| +#define WF_PSE_TOP_MDP3_PG_INFO_MDP3_SRC_CNT_MASK 0x0FFF0000 // MDP3_SRC_CNT[27..16] |
| +#define WF_PSE_TOP_MDP3_PG_INFO_MDP3_SRC_CNT_SHFT 16 |
| +#define WF_PSE_TOP_MDP3_PG_INFO_MDP3_RSV_CNT_ADDR WF_PSE_TOP_MDP3_PG_INFO_ADDR |
| +#define WF_PSE_TOP_MDP3_PG_INFO_MDP3_RSV_CNT_MASK 0x00000FFF // MDP3_RSV_CNT[11..0] |
| +#define WF_PSE_TOP_MDP3_PG_INFO_MDP3_RSV_CNT_SHFT 0 |
| + |
| +#define WF_PSE_TOP_FL_QUE_CTRL_0_EXECUTE_ADDR WF_PSE_TOP_FL_QUE_CTRL_0_ADDR |
| +#define WF_PSE_TOP_FL_QUE_CTRL_0_EXECUTE_MASK 0x80000000 // EXECUTE[31] |
| +#define WF_PSE_TOP_FL_QUE_CTRL_0_EXECUTE_SHFT 31 |
| +#define WF_PSE_TOP_FL_QUE_CTRL_0_Q_BUF_QID_ADDR WF_PSE_TOP_FL_QUE_CTRL_0_ADDR |
| +#define WF_PSE_TOP_FL_QUE_CTRL_0_Q_BUF_QID_MASK 0x7F000000 // Q_BUF_QID[30..24] |
| +#define WF_PSE_TOP_FL_QUE_CTRL_0_Q_BUF_QID_SHFT 24 |
| + |
| +#define WF_PSE_TOP_FL_QUE_CTRL_1_Q_BUF_PID_ADDR WF_PSE_TOP_FL_QUE_CTRL_1_ADDR |
| +#define WF_PSE_TOP_FL_QUE_CTRL_1_Q_BUF_PID_MASK 0x30000000 // Q_BUF_PID[29..28] |
| +#define WF_PSE_TOP_FL_QUE_CTRL_1_Q_BUF_PID_SHFT 28 |
| + |
| +#define WF_PSE_TOP_FL_QUE_CTRL_2_QUEUE_TAIL_FID_ADDR WF_PSE_TOP_FL_QUE_CTRL_2_ADDR |
| +#define WF_PSE_TOP_FL_QUE_CTRL_2_QUEUE_TAIL_FID_MASK 0x0FFF0000 // QUEUE_TAIL_FID[27..16] |
| +#define WF_PSE_TOP_FL_QUE_CTRL_2_QUEUE_TAIL_FID_SHFT 16 |
| +#define WF_PSE_TOP_FL_QUE_CTRL_2_QUEUE_HEAD_FID_ADDR WF_PSE_TOP_FL_QUE_CTRL_2_ADDR |
| +#define WF_PSE_TOP_FL_QUE_CTRL_2_QUEUE_HEAD_FID_MASK 0x00000FFF // QUEUE_HEAD_FID[11..0] |
| +#define WF_PSE_TOP_FL_QUE_CTRL_2_QUEUE_HEAD_FID_SHFT 0 |
| + |
| +#define WF_PSE_TOP_FL_QUE_CTRL_3_QUEUE_PAGE_NUM_ADDR WF_PSE_TOP_FL_QUE_CTRL_3_ADDR |
| +#define WF_PSE_TOP_FL_QUE_CTRL_3_QUEUE_PAGE_NUM_MASK 0x00FFF000 // QUEUE_PAGE_NUM[23..12] |
| +#define WF_PSE_TOP_FL_QUE_CTRL_3_QUEUE_PAGE_NUM_SHFT 12 |
| +#define WF_PSE_TOP_FL_QUE_CTRL_3_QUEUE_PKT_NUM_ADDR WF_PSE_TOP_FL_QUE_CTRL_3_ADDR |
| +#define WF_PSE_TOP_FL_QUE_CTRL_3_QUEUE_PKT_NUM_MASK 0x00000FFF // QUEUE_PKT_NUM[11..0] |
| +#define WF_PSE_TOP_FL_QUE_CTRL_3_QUEUE_PKT_NUM_SHFT 0 |
| + |
| +#define WF_PSE_TOP_FREEPG_CNT_FFA_CNT_ADDR WF_PSE_TOP_FREEPG_CNT_ADDR |
| +#define WF_PSE_TOP_FREEPG_CNT_FFA_CNT_MASK 0x0FFF0000 // FFA_CNT[27..16] |
| +#define WF_PSE_TOP_FREEPG_CNT_FFA_CNT_SHFT 16 |
| +#define WF_PSE_TOP_FREEPG_CNT_FREEPG_CNT_ADDR WF_PSE_TOP_FREEPG_CNT_ADDR |
| +#define WF_PSE_TOP_FREEPG_CNT_FREEPG_CNT_MASK 0x00000FFF // FREEPG_CNT[11..0] |
| +#define WF_PSE_TOP_FREEPG_CNT_FREEPG_CNT_SHFT 0 |
| + |
| +#define WF_PSE_TOP_FREEPG_HEAD_TAIL_FREEPG_TAIL_ADDR WF_PSE_TOP_FREEPG_HEAD_TAIL_ADDR |
| +#define WF_PSE_TOP_FREEPG_HEAD_TAIL_FREEPG_TAIL_MASK 0x0FFF0000 // FREEPG_TAIL[27..16] |
| +#define WF_PSE_TOP_FREEPG_HEAD_TAIL_FREEPG_TAIL_SHFT 16 |
| +#define WF_PSE_TOP_FREEPG_HEAD_TAIL_FREEPG_HEAD_ADDR WF_PSE_TOP_FREEPG_HEAD_TAIL_ADDR |
| +#define WF_PSE_TOP_FREEPG_HEAD_TAIL_FREEPG_HEAD_MASK 0x00000FFF // FREEPG_HEAD[11..0] |
| +#define WF_PSE_TOP_FREEPG_HEAD_TAIL_FREEPG_HEAD_SHFT 0 |
| + |
| +/* AGG */ |
| +#define BN0_WF_AGG_TOP_BASE 0x820e2000 |
| +#define BN1_WF_AGG_TOP_BASE 0x820f2000 |
| +#define IP1_BN0_WF_AGG_TOP_BASE 0x830e2000 |
| + |
| +#define BN0_WF_AGG_TOP_SCR_ADDR (BN0_WF_AGG_TOP_BASE + 0x0) // 2000 |
| +#define BN0_WF_AGG_TOP_SCR0_ADDR (BN0_WF_AGG_TOP_BASE + 0x4) // 2004 |
| +#define BN0_WF_AGG_TOP_SCR1_ADDR (BN0_WF_AGG_TOP_BASE + 0x8) // 2008 |
| +#define BN0_WF_AGG_TOP_BCR_ADDR (BN0_WF_AGG_TOP_BASE + 0xc) // 200C |
| +#define BN0_WF_AGG_TOP_BWCR_ADDR (BN0_WF_AGG_TOP_BASE + 0x10) // 2010 |
| +#define BN0_WF_AGG_TOP_ARCR0_ADDR (BN0_WF_AGG_TOP_BASE + 0x14) // 2014 |
| +#define BN0_WF_AGG_TOP_ARUCR_ADDR (BN0_WF_AGG_TOP_BASE + 0x18) // 2018 |
| +#define BN0_WF_AGG_TOP_ARDCR_ADDR (BN0_WF_AGG_TOP_BASE + 0x1c) // 201C |
| +#define BN0_WF_AGG_TOP_AALCR0_ADDR (BN0_WF_AGG_TOP_BASE + 0x20) // 2020 |
| +#define BN0_WF_AGG_TOP_AALCR1_ADDR (BN0_WF_AGG_TOP_BASE + 0x24) // 2024 |
| +#define BN0_WF_AGG_TOP_PCR0_ADDR (BN0_WF_AGG_TOP_BASE + 0x28) // 2028 |
| +#define BN0_WF_AGG_TOP_PCR1_ADDR (BN0_WF_AGG_TOP_BASE + 0x2c) // 202C |
| +#define BN0_WF_AGG_TOP_TTCR0_ADDR (BN0_WF_AGG_TOP_BASE + 0x30) // 2030 |
| +#define BN0_WF_AGG_TOP_TTCR1_ADDR (BN0_WF_AGG_TOP_BASE + 0x34) // 2034 |
| +#define BN0_WF_AGG_TOP_ACR1_ADDR (BN0_WF_AGG_TOP_BASE + 0x38) // 2038 |
| +#define BN0_WF_AGG_TOP_ACR4_ADDR (BN0_WF_AGG_TOP_BASE + 0x3c) // 203C |
| +#define BN0_WF_AGG_TOP_ACR5_ADDR (BN0_WF_AGG_TOP_BASE + 0x40) // 2040 |
| +#define BN0_WF_AGG_TOP_ACR6_ADDR (BN0_WF_AGG_TOP_BASE + 0x44) // 2044 |
| +#define BN0_WF_AGG_TOP_ACR8_ADDR (BN0_WF_AGG_TOP_BASE + 0x4c) // 204C |
| +#define BN0_WF_AGG_TOP_MRCR_ADDR (BN0_WF_AGG_TOP_BASE + 0x50) // 2050 |
| +#define BN0_WF_AGG_TOP_MMPDR_ADDR (BN0_WF_AGG_TOP_BASE + 0x54) // 2054 |
| +#define BN0_WF_AGG_TOP_GFPDR_ADDR (BN0_WF_AGG_TOP_BASE + 0x58) // 2058 |
| +#define BN0_WF_AGG_TOP_VHTPDR_ADDR (BN0_WF_AGG_TOP_BASE + 0x5c) // 205C |
| +#define BN0_WF_AGG_TOP_HEPDR_ADDR (BN0_WF_AGG_TOP_BASE + 0x60) // 2060 |
| +#define BN0_WF_AGG_TOP_CTCR_ADDR (BN0_WF_AGG_TOP_BASE + 0x64) // 2064 |
| +#define BN0_WF_AGG_TOP_ATCR3_ADDR (BN0_WF_AGG_TOP_BASE + 0x68) // 2068 |
| +#define BN0_WF_AGG_TOP_SRCR_ADDR (BN0_WF_AGG_TOP_BASE + 0x6c) // 206C |
| +#define BN0_WF_AGG_TOP_VBCR_ADDR (BN0_WF_AGG_TOP_BASE + 0x70) // 2070 |
| +#define BN0_WF_AGG_TOP_TCR_ADDR (BN0_WF_AGG_TOP_BASE + 0x74) // 2074 |
| +#define BN0_WF_AGG_TOP_SRHS_ADDR (BN0_WF_AGG_TOP_BASE + 0x78) // 2078 |
| +#define BN0_WF_AGG_TOP_DBRCR0_ADDR (BN0_WF_AGG_TOP_BASE + 0x7c) // 207C |
| +#define BN0_WF_AGG_TOP_DBRCR1_ADDR (BN0_WF_AGG_TOP_BASE + 0x80) // 2080 |
| +#define BN0_WF_AGG_TOP_CTETCR_ADDR (BN0_WF_AGG_TOP_BASE + 0x84) // 2084 |
| +#define BN0_WF_AGG_TOP_WPDR_ADDR (BN0_WF_AGG_TOP_BASE + 0x88) // 2088 |
| +#define BN0_WF_AGG_TOP_PLRPDR_ADDR (BN0_WF_AGG_TOP_BASE + 0x8c) // 208C |
| +#define BN0_WF_AGG_TOP_CECR_ADDR (BN0_WF_AGG_TOP_BASE + 0x90) // 2090 |
| +#define BN0_WF_AGG_TOP_OMRCR0_ADDR (BN0_WF_AGG_TOP_BASE + 0x94) // 2094 |
| +#define BN0_WF_AGG_TOP_OMRCR1_ADDR (BN0_WF_AGG_TOP_BASE + 0x98) // 2098 |
| +#define BN0_WF_AGG_TOP_OMRCR2_ADDR (BN0_WF_AGG_TOP_BASE + 0x9c) // 209C |
| +#define BN0_WF_AGG_TOP_OMRCR3_ADDR (BN0_WF_AGG_TOP_BASE + 0xa0) // 20A0 |
| +#define BN0_WF_AGG_TOP_TMCR_ADDR (BN0_WF_AGG_TOP_BASE + 0xa4) // 20A4 |
| +#define BN0_WF_AGG_TOP_TWTCR_ADDR (BN0_WF_AGG_TOP_BASE + 0xa8) // 20A8 |
| +#define BN0_WF_AGG_TOP_TWTSTACR_ADDR (BN0_WF_AGG_TOP_BASE + 0xac) // 20AC |
| +#define BN0_WF_AGG_TOP_TWTE0TB_ADDR (BN0_WF_AGG_TOP_BASE + 0xb0) // 20B0 |
| +#define BN0_WF_AGG_TOP_TWTE1TB_ADDR (BN0_WF_AGG_TOP_BASE + 0xb4) // 20B4 |
| +#define BN0_WF_AGG_TOP_TWTE2TB_ADDR (BN0_WF_AGG_TOP_BASE + 0xb8) // 20B8 |
| +#define BN0_WF_AGG_TOP_TWTE3TB_ADDR (BN0_WF_AGG_TOP_BASE + 0xbc) // 20BC |
| +#define BN0_WF_AGG_TOP_TWTE4TB_ADDR (BN0_WF_AGG_TOP_BASE + 0xc0) // 20C0 |
| +#define BN0_WF_AGG_TOP_TWTE5TB_ADDR (BN0_WF_AGG_TOP_BASE + 0xc4) // 20C4 |
| +#define BN0_WF_AGG_TOP_TWTE6TB_ADDR (BN0_WF_AGG_TOP_BASE + 0xc8) // 20C8 |
| +#define BN0_WF_AGG_TOP_TWTE7TB_ADDR (BN0_WF_AGG_TOP_BASE + 0xcc) // 20CC |
| +#define BN0_WF_AGG_TOP_TWTE8TB_ADDR (BN0_WF_AGG_TOP_BASE + 0xd0) // 20D0 |
| +#define BN0_WF_AGG_TOP_TWTE9TB_ADDR (BN0_WF_AGG_TOP_BASE + 0xd4) // 20D4 |
| +#define BN0_WF_AGG_TOP_TWTEATB_ADDR (BN0_WF_AGG_TOP_BASE + 0xd8) // 20D8 |
| +#define BN0_WF_AGG_TOP_TWTEBTB_ADDR (BN0_WF_AGG_TOP_BASE + 0xdc) // 20DC |
| +#define BN0_WF_AGG_TOP_TWTECTB_ADDR (BN0_WF_AGG_TOP_BASE + 0xe0) // 20E0 |
| +#define BN0_WF_AGG_TOP_TWTEDTB_ADDR (BN0_WF_AGG_TOP_BASE + 0xe4) // 20E4 |
| +#define BN0_WF_AGG_TOP_TWTEETB_ADDR (BN0_WF_AGG_TOP_BASE + 0xe8) // 20E8 |
| +#define BN0_WF_AGG_TOP_TWTEFTB_ADDR (BN0_WF_AGG_TOP_BASE + 0xec) // 20EC |
| +#define BN0_WF_AGG_TOP_AALCR2_ADDR (BN0_WF_AGG_TOP_BASE + 0xf0) // 20F0 |
| +#define BN0_WF_AGG_TOP_AALCR3_ADDR (BN0_WF_AGG_TOP_BASE + 0xf4) // 20F4 |
| +#define BN0_WF_AGG_TOP_AALCR4_ADDR (BN0_WF_AGG_TOP_BASE + 0xf8) // 20F8 |
| +#define BN0_WF_AGG_TOP_AALCR5_ADDR (BN0_WF_AGG_TOP_BASE + 0xfc) // 20FC |
| +#define BN0_WF_AGG_TOP_AALCR6_ADDR (BN0_WF_AGG_TOP_BASE + 0x100) // 2100 |
| +#define BN0_WF_AGG_TOP_AALCR7_ADDR (BN0_WF_AGG_TOP_BASE + 0x104) // 2104 |
| +#define BN0_WF_AGG_TOP_ATCR0_ADDR (BN0_WF_AGG_TOP_BASE + 0x108) // 2108 |
| +#define BN0_WF_AGG_TOP_ATCR1_ADDR (BN0_WF_AGG_TOP_BASE + 0x10c) // 210C |
| +#define BN0_WF_AGG_TOP_TCCR_ADDR (BN0_WF_AGG_TOP_BASE + 0x110) // 2110 |
| +#define BN0_WF_AGG_TOP_TFCR_ADDR (BN0_WF_AGG_TOP_BASE + 0x114) // 2114 |
| +#define BN0_WF_AGG_TOP_MUCR0_ADDR (BN0_WF_AGG_TOP_BASE + 0x118) // 2118 |
| +#define BN0_WF_AGG_TOP_MUCR1_ADDR (BN0_WF_AGG_TOP_BASE + 0x11c) // 211C |
| +#define BN0_WF_AGG_TOP_CSDCR0_ADDR (BN0_WF_AGG_TOP_BASE + 0x120) // 2120 |
| +#define BN0_WF_AGG_TOP_CSDCR1_ADDR (BN0_WF_AGG_TOP_BASE + 0x124) // 2124 |
| +#define BN0_WF_AGG_TOP_CSDCR2_ADDR (BN0_WF_AGG_TOP_BASE + 0x128) // 2128 |
| +#define BN0_WF_AGG_TOP_CSDCR3_ADDR (BN0_WF_AGG_TOP_BASE + 0x12c) // 212C |
| +#define BN0_WF_AGG_TOP_CSDCR4_ADDR (BN0_WF_AGG_TOP_BASE + 0x130) // 2130 |
| +#define BN0_WF_AGG_TOP_DYNSCR_ADDR (BN0_WF_AGG_TOP_BASE + 0x178) // 2178 |
| +#define BN0_WF_AGG_TOP_DYNSSCR_ADDR (BN0_WF_AGG_TOP_BASE + 0x198) // 2198 |
| +#define BN0_WF_AGG_TOP_TCDCNT0_ADDR (BN0_WF_AGG_TOP_BASE + 0x2c8) // 22C8 |
| +#define BN0_WF_AGG_TOP_TCDCNT1_ADDR (BN0_WF_AGG_TOP_BASE + 0x2cc) // 22CC |
| +#define BN0_WF_AGG_TOP_TCSR0_ADDR (BN0_WF_AGG_TOP_BASE + 0x2d0) // 22D0 |
| +#define BN0_WF_AGG_TOP_TCSR1_ADDR (BN0_WF_AGG_TOP_BASE + 0x2d4) // 22D4 |
| +#define BN0_WF_AGG_TOP_TCSR2_ADDR (BN0_WF_AGG_TOP_BASE + 0x2d8) // 22D8 |
| +#define BN0_WF_AGG_TOP_DCR_ADDR (BN0_WF_AGG_TOP_BASE + 0x2e4) // 22E4 |
| +#define BN0_WF_AGG_TOP_SMDCR_ADDR (BN0_WF_AGG_TOP_BASE + 0x2e8) // 22E8 |
| +#define BN0_WF_AGG_TOP_TXCMDSMCR_ADDR (BN0_WF_AGG_TOP_BASE + 0x2ec) // 22EC |
| +#define BN0_WF_AGG_TOP_SMCR0_ADDR (BN0_WF_AGG_TOP_BASE + 0x2f0) // 22F0 |
| +#define BN0_WF_AGG_TOP_SMCR1_ADDR (BN0_WF_AGG_TOP_BASE + 0x2f4) // 22F4 |
| +#define BN0_WF_AGG_TOP_SMCR2_ADDR (BN0_WF_AGG_TOP_BASE + 0x2f8) // 22F8 |
| +#define BN0_WF_AGG_TOP_SMCR3_ADDR (BN0_WF_AGG_TOP_BASE + 0x2fc) // 22FC |
| + |
| +#define BN0_WF_AGG_TOP_AALCR0_AC01_AGG_LIMIT_ADDR BN0_WF_AGG_TOP_AALCR0_ADDR |
| +#define BN0_WF_AGG_TOP_AALCR0_AC01_AGG_LIMIT_MASK 0x03FF0000 // AC01_AGG_LIMIT[25..16] |
| +#define BN0_WF_AGG_TOP_AALCR0_AC01_AGG_LIMIT_SHFT 16 |
| +#define BN0_WF_AGG_TOP_AALCR0_AC00_AGG_LIMIT_ADDR BN0_WF_AGG_TOP_AALCR0_ADDR |
| +#define BN0_WF_AGG_TOP_AALCR0_AC00_AGG_LIMIT_MASK 0x000003FF // AC00_AGG_LIMIT[9..0] |
| +#define BN0_WF_AGG_TOP_AALCR0_AC00_AGG_LIMIT_SHFT 0 |
| + |
| +#define BN0_WF_AGG_TOP_AALCR1_AC03_AGG_LIMIT_ADDR BN0_WF_AGG_TOP_AALCR1_ADDR |
| +#define BN0_WF_AGG_TOP_AALCR1_AC03_AGG_LIMIT_MASK 0x03FF0000 // AC03_AGG_LIMIT[25..16] |
| +#define BN0_WF_AGG_TOP_AALCR1_AC03_AGG_LIMIT_SHFT 16 |
| +#define BN0_WF_AGG_TOP_AALCR1_AC02_AGG_LIMIT_ADDR BN0_WF_AGG_TOP_AALCR1_ADDR |
| +#define BN0_WF_AGG_TOP_AALCR1_AC02_AGG_LIMIT_MASK 0x000003FF // AC02_AGG_LIMIT[9..0] |
| +#define BN0_WF_AGG_TOP_AALCR1_AC02_AGG_LIMIT_SHFT 0 |
| + |
| +#define BN0_WF_AGG_TOP_AALCR2_AC11_AGG_LIMIT_ADDR BN0_WF_AGG_TOP_AALCR2_ADDR |
| +#define BN0_WF_AGG_TOP_AALCR2_AC11_AGG_LIMIT_MASK 0x03FF0000 // AC11_AGG_LIMIT[25..16] |
| +#define BN0_WF_AGG_TOP_AALCR2_AC11_AGG_LIMIT_SHFT 16 |
| +#define BN0_WF_AGG_TOP_AALCR2_AC10_AGG_LIMIT_ADDR BN0_WF_AGG_TOP_AALCR2_ADDR |
| +#define BN0_WF_AGG_TOP_AALCR2_AC10_AGG_LIMIT_MASK 0x000003FF // AC10_AGG_LIMIT[9..0] |
| +#define BN0_WF_AGG_TOP_AALCR2_AC10_AGG_LIMIT_SHFT 0 |
| + |
| +#define BN0_WF_AGG_TOP_AALCR3_AC13_AGG_LIMIT_ADDR BN0_WF_AGG_TOP_AALCR3_ADDR |
| +#define BN0_WF_AGG_TOP_AALCR3_AC13_AGG_LIMIT_MASK 0x03FF0000 // AC13_AGG_LIMIT[25..16] |
| +#define BN0_WF_AGG_TOP_AALCR3_AC13_AGG_LIMIT_SHFT 16 |
| +#define BN0_WF_AGG_TOP_AALCR3_AC12_AGG_LIMIT_ADDR BN0_WF_AGG_TOP_AALCR3_ADDR |
| +#define BN0_WF_AGG_TOP_AALCR3_AC12_AGG_LIMIT_MASK 0x000003FF // AC12_AGG_LIMIT[9..0] |
| +#define BN0_WF_AGG_TOP_AALCR3_AC12_AGG_LIMIT_SHFT 0 |
| + |
| +#define BN0_WF_AGG_TOP_AALCR4_AC21_AGG_LIMIT_ADDR BN0_WF_AGG_TOP_AALCR4_ADDR |
| +#define BN0_WF_AGG_TOP_AALCR4_AC21_AGG_LIMIT_MASK 0x03FF0000 // AC21_AGG_LIMIT[25..16] |
| +#define BN0_WF_AGG_TOP_AALCR4_AC21_AGG_LIMIT_SHFT 16 |
| +#define BN0_WF_AGG_TOP_AALCR4_AC20_AGG_LIMIT_ADDR BN0_WF_AGG_TOP_AALCR4_ADDR |
| +#define BN0_WF_AGG_TOP_AALCR4_AC20_AGG_LIMIT_MASK 0x000003FF // AC20_AGG_LIMIT[9..0] |
| +#define BN0_WF_AGG_TOP_AALCR4_AC20_AGG_LIMIT_SHFT 0 |
| + |
| +#define BN0_WF_AGG_TOP_AALCR5_AC23_AGG_LIMIT_ADDR BN0_WF_AGG_TOP_AALCR5_ADDR |
| +#define BN0_WF_AGG_TOP_AALCR5_AC23_AGG_LIMIT_MASK 0x03FF0000 // AC23_AGG_LIMIT[25..16] |
| +#define BN0_WF_AGG_TOP_AALCR5_AC23_AGG_LIMIT_SHFT 16 |
| +#define BN0_WF_AGG_TOP_AALCR5_AC22_AGG_LIMIT_ADDR BN0_WF_AGG_TOP_AALCR5_ADDR |
| +#define BN0_WF_AGG_TOP_AALCR5_AC22_AGG_LIMIT_MASK 0x000003FF // AC22_AGG_LIMIT[9..0] |
| +#define BN0_WF_AGG_TOP_AALCR5_AC22_AGG_LIMIT_SHFT 0 |
| + |
| +#define BN0_WF_AGG_TOP_AALCR6_AC31_AGG_LIMIT_ADDR BN0_WF_AGG_TOP_AALCR6_ADDR |
| +#define BN0_WF_AGG_TOP_AALCR6_AC31_AGG_LIMIT_MASK 0x03FF0000 // AC31_AGG_LIMIT[25..16] |
| +#define BN0_WF_AGG_TOP_AALCR6_AC31_AGG_LIMIT_SHFT 16 |
| +#define BN0_WF_AGG_TOP_AALCR6_AC30_AGG_LIMIT_ADDR BN0_WF_AGG_TOP_AALCR6_ADDR |
| +#define BN0_WF_AGG_TOP_AALCR6_AC30_AGG_LIMIT_MASK 0x000003FF // AC30_AGG_LIMIT[9..0] |
| +#define BN0_WF_AGG_TOP_AALCR6_AC30_AGG_LIMIT_SHFT 0 |
| +#define BN0_WF_AGG_TOP_AALCR7_AC33_AGG_LIMIT_ADDR BN0_WF_AGG_TOP_AALCR7_ADDR |
| +#define BN0_WF_AGG_TOP_AALCR7_AC33_AGG_LIMIT_MASK 0x03FF0000 // AC33_AGG_LIMIT[25..16] |
| +#define BN0_WF_AGG_TOP_AALCR7_AC33_AGG_LIMIT_SHFT 16 |
| +#define BN0_WF_AGG_TOP_AALCR7_AC32_AGG_LIMIT_ADDR BN0_WF_AGG_TOP_AALCR7_ADDR |
| +#define BN0_WF_AGG_TOP_AALCR7_AC32_AGG_LIMIT_MASK 0x000003FF // AC32_AGG_LIMIT[9..0] |
| +#define BN0_WF_AGG_TOP_AALCR7_AC32_AGG_LIMIT_SHFT 0 |
| + |
| +/* MIB */ |
| +#define BN0_WF_MIB_TOP_TRARC0_ADDR (BN0_WF_MIB_TOP_BASE + 0x0B0) // D0B0 |
| +#define BN0_WF_MIB_TOP_TRARC1_ADDR (BN0_WF_MIB_TOP_BASE + 0x0B4) // D0B4 |
| +#define BN0_WF_MIB_TOP_TRARC2_ADDR (BN0_WF_MIB_TOP_BASE + 0x0B8) // D0B8 |
| +#define BN0_WF_MIB_TOP_TRARC3_ADDR (BN0_WF_MIB_TOP_BASE + 0x0BC) // D0BC |
| +#define BN0_WF_MIB_TOP_TRARC4_ADDR (BN0_WF_MIB_TOP_BASE + 0x0C0) // D0C0 |
| +#define BN0_WF_MIB_TOP_TRARC5_ADDR (BN0_WF_MIB_TOP_BASE + 0x0C4) // D0C4 |
| +#define BN0_WF_MIB_TOP_TRARC6_ADDR (BN0_WF_MIB_TOP_BASE + 0x0C8) // D0C8 |
| +#define BN0_WF_MIB_TOP_TRARC7_ADDR (BN0_WF_MIB_TOP_BASE + 0x0CC) // D0CC |
| + |
| +#define BN0_WF_MIB_TOP_TRDR0_ADDR (BN0_WF_MIB_TOP_BASE + 0x9B4) // D9B4 |
| +#define BN0_WF_MIB_TOP_TRDR1_ADDR (BN0_WF_MIB_TOP_BASE + 0x9B8) // D9B8 |
| +#define BN0_WF_MIB_TOP_TRDR2_ADDR (BN0_WF_MIB_TOP_BASE + 0x9BC) // D9BC |
| +#define BN0_WF_MIB_TOP_TRDR3_ADDR (BN0_WF_MIB_TOP_BASE + 0x9C0) // D9C0 |
| +#define BN0_WF_MIB_TOP_TRDR4_ADDR (BN0_WF_MIB_TOP_BASE + 0x9C4) // D9C4 |
| +#define BN0_WF_MIB_TOP_TRDR5_ADDR (BN0_WF_MIB_TOP_BASE + 0x9C8) // D9C8 |
| +#define BN0_WF_MIB_TOP_TRDR6_ADDR (BN0_WF_MIB_TOP_BASE + 0x9CC) // D9CC |
| +#define BN0_WF_MIB_TOP_TRDR7_ADDR (BN0_WF_MIB_TOP_BASE + 0x9D0) // D9D0 |
| +#define BN0_WF_MIB_TOP_TRDR8_ADDR (BN0_WF_MIB_TOP_BASE + 0x9D4) // D9D4 |
| +#define BN0_WF_MIB_TOP_TRDR9_ADDR (BN0_WF_MIB_TOP_BASE + 0x9D8) // D9D8 |
| +#define BN0_WF_MIB_TOP_TRDR10_ADDR (BN0_WF_MIB_TOP_BASE + 0x9DC) // D9DC |
| +#define BN0_WF_MIB_TOP_TRDR11_ADDR (BN0_WF_MIB_TOP_BASE + 0x9E0) // D9E0 |
| +#define BN0_WF_MIB_TOP_TRDR12_ADDR (BN0_WF_MIB_TOP_BASE + 0x9E4) // D9E4 |
| +#define BN0_WF_MIB_TOP_TRDR13_ADDR (BN0_WF_MIB_TOP_BASE + 0x9E8) // D9E8 |
| +#define BN0_WF_MIB_TOP_TRDR14_ADDR (BN0_WF_MIB_TOP_BASE + 0x9EC) // D9EC |
| +#define BN0_WF_MIB_TOP_TRDR15_ADDR (BN0_WF_MIB_TOP_BASE + 0x9F0) // D9F0 |
| + |
| +#define BN0_WF_MIB_TOP_TRARC0_AGG_RANG_SEL_1_ADDR BN0_WF_MIB_TOP_TRARC0_ADDR |
| +#define BN0_WF_MIB_TOP_TRARC0_AGG_RANG_SEL_1_MASK 0x03FF0000 // AGG_RANG_SEL_1[25..16] |
| +#define BN0_WF_MIB_TOP_TRARC0_AGG_RANG_SEL_1_SHFT 16 |
| +#define BN0_WF_MIB_TOP_TRARC0_AGG_RANG_SEL_0_ADDR BN0_WF_MIB_TOP_TRARC0_ADDR |
| +#define BN0_WF_MIB_TOP_TRARC0_AGG_RANG_SEL_0_MASK 0x000003FF // AGG_RANG_SEL_0[9..0] |
| +#define BN0_WF_MIB_TOP_TRARC0_AGG_RANG_SEL_0_SHFT 0 |
| + |
| +#define BN0_WF_MIB_TOP_TRARC1_AGG_RANG_SEL_3_ADDR BN0_WF_MIB_TOP_TRARC1_ADDR |
| +#define BN0_WF_MIB_TOP_TRARC1_AGG_RANG_SEL_3_MASK 0x03FF0000 // AGG_RANG_SEL_3[25..16] |
| +#define BN0_WF_MIB_TOP_TRARC1_AGG_RANG_SEL_3_SHFT 16 |
| +#define BN0_WF_MIB_TOP_TRARC1_AGG_RANG_SEL_2_ADDR BN0_WF_MIB_TOP_TRARC1_ADDR |
| +#define BN0_WF_MIB_TOP_TRARC1_AGG_RANG_SEL_2_MASK 0x000003FF // AGG_RANG_SEL_2[9..0] |
| +#define BN0_WF_MIB_TOP_TRARC1_AGG_RANG_SEL_2_SHFT 0 |
| + |
| +#define BN0_WF_MIB_TOP_TRARC2_AGG_RANG_SEL_5_ADDR BN0_WF_MIB_TOP_TRARC2_ADDR |
| +#define BN0_WF_MIB_TOP_TRARC2_AGG_RANG_SEL_5_MASK 0x03FF0000 // AGG_RANG_SEL_5[25..16] |
| +#define BN0_WF_MIB_TOP_TRARC2_AGG_RANG_SEL_5_SHFT 16 |
| +#define BN0_WF_MIB_TOP_TRARC2_AGG_RANG_SEL_4_ADDR BN0_WF_MIB_TOP_TRARC2_ADDR |
| +#define BN0_WF_MIB_TOP_TRARC2_AGG_RANG_SEL_4_MASK 0x000003FF // AGG_RANG_SEL_4[9..0] |
| +#define BN0_WF_MIB_TOP_TRARC2_AGG_RANG_SEL_4_SHFT 0 |
| + |
| +#define BN0_WF_MIB_TOP_TRARC3_AGG_RANG_SEL_7_ADDR BN0_WF_MIB_TOP_TRARC3_ADDR |
| +#define BN0_WF_MIB_TOP_TRARC3_AGG_RANG_SEL_7_MASK 0x03FF0000 // AGG_RANG_SEL_7[25..16] |
| +#define BN0_WF_MIB_TOP_TRARC3_AGG_RANG_SEL_7_SHFT 16 |
| +#define BN0_WF_MIB_TOP_TRARC3_AGG_RANG_SEL_6_ADDR BN0_WF_MIB_TOP_TRARC3_ADDR |
| +#define BN0_WF_MIB_TOP_TRARC3_AGG_RANG_SEL_6_MASK 0x000003FF // AGG_RANG_SEL_6[9..0] |
| +#define BN0_WF_MIB_TOP_TRARC3_AGG_RANG_SEL_6_SHFT 0 |
| + |
| +#define BN0_WF_MIB_TOP_TRARC4_AGG_RANG_SEL_9_ADDR BN0_WF_MIB_TOP_TRARC4_ADDR |
| +#define BN0_WF_MIB_TOP_TRARC4_AGG_RANG_SEL_9_MASK 0x03FF0000 // AGG_RANG_SEL_9[25..16] |
| +#define BN0_WF_MIB_TOP_TRARC4_AGG_RANG_SEL_9_SHFT 16 |
| +#define BN0_WF_MIB_TOP_TRARC4_AGG_RANG_SEL_8_ADDR BN0_WF_MIB_TOP_TRARC4_ADDR |
| +#define BN0_WF_MIB_TOP_TRARC4_AGG_RANG_SEL_8_MASK 0x000003FF // AGG_RANG_SEL_8[9..0] |
| +#define BN0_WF_MIB_TOP_TRARC4_AGG_RANG_SEL_8_SHFT 0 |
| + |
| +#define BN0_WF_MIB_TOP_TRARC5_AGG_RANG_SEL_11_ADDR BN0_WF_MIB_TOP_TRARC5_ADDR |
| +#define BN0_WF_MIB_TOP_TRARC5_AGG_RANG_SEL_11_MASK 0x03FF0000 // AGG_RANG_SEL_11[25..16] |
| +#define BN0_WF_MIB_TOP_TRARC5_AGG_RANG_SEL_11_SHFT 16 |
| +#define BN0_WF_MIB_TOP_TRARC5_AGG_RANG_SEL_10_ADDR BN0_WF_MIB_TOP_TRARC5_ADDR |
| +#define BN0_WF_MIB_TOP_TRARC5_AGG_RANG_SEL_10_MASK 0x000003FF // AGG_RANG_SEL_10[9..0] |
| +#define BN0_WF_MIB_TOP_TRARC5_AGG_RANG_SEL_10_SHFT 0 |
| + |
| +#define BN0_WF_MIB_TOP_TRARC6_AGG_RANG_SEL_13_ADDR BN0_WF_MIB_TOP_TRARC6_ADDR |
| +#define BN0_WF_MIB_TOP_TRARC6_AGG_RANG_SEL_13_MASK 0x03FF0000 // AGG_RANG_SEL_13[25..16] |
| +#define BN0_WF_MIB_TOP_TRARC6_AGG_RANG_SEL_13_SHFT 16 |
| +#define BN0_WF_MIB_TOP_TRARC6_AGG_RANG_SEL_12_ADDR BN0_WF_MIB_TOP_TRARC6_ADDR |
| +#define BN0_WF_MIB_TOP_TRARC6_AGG_RANG_SEL_12_MASK 0x000003FF // AGG_RANG_SEL_12[9..0] |
| +#define BN0_WF_MIB_TOP_TRARC6_AGG_RANG_SEL_12_SHFT 0 |
| + |
| +#define BN0_WF_MIB_TOP_TRARC7_AGG_RANG_SEL_14_ADDR BN0_WF_MIB_TOP_TRARC7_ADDR |
| +#define BN0_WF_MIB_TOP_TRARC7_AGG_RANG_SEL_14_MASK 0x000003FF // AGG_RANG_SEL_14[9..0] |
| +#define BN0_WF_MIB_TOP_TRARC7_AGG_RANG_SEL_14_SHFT 0 |
| + |
| +/* RXD */ |
| +enum { |
| + BMAC_GROUP_VLD_1 = 0x01, |
| + BMAC_GROUP_VLD_2 = 0x02, |
| + BMAC_GROUP_VLD_3 = 0x04, |
| + BMAC_GROUP_VLD_4 = 0x08, |
| + BMAC_GROUP_VLD_5 = 0x10, |
| +}; |
| + |
| +// DW0 |
| +#define WF_RX_DESCRIPTOR_RX_BYTE_COUNT_DW 0 |
| +#define WF_RX_DESCRIPTOR_RX_BYTE_COUNT_ADDR 0 |
| +#define WF_RX_DESCRIPTOR_RX_BYTE_COUNT_MASK 0x0000ffff // 15- 0 |
| +#define WF_RX_DESCRIPTOR_RX_BYTE_COUNT_SHIFT 0 |
| +#define WF_RX_DESCRIPTOR_PACKET_TYPE_DW 0 |
| +#define WF_RX_DESCRIPTOR_PACKET_TYPE_ADDR 0 |
| +#define WF_RX_DESCRIPTOR_PACKET_TYPE_MASK 0xf8000000 // 31-27 |
| +#define WF_RX_DESCRIPTOR_PACKET_TYPE_SHIFT 27 |
| +// DW1 |
| +#define WF_RX_DESCRIPTOR_MLD_ID_DW 1 |
| +#define WF_RX_DESCRIPTOR_MLD_ID_ADDR 4 |
| +#define WF_RX_DESCRIPTOR_MLD_ID_MASK 0x00000fff // 11- 0 |
| +#define WF_RX_DESCRIPTOR_MLD_ID_SHIFT 0 |
| +#define WF_RX_DESCRIPTOR_GROUP_VLD_DW 1 |
| +#define WF_RX_DESCRIPTOR_GROUP_VLD_ADDR 4 |
| +#define WF_RX_DESCRIPTOR_GROUP_VLD_MASK 0x001f0000 // 20-16 |
| +#define WF_RX_DESCRIPTOR_GROUP_VLD_SHIFT 16 |
| +#define WF_RX_DESCRIPTOR_KID_DW 1 |
| +#define WF_RX_DESCRIPTOR_KID_ADDR 4 |
| +#define WF_RX_DESCRIPTOR_KID_MASK 0x00600000 // 22-21 |
| +#define WF_RX_DESCRIPTOR_KID_SHIFT 21 |
| +#define WF_RX_DESCRIPTOR_CM_DW 1 |
| +#define WF_RX_DESCRIPTOR_CM_ADDR 4 |
| +#define WF_RX_DESCRIPTOR_CM_MASK 0x00800000 // 23-23 |
| +#define WF_RX_DESCRIPTOR_CM_SHIFT 23 |
| +#define WF_RX_DESCRIPTOR_CLM_DW 1 |
| +#define WF_RX_DESCRIPTOR_CLM_ADDR 4 |
| +#define WF_RX_DESCRIPTOR_CLM_MASK 0x01000000 // 24-24 |
| +#define WF_RX_DESCRIPTOR_CLM_SHIFT 24 |
| +#define WF_RX_DESCRIPTOR_I_DW 1 |
| +#define WF_RX_DESCRIPTOR_I_ADDR 4 |
| +#define WF_RX_DESCRIPTOR_I_MASK 0x02000000 // 25-25 |
| +#define WF_RX_DESCRIPTOR_I_SHIFT 25 |
| +#define WF_RX_DESCRIPTOR_T_DW 1 |
| +#define WF_RX_DESCRIPTOR_T_ADDR 4 |
| +#define WF_RX_DESCRIPTOR_T_MASK 0x04000000 // 26-26 |
| +#define WF_RX_DESCRIPTOR_T_SHIFT 26 |
| +#define WF_RX_DESCRIPTOR_BN_DW 1 |
| +#define WF_RX_DESCRIPTOR_BN_ADDR 4 |
| +#define WF_RX_DESCRIPTOR_BN_MASK 0x18000000 // 28-27 |
| +#define WF_RX_DESCRIPTOR_BN_SHIFT 27 |
| +#define WF_RX_DESCRIPTOR_BIPN_FAIL_DW 1 |
| +#define WF_RX_DESCRIPTOR_BIPN_FAIL_ADDR 4 |
| +#define WF_RX_DESCRIPTOR_BIPN_FAIL_MASK 0x20000000 // 29-29 |
| +#define WF_RX_DESCRIPTOR_BIPN_FAIL_SHIFT 29 |
| +// DW2 |
| +#define WF_RX_DESCRIPTOR_BSSID_DW 2 |
| +#define WF_RX_DESCRIPTOR_BSSID_ADDR 8 |
| +#define WF_RX_DESCRIPTOR_BSSID_MASK 0x0000003f // 5- 0 |
| +#define WF_RX_DESCRIPTOR_BSSID_SHIFT 0 |
| +#define WF_RX_DESCRIPTOR_H_DW 2 |
| +#define WF_RX_DESCRIPTOR_H_ADDR 8 |
| +#define WF_RX_DESCRIPTOR_H_MASK 0x00000080 // 7- 7 |
| +#define WF_RX_DESCRIPTOR_H_SHIFT 7 |
| +#define WF_RX_DESCRIPTOR_HEADER_LENGTH_DW 2 |
| +#define WF_RX_DESCRIPTOR_HEADER_LENGTH_ADDR 8 |
| +#define WF_RX_DESCRIPTOR_HEADER_LENGTH_MASK 0x00001f00 // 12- 8 |
| +#define WF_RX_DESCRIPTOR_HEADER_LENGTH_SHIFT 8 |
| +#define WF_RX_DESCRIPTOR_HO_DW 2 |
| +#define WF_RX_DESCRIPTOR_HO_ADDR 8 |
| +#define WF_RX_DESCRIPTOR_HO_MASK 0x0000e000 // 15-13 |
| +#define WF_RX_DESCRIPTOR_HO_SHIFT 13 |
| +#define WF_RX_DESCRIPTOR_SEC_MODE_DW 2 |
| +#define WF_RX_DESCRIPTOR_SEC_MODE_ADDR 8 |
| +#define WF_RX_DESCRIPTOR_SEC_MODE_MASK 0x001f0000 // 20-16 |
| +#define WF_RX_DESCRIPTOR_SEC_MODE_SHIFT 16 |
| +#define WF_RX_DESCRIPTOR_MUBAR_DW 2 |
| +#define WF_RX_DESCRIPTOR_MUBAR_ADDR 8 |
| +#define WF_RX_DESCRIPTOR_MUBAR_MASK 0x00200000 // 21-21 |
| +#define WF_RX_DESCRIPTOR_MUBAR_SHIFT 21 |
| +#define WF_RX_DESCRIPTOR_SWBIT_DW 2 |
| +#define WF_RX_DESCRIPTOR_SWBIT_ADDR 8 |
| +#define WF_RX_DESCRIPTOR_SWBIT_MASK 0x00400000 // 22-22 |
| +#define WF_RX_DESCRIPTOR_SWBIT_SHIFT 22 |
| +#define WF_RX_DESCRIPTOR_DAF_DW 2 |
| +#define WF_RX_DESCRIPTOR_DAF_ADDR 8 |
| +#define WF_RX_DESCRIPTOR_DAF_MASK 0x00800000 // 23-23 |
| +#define WF_RX_DESCRIPTOR_DAF_SHIFT 23 |
| +#define WF_RX_DESCRIPTOR_EL_DW 2 |
| +#define WF_RX_DESCRIPTOR_EL_ADDR 8 |
| +#define WF_RX_DESCRIPTOR_EL_MASK 0x01000000 // 24-24 |
| +#define WF_RX_DESCRIPTOR_EL_SHIFT 24 |
| +#define WF_RX_DESCRIPTOR_HTF_DW 2 |
| +#define WF_RX_DESCRIPTOR_HTF_ADDR 8 |
| +#define WF_RX_DESCRIPTOR_HTF_MASK 0x02000000 // 25-25 |
| +#define WF_RX_DESCRIPTOR_HTF_SHIFT 25 |
| +#define WF_RX_DESCRIPTOR_INTF_DW 2 |
| +#define WF_RX_DESCRIPTOR_INTF_ADDR 8 |
| +#define WF_RX_DESCRIPTOR_INTF_MASK 0x04000000 // 26-26 |
| +#define WF_RX_DESCRIPTOR_INTF_SHIFT 26 |
| +#define WF_RX_DESCRIPTOR_FRAG_DW 2 |
| +#define WF_RX_DESCRIPTOR_FRAG_ADDR 8 |
| +#define WF_RX_DESCRIPTOR_FRAG_MASK 0x08000000 // 27-27 |
| +#define WF_RX_DESCRIPTOR_FRAG_SHIFT 27 |
| +#define WF_RX_DESCRIPTOR_NUL_DW 2 |
| +#define WF_RX_DESCRIPTOR_NUL_ADDR 8 |
| +#define WF_RX_DESCRIPTOR_NUL_MASK 0x10000000 // 28-28 |
| +#define WF_RX_DESCRIPTOR_NUL_SHIFT 28 |
| +#define WF_RX_DESCRIPTOR_NDATA_DW 2 |
| +#define WF_RX_DESCRIPTOR_NDATA_ADDR 8 |
| +#define WF_RX_DESCRIPTOR_NDATA_MASK 0x20000000 // 29-29 |
| +#define WF_RX_DESCRIPTOR_NDATA_SHIFT 29 |
| +#define WF_RX_DESCRIPTOR_NAMP_DW 2 |
| +#define WF_RX_DESCRIPTOR_NAMP_ADDR 8 |
| +#define WF_RX_DESCRIPTOR_NAMP_MASK 0x40000000 // 30-30 |
| +#define WF_RX_DESCRIPTOR_NAMP_SHIFT 30 |
| +#define WF_RX_DESCRIPTOR_BF_RPT_DW 2 |
| +#define WF_RX_DESCRIPTOR_BF_RPT_ADDR 8 |
| +#define WF_RX_DESCRIPTOR_BF_RPT_MASK 0x80000000 // 31-31 |
| +#define WF_RX_DESCRIPTOR_BF_RPT_SHIFT 31 |
| +// DW3 |
| +#define WF_RX_DESCRIPTOR_RXV_SN_DW 3 |
| +#define WF_RX_DESCRIPTOR_RXV_SN_ADDR 12 |
| +#define WF_RX_DESCRIPTOR_RXV_SN_MASK 0x000000ff // 7- 0 |
| +#define WF_RX_DESCRIPTOR_RXV_SN_SHIFT 0 |
| +#define WF_RX_DESCRIPTOR_CH_FREQUENCY_DW 3 |
| +#define WF_RX_DESCRIPTOR_CH_FREQUENCY_ADDR 12 |
| +#define WF_RX_DESCRIPTOR_CH_FREQUENCY_MASK 0x0000ff00 // 15- 8 |
| +#define WF_RX_DESCRIPTOR_CH_FREQUENCY_SHIFT 8 |
| +#define WF_RX_DESCRIPTOR_A1_TYPE_DW 3 |
| +#define WF_RX_DESCRIPTOR_A1_TYPE_ADDR 12 |
| +#define WF_RX_DESCRIPTOR_A1_TYPE_MASK 0x00030000 // 17-16 |
| +#define WF_RX_DESCRIPTOR_A1_TYPE_SHIFT 16 |
| +#define WF_RX_DESCRIPTOR_HTC_DW 3 |
| +#define WF_RX_DESCRIPTOR_HTC_ADDR 12 |
| +#define WF_RX_DESCRIPTOR_HTC_MASK 0x00040000 // 18-18 |
| +#define WF_RX_DESCRIPTOR_HTC_SHIFT 18 |
| +#define WF_RX_DESCRIPTOR_TCL_DW 3 |
| +#define WF_RX_DESCRIPTOR_TCL_ADDR 12 |
| +#define WF_RX_DESCRIPTOR_TCL_MASK 0x00080000 // 19-19 |
| +#define WF_RX_DESCRIPTOR_TCL_SHIFT 19 |
| +#define WF_RX_DESCRIPTOR_BBM_DW 3 |
| +#define WF_RX_DESCRIPTOR_BBM_ADDR 12 |
| +#define WF_RX_DESCRIPTOR_BBM_MASK 0x00100000 // 20-20 |
| +#define WF_RX_DESCRIPTOR_BBM_SHIFT 20 |
| +#define WF_RX_DESCRIPTOR_BU_DW 3 |
| +#define WF_RX_DESCRIPTOR_BU_ADDR 12 |
| +#define WF_RX_DESCRIPTOR_BU_MASK 0x00200000 // 21-21 |
| +#define WF_RX_DESCRIPTOR_BU_SHIFT 21 |
| +#define WF_RX_DESCRIPTOR_CO_ANT_DW 3 |
| +#define WF_RX_DESCRIPTOR_CO_ANT_ADDR 12 |
| +#define WF_RX_DESCRIPTOR_CO_ANT_MASK 0x00400000 // 22-22 |
| +#define WF_RX_DESCRIPTOR_CO_ANT_SHIFT 22 |
| +#define WF_RX_DESCRIPTOR_BF_CQI_DW 3 |
| +#define WF_RX_DESCRIPTOR_BF_CQI_ADDR 12 |
| +#define WF_RX_DESCRIPTOR_BF_CQI_MASK 0x00800000 // 23-23 |
| +#define WF_RX_DESCRIPTOR_BF_CQI_SHIFT 23 |
| +#define WF_RX_DESCRIPTOR_FC_DW 3 |
| +#define WF_RX_DESCRIPTOR_FC_ADDR 12 |
| +#define WF_RX_DESCRIPTOR_FC_MASK 0x01000000 // 24-24 |
| +#define WF_RX_DESCRIPTOR_FC_SHIFT 24 |
| +#define WF_RX_DESCRIPTOR_VLAN_DW 3 |
| +#define WF_RX_DESCRIPTOR_VLAN_ADDR 12 |
| +#define WF_RX_DESCRIPTOR_VLAN_MASK 0x80000000 // 31-31 |
| +#define WF_RX_DESCRIPTOR_VLAN_SHIFT 31 |
| +// DW4 |
| +#define WF_RX_DESCRIPTOR_PF_DW 4 |
| +#define WF_RX_DESCRIPTOR_PF_ADDR 16 |
| +#define WF_RX_DESCRIPTOR_PF_MASK 0x00000003 // 1- 0 |
| +#define WF_RX_DESCRIPTOR_PF_SHIFT 0 |
| +#define WF_RX_DESCRIPTOR_MAC_DW 4 |
| +#define WF_RX_DESCRIPTOR_MAC_ADDR 16 |
| +#define WF_RX_DESCRIPTOR_MAC_MASK 0x00000004 // 2- 2 |
| +#define WF_RX_DESCRIPTOR_MAC_SHIFT 2 |
| +#define WF_RX_DESCRIPTOR_TID_DW 4 |
| +#define WF_RX_DESCRIPTOR_TID_ADDR 16 |
| +#define WF_RX_DESCRIPTOR_TID_MASK 0x00000078 // 6- 3 |
| +#define WF_RX_DESCRIPTOR_TID_SHIFT 3 |
| +#define WF_RX_DESCRIPTOR_ETHER_TYPE_OFFSET_DW 4 |
| +#define WF_RX_DESCRIPTOR_ETHER_TYPE_OFFSET_ADDR 16 |
| +#define WF_RX_DESCRIPTOR_ETHER_TYPE_OFFSET_MASK 0x00003f80 // 13- 7 |
| +#define WF_RX_DESCRIPTOR_ETHER_TYPE_OFFSET_SHIFT 7 |
| +#define WF_RX_DESCRIPTOR_IP_DW 4 |
| +#define WF_RX_DESCRIPTOR_IP_ADDR 16 |
| +#define WF_RX_DESCRIPTOR_IP_MASK 0x00004000 // 14-14 |
| +#define WF_RX_DESCRIPTOR_IP_SHIFT 14 |
| +#define WF_RX_DESCRIPTOR_UT_DW 4 |
| +#define WF_RX_DESCRIPTOR_UT_ADDR 16 |
| +#define WF_RX_DESCRIPTOR_UT_MASK 0x00008000 // 15-15 |
| +#define WF_RX_DESCRIPTOR_UT_SHIFT 15 |
| +#define WF_RX_DESCRIPTOR_PSE_FID_DW 4 |
| +#define WF_RX_DESCRIPTOR_PSE_FID_ADDR 16 |
| +#define WF_RX_DESCRIPTOR_PSE_FID_MASK 0x0fff0000 // 27-16 |
| +#define WF_RX_DESCRIPTOR_PSE_FID_SHIFT 16 |
| +// DW5 |
| +// DW6 |
| +#define WF_RX_DESCRIPTOR_CLS_BITMAP_31_0__DW 6 |
| +#define WF_RX_DESCRIPTOR_CLS_BITMAP_31_0__ADDR 24 |
| +#define WF_RX_DESCRIPTOR_CLS_BITMAP_31_0__MASK 0xffffffff // 31- 0 |
| +#define WF_RX_DESCRIPTOR_CLS_BITMAP_31_0__SHIFT 0 |
| +// DW7 |
| +#define WF_RX_DESCRIPTOR_CLS_BITMAP_33_32__DW 7 |
| +#define WF_RX_DESCRIPTOR_CLS_BITMAP_33_32__ADDR 28 |
| +#define WF_RX_DESCRIPTOR_CLS_BITMAP_33_32__MASK 0x00000003 // 1- 0 |
| +#define WF_RX_DESCRIPTOR_CLS_BITMAP_33_32__SHIFT 0 |
| +#define WF_RX_DESCRIPTOR_DP_DW 7 |
| +#define WF_RX_DESCRIPTOR_DP_ADDR 28 |
| +#define WF_RX_DESCRIPTOR_DP_MASK 0x00080000 // 19-19 |
| +#define WF_RX_DESCRIPTOR_DP_SHIFT 19 |
| +#define WF_RX_DESCRIPTOR_CLS_DW 7 |
| +#define WF_RX_DESCRIPTOR_CLS_ADDR 28 |
| +#define WF_RX_DESCRIPTOR_CLS_MASK 0x00100000 // 20-20 |
| +#define WF_RX_DESCRIPTOR_CLS_SHIFT 20 |
| +#define WF_RX_DESCRIPTOR_OFLD_DW 7 |
| +#define WF_RX_DESCRIPTOR_OFLD_ADDR 28 |
| +#define WF_RX_DESCRIPTOR_OFLD_MASK 0x00600000 // 22-21 |
| +#define WF_RX_DESCRIPTOR_OFLD_SHIFT 21 |
| +#define WF_RX_DESCRIPTOR_MGC_DW 7 |
| +#define WF_RX_DESCRIPTOR_MGC_ADDR 28 |
| +#define WF_RX_DESCRIPTOR_MGC_MASK 0x00800000 // 23-23 |
| +#define WF_RX_DESCRIPTOR_MGC_SHIFT 23 |
| +#define WF_RX_DESCRIPTOR_WOL_DW 7 |
| +#define WF_RX_DESCRIPTOR_WOL_ADDR 28 |
| +#define WF_RX_DESCRIPTOR_WOL_MASK 0x1f000000 // 28-24 |
| +#define WF_RX_DESCRIPTOR_WOL_SHIFT 24 |
| +#define WF_RX_DESCRIPTOR_PF_MODE_DW 7 |
| +#define WF_RX_DESCRIPTOR_PF_MODE_ADDR 28 |
| +#define WF_RX_DESCRIPTOR_PF_MODE_MASK 0x20000000 // 29-29 |
| +#define WF_RX_DESCRIPTOR_PF_MODE_SHIFT 29 |
| +#define WF_RX_DESCRIPTOR_PF_STS_DW 7 |
| +#define WF_RX_DESCRIPTOR_PF_STS_ADDR 28 |
| +#define WF_RX_DESCRIPTOR_PF_STS_MASK 0xc0000000 // 31-30 |
| +#define WF_RX_DESCRIPTOR_PF_STS_SHIFT 30 |
| +// DW8 |
| +#define WF_RX_DESCRIPTOR_FRAME_CONTROL_FIELD_DW 8 |
| +#define WF_RX_DESCRIPTOR_FRAME_CONTROL_FIELD_ADDR 32 |
| +#define WF_RX_DESCRIPTOR_FRAME_CONTROL_FIELD_MASK 0x0000ffff // 15- 0 |
| +#define WF_RX_DESCRIPTOR_FRAME_CONTROL_FIELD_SHIFT 0 |
| +#define WF_RX_DESCRIPTOR_PEER_MLD_ADDRESS_15_0__DW 8 |
| +#define WF_RX_DESCRIPTOR_PEER_MLD_ADDRESS_15_0__ADDR 32 |
| +#define WF_RX_DESCRIPTOR_PEER_MLD_ADDRESS_15_0__MASK 0xffff0000 // 31-16 |
| +#define WF_RX_DESCRIPTOR_PEER_MLD_ADDRESS_15_0__SHIFT 16 |
| +// DW9 |
| +#define WF_RX_DESCRIPTOR_PEER_MLD_ADDRESS_47_16__DW 9 |
| +#define WF_RX_DESCRIPTOR_PEER_MLD_ADDRESS_47_16__ADDR 36 |
| +#define WF_RX_DESCRIPTOR_PEER_MLD_ADDRESS_47_16__MASK 0xffffffff // 31- 0 |
| +#define WF_RX_DESCRIPTOR_PEER_MLD_ADDRESS_47_16__SHIFT 0 |
| +// DW10 |
| +#define WF_RX_DESCRIPTOR_FRAGMENT_NUMBER_DW 10 |
| +#define WF_RX_DESCRIPTOR_FRAGMENT_NUMBER_ADDR 40 |
| +#define WF_RX_DESCRIPTOR_FRAGMENT_NUMBER_MASK 0x0000000f // 3- 0 |
| +#define WF_RX_DESCRIPTOR_FRAGMENT_NUMBER_SHIFT 0 |
| +#define WF_RX_DESCRIPTOR_SEQUENCE_NUMBER_DW 10 |
| +#define WF_RX_DESCRIPTOR_SEQUENCE_NUMBER_ADDR 40 |
| +#define WF_RX_DESCRIPTOR_SEQUENCE_NUMBER_MASK 0x0000fff0 // 15- 4 |
| +#define WF_RX_DESCRIPTOR_SEQUENCE_NUMBER_SHIFT 4 |
| +#define WF_RX_DESCRIPTOR_QOS_CONTROL_FIELD_DW 10 |
| +#define WF_RX_DESCRIPTOR_QOS_CONTROL_FIELD_ADDR 40 |
| +#define WF_RX_DESCRIPTOR_QOS_CONTROL_FIELD_MASK 0xffff0000 // 31-16 |
| +#define WF_RX_DESCRIPTOR_QOS_CONTROL_FIELD_SHIFT 16 |
| +// DW11 |
| +#define WF_RX_DESCRIPTOR_HT_CONTROL_FIELD_DW 11 |
| +#define WF_RX_DESCRIPTOR_HT_CONTROL_FIELD_ADDR 44 |
| +#define WF_RX_DESCRIPTOR_HT_CONTROL_FIELD_MASK 0xffffffff // 31- 0 |
| +#define WF_RX_DESCRIPTOR_HT_CONTROL_FIELD_SHIFT 0 |
| +// DW12 |
| +#define WF_RX_DESCRIPTOR_PN_31_0__DW 12 |
| +#define WF_RX_DESCRIPTOR_PN_31_0__ADDR 48 |
| +#define WF_RX_DESCRIPTOR_PN_31_0__MASK 0xffffffff // 31- 0 |
| +#define WF_RX_DESCRIPTOR_PN_31_0__SHIFT 0 |
| +// DW13 |
| +#define WF_RX_DESCRIPTOR_PN_63_32__DW 13 |
| +#define WF_RX_DESCRIPTOR_PN_63_32__ADDR 52 |
| +#define WF_RX_DESCRIPTOR_PN_63_32__MASK 0xffffffff // 31- 0 |
| +#define WF_RX_DESCRIPTOR_PN_63_32__SHIFT 0 |
| +// DW14 |
| +#define WF_RX_DESCRIPTOR_PN_95_64__DW 14 |
| +#define WF_RX_DESCRIPTOR_PN_95_64__ADDR 56 |
| +#define WF_RX_DESCRIPTOR_PN_95_64__MASK 0xffffffff // 31- 0 |
| +#define WF_RX_DESCRIPTOR_PN_95_64__SHIFT 0 |
| +// DW15 |
| +#define WF_RX_DESCRIPTOR_PN_127_96__DW 15 |
| +#define WF_RX_DESCRIPTOR_PN_127_96__ADDR 60 |
| +#define WF_RX_DESCRIPTOR_PN_127_96__MASK 0xffffffff // 31- 0 |
| +#define WF_RX_DESCRIPTOR_PN_127_96__SHIFT 0 |
| +// DW16 |
| +#define WF_RX_DESCRIPTOR_TIMESTAMP_DW 16 |
| +#define WF_RX_DESCRIPTOR_TIMESTAMP_ADDR 64 |
| +#define WF_RX_DESCRIPTOR_TIMESTAMP_MASK 0xffffffff // 31- 0 |
| +#define WF_RX_DESCRIPTOR_TIMESTAMP_SHIFT 0 |
| +// DW17 |
| +#define WF_RX_DESCRIPTOR_CRC_DW 17 |
| +#define WF_RX_DESCRIPTOR_CRC_ADDR 68 |
| +#define WF_RX_DESCRIPTOR_CRC_MASK 0xffffffff // 31- 0 |
| +#define WF_RX_DESCRIPTOR_CRC_SHIFT 0 |
| +// DW18 |
| +// DW19 |
| +// DW20 |
| +#define WF_RX_DESCRIPTOR_P_RXV_DW 20 |
| +#define WF_RX_DESCRIPTOR_P_RXV_ADDR 80 |
| +#define WF_RX_DESCRIPTOR_P_RXV_MASK 0xffffffff // 31- 0 |
| +#define WF_RX_DESCRIPTOR_P_RXV_SHIFT 0 |
| +// DW21 |
| +// DO NOT process repeat field(p_rxv) |
| +// DW22 |
| +#define WF_RX_DESCRIPTOR_DBW_DW 22 |
| +#define WF_RX_DESCRIPTOR_DBW_ADDR 88 |
| +#define WF_RX_DESCRIPTOR_DBW_MASK 0x00000007 // 2- 0 |
| +#define WF_RX_DESCRIPTOR_DBW_SHIFT 0 |
| +#define WF_RX_DESCRIPTOR_GI_DW 22 |
| +#define WF_RX_DESCRIPTOR_GI_ADDR 88 |
| +#define WF_RX_DESCRIPTOR_GI_MASK 0x00000018 // 4- 3 |
| +#define WF_RX_DESCRIPTOR_GI_SHIFT 3 |
| +#define WF_RX_DESCRIPTOR_DCM_DW 22 |
| +#define WF_RX_DESCRIPTOR_DCM_ADDR 88 |
| +#define WF_RX_DESCRIPTOR_DCM_MASK 0x00000020 // 5- 5 |
| +#define WF_RX_DESCRIPTOR_DCM_SHIFT 5 |
| +#define WF_RX_DESCRIPTOR_NUM_RX_DW 22 |
| +#define WF_RX_DESCRIPTOR_NUM_RX_ADDR 88 |
| +#define WF_RX_DESCRIPTOR_NUM_RX_MASK 0x000001c0 // 8- 6 |
| +#define WF_RX_DESCRIPTOR_NUM_RX_SHIFT 6 |
| +#define WF_RX_DESCRIPTOR_STBC_DW 22 |
| +#define WF_RX_DESCRIPTOR_STBC_ADDR 88 |
| +#define WF_RX_DESCRIPTOR_STBC_MASK 0x00000600 // 10- 9 |
| +#define WF_RX_DESCRIPTOR_STBC_SHIFT 9 |
| +#define WF_RX_DESCRIPTOR_TX_MODE_DW 22 |
| +#define WF_RX_DESCRIPTOR_TX_MODE_ADDR 88 |
| +#define WF_RX_DESCRIPTOR_TX_MODE_MASK 0x00007800 // 14-11 |
| +#define WF_RX_DESCRIPTOR_TX_MODE_SHIFT 11 |
| +// DW23 |
| +#define WF_RX_DESCRIPTOR_RCPI_DW 23 |
| +#define WF_RX_DESCRIPTOR_RCPI_ADDR 92 |
| +#define WF_RX_DESCRIPTOR_RCPI_MASK 0xffffffff // 31- 0 |
| +#define WF_RX_DESCRIPTOR_RCPI_SHIFT 0 |
| +// DW24 |
| +#define WF_RX_DESCRIPTOR_C_RXV_DW 24 |
| +#define WF_RX_DESCRIPTOR_C_RXV_ADDR 96 |
| +#define WF_RX_DESCRIPTOR_C_RXV_MASK 0xffffffff // 31- 0 |
| +#define WF_RX_DESCRIPTOR_C_RXV_SHIFT 0 |
| +// DW25 |
| +// DO NOT process repeat field(c_rxv) |
| +// DW26 |
| +// DO NOT process repeat field(c_rxv) |
| +// DW27 |
| +// DO NOT process repeat field(c_rxv) |
| +// DW28 |
| +// DO NOT process repeat field(c_rxv) |
| +// DW29 |
| +// DO NOT process repeat field(c_rxv) |
| +// DW30 |
| +// DO NOT process repeat field(c_rxv) |
| +// DW31 |
| +// DO NOT process repeat field(c_rxv) |
| +// DW32 |
| +// DO NOT process repeat field(c_rxv) |
| +// DW33 |
| +// DO NOT process repeat field(c_rxv) |
| +// DW34 |
| +// DO NOT process repeat field(c_rxv) |
| +// DW35 |
| +// DO NOT process repeat field(c_rxv) |
| +// DW36 |
| +// DO NOT process repeat field(c_rxv) |
| +// DW37 |
| +// DO NOT process repeat field(c_rxv) |
| +// DW38 |
| +// DO NOT process repeat field(c_rxv) |
| +// DW39 |
| +// DO NOT process repeat field(c_rxv) |
| +// DW40 |
| +// DO NOT process repeat field(c_rxv) |
| +// DW41 |
| +// DO NOT process repeat field(c_rxv) |
| +// DW42 |
| +// DO NOT process repeat field(c_rxv) |
| +// DW43 |
| +// DO NOT process repeat field(c_rxv) |
| +// DW44 |
| +// DO NOT process repeat field(c_rxv) |
| +// DW45 |
| +// DO NOT process repeat field(c_rxv) |
| +// DW46 |
| +// DW47 |
| + |
| +/* TXD */ |
| +// DW0 |
| +#define WF_TX_DESCRIPTOR_TX_BYTE_COUNT_DW 0 |
| +#define WF_TX_DESCRIPTOR_TX_BYTE_COUNT_ADDR 0 |
| +#define WF_TX_DESCRIPTOR_TX_BYTE_COUNT_MASK 0x0000ffff // 15- 0 |
| +#define WF_TX_DESCRIPTOR_TX_BYTE_COUNT_SHIFT 0 |
| +#define WF_TX_DESCRIPTOR_ETHER_TYPE_OFFSET_DW 0 |
| +#define WF_TX_DESCRIPTOR_ETHER_TYPE_OFFSET_ADDR 0 |
| +#define WF_TX_DESCRIPTOR_ETHER_TYPE_OFFSET_MASK 0x007f0000 // 22-16 |
| +#define WF_TX_DESCRIPTOR_ETHER_TYPE_OFFSET_SHIFT 16 |
| +#define WF_TX_DESCRIPTOR_PKT_FT_DW 0 |
| +#define WF_TX_DESCRIPTOR_PKT_FT_ADDR 0 |
| +#define WF_TX_DESCRIPTOR_PKT_FT_MASK 0x01800000 // 24-23 |
| +#define WF_TX_DESCRIPTOR_PKT_FT_SHIFT 23 |
| +#define WF_TX_DESCRIPTOR_Q_IDX_DW 0 |
| +#define WF_TX_DESCRIPTOR_Q_IDX_ADDR 0 |
| +#define WF_TX_DESCRIPTOR_Q_IDX_MASK 0xfe000000 // 31-25 |
| +#define WF_TX_DESCRIPTOR_Q_IDX_SHIFT 25 |
| +// DW1 |
| +#define WF_TX_DESCRIPTOR_MLD_ID_DW 1 |
| +#define WF_TX_DESCRIPTOR_MLD_ID_ADDR 4 |
| +#define WF_TX_DESCRIPTOR_MLD_ID_MASK 0x00000fff // 11- 0 |
| +#define WF_TX_DESCRIPTOR_MLD_ID_SHIFT 0 |
| +#define WF_TX_DESCRIPTOR_TGID_DW 1 |
| +#define WF_TX_DESCRIPTOR_TGID_ADDR 4 |
| +#define WF_TX_DESCRIPTOR_TGID_MASK 0x00003000 // 13-12 |
| +#define WF_TX_DESCRIPTOR_TGID_SHIFT 12 |
| +#define WF_TX_DESCRIPTOR_HF_DW 1 |
| +#define WF_TX_DESCRIPTOR_HF_ADDR 4 |
| +#define WF_TX_DESCRIPTOR_HF_MASK 0x0000c000 // 15-14 |
| +#define WF_TX_DESCRIPTOR_HF_SHIFT 14 |
| +#define WF_TX_DESCRIPTOR_HEADER_LENGTH_DW 1 |
| +#define WF_TX_DESCRIPTOR_HEADER_LENGTH_ADDR 4 |
| +#define WF_TX_DESCRIPTOR_HEADER_LENGTH_MASK 0x001f0000 // 20-16 |
| +#define WF_TX_DESCRIPTOR_HEADER_LENGTH_SHIFT 16 |
| +#define WF_TX_DESCRIPTOR_MRD_DW 1 |
| +#define WF_TX_DESCRIPTOR_MRD_ADDR 4 |
| +#define WF_TX_DESCRIPTOR_MRD_MASK 0x00010000 // 16-16 |
| +#define WF_TX_DESCRIPTOR_MRD_SHIFT 16 |
| +#define WF_TX_DESCRIPTOR_EOSP_DW 1 |
| +#define WF_TX_DESCRIPTOR_EOSP_ADDR 4 |
| +#define WF_TX_DESCRIPTOR_EOSP_MASK 0x00020000 // 17-17 |
| +#define WF_TX_DESCRIPTOR_EOSP_SHIFT 17 |
| +#define WF_TX_DESCRIPTOR_EOSP_DW 1 |
| +#define WF_TX_DESCRIPTOR_EOSP_ADDR 4 |
| +#define WF_TX_DESCRIPTOR_EOSP_MASK 0x00020000 // 17-17 |
| +#define WF_TX_DESCRIPTOR_EOSP_SHIFT 17 |
| +#define WF_TX_DESCRIPTOR_AMS_DW 1 |
| +#define WF_TX_DESCRIPTOR_AMS_ADDR 4 |
| +#define WF_TX_DESCRIPTOR_AMS_MASK 0x00040000 // 18-18 |
| +#define WF_TX_DESCRIPTOR_AMS_SHIFT 18 |
| +#define WF_TX_DESCRIPTOR_RMVL_DW 1 |
| +#define WF_TX_DESCRIPTOR_RMVL_ADDR 4 |
| +#define WF_TX_DESCRIPTOR_RMVL_MASK 0x00040000 // 18-18 |
| +#define WF_TX_DESCRIPTOR_RMVL_SHIFT 18 |
| +#define WF_TX_DESCRIPTOR_VLAN_DW 1 |
| +#define WF_TX_DESCRIPTOR_VLAN_ADDR 4 |
| +#define WF_TX_DESCRIPTOR_VLAN_MASK 0x00080000 // 19-19 |
| +#define WF_TX_DESCRIPTOR_VLAN_SHIFT 19 |
| +#define WF_TX_DESCRIPTOR_ETYP_DW 1 |
| +#define WF_TX_DESCRIPTOR_ETYP_ADDR 4 |
| +#define WF_TX_DESCRIPTOR_ETYP_MASK 0x00100000 // 20-20 |
| +#define WF_TX_DESCRIPTOR_ETYP_SHIFT 20 |
| +#define WF_TX_DESCRIPTOR_TID_MGMT_TYPE_DW 1 |
| +#define WF_TX_DESCRIPTOR_TID_MGMT_TYPE_ADDR 4 |
| +#define WF_TX_DESCRIPTOR_TID_MGMT_TYPE_MASK 0x01e00000 // 24-21 |
| +#define WF_TX_DESCRIPTOR_TID_MGMT_TYPE_SHIFT 21 |
| +#define WF_TX_DESCRIPTOR_OM_DW 1 |
| +#define WF_TX_DESCRIPTOR_OM_ADDR 4 |
| +#define WF_TX_DESCRIPTOR_OM_MASK 0x7e000000 // 30-25 |
| +#define WF_TX_DESCRIPTOR_OM_SHIFT 25 |
| +#define WF_TX_DESCRIPTOR_FR_DW 1 |
| +#define WF_TX_DESCRIPTOR_FR_ADDR 4 |
| +#define WF_TX_DESCRIPTOR_FR_MASK 0x80000000 // 31-31 |
| +#define WF_TX_DESCRIPTOR_FR_SHIFT 31 |
| +// DW2 |
| +#define WF_TX_DESCRIPTOR_SUBTYPE_DW 2 |
| +#define WF_TX_DESCRIPTOR_SUBTYPE_ADDR 8 |
| +#define WF_TX_DESCRIPTOR_SUBTYPE_MASK 0x0000000f // 3- 0 |
| +#define WF_TX_DESCRIPTOR_SUBTYPE_SHIFT 0 |
| +#define WF_TX_DESCRIPTOR_FTYPE_DW 2 |
| +#define WF_TX_DESCRIPTOR_FTYPE_ADDR 8 |
| +#define WF_TX_DESCRIPTOR_FTYPE_MASK 0x00000030 // 5- 4 |
| +#define WF_TX_DESCRIPTOR_FTYPE_SHIFT 4 |
| +#define WF_TX_DESCRIPTOR_BF_TYPE_DW 2 |
| +#define WF_TX_DESCRIPTOR_BF_TYPE_ADDR 8 |
| +#define WF_TX_DESCRIPTOR_BF_TYPE_MASK 0x000000c0 // 7- 6 |
| +#define WF_TX_DESCRIPTOR_BF_TYPE_SHIFT 6 |
| +#define WF_TX_DESCRIPTOR_OM_MAP_DW 2 |
| +#define WF_TX_DESCRIPTOR_OM_MAP_ADDR 8 |
| +#define WF_TX_DESCRIPTOR_OM_MAP_MASK 0x00000100 // 8- 8 |
| +#define WF_TX_DESCRIPTOR_OM_MAP_SHIFT 8 |
| +#define WF_TX_DESCRIPTOR_RTS_DW 2 |
| +#define WF_TX_DESCRIPTOR_RTS_ADDR 8 |
| +#define WF_TX_DESCRIPTOR_RTS_MASK 0x00000200 // 9- 9 |
| +#define WF_TX_DESCRIPTOR_RTS_SHIFT 9 |
| +#define WF_TX_DESCRIPTOR_HEADER_PADDING_DW 2 |
| +#define WF_TX_DESCRIPTOR_HEADER_PADDING_ADDR 8 |
| +#define WF_TX_DESCRIPTOR_HEADER_PADDING_MASK 0x00000c00 // 11-10 |
| +#define WF_TX_DESCRIPTOR_HEADER_PADDING_SHIFT 10 |
| +#define WF_TX_DESCRIPTOR_DU_DW 2 |
| +#define WF_TX_DESCRIPTOR_DU_ADDR 8 |
| +#define WF_TX_DESCRIPTOR_DU_MASK 0x00001000 // 12-12 |
| +#define WF_TX_DESCRIPTOR_DU_SHIFT 12 |
| +#define WF_TX_DESCRIPTOR_HE_DW 2 |
| +#define WF_TX_DESCRIPTOR_HE_ADDR 8 |
| +#define WF_TX_DESCRIPTOR_HE_MASK 0x00002000 // 13-13 |
| +#define WF_TX_DESCRIPTOR_HE_SHIFT 13 |
| +#define WF_TX_DESCRIPTOR_FRAG_DW 2 |
| +#define WF_TX_DESCRIPTOR_FRAG_ADDR 8 |
| +#define WF_TX_DESCRIPTOR_FRAG_MASK 0x0000c000 // 15-14 |
| +#define WF_TX_DESCRIPTOR_FRAG_SHIFT 14 |
| +#define WF_TX_DESCRIPTOR_REMAINING_TX_TIME_DW 2 |
| +#define WF_TX_DESCRIPTOR_REMAINING_TX_TIME_ADDR 8 |
| +#define WF_TX_DESCRIPTOR_REMAINING_TX_TIME_MASK 0x03ff0000 // 25-16 |
| +#define WF_TX_DESCRIPTOR_REMAINING_TX_TIME_SHIFT 16 |
| +#define WF_TX_DESCRIPTOR_POWER_OFFSET_DW 2 |
| +#define WF_TX_DESCRIPTOR_POWER_OFFSET_ADDR 8 |
| +#define WF_TX_DESCRIPTOR_POWER_OFFSET_MASK 0xfc000000 // 31-26 |
| +#define WF_TX_DESCRIPTOR_POWER_OFFSET_SHIFT 26 |
| +// DW3 |
| +#define WF_TX_DESCRIPTOR_NA_DW 3 |
| +#define WF_TX_DESCRIPTOR_NA_ADDR 12 |
| +#define WF_TX_DESCRIPTOR_NA_MASK 0x00000001 // 0- 0 |
| +#define WF_TX_DESCRIPTOR_NA_SHIFT 0 |
| +#define WF_TX_DESCRIPTOR_PF_DW 3 |
| +#define WF_TX_DESCRIPTOR_PF_ADDR 12 |
| +#define WF_TX_DESCRIPTOR_PF_MASK 0x00000002 // 1- 1 |
| +#define WF_TX_DESCRIPTOR_PF_SHIFT 1 |
| +#define WF_TX_DESCRIPTOR_EMRD_DW 3 |
| +#define WF_TX_DESCRIPTOR_EMRD_ADDR 12 |
| +#define WF_TX_DESCRIPTOR_EMRD_MASK 0x00000004 // 2- 2 |
| +#define WF_TX_DESCRIPTOR_EMRD_SHIFT 2 |
| +#define WF_TX_DESCRIPTOR_EEOSP_DW 3 |
| +#define WF_TX_DESCRIPTOR_EEOSP_ADDR 12 |
| +#define WF_TX_DESCRIPTOR_EEOSP_MASK 0x00000008 // 3- 3 |
| +#define WF_TX_DESCRIPTOR_EEOSP_SHIFT 3 |
| +#define WF_TX_DESCRIPTOR_BM_DW 3 |
| +#define WF_TX_DESCRIPTOR_BM_ADDR 12 |
| +#define WF_TX_DESCRIPTOR_BM_MASK 0x00000010 // 4- 4 |
| +#define WF_TX_DESCRIPTOR_BM_SHIFT 4 |
| +#define WF_TX_DESCRIPTOR_HW_AMSDU_CAP_DW 3 |
| +#define WF_TX_DESCRIPTOR_HW_AMSDU_CAP_ADDR 12 |
| +#define WF_TX_DESCRIPTOR_HW_AMSDU_CAP_MASK 0x00000020 // 5- 5 |
| +#define WF_TX_DESCRIPTOR_HW_AMSDU_CAP_SHIFT 5 |
| +#define WF_TX_DESCRIPTOR_TX_COUNT_DW 3 |
| +#define WF_TX_DESCRIPTOR_TX_COUNT_ADDR 12 |
| +#define WF_TX_DESCRIPTOR_TX_COUNT_MASK 0x000007c0 // 10- 6 |
| +#define WF_TX_DESCRIPTOR_TX_COUNT_SHIFT 6 |
| +#define WF_TX_DESCRIPTOR_REMAINING_TX_COUNT_DW 3 |
| +#define WF_TX_DESCRIPTOR_REMAINING_TX_COUNT_ADDR 12 |
| +#define WF_TX_DESCRIPTOR_REMAINING_TX_COUNT_MASK 0x0000f800 // 15-11 |
| +#define WF_TX_DESCRIPTOR_REMAINING_TX_COUNT_SHIFT 11 |
| +#define WF_TX_DESCRIPTOR_SN_DW 3 |
| +#define WF_TX_DESCRIPTOR_SN_ADDR 12 |
| +#define WF_TX_DESCRIPTOR_SN_MASK 0x0fff0000 // 27-16 |
| +#define WF_TX_DESCRIPTOR_SN_SHIFT 16 |
| +#define WF_TX_DESCRIPTOR_BA_DIS_DW 3 |
| +#define WF_TX_DESCRIPTOR_BA_DIS_ADDR 12 |
| +#define WF_TX_DESCRIPTOR_BA_DIS_MASK 0x10000000 // 28-28 |
| +#define WF_TX_DESCRIPTOR_BA_DIS_SHIFT 28 |
| +#define WF_TX_DESCRIPTOR_PM_DW 3 |
| +#define WF_TX_DESCRIPTOR_PM_ADDR 12 |
| +#define WF_TX_DESCRIPTOR_PM_MASK 0x20000000 // 29-29 |
| +#define WF_TX_DESCRIPTOR_PM_SHIFT 29 |
| +#define WF_TX_DESCRIPTOR_PN_VLD_DW 3 |
| +#define WF_TX_DESCRIPTOR_PN_VLD_ADDR 12 |
| +#define WF_TX_DESCRIPTOR_PN_VLD_MASK 0x40000000 // 30-30 |
| +#define WF_TX_DESCRIPTOR_PN_VLD_SHIFT 30 |
| +#define WF_TX_DESCRIPTOR_SN_VLD_DW 3 |
| +#define WF_TX_DESCRIPTOR_SN_VLD_ADDR 12 |
| +#define WF_TX_DESCRIPTOR_SN_VLD_MASK 0x80000000 // 31-31 |
| +#define WF_TX_DESCRIPTOR_SN_VLD_SHIFT 31 |
| +// DW4 |
| +#define WF_TX_DESCRIPTOR_PN_31_0__DW 4 |
| +#define WF_TX_DESCRIPTOR_PN_31_0__ADDR 16 |
| +#define WF_TX_DESCRIPTOR_PN_31_0__MASK 0xffffffff // 31- 0 |
| +#define WF_TX_DESCRIPTOR_PN_31_0__SHIFT 0 |
| +// DW5 |
| +#define WF_TX_DESCRIPTOR_PID_DW 5 |
| +#define WF_TX_DESCRIPTOR_PID_ADDR 20 |
| +#define WF_TX_DESCRIPTOR_PID_MASK 0x000000ff // 7- 0 |
| +#define WF_TX_DESCRIPTOR_PID_SHIFT 0 |
| +#define WF_TX_DESCRIPTOR_TXSFM_DW 5 |
| +#define WF_TX_DESCRIPTOR_TXSFM_ADDR 20 |
| +#define WF_TX_DESCRIPTOR_TXSFM_MASK 0x00000100 // 8- 8 |
| +#define WF_TX_DESCRIPTOR_TXSFM_SHIFT 8 |
| +#define WF_TX_DESCRIPTOR_TXS2M_DW 5 |
| +#define WF_TX_DESCRIPTOR_TXS2M_ADDR 20 |
| +#define WF_TX_DESCRIPTOR_TXS2M_MASK 0x00000200 // 9- 9 |
| +#define WF_TX_DESCRIPTOR_TXS2M_SHIFT 9 |
| +#define WF_TX_DESCRIPTOR_TXS2H_DW 5 |
| +#define WF_TX_DESCRIPTOR_TXS2H_ADDR 20 |
| +#define WF_TX_DESCRIPTOR_TXS2H_MASK 0x00000400 // 10-10 |
| +#define WF_TX_DESCRIPTOR_TXS2H_SHIFT 10 |
| +#define WF_TX_DESCRIPTOR_FBCZ_DW 5 |
| +#define WF_TX_DESCRIPTOR_FBCZ_ADDR 20 |
| +#define WF_TX_DESCRIPTOR_FBCZ_MASK 0x00001000 // 12-12 |
| +#define WF_TX_DESCRIPTOR_FBCZ_SHIFT 12 |
| +#define WF_TX_DESCRIPTOR_BYPASS_RBB_DW 5 |
| +#define WF_TX_DESCRIPTOR_BYPASS_RBB_ADDR 20 |
| +#define WF_TX_DESCRIPTOR_BYPASS_RBB_MASK 0x00002000 // 13-13 |
| +#define WF_TX_DESCRIPTOR_BYPASS_RBB_SHIFT 13 |
| +#define WF_TX_DESCRIPTOR_BYPASS_TBB_DW 5 |
| +#define WF_TX_DESCRIPTOR_BYPASS_TBB_ADDR 20 |
| +#define WF_TX_DESCRIPTOR_BYPASS_TBB_MASK 0x00004000 // 14-14 |
| +#define WF_TX_DESCRIPTOR_BYPASS_TBB_SHIFT 14 |
| +#define WF_TX_DESCRIPTOR_FL_DW 5 |
| +#define WF_TX_DESCRIPTOR_FL_ADDR 20 |
| +#define WF_TX_DESCRIPTOR_FL_MASK 0x00008000 // 15-15 |
| +#define WF_TX_DESCRIPTOR_FL_SHIFT 15 |
| +#define WF_TX_DESCRIPTOR_PN_47_32__DW 5 |
| +#define WF_TX_DESCRIPTOR_PN_47_32__ADDR 20 |
| +#define WF_TX_DESCRIPTOR_PN_47_32__MASK 0xffff0000 // 31-16 |
| +#define WF_TX_DESCRIPTOR_PN_47_32__SHIFT 16 |
| +// DW6 |
| +#define WF_TX_DESCRIPTOR_AMSDU_CAP_UTXB_DW 6 |
| +#define WF_TX_DESCRIPTOR_AMSDU_CAP_UTXB_ADDR 24 |
| +#define WF_TX_DESCRIPTOR_AMSDU_CAP_UTXB_MASK 0x00000002 // 1- 1 |
| +#define WF_TX_DESCRIPTOR_AMSDU_CAP_UTXB_SHIFT 1 |
| +#define WF_TX_DESCRIPTOR_DAS_DW 6 |
| +#define WF_TX_DESCRIPTOR_DAS_ADDR 24 |
| +#define WF_TX_DESCRIPTOR_DAS_MASK 0x00000004 // 2- 2 |
| +#define WF_TX_DESCRIPTOR_DAS_SHIFT 2 |
| +#define WF_TX_DESCRIPTOR_DIS_MAT_DW 6 |
| +#define WF_TX_DESCRIPTOR_DIS_MAT_ADDR 24 |
| +#define WF_TX_DESCRIPTOR_DIS_MAT_MASK 0x00000008 // 3- 3 |
| +#define WF_TX_DESCRIPTOR_DIS_MAT_SHIFT 3 |
| +#define WF_TX_DESCRIPTOR_MSDU_COUNT_DW 6 |
| +#define WF_TX_DESCRIPTOR_MSDU_COUNT_ADDR 24 |
| +#define WF_TX_DESCRIPTOR_MSDU_COUNT_MASK 0x000003f0 // 9- 4 |
| +#define WF_TX_DESCRIPTOR_MSDU_COUNT_SHIFT 4 |
| +#define WF_TX_DESCRIPTOR_TIMESTAMP_OFFSET_IDX_DW 6 |
| +#define WF_TX_DESCRIPTOR_TIMESTAMP_OFFSET_IDX_ADDR 24 |
| +#define WF_TX_DESCRIPTOR_TIMESTAMP_OFFSET_IDX_MASK 0x00007c00 // 14-10 |
| +#define WF_TX_DESCRIPTOR_TIMESTAMP_OFFSET_IDX_SHIFT 10 |
| +#define WF_TX_DESCRIPTOR_TIMESTAMP_OFFSET_EN_DW 6 |
| +#define WF_TX_DESCRIPTOR_TIMESTAMP_OFFSET_EN_ADDR 24 |
| +#define WF_TX_DESCRIPTOR_TIMESTAMP_OFFSET_EN_MASK 0x00008000 // 15-15 |
| +#define WF_TX_DESCRIPTOR_TIMESTAMP_OFFSET_EN_SHIFT 15 |
| +#define WF_TX_DESCRIPTOR_FIXED_RATE_IDX_DW 6 |
| +#define WF_TX_DESCRIPTOR_FIXED_RATE_IDX_ADDR 24 |
| +#define WF_TX_DESCRIPTOR_FIXED_RATE_IDX_MASK 0x003f0000 // 21-16 |
| +#define WF_TX_DESCRIPTOR_FIXED_RATE_IDX_SHIFT 16 |
| +#define WF_TX_DESCRIPTOR_BW_DW 6 |
| +#define WF_TX_DESCRIPTOR_BW_ADDR 24 |
| +#define WF_TX_DESCRIPTOR_BW_MASK 0x03c00000 // 25-22 |
| +#define WF_TX_DESCRIPTOR_BW_SHIFT 22 |
| +#define WF_TX_DESCRIPTOR_VTA_DW 6 |
| +#define WF_TX_DESCRIPTOR_VTA_ADDR 24 |
| +#define WF_TX_DESCRIPTOR_VTA_MASK 0x10000000 // 28-28 |
| +#define WF_TX_DESCRIPTOR_VTA_SHIFT 28 |
| +#define WF_TX_DESCRIPTOR_SRC_DW 6 |
| +#define WF_TX_DESCRIPTOR_SRC_ADDR 24 |
| +#define WF_TX_DESCRIPTOR_SRC_MASK 0xc0000000 // 31-30 |
| +#define WF_TX_DESCRIPTOR_SRC_SHIFT 30 |
| +// DW7 |
| +#define WF_TX_DESCRIPTOR_SW_TX_TIME_DW 7 |
| +#define WF_TX_DESCRIPTOR_SW_TX_TIME_ADDR 28 |
| +#define WF_TX_DESCRIPTOR_SW_TX_TIME_MASK 0x000003ff // 9- 0 |
| +#define WF_TX_DESCRIPTOR_SW_TX_TIME_SHIFT 0 |
| +#define WF_TX_DESCRIPTOR_UT_DW 7 |
| +#define WF_TX_DESCRIPTOR_UT_ADDR 28 |
| +#define WF_TX_DESCRIPTOR_UT_MASK 0x00008000 // 15-15 |
| +#define WF_TX_DESCRIPTOR_UT_SHIFT 15 |
| +#define WF_TX_DESCRIPTOR_CTXD_CNT_DW 7 |
| +#define WF_TX_DESCRIPTOR_CTXD_CNT_ADDR 28 |
| +#define WF_TX_DESCRIPTOR_CTXD_CNT_MASK 0x03c00000 // 25-22 |
| +#define WF_TX_DESCRIPTOR_CTXD_CNT_SHIFT 22 |
| +#define WF_TX_DESCRIPTOR_CTXD_DW 7 |
| +#define WF_TX_DESCRIPTOR_CTXD_ADDR 28 |
| +#define WF_TX_DESCRIPTOR_CTXD_MASK 0x04000000 // 26-26 |
| +#define WF_TX_DESCRIPTOR_CTXD_SHIFT 26 |
| +#define WF_TX_DESCRIPTOR_HM_DW 7 |
| +#define WF_TX_DESCRIPTOR_HM_ADDR 28 |
| +#define WF_TX_DESCRIPTOR_HM_MASK 0x08000000 // 27-27 |
| +#define WF_TX_DESCRIPTOR_HM_SHIFT 27 |
| +#define WF_TX_DESCRIPTOR_DP_DW 7 |
| +#define WF_TX_DESCRIPTOR_DP_ADDR 28 |
| +#define WF_TX_DESCRIPTOR_DP_MASK 0x10000000 // 28-28 |
| +#define WF_TX_DESCRIPTOR_DP_SHIFT 28 |
| +#define WF_TX_DESCRIPTOR_IP_DW 7 |
| +#define WF_TX_DESCRIPTOR_IP_ADDR 28 |
| +#define WF_TX_DESCRIPTOR_IP_MASK 0x20000000 // 29-29 |
| +#define WF_TX_DESCRIPTOR_IP_SHIFT 29 |
| +#define WF_TX_DESCRIPTOR_TXD_LEN_DW 7 |
| +#define WF_TX_DESCRIPTOR_TXD_LEN_ADDR 28 |
| +#define WF_TX_DESCRIPTOR_TXD_LEN_MASK 0xc0000000 // 31-30 |
| +#define WF_TX_DESCRIPTOR_TXD_LEN_SHIFT 30 |
| +// DW8 |
| +#define WF_TX_DESCRIPTOR_MSDU0_DW 8 |
| +#define WF_TX_DESCRIPTOR_MSDU0_ADDR 32 |
| +#define WF_TX_DESCRIPTOR_MSDU0_MASK 0x0000ffff // 15- 0 |
| +#define WF_TX_DESCRIPTOR_MSDU0_SHIFT 0 |
| +#define WF_TX_DESCRIPTOR_MSDU1_DW 8 |
| +#define WF_TX_DESCRIPTOR_MSDU1_ADDR 32 |
| +#define WF_TX_DESCRIPTOR_MSDU1_MASK 0xffff0000 // 31-16 |
| +#define WF_TX_DESCRIPTOR_MSDU1_SHIFT 16 |
| +// DW9 |
| +#define WF_TX_DESCRIPTOR_MSDU2_DW 9 |
| +#define WF_TX_DESCRIPTOR_MSDU2_ADDR 36 |
| +#define WF_TX_DESCRIPTOR_MSDU2_MASK 0x0000ffff // 15- 0 |
| +#define WF_TX_DESCRIPTOR_MSDU2_SHIFT 0 |
| +#define WF_TX_DESCRIPTOR_MSDU3_DW 9 |
| +#define WF_TX_DESCRIPTOR_MSDU3_ADDR 36 |
| +#define WF_TX_DESCRIPTOR_MSDU3_MASK 0xffff0000 // 31-16 |
| +#define WF_TX_DESCRIPTOR_MSDU3_SHIFT 16 |
| +// DW10 |
| +#define WF_TX_DESCRIPTOR_TXP0_DW 10 |
| +#define WF_TX_DESCRIPTOR_TXP0_ADDR 40 |
| +#define WF_TX_DESCRIPTOR_TXP0_MASK 0xffffffff // 31- 0 |
| +#define WF_TX_DESCRIPTOR_TXP0_SHIFT 0 |
| +// DW11 |
| +// DO NOT process repeat field(txp[0]) |
| +#define WF_TX_DESCRIPTOR_TXP1_DW 11 |
| +#define WF_TX_DESCRIPTOR_TXP1_ADDR 44 |
| +#define WF_TX_DESCRIPTOR_TXP1_MASK 0xffff0000 // 31-16 |
| +#define WF_TX_DESCRIPTOR_TXP1_SHIFT 16 |
| +// DW12 |
| +// DO NOT process repeat field(txp[1]) |
| +// DW13 |
| +#define WF_TX_DESCRIPTOR_TXP2_DW 13 |
| +#define WF_TX_DESCRIPTOR_TXP2_ADDR 52 |
| +#define WF_TX_DESCRIPTOR_TXP2_MASK 0xffffffff // 31- 0 |
| +#define WF_TX_DESCRIPTOR_TXP2_SHIFT 0 |
| +// DW14 |
| +// DO NOT process repeat field(txp[2]) |
| +#define WF_TX_DESCRIPTOR_TXP3_DW 14 |
| +#define WF_TX_DESCRIPTOR_TXP3_ADDR 56 |
| +#define WF_TX_DESCRIPTOR_TXP3_MASK 0xffff0000 // 31-16 |
| +#define WF_TX_DESCRIPTOR_TXP3_SHIFT 16 |
| +// DW15 |
| +// DO NOT process repeat field(txp[3]) |
| +// DW16 |
| +#define WF_TX_DESCRIPTOR_MSDU4_DW 16 |
| +#define WF_TX_DESCRIPTOR_MSDU4_ADDR 64 |
| +#define WF_TX_DESCRIPTOR_MSDU4_MASK 0x0000ffff // 15- 0 |
| +#define WF_TX_DESCRIPTOR_MSDU4_SHIFT 0 |
| +#define WF_TX_DESCRIPTOR_MSDU5_DW 16 |
| +#define WF_TX_DESCRIPTOR_MSDU5_ADDR 64 |
| +#define WF_TX_DESCRIPTOR_MSDU5_MASK 0xffff0000 // 31-16 |
| +#define WF_TX_DESCRIPTOR_MSDU5_SHIFT 16 |
| +// DW17 |
| +#define WF_TX_DESCRIPTOR_MSDU6_DW 17 |
| +#define WF_TX_DESCRIPTOR_MSDU6_ADDR 68 |
| +#define WF_TX_DESCRIPTOR_MSDU6_MASK 0x0000ffff // 15- 0 |
| +#define WF_TX_DESCRIPTOR_MSDU6_SHIFT 0 |
| +#define WF_TX_DESCRIPTOR_MSDU7_DW 17 |
| +#define WF_TX_DESCRIPTOR_MSDU7_ADDR 68 |
| +#define WF_TX_DESCRIPTOR_MSDU7_MASK 0xffff0000 // 31-16 |
| +#define WF_TX_DESCRIPTOR_MSDU7_SHIFT 16 |
| +// DW18 |
| +#define WF_TX_DESCRIPTOR_TXP4_DW 18 |
| +#define WF_TX_DESCRIPTOR_TXP4_ADDR 72 |
| +#define WF_TX_DESCRIPTOR_TXP4_MASK 0xffffffff // 31- 0 |
| +#define WF_TX_DESCRIPTOR_TXP4_SHIFT 0 |
| +// DW19 |
| +// DO NOT process repeat field(txp[4]) |
| +#define WF_TX_DESCRIPTOR_TXP5_DW 19 |
| +#define WF_TX_DESCRIPTOR_TXP5_ADDR 76 |
| +#define WF_TX_DESCRIPTOR_TXP5_MASK 0xffff0000 // 31-16 |
| +#define WF_TX_DESCRIPTOR_TXP5_SHIFT 16 |
| +// DW20 |
| +// DO NOT process repeat field(txp[5]) |
| +// DW21 |
| +#define WF_TX_DESCRIPTOR_TXP6_DW 21 |
| +#define WF_TX_DESCRIPTOR_TXP6_ADDR 84 |
| +#define WF_TX_DESCRIPTOR_TXP6_MASK 0xffffffff // 31- 0 |
| +#define WF_TX_DESCRIPTOR_TXP6_SHIFT 0 |
| +// DW22 |
| +// DO NOT process repeat field(txp[6]) |
| +#define WF_TX_DESCRIPTOR_TXP7_DW 22 |
| +#define WF_TX_DESCRIPTOR_TXP7_ADDR 88 |
| +#define WF_TX_DESCRIPTOR_TXP7_MASK 0xffff0000 // 31-16 |
| +#define WF_TX_DESCRIPTOR_TXP7_SHIFT 16 |
| +// DW23 |
| +// DO NOT process repeat field(txp[7]) |
| +// DW24 |
| +#define WF_TX_DESCRIPTOR_TXP8_DW 24 |
| +#define WF_TX_DESCRIPTOR_TXP8_ADDR 96 |
| +#define WF_TX_DESCRIPTOR_TXP8_MASK 0xffffffff // 31- 0 |
| +#define WF_TX_DESCRIPTOR_TXP8_SHIFT 0 |
| +// DW25 |
| +// DO NOT process repeat field(txp[8]) |
| +#define WF_TX_DESCRIPTOR_TXP9_DW 25 |
| +#define WF_TX_DESCRIPTOR_TXP9_ADDR 100 |
| +#define WF_TX_DESCRIPTOR_TXP9_MASK 0xffff0000 // 31-16 |
| +#define WF_TX_DESCRIPTOR_TXP9_SHIFT 16 |
| +// DW26 |
| +// DO NOT process repeat field(txp[9]) |
| +// DW27 |
| +#define WF_TX_DESCRIPTOR_TXP10_DW 27 |
| +#define WF_TX_DESCRIPTOR_TXP10_ADDR 108 |
| +#define WF_TX_DESCRIPTOR_TXP10_MASK 0xffffffff // 31- 0 |
| +#define WF_TX_DESCRIPTOR_TXP10_SHIFT 0 |
| +// DW28 |
| +// DO NOT process repeat field(txp[10]) |
| +#define WF_TX_DESCRIPTOR_TXP11_DW 28 |
| +#define WF_TX_DESCRIPTOR_TXP11_ADDR 112 |
| +#define WF_TX_DESCRIPTOR_TXP11_MASK 0xffff0000 // 31-16 |
| +#define WF_TX_DESCRIPTOR_TXP11_SHIFT 16 |
| +// DW29 |
| +// DO NOT process repeat field(txp[11]) |
| +// DW30 |
| +#define WF_TX_DESCRIPTOR_TXP12_DW 30 |
| +#define WF_TX_DESCRIPTOR_TXP12_ADDR 120 |
| +#define WF_TX_DESCRIPTOR_TXP12_MASK 0xffffffff // 31- 0 |
| +#define WF_TX_DESCRIPTOR_TXP12_SHIFT 0 |
| +// DW31 |
| +// DO NOT process repeat field(txp[12]) |
| +#define WF_TX_DESCRIPTOR_TXP13_DW 31 |
| +#define WF_TX_DESCRIPTOR_TXP13_ADDR 124 |
| +#define WF_TX_DESCRIPTOR_TXP13_MASK 0xffff0000 // 31-16 |
| +#define WF_TX_DESCRIPTOR_TXP13_SHIFT 16 |
| +// DW32 |
| +// DO NOT process repeat field(txp[13]) |
| +// DW33 |
| +#define WF_TX_DESCRIPTOR_TXP14_DW 33 |
| +#define WF_TX_DESCRIPTOR_TXP14_ADDR 132 |
| +#define WF_TX_DESCRIPTOR_TXP14_MASK 0xffffffff // 31- 0 |
| +#define WF_TX_DESCRIPTOR_TXP14_SHIFT 0 |
| +// DW34 |
| +// DO NOT process repeat field(txp[14]) |
| +#define WF_TX_DESCRIPTOR_TXP15_DW 34 |
| +#define WF_TX_DESCRIPTOR_TXP15_ADDR 136 |
| +#define WF_TX_DESCRIPTOR_TXP15_MASK 0xffff0000 // 31-16 |
| +#define WF_TX_DESCRIPTOR_TXP15_SHIFT 16 |
| +// DW35 |
| +// DO NOT process repeat field(txp[15]) |
| +// DW36 |
| +#define WF_TX_DESCRIPTOR_TXP16_DW 36 |
| +#define WF_TX_DESCRIPTOR_TXP16_ADDR 144 |
| +#define WF_TX_DESCRIPTOR_TXP16_MASK 0xffffffff // 31- 0 |
| +#define WF_TX_DESCRIPTOR_TXP16_SHIFT 0 |
| +// DW37 |
| +// DO NOT process repeat field(txp[16]) |
| +#define WF_TX_DESCRIPTOR_TXP17_DW 37 |
| +#define WF_TX_DESCRIPTOR_TXP17_ADDR 148 |
| +#define WF_TX_DESCRIPTOR_TXP17_MASK 0xffff0000 // 31-16 |
| +#define WF_TX_DESCRIPTOR_TXP17_SHIFT 16 |
| +// DW38 |
| +// DO NOT process repeat field(txp[17]) |
| +// DW39 |
| +#define WF_TX_DESCRIPTOR_TXP18_DW 39 |
| +#define WF_TX_DESCRIPTOR_TXP18_ADDR 156 |
| +#define WF_TX_DESCRIPTOR_TXP18_MASK 0xffffffff // 31- 0 |
| +#define WF_TX_DESCRIPTOR_TXP18_SHIFT 0 |
| +// DW40 |
| +// DO NOT process repeat field(txp[18]) |
| +#define WF_TX_DESCRIPTOR_TXP19_DW 40 |
| +#define WF_TX_DESCRIPTOR_TXP19_ADDR 160 |
| +#define WF_TX_DESCRIPTOR_TXP19_MASK 0xffff0000 // 31-16 |
| +#define WF_TX_DESCRIPTOR_TXP19_SHIFT 16 |
| +// DW41 |
| +// DO NOT process repeat field(txp[19]) |
| +// DW42 |
| +#define WF_TX_DESCRIPTOR_TXP20_DW 42 |
| +#define WF_TX_DESCRIPTOR_TXP20_ADDR 168 |
| +#define WF_TX_DESCRIPTOR_TXP20_MASK 0xffffffff // 31- 0 |
| +#define WF_TX_DESCRIPTOR_TXP20_SHIFT 0 |
| +// DW43 |
| +// DO NOT process repeat field(txp[20]) |
| +#define WF_TX_DESCRIPTOR_TXP21_DW 43 |
| +#define WF_TX_DESCRIPTOR_TXP21_ADDR 172 |
| +#define WF_TX_DESCRIPTOR_TXP21_MASK 0xffff0000 // 31-16 |
| +#define WF_TX_DESCRIPTOR_TXP21_SHIFT 16 |
| +// DW44 |
| +// DO NOT process repeat field(txp[21]) |
| +// DW45 |
| +#define WF_TX_DESCRIPTOR_TXP22_DW 45 |
| +#define WF_TX_DESCRIPTOR_TXP22_ADDR 180 |
| +#define WF_TX_DESCRIPTOR_TXP22_MASK 0xffffffff // 31- 0 |
| +#define WF_TX_DESCRIPTOR_TXP22_SHIFT 0 |
| +// DW46 |
| +// DO NOT process repeat field(txp[22]) |
| +#define WF_TX_DESCRIPTOR_TXP23_DW 46 |
| +#define WF_TX_DESCRIPTOR_TXP23_ADDR 184 |
| +#define WF_TX_DESCRIPTOR_TXP23_MASK 0xffff0000 // 31-16 |
| +#define WF_TX_DESCRIPTOR_TXP23_SHIFT 16 |
| +// DW47 |
| +// DO NOT process repeat field(txp[23]) |
| +// DW48 |
| +#define WF_TX_DESCRIPTOR_TXP24_DW 48 |
| +#define WF_TX_DESCRIPTOR_TXP24_ADDR 192 |
| +#define WF_TX_DESCRIPTOR_TXP24_MASK 0xffffffff // 31- 0 |
| +#define WF_TX_DESCRIPTOR_TXP24_SHIFT 0 |
| +// DW49 |
| +// DO NOT process repeat field(txp[24]) |
| +#define WF_TX_DESCRIPTOR_TXP25_DW 49 |
| +#define WF_TX_DESCRIPTOR_TXP25_ADDR 196 |
| +#define WF_TX_DESCRIPTOR_TXP25_MASK 0xffff0000 // 31-16 |
| +#define WF_TX_DESCRIPTOR_TXP25_SHIFT 16 |
| +// DW50 |
| +// DO NOT process repeat field(txp[25]) |
| +// DW51 |
| +#define WF_TX_DESCRIPTOR_TXP26_DW 51 |
| +#define WF_TX_DESCRIPTOR_TXP26_ADDR 204 |
| +#define WF_TX_DESCRIPTOR_TXP26_MASK 0xffffffff // 31- 0 |
| +#define WF_TX_DESCRIPTOR_TXP26_SHIFT 0 |
| +// DW52 |
| +// DO NOT process repeat field(txp[26]) |
| +#define WF_TX_DESCRIPTOR_TXP27_DW 52 |
| +#define WF_TX_DESCRIPTOR_TXP27_ADDR 208 |
| +#define WF_TX_DESCRIPTOR_TXP27_MASK 0xffff0000 // 31-16 |
| +#define WF_TX_DESCRIPTOR_TXP27_SHIFT 16 |
| +// DW53 |
| +// DO NOT process repeat field(txp[27]) |
| +// DW54 |
| +#define WF_TX_DESCRIPTOR_TXP28_DW 54 |
| +#define WF_TX_DESCRIPTOR_TXP28_ADDR 216 |
| +#define WF_TX_DESCRIPTOR_TXP28_MASK 0xffffffff // 31- 0 |
| +#define WF_TX_DESCRIPTOR_TXP28_SHIFT 0 |
| +// DW55 |
| +// DO NOT process repeat field(txp[28]) |
| +#define WF_TX_DESCRIPTOR_TXP29_DW 55 |
| +#define WF_TX_DESCRIPTOR_TXP29_ADDR 220 |
| +#define WF_TX_DESCRIPTOR_TXP29_MASK 0xffff0000 // 31-16 |
| +#define WF_TX_DESCRIPTOR_TXP29_SHIFT 16 |
| +// DW56 |
| +// DO NOT process repeat field(txp[29]) |
| +// DW57 |
| +#define WF_TX_DESCRIPTOR_TXP30_DW 57 |
| +#define WF_TX_DESCRIPTOR_TXP30_ADDR 228 |
| +#define WF_TX_DESCRIPTOR_TXP30_MASK 0xffffffff // 31- 0 |
| +#define WF_TX_DESCRIPTOR_TXP30_SHIFT 0 |
| +// DW58 |
| +// DO NOT process repeat field(txp[30]) |
| +#define WF_TX_DESCRIPTOR_TXP31_DW 58 |
| +#define WF_TX_DESCRIPTOR_TXP31_ADDR 232 |
| +#define WF_TX_DESCRIPTOR_TXP31_MASK 0xffff0000 // 31-16 |
| +#define WF_TX_DESCRIPTOR_TXP31_SHIFT 16 |
| +// DW59 |
| +// DO NOT process repeat field(txp[31]) |
| + |
| +/* TXP PAO */ |
| +#define HIF_TXP_V2_SIZE (24 * 4) |
| +/* DW0 */ |
| +#define HIF_TXD_VERSION_SHIFT 19 |
| +#define HIF_TXD_VERSION_MASK 0x00780000 |
| + |
| +/* DW8 */ |
| +#define HIF_TXP_PRIORITY_SHIFT 0 |
| +#define HIF_TXP_PRIORITY_MASK 0x00000001 |
| +#define HIF_TXP_FIXED_RATE_SHIFT 1 |
| +#define HIF_TXP_FIXED_RATE_MASK 0x00000002 |
| +#define HIF_TXP_TCP_SHIFT 2 |
| +#define HIF_TXP_TCP_MASK 0x00000004 |
| +#define HIF_TXP_NON_CIPHER_SHIFT 3 |
| +#define HIF_TXP_NON_CIPHER_MASK 0x00000008 |
| +#define HIF_TXP_VLAN_SHIFT 4 |
| +#define HIF_TXP_VLAN_MASK 0x00000010 |
| +#define HIF_TXP_BC_MC_FLAG_SHIFT 5 |
| +#define HIF_TXP_BC_MC_FLAG_MASK 0x00000060 |
| +#define HIF_TXP_FR_HOST_SHIFT 7 |
| +#define HIF_TXP_FR_HOST_MASK 0x00000080 |
| +#define HIF_TXP_ETYPE_SHIFT 8 |
| +#define HIF_TXP_ETYPE_MASK 0x00000100 |
| +#define HIF_TXP_TXP_AMSDU_SHIFT 9 |
| +#define HIF_TXP_TXP_AMSDU_MASK 0x00000200 |
| +#define HIF_TXP_TXP_MC_CLONE_SHIFT 10 |
| +#define HIF_TXP_TXP_MC_CLONE_MASK 0x00000400 |
| +#define HIF_TXP_TOKEN_ID_SHIFT 16 |
| +#define HIF_TXP_TOKEN_ID_MASK 0xffff0000 |
| + |
| +/* DW9 */ |
| +#define HIF_TXP_BSS_IDX_SHIFT 0 |
| +#define HIF_TXP_BSS_IDX_MASK 0x000000ff |
| +#define HIF_TXP_USER_PRIORITY_SHIFT 8 |
| +#define HIF_TXP_USER_PRIORITY_MASK 0x0000ff00 |
| +#define HIF_TXP_BUF_NUM_SHIFT 16 |
| +#define HIF_TXP_BUF_NUM_MASK 0x001f0000 |
| +#define HIF_TXP_MSDU_CNT_SHIFT 21 |
| +#define HIF_TXP_MSDU_CNT_MASK 0x03e00000 |
| +#define HIF_TXP_SRC_SHIFT 26 |
| +#define HIF_TXP_SRC_MASK 0x0c000000 |
| + |
| +/* DW10 */ |
| +#define HIF_TXP_ETH_TYPE_SHIFT 0 |
| +#define HIF_TXP_ETH_TYPE_MASK 0x0000ffff |
| +#define HIF_TXP_WLAN_IDX_SHIFT 16 |
| +#define HIF_TXP_WLAN_IDX_MASK 0x0fff0000 |
| + |
| +/* DW11 */ |
| +#define HIF_TXP_PPE_INFO_SHIFT 0 |
| +#define HIF_TXP_PPE_INFO_MASK 0xffffffff |
| + |
| +/* DW12 - DW31 */ |
| +#define HIF_TXP_BUF_PTR0_L_SHIFT 0 |
| +#define HIF_TXP_BUF_PTR0_L_MASK 0xffffffff |
| +#define HIF_TXP_BUF_LEN0_SHIFT 0 |
| +#define HIF_TXP_BUF_LEN0_MASK 0x00000fff |
| +#define HIF_TXP_BUF_PTR0_H_SHIFT 12 |
| +#define HIF_TXP_BUF_PTR0_H_MASK 0x0000f000 |
| +#define HIF_TXP_BUF_LEN1_SHIFT 16 |
| +#define HIF_TXP_BUF_LEN1_MASK 0x0fff0000 |
| +#define HIF_TXP_BUF_PTR1_H_SHIFT 28 |
| +#define HIF_TXP_BUF_PTR1_H_MASK 0xf0000000 |
| +#define HIF_TXP_BUF_PTR1_L_SHIFT 0 |
| +#define HIF_TXP_BUF_PTR1_L_MASK 0xffffffff |
| + |
| +/* DW31 */ |
| +#define HIF_TXP_ML_SHIFT 16 |
| +#define HIF_TXP_ML_MASK 0xffff0000 |
| + |
| +#endif |
| +#endif |
| diff --git a/besra/mtk_debugfs.c b/besra/mtk_debugfs.c |
| new file mode 100644 |
| index 00000000..ea6a2620 |
| --- /dev/null |
| +++ b/besra/mtk_debugfs.c |
| @@ -0,0 +1,3576 @@ |
| +#include<linux/inet.h> |
| +#include "besra.h" |
| +#include "mtk_debug.h" |
| +#include "../mt76.h" |
| +#include "mcu.h" |
| +#include "mac.h" |
| + |
| +#ifdef CONFIG_MTK_DEBUG |
| + |
| +void besra_packet_log_to_host(struct besra_dev *dev, const void *data, int len, int type, int des_len) |
| +{ |
| + struct bin_debug_hdr *hdr; |
| + char *buf; |
| + |
| + if (len > 1500 - sizeof(*hdr)) |
| + len = 1500 - sizeof(*hdr); |
| + |
| + buf = kzalloc(sizeof(*hdr) + len, GFP_KERNEL); |
| + if (!buf) |
| + return; |
| + |
| + hdr = (struct bin_debug_hdr *)buf; |
| + hdr->magic_num = cpu_to_le32(PKT_BIN_DEBUG_MAGIC); |
| + hdr->serial_id = cpu_to_le16(dev->fw_debug_seq++); |
| + hdr->msg_type = cpu_to_le16(type); |
| + hdr->len = cpu_to_le16(len); |
| + hdr->des_len = cpu_to_le16(des_len); |
| + |
| + memcpy(buf + sizeof(*hdr), data, len); |
| + |
| + besra_debugfs_rx_log(dev, buf, sizeof(*hdr) + len); |
| +} |
| + |
| +/* DBG MODLE */ |
| +static int |
| +besra_fw_debug_module_set(void *data, u64 module) |
| +{ |
| + struct besra_dev *dev = data; |
| + |
| + dev->dbg.fw_dbg_module = module; |
| + return 0; |
| +} |
| + |
| +static int |
| +besra_fw_debug_module_get(void *data, u64 *module) |
| +{ |
| + struct besra_dev *dev = data; |
| + |
| + *module = dev->dbg.fw_dbg_module; |
| + return 0; |
| +} |
| + |
| +DEFINE_DEBUGFS_ATTRIBUTE(fops_fw_debug_module, besra_fw_debug_module_get, |
| + besra_fw_debug_module_set, "%lld\n"); |
| + |
| +static int |
| +besra_fw_debug_level_set(void *data, u64 level) |
| +{ |
| + struct besra_dev *dev = data; |
| + |
| + dev->dbg.fw_dbg_lv = level; |
| + besra_mcu_fw_dbg_ctrl(dev, dev->dbg.fw_dbg_module, dev->dbg.fw_dbg_lv); |
| + return 0; |
| +} |
| + |
| +static int |
| +besra_fw_debug_level_get(void *data, u64 *level) |
| +{ |
| + struct besra_dev *dev = data; |
| + |
| + *level = dev->dbg.fw_dbg_lv; |
| + return 0; |
| +} |
| + |
| +DEFINE_DEBUGFS_ATTRIBUTE(fops_fw_debug_level, besra_fw_debug_level_get, |
| + besra_fw_debug_level_set, "%lld\n"); |
| + |
| +/* WTBL INFO */ |
| +static int |
| +besra_wtbl_read_raw(struct besra_dev *dev, u16 idx, |
| + enum besra_wtbl_type type, u16 start_dw, |
| + u16 len, void *buf) |
| +{ |
| + u32 *dest_cpy = (u32 *)buf; |
| + u32 size_dw = len; |
| + u32 src = 0; |
| + |
| + if (!buf) |
| + return 0xFF; |
| + |
| + if (type == WTBL_TYPE_LMAC) { |
| + mt76_wr(dev, MT_DBG_WTBLON_TOP_WDUCR_ADDR, |
| + FIELD_PREP(MT_DBG_WTBLON_TOP_WDUCR_GROUP, (idx >> 7))); |
| + src = LWTBL_IDX2BASE(idx, start_dw); |
| + } else if (type == WTBL_TYPE_UMAC) { |
| + mt76_wr(dev, MT_DBG_UWTBL_TOP_WDUCR_ADDR, |
| + FIELD_PREP(MT_DBG_UWTBL_TOP_WDUCR_GROUP, (idx >> 7))); |
| + src = UWTBL_IDX2BASE(idx, start_dw); |
| + } else if (type == WTBL_TYPE_KEY) { |
| + mt76_wr(dev, MT_DBG_UWTBL_TOP_WDUCR_ADDR, |
| + MT_DBG_UWTBL_TOP_WDUCR_TARGET | |
| + FIELD_PREP(MT_DBG_UWTBL_TOP_WDUCR_GROUP, (idx >> 7))); |
| + src = KEYTBL_IDX2BASE(idx, start_dw); |
| + } |
| + |
| + while (size_dw--) { |
| + *dest_cpy++ = mt76_rr(dev, src); |
| + src += 4; |
| + }; |
| + |
| + return 0; |
| +} |
| + |
| +static int |
| +besra_wtbl_write_raw(struct besra_dev *dev, u16 idx, |
| + enum besra_wtbl_type type, u16 start_dw, |
| + u32 val) |
| +{ |
| + u32 addr = 0; |
| + |
| + if (type == WTBL_TYPE_LMAC) { |
| + mt76_wr(dev, MT_DBG_WTBLON_TOP_WDUCR_ADDR, |
| + FIELD_PREP(MT_DBG_WTBLON_TOP_WDUCR_GROUP, (idx >> 7))); |
| + addr = LWTBL_IDX2BASE(idx, start_dw); |
| + } else if (type == WTBL_TYPE_UMAC) { |
| + mt76_wr(dev, MT_DBG_UWTBL_TOP_WDUCR_ADDR, |
| + FIELD_PREP(MT_DBG_UWTBL_TOP_WDUCR_GROUP, (idx >> 7))); |
| + addr = UWTBL_IDX2BASE(idx, start_dw); |
| + } else if (type == WTBL_TYPE_KEY) { |
| + mt76_wr(dev, MT_DBG_UWTBL_TOP_WDUCR_ADDR, |
| + MT_DBG_UWTBL_TOP_WDUCR_TARGET | |
| + FIELD_PREP(MT_DBG_UWTBL_TOP_WDUCR_GROUP, (idx >> 7))); |
| + addr = KEYTBL_IDX2BASE(idx, start_dw); |
| + } |
| + |
| + mt76_wr(dev, addr, val); |
| + |
| + return 0; |
| +} |
| + |
| +static const struct berse_wtbl_parse WTBL_LMAC_DW0[] = { |
| + {"MUAR_IDX", WF_LWTBL_MUAR_MASK, WF_LWTBL_MUAR_SHIFT,false}, |
| + {"RCA1", WF_LWTBL_RCA1_MASK, NO_SHIFT_DEFINE, false}, |
| + {"KID", WF_LWTBL_KID_MASK, WF_LWTBL_KID_SHIFT, false}, |
| + {"RCID", WF_LWTBL_RCID_MASK, NO_SHIFT_DEFINE, false}, |
| + {"BAND", WF_LWTBL_BAND_MASK, WF_LWTBL_BAND_SHIFT,false}, |
| + {"RV", WF_LWTBL_RV_MASK, NO_SHIFT_DEFINE, false}, |
| + {"RCA2", WF_LWTBL_RCA2_MASK, NO_SHIFT_DEFINE, false}, |
| + {"WPI_FLAG", WF_LWTBL_WPI_FLAG_MASK, NO_SHIFT_DEFINE,true}, |
| + {NULL,} |
| +}; |
| + |
| +static void parse_fmac_lwtbl_dw0_1(struct seq_file *s, u8 *lwtbl) |
| +{ |
| + u32 *addr = 0; |
| + u32 dw_value = 0; |
| + u16 i = 0; |
| + |
| + seq_printf(s, "\t\n"); |
| + seq_printf(s, "LinkAddr: %02x:%02x:%02x:%02x:%02x:%02x(D0[B0~15], D1[B0~31])\n", |
| + lwtbl[4], lwtbl[5], lwtbl[6], lwtbl[7], lwtbl[0], lwtbl[1]); |
| + |
| + /* LMAC WTBL DW 0 */ |
| + seq_printf(s, "\t\n"); |
| + seq_printf(s, "LWTBL DW 0/1\n"); |
| + addr = (u32 *)&(lwtbl[WTBL_GROUP_PEER_INFO_DW_0*4]); |
| + dw_value = *addr; |
| + |
| + while (WTBL_LMAC_DW0[i].name) { |
| + |
| + if (WTBL_LMAC_DW0[i].shift == NO_SHIFT_DEFINE) |
| + seq_printf(s, "\t%s:%d\n", WTBL_LMAC_DW0[i].name, |
| + (dw_value & WTBL_LMAC_DW0[i].mask) ? 1 : 0); |
| + else |
| + seq_printf(s, "\t%s:%u\n", WTBL_LMAC_DW0[i].name, |
| + (dw_value & WTBL_LMAC_DW0[i].mask) >> WTBL_LMAC_DW0[i].shift); |
| + i++; |
| + } |
| +} |
| + |
| +static const struct berse_wtbl_parse WTBL_LMAC_DW2[] = { |
| + {"AID", WF_LWTBL_AID_MASK, WF_LWTBL_AID_SHIFT, false}, |
| + {"GID_SU", WF_LWTBL_GID_SU_MASK, NO_SHIFT_DEFINE, false}, |
| + {"SPP_EN", WF_LWTBL_SPP_EN_MASK, NO_SHIFT_DEFINE, false}, |
| + {"WPI_EVEN", WF_LWTBL_WPI_EVEN_MASK, NO_SHIFT_DEFINE, false}, |
| + {"AAD_OM", WF_LWTBL_AAD_OM_MASK, NO_SHIFT_DEFINE, false}, |
| + {"CIPHER_PGTK",WF_LWTBL_CIPHER_SUIT_PGTK_MASK, WF_LWTBL_CIPHER_SUIT_PGTK_SHIFT, true}, |
| + {"FROM_DS", WF_LWTBL_FD_MASK, NO_SHIFT_DEFINE, false}, |
| + {"TO_DS", WF_LWTBL_TD_MASK, NO_SHIFT_DEFINE, false}, |
| + {"SW", WF_LWTBL_SW_MASK, NO_SHIFT_DEFINE, false}, |
| + {"UL", WF_LWTBL_UL_MASK, NO_SHIFT_DEFINE, false}, |
| + {"TX_POWER_SAVE", WF_LWTBL_TX_PS_MASK, NO_SHIFT_DEFINE, true}, |
| + {"QOS", WF_LWTBL_QOS_MASK, NO_SHIFT_DEFINE, false}, |
| + {"HT", WF_LWTBL_HT_MASK, NO_SHIFT_DEFINE, false}, |
| + {"VHT", WF_LWTBL_VHT_MASK, NO_SHIFT_DEFINE, false}, |
| + {"HE", WF_LWTBL_HE_MASK, NO_SHIFT_DEFINE, false}, |
| + {"EHT", WF_LWTBL_EHT_MASK, NO_SHIFT_DEFINE, false}, |
| + {"MESH", WF_LWTBL_MESH_MASK, NO_SHIFT_DEFINE, true}, |
| + {NULL,} |
| +}; |
| + |
| +static void parse_fmac_lwtbl_dw2(struct seq_file *s, u8 *lwtbl) |
| +{ |
| + u32 *addr = 0; |
| + u32 dw_value = 0; |
| + u16 i = 0; |
| + |
| + /* LMAC WTBL DW 2 */ |
| + seq_printf(s, "\t\n"); |
| + seq_printf(s, "LWTBL DW 2\n"); |
| + addr = (u32 *)&(lwtbl[WTBL_GROUP_TRX_CAP_DW_2*4]); |
| + dw_value = *addr; |
| + |
| + while (WTBL_LMAC_DW2[i].name) { |
| + |
| + if (WTBL_LMAC_DW2[i].shift == NO_SHIFT_DEFINE) |
| + seq_printf(s, "\t%s:%d\n", WTBL_LMAC_DW2[i].name, |
| + (dw_value & WTBL_LMAC_DW2[i].mask) ? 1 : 0); |
| + else |
| + seq_printf(s, "\t%s:%u\n", WTBL_LMAC_DW2[i].name, |
| + (dw_value & WTBL_LMAC_DW2[i].mask) >> WTBL_LMAC_DW2[i].shift); |
| + i++; |
| + } |
| +} |
| + |
| +static const struct berse_wtbl_parse WTBL_LMAC_DW3[] = { |
| + {"WMM_Q", WF_LWTBL_WMM_Q_MASK, WF_LWTBL_WMM_Q_SHIFT, false}, |
| + {"EHT_SIG_MCS", WF_LWTBL_EHT_SIG_MCS_MASK, WF_LWTBL_EHT_SIG_MCS_SHIFT, false}, |
| + {"HDRT_MODE", WF_LWTBL_HDRT_MODE_MASK, NO_SHIFT_DEFINE, false}, |
| + {"BEAM_CHG", WF_LWTBL_BEAM_CHG_MASK, NO_SHIFT_DEFINE, false}, |
| + {"EHT_LTF_SYM_NUM", WF_LWTBL_EHT_LTF_SYM_NUM_OPT_MASK, WF_LWTBL_EHT_LTF_SYM_NUM_OPT_SHIFT, true}, |
| + {"PFMU_IDX", WF_LWTBL_PFMU_IDX_MASK, WF_LWTBL_PFMU_IDX_SHIFT, false}, |
| + {"ULPF_IDX", WF_LWTBL_ULPF_IDX_MASK, WF_LWTBL_ULPF_IDX_SHIFT, false}, |
| + {"RIBF", WF_LWTBL_RIBF_MASK, NO_SHIFT_DEFINE, false}, |
| + {"ULPF", WF_LWTBL_ULPF_MASK, NO_SHIFT_DEFINE, true}, |
| + {"TBF_HT", WF_LWTBL_TBF_HT_MASK, NO_SHIFT_DEFINE, false}, |
| + {"TBF_VHT", WF_LWTBL_TBF_VHT_MASK, NO_SHIFT_DEFINE, false}, |
| + {"TBF_HE", WF_LWTBL_TBF_HE_MASK, NO_SHIFT_DEFINE, false}, |
| + {"TBF_EHT", WF_LWTBL_TBF_EHT_MASK, NO_SHIFT_DEFINE, false}, |
| + {"IGN_FBK", WF_LWTBL_IGN_FBK_MASK, NO_SHIFT_DEFINE, true}, |
| + {NULL,} |
| +}; |
| + |
| +static void parse_fmac_lwtbl_dw3(struct seq_file *s, u8 *lwtbl) |
| +{ |
| + u32 *addr = 0; |
| + u32 dw_value = 0; |
| + u16 i = 0; |
| + |
| + /* LMAC WTBL DW 3 */ |
| + seq_printf(s, "\t\n"); |
| + seq_printf(s, "LWTBL DW 3\n"); |
| + addr = (u32 *)&(lwtbl[WTBL_GROUP_TRX_CAP_DW_3*4]); |
| + dw_value = *addr; |
| + |
| + while (WTBL_LMAC_DW3[i].name) { |
| + |
| + if (WTBL_LMAC_DW3[i].shift == NO_SHIFT_DEFINE) |
| + seq_printf(s, "\t%s:%d\n", WTBL_LMAC_DW3[i].name, |
| + (dw_value & WTBL_LMAC_DW3[i].mask) ? 1 : 0); |
| + else |
| + seq_printf(s, "\t%s:%u\n", WTBL_LMAC_DW3[i].name, |
| + (dw_value & WTBL_LMAC_DW3[i].mask) >> WTBL_LMAC_DW3[i].shift); |
| + i++; |
| + } |
| +} |
| + |
| +static const struct berse_wtbl_parse WTBL_LMAC_DW4[] = { |
| + {"ANT_ID_STS0", WF_LWTBL_ANT_ID0_MASK, WF_LWTBL_ANT_ID0_SHIFT, false}, |
| + {"STS1", WF_LWTBL_ANT_ID1_MASK, WF_LWTBL_ANT_ID1_SHIFT, false}, |
| + {"STS2", WF_LWTBL_ANT_ID2_MASK, WF_LWTBL_ANT_ID2_SHIFT, false}, |
| + {"STS3", WF_LWTBL_ANT_ID3_MASK, WF_LWTBL_ANT_ID3_SHIFT, true}, |
| + {"ANT_ID_STS4", WF_LWTBL_ANT_ID4_MASK, WF_LWTBL_ANT_ID4_SHIFT, false}, |
| + {"STS5", WF_LWTBL_ANT_ID5_MASK, WF_LWTBL_ANT_ID5_SHIFT, false}, |
| + {"STS6", WF_LWTBL_ANT_ID6_MASK, WF_LWTBL_ANT_ID6_SHIFT, false}, |
| + {"STS7", WF_LWTBL_ANT_ID7_MASK, WF_LWTBL_ANT_ID7_SHIFT, true}, |
| + {"PE", WF_LWTBL_PE_MASK, WF_LWTBL_PE_SHIFT, false}, |
| + {"DIS_RHTR", WF_LWTBL_DIS_RHTR_MASK, NO_SHIFT_DEFINE, false}, |
| + {"LDPC_HT", WF_LWTBL_LDPC_HT_MASK, NO_SHIFT_DEFINE, false}, |
| + {"LDPC_VHT", WF_LWTBL_LDPC_VHT_MASK, NO_SHIFT_DEFINE, false}, |
| + {"LDPC_HE", WF_LWTBL_LDPC_HE_MASK, NO_SHIFT_DEFINE, false}, |
| + {"LDPC_EHT", WF_LWTBL_LDPC_EHT_MASK, NO_SHIFT_DEFINE, true}, |
| + {NULL,} |
| +}; |
| + |
| +static void parse_fmac_lwtbl_dw4(struct seq_file *s, u8 *lwtbl) |
| +{ |
| + u32 *addr = 0; |
| + u32 dw_value = 0; |
| + u16 i = 0; |
| + |
| + /* LMAC WTBL DW 4 */ |
| + seq_printf(s, "\t\n"); |
| + seq_printf(s, "LWTBL DW 4\n"); |
| + addr = (u32 *)&(lwtbl[WTBL_GROUP_TRX_CAP_DW_4*4]); |
| + dw_value = *addr; |
| + |
| + while (WTBL_LMAC_DW4[i].name) { |
| + if (WTBL_LMAC_DW4[i].shift == NO_SHIFT_DEFINE) |
| + seq_printf(s, "\t%s:%d\n", WTBL_LMAC_DW4[i].name, |
| + (dw_value & WTBL_LMAC_DW4[i].mask) ? 1 : 0); |
| + else |
| + seq_printf(s, "\t%s:%u\n", WTBL_LMAC_DW4[i].name, |
| + (dw_value & WTBL_LMAC_DW4[i].mask) >> WTBL_LMAC_DW4[i].shift); |
| + i++; |
| + } |
| +} |
| + |
| +static const struct berse_wtbl_parse WTBL_LMAC_DW5[] = { |
| + {"AF", WF_LWTBL_AF_MASK, WF_LWTBL_AF_SHIFT, false}, |
| + {"AF_HE", WF_LWTBL_AF_HE_MASK, WF_LWTBL_AF_HE_SHIFT,false}, |
| + {"RTS", WF_LWTBL_RTS_MASK, NO_SHIFT_DEFINE, false}, |
| + {"SMPS", WF_LWTBL_SMPS_MASK, NO_SHIFT_DEFINE, false}, |
| + {"DYN_BW", WF_LWTBL_DYN_BW_MASK, NO_SHIFT_DEFINE, true}, |
| + {"MMSS", WF_LWTBL_MMSS_MASK, WF_LWTBL_MMSS_SHIFT,false}, |
| + {"USR", WF_LWTBL_USR_MASK, NO_SHIFT_DEFINE, false}, |
| + {"SR_RATE", WF_LWTBL_SR_R_MASK, WF_LWTBL_SR_R_SHIFT,false}, |
| + {"SR_ABORT", WF_LWTBL_SR_ABORT_MASK, NO_SHIFT_DEFINE, true}, |
| + {"TX_POWER_OFFSET", WF_LWTBL_TX_POWER_OFFSET_MASK, WF_LWTBL_TX_POWER_OFFSET_SHIFT, false}, |
| + {"LTF_EHT", WF_LWTBL_LTF_EHT_MASK, WF_LWTBL_LTF_EHT_SHIFT, false}, |
| + {"GI_EHT", WF_LWTBL_GI_EHT_MASK, WF_LWTBL_GI_EHT_SHIFT, false}, |
| + {"DOPPL", WF_LWTBL_DOPPL_MASK, NO_SHIFT_DEFINE, false}, |
| + {"TXOP_PS_CAP", WF_LWTBL_TXOP_PS_CAP_MASK, NO_SHIFT_DEFINE, false}, |
| + {"DONOT_UPDATE_I_PSM", WF_LWTBL_DU_I_PSM_MASK, NO_SHIFT_DEFINE, true}, |
| + {"I_PSM", WF_LWTBL_I_PSM_MASK, NO_SHIFT_DEFINE, false}, |
| + {"PSM", WF_LWTBL_PSM_MASK, NO_SHIFT_DEFINE, false}, |
| + {"SKIP_TX", WF_LWTBL_SKIP_TX_MASK, NO_SHIFT_DEFINE, true}, |
| + {NULL,} |
| +}; |
| + |
| +static void parse_fmac_lwtbl_dw5(struct seq_file *s, u8 *lwtbl) |
| +{ |
| + u32 *addr = 0; |
| + u32 dw_value = 0; |
| + u16 i = 0; |
| + |
| + /* LMAC WTBL DW 5 */ |
| + seq_printf(s, "\t\n"); |
| + seq_printf(s, "LWTBL DW 5\n"); |
| + addr = (u32 *)&(lwtbl[WTBL_GROUP_TRX_CAP_DW_5*4]); |
| + dw_value = *addr; |
| + |
| + while (WTBL_LMAC_DW5[i].name) { |
| + if (WTBL_LMAC_DW5[i].shift == NO_SHIFT_DEFINE) |
| + seq_printf(s, "\t%s:%d\n", WTBL_LMAC_DW5[i].name, |
| + (dw_value & WTBL_LMAC_DW5[i].mask) ? 1 : 0); |
| + else |
| + seq_printf(s, "\t%s:%u\n", WTBL_LMAC_DW5[i].name, |
| + (dw_value & WTBL_LMAC_DW5[i].mask) >> WTBL_LMAC_DW5[i].shift); |
| + i++; |
| + } |
| +} |
| + |
| +static const struct berse_wtbl_parse WTBL_LMAC_DW6[] = { |
| + {"CBRN", WF_LWTBL_CBRN_MASK, WF_LWTBL_CBRN_SHIFT, false}, |
| + {"DBNSS_EN", WF_LWTBL_DBNSS_EN_MASK, NO_SHIFT_DEFINE, false}, |
| + {"BAF_EN", WF_LWTBL_BAF_EN_MASK, NO_SHIFT_DEFINE, false}, |
| + {"RDGBA", WF_LWTBL_RDGBA_MASK, NO_SHIFT_DEFINE, false}, |
| + {"RDG", WF_LWTBL_R_MASK, NO_SHIFT_DEFINE, false}, |
| + {"SPE_IDX", WF_LWTBL_SPE_IDX_MASK, WF_LWTBL_SPE_IDX_SHIFT, true}, |
| + {"G2", WF_LWTBL_G2_MASK, NO_SHIFT_DEFINE, false}, |
| + {"G4", WF_LWTBL_G4_MASK, NO_SHIFT_DEFINE, false}, |
| + {"G8", WF_LWTBL_G8_MASK, NO_SHIFT_DEFINE, false}, |
| + {"G16", WF_LWTBL_G16_MASK, NO_SHIFT_DEFINE, true}, |
| + {"G2_LTF", WF_LWTBL_G2_LTF_MASK, WF_LWTBL_G2_LTF_SHIFT, false}, |
| + {"G4_LTF", WF_LWTBL_G4_LTF_MASK, WF_LWTBL_G4_LTF_SHIFT, false}, |
| + {"G8_LTF", WF_LWTBL_G8_LTF_MASK, WF_LWTBL_G8_LTF_SHIFT, false}, |
| + {"G16_LTF", WF_LWTBL_G16_LTF_MASK, WF_LWTBL_G16_LTF_SHIFT, true}, |
| + {"G2_HE", WF_LWTBL_G2_HE_MASK, WF_LWTBL_G2_HE_SHIFT, false}, |
| + {"G4_HE", WF_LWTBL_G4_HE_MASK, WF_LWTBL_G4_HE_SHIFT, false}, |
| + {"G8_HE", WF_LWTBL_G8_HE_MASK, WF_LWTBL_G8_HE_SHIFT, false}, |
| + {"G16_HE", WF_LWTBL_G16_HE_MASK, WF_LWTBL_G16_HE_SHIFT, true}, |
| + {NULL,} |
| +}; |
| + |
| +static void parse_fmac_lwtbl_dw6(struct seq_file *s, u8 *lwtbl) |
| +{ |
| + u32 *addr = 0; |
| + u32 dw_value = 0; |
| + u16 i = 0; |
| + |
| + /* LMAC WTBL DW 6 */ |
| + seq_printf(s, "\t\n"); |
| + seq_printf(s, "LWTBL DW 6\n"); |
| + addr = (u32 *)&(lwtbl[WTBL_GROUP_TRX_CAP_DW_6*4]); |
| + dw_value = *addr; |
| + |
| + while (WTBL_LMAC_DW6[i].name) { |
| + if (WTBL_LMAC_DW6[i].shift == NO_SHIFT_DEFINE) |
| + seq_printf(s, "\t%s:%d\n", WTBL_LMAC_DW6[i].name, |
| + (dw_value & WTBL_LMAC_DW6[i].mask) ? 1 : 0); |
| + else |
| + seq_printf(s, "\t%s:%u\n", WTBL_LMAC_DW6[i].name, |
| + (dw_value & WTBL_LMAC_DW6[i].mask) >> WTBL_LMAC_DW6[i].shift); |
| + i++; |
| + } |
| +} |
| + |
| +static void parse_fmac_lwtbl_dw7(struct seq_file *s, u8 *lwtbl) |
| +{ |
| + u32 *addr = 0; |
| + u32 dw_value = 0; |
| + int i = 0; |
| + |
| + /* LMAC WTBL DW 7 */ |
| + seq_printf(s, "\t\n"); |
| + seq_printf(s, "LWTBL DW 7\n"); |
| + addr = (u32 *)&(lwtbl[WTBL_GROUP_TRX_CAP_DW_7*4]); |
| + dw_value = *addr; |
| + |
| + for (i = 0; i < 8; i++) { |
| + seq_printf(s, "\tBA_WIN_SIZE%u:%lu\n", i, ((dw_value & BITS(i*4, i*4+3)) >> i*4)); |
| + } |
| +} |
| + |
| +static const struct berse_wtbl_parse WTBL_LMAC_DW8[] = { |
| + {"RTS_FAIL_CNT_AC0", WF_LWTBL_AC0_RTS_FAIL_CNT_MASK, WF_LWTBL_AC0_RTS_FAIL_CNT_SHIFT, false}, |
| + {"AC1", WF_LWTBL_AC1_RTS_FAIL_CNT_MASK, WF_LWTBL_AC1_RTS_FAIL_CNT_SHIFT, false}, |
| + {"AC2", WF_LWTBL_AC2_RTS_FAIL_CNT_MASK, WF_LWTBL_AC2_RTS_FAIL_CNT_SHIFT, false}, |
| + {"AC3", WF_LWTBL_AC3_RTS_FAIL_CNT_MASK, WF_LWTBL_AC3_RTS_FAIL_CNT_SHIFT, true}, |
| + {"PARTIAL_AID", WF_LWTBL_PARTIAL_AID_MASK, WF_LWTBL_PARTIAL_AID_SHIFT, false}, |
| + {"CHK_PER", WF_LWTBL_CHK_PER_MASK, NO_SHIFT_DEFINE, true}, |
| + {NULL,} |
| +}; |
| + |
| +static void parse_fmac_lwtbl_dw8(struct seq_file *s, u8 *lwtbl) |
| +{ |
| + u32 *addr = 0; |
| + u32 dw_value = 0; |
| + u16 i = 0; |
| + |
| + /* LMAC WTBL DW 8 */ |
| + seq_printf(s, "\t\n"); |
| + seq_printf(s, "LWTBL DW 8\n"); |
| + addr = (u32 *)&(lwtbl[WTBL_GROUP_TRX_CAP_DW_8*4]); |
| + dw_value = *addr; |
| + |
| + while (WTBL_LMAC_DW8[i].name) { |
| + if (WTBL_LMAC_DW8[i].shift == NO_SHIFT_DEFINE) |
| + seq_printf(s, "\t%s:%d\n", WTBL_LMAC_DW8[i].name, |
| + (dw_value & WTBL_LMAC_DW8[i].mask) ? 1 : 0); |
| + else |
| + seq_printf(s, "\t%s:%u\n", WTBL_LMAC_DW8[i].name, |
| + (dw_value & WTBL_LMAC_DW8[i].mask) >> WTBL_LMAC_DW8[i].shift); |
| + i++; |
| + } |
| +} |
| + |
| +static const struct berse_wtbl_parse WTBL_LMAC_DW9[] = { |
| + {"RX_AVG_MPDU_SIZE", WF_LWTBL_RX_AVG_MPDU_SIZE_MASK, WF_LWTBL_RX_AVG_MPDU_SIZE_SHIFT, false}, |
| + {"PRITX_SW_MODE", WF_LWTBL_PRITX_SW_MODE_MASK, NO_SHIFT_DEFINE, false}, |
| + {"PRITX_ERSU", WF_LWTBL_PRITX_ERSU_MASK, NO_SHIFT_DEFINE, false}, |
| + {"PRITX_PLR", WF_LWTBL_PRITX_PLR_MASK, NO_SHIFT_DEFINE, true}, |
| + {"PRITX_DCM", WF_LWTBL_PRITX_DCM_MASK, NO_SHIFT_DEFINE, false}, |
| + {"PRITX_ER106T", WF_LWTBL_PRITX_ER106T_MASK, NO_SHIFT_DEFINE, true}, |
| + /* {"FCAP(0:20 1:~40)", WTBL_FCAP_20_TO_160_MHZ, WTBL_FCAP_20_TO_160_MHZ_OFFSET}, */ |
| + {"MPDU_FAIL_CNT", WF_LWTBL_MPDU_FAIL_CNT_MASK, WF_LWTBL_MPDU_FAIL_CNT_SHIFT, false}, |
| + {"MPDU_OK_CNT", WF_LWTBL_MPDU_OK_CNT_MASK, WF_LWTBL_MPDU_OK_CNT_SHIFT, false}, |
| + {"RATE_IDX", WF_LWTBL_RATE_IDX_MASK, WF_LWTBL_RATE_IDX_SHIFT, true}, |
| + {NULL,} |
| +}; |
| + |
| +char *fcap_name[] = {"20MHz", "20/40MHz", "20/40/80MHz", "20/40/80/160/80+80MHz", "20/40/80/160/80+80/320MHz"}; |
| + |
| +static void parse_fmac_lwtbl_dw9(struct seq_file *s, u8 *lwtbl) |
| +{ |
| + u32 *addr = 0; |
| + u32 dw_value = 0; |
| + u16 i = 0; |
| + |
| + /* LMAC WTBL DW 9 */ |
| + seq_printf(s, "\t\n"); |
| + seq_printf(s, "LWTBL DW 9\n"); |
| + addr = (u32 *)&(lwtbl[WTBL_GROUP_TRX_CAP_DW_9*4]); |
| + dw_value = *addr; |
| + |
| + while (WTBL_LMAC_DW9[i].name) { |
| + if (WTBL_LMAC_DW9[i].shift == NO_SHIFT_DEFINE) |
| + seq_printf(s, "\t%s:%d\n", WTBL_LMAC_DW9[i].name, |
| + (dw_value & WTBL_LMAC_DW9[i].mask) ? 1 : 0); |
| + else |
| + seq_printf(s, "\t%s:%u\n", WTBL_LMAC_DW9[i].name, |
| + (dw_value & WTBL_LMAC_DW9[i].mask) >> WTBL_LMAC_DW9[i].shift); |
| + i++; |
| + } |
| + |
| + /* FCAP parser */ |
| + seq_printf(s, "\t\n"); |
| + seq_printf(s, "FCAP:%s\n", fcap_name[(dw_value & WF_LWTBL_FCAP_MASK) >> WF_LWTBL_FCAP_SHIFT]); |
| +} |
| + |
| +#define HW_TX_RATE_TO_MODE(_x) (((_x) & WTBL_RATE_TX_MODE_MASK) >> WTBL_RATE_TX_MODE_OFFSET) |
| +#define HW_TX_RATE_TO_MCS(_x, _mode) ((_x) & WTBL_RATE_TX_RATE_MASK >> WTBL_RATE_TX_RATE_OFFSET) |
| +#define HW_TX_RATE_TO_NSS(_x) (((_x) & WTBL_RATE_NSTS_MASK) >> WTBL_RATE_NSTS_OFFSET) |
| +#define HW_TX_RATE_TO_STBC(_x) (((_x) & WTBL_RATE_STBC_MASK) >> WTBL_RATE_STBC_OFFSET) |
| + |
| +#define MAX_TX_MODE 16 |
| +static char *HW_TX_MODE_STR[] = {"CCK", "OFDM", "HT-Mix", "HT-GF", "VHT", |
| + "N/A", "N/A", "N/A", |
| + "HE_SU", "HE_EXT_SU", "HE_TRIG", "HE_MU", |
| + "N/A", |
| + "EHT_EXT_SU", "EHT_TRIG", "EHT_MU", |
| + "N/A"}; |
| +static char *HW_TX_RATE_CCK_STR[] = {"1M", "2Mlong", "5.5Mlong", "11Mlong", "N/A", "2Mshort", "5.5Mshort", "11Mshort", "N/A"}; |
| +static char *HW_TX_RATE_OFDM_STR[] = {"6M", "9M", "12M", "18M", "24M", "36M", "48M", "54M", "N/A"}; |
| + |
| +static char *hw_rate_ofdm_str(uint16_t ofdm_idx) |
| +{ |
| + switch (ofdm_idx) { |
| + case 11: /* 6M */ |
| + return HW_TX_RATE_OFDM_STR[0]; |
| + |
| + case 15: /* 9M */ |
| + return HW_TX_RATE_OFDM_STR[1]; |
| + |
| + case 10: /* 12M */ |
| + return HW_TX_RATE_OFDM_STR[2]; |
| + |
| + case 14: /* 18M */ |
| + return HW_TX_RATE_OFDM_STR[3]; |
| + |
| + case 9: /* 24M */ |
| + return HW_TX_RATE_OFDM_STR[4]; |
| + |
| + case 13: /* 36M */ |
| + return HW_TX_RATE_OFDM_STR[5]; |
| + |
| + case 8: /* 48M */ |
| + return HW_TX_RATE_OFDM_STR[6]; |
| + |
| + case 12: /* 54M */ |
| + return HW_TX_RATE_OFDM_STR[7]; |
| + |
| + default: |
| + return HW_TX_RATE_OFDM_STR[8]; |
| + } |
| +} |
| + |
| +static char *hw_rate_str(u8 mode, uint16_t rate_idx) |
| +{ |
| + if (mode == 0) |
| + return rate_idx < 8 ? HW_TX_RATE_CCK_STR[rate_idx] : HW_TX_RATE_CCK_STR[8]; |
| + else if (mode == 1) |
| + return hw_rate_ofdm_str(rate_idx); |
| + else |
| + return "MCS"; |
| +} |
| + |
| +static void |
| +parse_rate(struct seq_file *s, uint16_t rate_idx, uint16_t txrate) |
| +{ |
| + uint16_t txmode, mcs, nss, stbc; |
| + |
| + txmode = HW_TX_RATE_TO_MODE(txrate); |
| + mcs = HW_TX_RATE_TO_MCS(txrate, txmode); |
| + nss = HW_TX_RATE_TO_NSS(txrate); |
| + stbc = HW_TX_RATE_TO_STBC(txrate); |
| + |
| + seq_printf(s, "\tRate%d(0x%x):TxMode=%d(%s), TxRate=%d(%s), Nsts=%d, STBC=%d\n", |
| + rate_idx + 1, txrate, |
| + txmode, (txmode < MAX_TX_MODE ? HW_TX_MODE_STR[txmode] : HW_TX_MODE_STR[MAX_TX_MODE]), |
| + mcs, hw_rate_str(txmode, mcs), nss, stbc); |
| +} |
| + |
| + |
| +static const struct berse_wtbl_parse WTBL_LMAC_DW10[] = { |
| + {"RATE1", WF_LWTBL_RATE1_MASK, WF_LWTBL_RATE1_SHIFT}, |
| + {"RATE2", WF_LWTBL_RATE2_MASK, WF_LWTBL_RATE2_SHIFT}, |
| + {NULL,} |
| +}; |
| + |
| +static void parse_fmac_lwtbl_dw10(struct seq_file *s, u8 *lwtbl) |
| +{ |
| + u32 *addr = 0; |
| + u32 dw_value = 0; |
| + u16 i = 0; |
| + |
| + /* LMAC WTBL DW 10 */ |
| + seq_printf(s, "\t\n"); |
| + seq_printf(s, "LWTBL DW 10\n"); |
| + addr = (u32 *)&(lwtbl[WTBL_GROUP_AUTO_RATE_1_2*4]); |
| + dw_value = *addr; |
| + |
| + while (WTBL_LMAC_DW10[i].name) { |
| + parse_rate(s, i, (dw_value & WTBL_LMAC_DW10[i].mask) >> WTBL_LMAC_DW10[i].shift); |
| + i++; |
| + } |
| +} |
| + |
| +static const struct berse_wtbl_parse WTBL_LMAC_DW11[] = { |
| + {"RATE3", WF_LWTBL_RATE3_MASK, WF_LWTBL_RATE3_SHIFT}, |
| + {"RATE4", WF_LWTBL_RATE4_MASK, WF_LWTBL_RATE4_SHIFT}, |
| + {NULL,} |
| +}; |
| + |
| +static void parse_fmac_lwtbl_dw11(struct seq_file *s, u8 *lwtbl) |
| +{ |
| + u32 *addr = 0; |
| + u32 dw_value = 0; |
| + u16 i = 0; |
| + |
| + /* LMAC WTBL DW 11 */ |
| + seq_printf(s, "\t\n"); |
| + seq_printf(s, "LWTBL DW 11\n"); |
| + addr = (u32 *)&(lwtbl[WTBL_GROUP_AUTO_RATE_3_4*4]); |
| + dw_value = *addr; |
| + |
| + while (WTBL_LMAC_DW11[i].name) { |
| + parse_rate(s, i+2, (dw_value & WTBL_LMAC_DW11[i].mask) >> WTBL_LMAC_DW11[i].shift); |
| + i++; |
| + } |
| +} |
| + |
| +static const struct berse_wtbl_parse WTBL_LMAC_DW12[] = { |
| + {"RATE5", WF_LWTBL_RATE5_MASK, WF_LWTBL_RATE5_SHIFT}, |
| + {"RATE6", WF_LWTBL_RATE6_MASK, WF_LWTBL_RATE6_SHIFT}, |
| + {NULL,} |
| +}; |
| + |
| +static void parse_fmac_lwtbl_dw12(struct seq_file *s, u8 *lwtbl) |
| +{ |
| + u32 *addr = 0; |
| + u32 dw_value = 0; |
| + u16 i = 0; |
| + |
| + /* LMAC WTBL DW 12 */ |
| + seq_printf(s, "\t\n"); |
| + seq_printf(s, "LWTBL DW 12\n"); |
| + addr = (u32 *)&(lwtbl[WTBL_GROUP_AUTO_RATE_5_6*4]); |
| + dw_value = *addr; |
| + |
| + while (WTBL_LMAC_DW12[i].name) { |
| + parse_rate(s, i+4, (dw_value & WTBL_LMAC_DW12[i].mask) >> WTBL_LMAC_DW12[i].shift); |
| + i++; |
| + } |
| +} |
| + |
| +static const struct berse_wtbl_parse WTBL_LMAC_DW13[] = { |
| + {"RATE7", WF_LWTBL_RATE7_MASK, WF_LWTBL_RATE7_SHIFT}, |
| + {"RATE8", WF_LWTBL_RATE8_MASK, WF_LWTBL_RATE8_SHIFT}, |
| + {NULL,} |
| +}; |
| + |
| +static void parse_fmac_lwtbl_dw13(struct seq_file *s, u8 *lwtbl) |
| +{ |
| + u32 *addr = 0; |
| + u32 dw_value = 0; |
| + u16 i = 0; |
| + |
| + /* LMAC WTBL DW 13 */ |
| + seq_printf(s, "\t\n"); |
| + seq_printf(s, "LWTBL DW 13\n"); |
| + addr = (u32 *)&(lwtbl[WTBL_GROUP_AUTO_RATE_7_8*4]); |
| + dw_value = *addr; |
| + |
| + while (WTBL_LMAC_DW13[i].name) { |
| + parse_rate(s, i+6, (dw_value & WTBL_LMAC_DW13[i].mask) >> WTBL_LMAC_DW13[i].shift); |
| + i++; |
| + } |
| +} |
| + |
| +static const struct berse_wtbl_parse WTBL_LMAC_DW14_BMC[] = { |
| + {"CIPHER_IGTK", WF_LWTBL_CIPHER_SUIT_IGTK_MASK, WF_LWTBL_CIPHER_SUIT_IGTK_SHIFT, false}, |
| + {"CIPHER_BIGTK", WF_LWTBL_CIPHER_SUIT_BIGTK_MASK, WF_LWTBL_CIPHER_SUIT_BIGTK_SHIFT, true}, |
| + {NULL,} |
| +}; |
| + |
| +static void parse_fmac_lwtbl_dw14(struct seq_file *s, u8 *lwtbl) |
| +{ |
| + u32 *addr, *muar_addr = 0; |
| + u32 dw_value, muar_dw_value = 0; |
| + u16 i = 0; |
| + |
| + /* DUMP DW14 for BMC entry only */ |
| + muar_addr = (u32 *)&(lwtbl[WF_LWTBL_MUAR_DW*4]); |
| + muar_dw_value = *muar_addr; |
| + if (((muar_dw_value & WF_LWTBL_MUAR_MASK) >> WF_LWTBL_MUAR_SHIFT) |
| + == MUAR_INDEX_OWN_MAC_ADDR_BC_MC) { |
| + /* LMAC WTBL DW 14 */ |
| + seq_printf(s, "\t\n"); |
| + seq_printf(s, "LWTBL DW 14\n"); |
| + addr = (u32 *)&(lwtbl[WF_LWTBL_CIPHER_SUIT_IGTK_DW*4]); |
| + dw_value = *addr; |
| + |
| + while (WTBL_LMAC_DW14_BMC[i].name) { |
| + parse_rate(s, i+6, (dw_value & WTBL_LMAC_DW14_BMC[i].mask) >> WTBL_LMAC_DW14_BMC[i].shift); |
| + i++; |
| + } |
| + } |
| +} |
| + |
| +static const struct berse_wtbl_parse WTBL_LMAC_DW28[] = { |
| + {"RELATED_IDX0", WF_LWTBL_RELATED_IDX0_MASK, WF_LWTBL_RELATED_IDX0_SHIFT, false}, |
| + {"RELATED_BAND0", WF_LWTBL_RELATED_BAND0_MASK, WF_LWTBL_RELATED_BAND0_SHIFT, false}, |
| + {"PRI_MLD_BAND", WF_LWTBL_PRIMARY_MLD_BAND_MASK, WF_LWTBL_PRIMARY_MLD_BAND_SHIFT, true}, |
| + {"RELATED_IDX0", WF_LWTBL_RELATED_IDX1_MASK, WF_LWTBL_RELATED_IDX1_SHIFT, false}, |
| + {"RELATED_BAND1", WF_LWTBL_RELATED_BAND1_MASK, WF_LWTBL_RELATED_BAND1_SHIFT, false}, |
| + {"SEC_MLD_BAND", WF_LWTBL_SECONDARY_MLD_BAND_MASK, WF_LWTBL_SECONDARY_MLD_BAND_SHIFT, true}, |
| + {NULL,} |
| +}; |
| + |
| +static void parse_fmac_lwtbl_dw28(struct seq_file *s, u8 *lwtbl) |
| +{ |
| + u32 *addr = 0; |
| + u32 dw_value = 0; |
| + u16 i = 0; |
| + |
| + /* LMAC WTBL DW 28 */ |
| + seq_printf(s, "\t\n"); |
| + seq_printf(s, "LWTBL DW 28\n"); |
| + addr = (u32 *)&(lwtbl[WTBL_GROUP_MLO_INFO_LINE_1*4]); |
| + dw_value = *addr; |
| + |
| + while (WTBL_LMAC_DW28[i].name) { |
| + if (WTBL_LMAC_DW28[i].shift == NO_SHIFT_DEFINE) |
| + seq_printf(s, "\t%s:%d\n", WTBL_LMAC_DW28[i].name, |
| + (dw_value & WTBL_LMAC_DW28[i].mask) ? 1 : 0); |
| + else |
| + seq_printf(s, "\t%s:%u\n", WTBL_LMAC_DW28[i].name, |
| + (dw_value & WTBL_LMAC_DW28[i].mask) >> |
| + WTBL_LMAC_DW28[i].shift); |
| + i++; |
| + } |
| +} |
| + |
| +static const struct berse_wtbl_parse WTBL_LMAC_DW29[] = { |
| + {"DISPATCH_POLICY_MLD_TID0", WF_LWTBL_DISPATCH_POLICY0_MASK, WF_LWTBL_DISPATCH_POLICY0_SHIFT, false}, |
| + {"MLD_TID1", WF_LWTBL_DISPATCH_POLICY1_MASK, WF_LWTBL_DISPATCH_POLICY1_SHIFT, false}, |
| + {"MLD_TID2", WF_LWTBL_DISPATCH_POLICY2_MASK, WF_LWTBL_DISPATCH_POLICY2_SHIFT, false}, |
| + {"MLD_TID3", WF_LWTBL_DISPATCH_POLICY3_MASK, WF_LWTBL_DISPATCH_POLICY3_SHIFT, true}, |
| + {"MLD_TID4", WF_LWTBL_DISPATCH_POLICY4_MASK, WF_LWTBL_DISPATCH_POLICY4_SHIFT, false}, |
| + {"MLD_TID5", WF_LWTBL_DISPATCH_POLICY5_MASK, WF_LWTBL_DISPATCH_POLICY5_SHIFT, false}, |
| + {"MLD_TID6", WF_LWTBL_DISPATCH_POLICY6_MASK, WF_LWTBL_DISPATCH_POLICY6_SHIFT, false}, |
| + {"MLD_TID7", WF_LWTBL_DISPATCH_POLICY7_MASK, WF_LWTBL_DISPATCH_POLICY7_SHIFT, true}, |
| + {"OMLD_ID", WF_LWTBL_OWN_MLD_ID_MASK, WF_LWTBL_OWN_MLD_ID_SHIFT, false}, |
| + {"EMLSR0", WF_LWTBL_EMLSR0_MASK, NO_SHIFT_DEFINE, false}, |
| + {"EMLMR0", WF_LWTBL_EMLMR0_MASK, NO_SHIFT_DEFINE, false}, |
| + {"EMLSR1", WF_LWTBL_EMLSR1_MASK, NO_SHIFT_DEFINE, false}, |
| + {"EMLMR1", WF_LWTBL_EMLMR1_MASK, NO_SHIFT_DEFINE, true}, |
| + {"EMLSR2", WF_LWTBL_EMLSR2_MASK, NO_SHIFT_DEFINE, false}, |
| + {"EMLMR2", WF_LWTBL_EMLMR2_MASK, NO_SHIFT_DEFINE, false}, |
| + {"STR_BITMAP", WF_LWTBL_STR_BITMAP_MASK, WF_LWTBL_STR_BITMAP_SHIFT, true}, |
| + {NULL,} |
| +}; |
| + |
| +static void parse_fmac_lwtbl_dw29(struct seq_file *s, u8 *lwtbl) |
| +{ |
| + u32 *addr = 0; |
| + u32 dw_value = 0; |
| + u16 i = 0; |
| + |
| + /* LMAC WTBL DW 29 */ |
| + seq_printf(s, "\t\n"); |
| + seq_printf(s, "LWTBL DW 29\n"); |
| + addr = (u32 *)&(lwtbl[WTBL_GROUP_MLO_INFO_LINE_2*4]); |
| + dw_value = *addr; |
| + |
| + while (WTBL_LMAC_DW29[i].name) { |
| + if (WTBL_LMAC_DW29[i].shift == NO_SHIFT_DEFINE) |
| + seq_printf(s, "\t%s:%d\n", WTBL_LMAC_DW29[i].name, |
| + (dw_value & WTBL_LMAC_DW29[i].mask) ? 1 : 0); |
| + else |
| + seq_printf(s, "\t%s:%u\n", WTBL_LMAC_DW29[i].name, |
| + (dw_value & WTBL_LMAC_DW29[i].mask) >> |
| + WTBL_LMAC_DW29[i].shift); |
| + i++; |
| + } |
| +} |
| + |
| +static const struct berse_wtbl_parse WTBL_LMAC_DW30[] = { |
| + {"DISPATCH_ORDER", WF_LWTBL_DISPATCH_ORDER_MASK, WF_LWTBL_DISPATCH_ORDER_SHIFT, false}, |
| + {"DISPATCH_RATIO", WF_LWTBL_DISPATCH_RATIO_MASK, WF_LWTBL_DISPATCH_RATIO_SHIFT, false}, |
| + {"LINK_MGF", WF_LWTBL_LINK_MGF_MASK, WF_LWTBL_LINK_MGF_SHIFT, true}, |
| + {NULL,} |
| +}; |
| + |
| +static void parse_fmac_lwtbl_dw30(struct seq_file *s, u8 *lwtbl) |
| +{ |
| + u32 *addr = 0; |
| + u32 dw_value = 0; |
| + u16 i = 0; |
| + |
| + /* LMAC WTBL DW 30 */ |
| + seq_printf(s, "\t\n"); |
| + seq_printf(s, "LWTBL DW 30\n"); |
| + addr = (u32 *)&(lwtbl[WTBL_GROUP_MLO_INFO_LINE_3*4]); |
| + dw_value = *addr; |
| + |
| + |
| + while (WTBL_LMAC_DW30[i].name) { |
| + if (WTBL_LMAC_DW30[i].shift == NO_SHIFT_DEFINE) |
| + seq_printf(s, "\t%s:%d\n", WTBL_LMAC_DW30[i].name, |
| + (dw_value & WTBL_LMAC_DW30[i].mask) ? 1 : 0); |
| + else |
| + seq_printf(s, "\t%s:%u\n", WTBL_LMAC_DW30[i].name, |
| + (dw_value & WTBL_LMAC_DW30[i].mask) >> WTBL_LMAC_DW30[i].shift); |
| + i++; |
| + } |
| +} |
| + |
| +static const struct berse_wtbl_parse WTBL_LMAC_DW31[] = { |
| + {"NEGO_WINSIZE0", WF_LWTBL_NEGOTIATED_WINSIZE0_MASK, WF_LWTBL_NEGOTIATED_WINSIZE0_SHIFT, false}, |
| + {"WINSIZE1", WF_LWTBL_NEGOTIATED_WINSIZE1_MASK, WF_LWTBL_NEGOTIATED_WINSIZE1_SHIFT, false}, |
| + {"WINSIZE2", WF_LWTBL_NEGOTIATED_WINSIZE2_MASK, WF_LWTBL_NEGOTIATED_WINSIZE2_SHIFT, false}, |
| + {"WINSIZE3", WF_LWTBL_NEGOTIATED_WINSIZE3_MASK, WF_LWTBL_NEGOTIATED_WINSIZE3_SHIFT, true}, |
| + {"WINSIZE4", WF_LWTBL_NEGOTIATED_WINSIZE4_MASK, WF_LWTBL_NEGOTIATED_WINSIZE4_SHIFT, false}, |
| + {"WINSIZE5", WF_LWTBL_NEGOTIATED_WINSIZE5_MASK, WF_LWTBL_NEGOTIATED_WINSIZE5_SHIFT, false}, |
| + {"WINSIZE6", WF_LWTBL_NEGOTIATED_WINSIZE6_MASK, WF_LWTBL_NEGOTIATED_WINSIZE6_SHIFT, false}, |
| + {"WINSIZE7", WF_LWTBL_NEGOTIATED_WINSIZE7_MASK, WF_LWTBL_NEGOTIATED_WINSIZE7_SHIFT, true}, |
| + {"CASCAD", WF_LWTBL_CASCAD_MASK, NO_SHIFT_DEFINE, false}, |
| + {"ALL_ACK", WF_LWTBL_ALL_ACK_MASK, NO_SHIFT_DEFINE, false}, |
| + {"MPDU_SIZE", WF_LWTBL_MPDU_SIZE_MASK, WF_LWTBL_MPDU_SIZE_SHIFT, false}, |
| + {"BA_MODE", WF_LWTBL_BA_MODE_MASK, WF_LWTBL_BA_MODE_SHIFT, true}, |
| + {NULL,} |
| +}; |
| + |
| +static void parse_fmac_lwtbl_dw31(struct seq_file *s, u8 *lwtbl) |
| +{ |
| + u32 *addr = 0; |
| + u32 dw_value = 0; |
| + u16 i = 0; |
| + |
| + /* LMAC WTBL DW 31 */ |
| + seq_printf(s, "\t\n"); |
| + seq_printf(s, "LWTBL DW 31\n"); |
| + addr = (u32 *)&(lwtbl[WTBL_GROUP_RESP_INFO_DW_31*4]); |
| + dw_value = *addr; |
| + |
| + while (WTBL_LMAC_DW31[i].name) { |
| + if (WTBL_LMAC_DW31[i].shift == NO_SHIFT_DEFINE) |
| + seq_printf(s, "\t%s:%d\n", WTBL_LMAC_DW31[i].name, |
| + (dw_value & WTBL_LMAC_DW31[i].mask) ? 1 : 0); |
| + else |
| + seq_printf(s, "\t%s:%u\n", WTBL_LMAC_DW31[i].name, |
| + (dw_value & WTBL_LMAC_DW31[i].mask) >> |
| + WTBL_LMAC_DW31[i].shift); |
| + i++; |
| + } |
| +} |
| + |
| +static const struct berse_wtbl_parse WTBL_LMAC_DW32[] = { |
| + {"OM_INFO", WF_LWTBL_OM_INFO_MASK, WF_LWTBL_OM_INFO_SHIFT, false}, |
| + {"OM_RXD_DUP_MODE", WF_LWTBL_RXD_DUP_FOR_OM_CHG_MASK, NO_SHIFT_DEFINE, false}, |
| + {"RXD_DUP_WHITE_LIST", WF_LWTBL_RXD_DUP_WHITE_LIST_MASK, WF_LWTBL_RXD_DUP_WHITE_LIST_SHIFT, false}, |
| + {"RXD_DUP_MODE", WF_LWTBL_RXD_DUP_MODE_MASK, WF_LWTBL_RXD_DUP_MODE_SHIFT, false}, |
| + {"DROP", WF_LWTBL_DROP_MASK, NO_SHIFT_DEFINE, false}, |
| + {"ACK_EN", WF_LWTBL_ACK_EN_MASK, NO_SHIFT_DEFINE, true}, |
| + {NULL,} |
| +}; |
| + |
| +static void parse_fmac_lwtbl_dw32(struct seq_file *s, u8 *lwtbl) |
| +{ |
| + u32 *addr = 0; |
| + u32 dw_value = 0; |
| + u16 i = 0; |
| + |
| + /* LMAC WTBL DW 32 */ |
| + seq_printf(s, "\t\n"); |
| + seq_printf(s, "LWTBL DW 32\n"); |
| + addr = (u32 *)&(lwtbl[WTBL_GROUP_RX_DUP_INFO_DW_32*4]); |
| + dw_value = *addr; |
| + |
| + while (WTBL_LMAC_DW32[i].name) { |
| + if (WTBL_LMAC_DW32[i].shift == NO_SHIFT_DEFINE) |
| + seq_printf(s, "\t%s:%d\n", WTBL_LMAC_DW32[i].name, |
| + (dw_value & WTBL_LMAC_DW32[i].mask) ? 1 : 0); |
| + else |
| + seq_printf(s, "\t%s:%u\n", WTBL_LMAC_DW32[i].name, |
| + (dw_value & WTBL_LMAC_DW32[i].mask) >> |
| + WTBL_LMAC_DW32[i].shift); |
| + i++; |
| + } |
| +} |
| + |
| +static const struct berse_wtbl_parse WTBL_LMAC_DW33[] = { |
| + {"USER_RSSI", WF_LWTBL_USER_RSSI_MASK, WF_LWTBL_USER_RSSI_SHIFT, false}, |
| + {"USER_SNR", WF_LWTBL_USER_SNR_MASK, WF_LWTBL_USER_SNR_SHIFT, false}, |
| + {"RAPID_REACTION_RATE", WF_LWTBL_RAPID_REACTION_RATE_MASK, WF_LWTBL_RAPID_REACTION_RATE_SHIFT, true}, |
| + {"HT_AMSDU(Read Only)", WF_LWTBL_HT_AMSDU_MASK, NO_SHIFT_DEFINE, false}, |
| + {"AMSDU_CROSS_LG(Read Only)", WF_LWTBL_AMSDU_CROSS_LG_MASK, NO_SHIFT_DEFINE, true}, |
| + {NULL,} |
| +}; |
| + |
| +static void parse_fmac_lwtbl_dw33(struct seq_file *s, u8 *lwtbl) |
| +{ |
| + u32 *addr = 0; |
| + u32 dw_value = 0; |
| + u16 i = 0; |
| + |
| + /* LMAC WTBL DW 33 */ |
| + seq_printf(s, "\t\n"); |
| + seq_printf(s, "LWTBL DW 33\n"); |
| + addr = (u32 *)&(lwtbl[WTBL_GROUP_RX_STAT_CNT_LINE_1*4]); |
| + dw_value = *addr; |
| + |
| + while (WTBL_LMAC_DW33[i].name) { |
| + if (WTBL_LMAC_DW33[i].shift == NO_SHIFT_DEFINE) |
| + seq_printf(s, "\t%s:%d\n", WTBL_LMAC_DW33[i].name, |
| + (dw_value & WTBL_LMAC_DW33[i].mask) ? 1 : 0); |
| + else |
| + seq_printf(s, "\t%s:%u\n", WTBL_LMAC_DW33[i].name, |
| + (dw_value & WTBL_LMAC_DW33[i].mask) >> |
| + WTBL_LMAC_DW33[i].shift); |
| + i++; |
| + } |
| +} |
| + |
| +static const struct berse_wtbl_parse WTBL_LMAC_DW34[] = { |
| + {"RESP_RCPI0", WF_LWTBL_RESP_RCPI0_MASK, WF_LWTBL_RESP_RCPI0_SHIFT, false}, |
| + {"RCPI1", WF_LWTBL_RESP_RCPI1_MASK, WF_LWTBL_RESP_RCPI1_SHIFT, false}, |
| + {"RCPI2", WF_LWTBL_RESP_RCPI2_MASK, WF_LWTBL_RESP_RCPI2_SHIFT, false}, |
| + {"RCPI3", WF_LWTBL_RESP_RCPI3_MASK, WF_LWTBL_RESP_RCPI3_SHIFT, true}, |
| + {NULL,} |
| +}; |
| + |
| +static void parse_fmac_lwtbl_dw34(struct seq_file *s, u8 *lwtbl) |
| +{ |
| + u32 *addr = 0; |
| + u32 dw_value = 0; |
| + u16 i = 0; |
| + |
| + /* LMAC WTBL DW 34 */ |
| + seq_printf(s, "\t\n"); |
| + seq_printf(s, "LWTBL DW 34\n"); |
| + addr = (u32 *)&(lwtbl[WTBL_GROUP_RX_STAT_CNT_LINE_2*4]); |
| + dw_value = *addr; |
| + |
| + |
| + while (WTBL_LMAC_DW34[i].name) { |
| + if (WTBL_LMAC_DW34[i].shift == NO_SHIFT_DEFINE) |
| + seq_printf(s, "\t%s:%d\n", WTBL_LMAC_DW34[i].name, |
| + (dw_value & WTBL_LMAC_DW34[i].mask) ? 1 : 0); |
| + else |
| + seq_printf(s, "\t%s:%u\n", WTBL_LMAC_DW34[i].name, |
| + (dw_value & WTBL_LMAC_DW34[i].mask) >> |
| + WTBL_LMAC_DW34[i].shift); |
| + i++; |
| + } |
| +} |
| + |
| +static const struct berse_wtbl_parse WTBL_LMAC_DW35[] = { |
| + {"SNR 0", WF_LWTBL_SNR_RX0_MASK, WF_LWTBL_SNR_RX0_SHIFT, false}, |
| + {"SNR 1", WF_LWTBL_SNR_RX1_MASK, WF_LWTBL_SNR_RX1_SHIFT, false}, |
| + {"SNR 2", WF_LWTBL_SNR_RX2_MASK, WF_LWTBL_SNR_RX2_SHIFT, false}, |
| + {"SNR 3", WF_LWTBL_SNR_RX3_MASK, WF_LWTBL_SNR_RX3_SHIFT, true}, |
| + {NULL,} |
| +}; |
| + |
| +static void parse_fmac_lwtbl_dw35(struct seq_file *s, u8 *lwtbl) |
| +{ |
| + u32 *addr = 0; |
| + u32 dw_value = 0; |
| + u16 i = 0; |
| + |
| + /* LMAC WTBL DW 35 */ |
| + seq_printf(s, "\t\n"); |
| + seq_printf(s, "LWTBL DW 35\n"); |
| + addr = (u32 *)&(lwtbl[WTBL_GROUP_RX_STAT_CNT_LINE_3*4]); |
| + dw_value = *addr; |
| + |
| + |
| + while (WTBL_LMAC_DW35[i].name) { |
| + if (WTBL_LMAC_DW35[i].shift == NO_SHIFT_DEFINE) |
| + seq_printf(s, "\t%s:%d\n", WTBL_LMAC_DW35[i].name, |
| + (dw_value & WTBL_LMAC_DW35[i].mask) ? 1 : 0); |
| + else |
| + seq_printf(s, "\t%s:%u\n", WTBL_LMAC_DW35[i].name, |
| + (dw_value & WTBL_LMAC_DW35[i].mask) >> |
| + WTBL_LMAC_DW35[i].shift); |
| + i++; |
| + } |
| +} |
| + |
| +static void parse_fmac_lwtbl_rx_stats(struct seq_file *s, u8 *lwtbl) |
| +{ |
| + parse_fmac_lwtbl_dw33(s, lwtbl); |
| + parse_fmac_lwtbl_dw34(s, lwtbl); |
| + parse_fmac_lwtbl_dw35(s, lwtbl); |
| +} |
| + |
| +static void parse_fmac_lwtbl_mlo_info(struct seq_file *s, u8 *lwtbl) |
| +{ |
| + parse_fmac_lwtbl_dw28(s, lwtbl); |
| + parse_fmac_lwtbl_dw29(s, lwtbl); |
| + parse_fmac_lwtbl_dw30(s, lwtbl); |
| +} |
| + |
| +static const struct berse_wtbl_parse WTBL_UMAC_DW9[] = { |
| + {"RELATED_IDX0", WF_UWTBL_RELATED_IDX0_MASK, WF_UWTBL_RELATED_IDX0_SHIFT, false}, |
| + {"RELATED_BAND0", WF_UWTBL_RELATED_BAND0_MASK, WF_UWTBL_RELATED_BAND0_SHIFT, false}, |
| + {"PRI_MLD_BAND", WF_UWTBL_PRIMARY_MLD_BAND_MASK, WF_UWTBL_PRIMARY_MLD_BAND_SHIFT, true}, |
| + {"RELATED_IDX0", WF_UWTBL_RELATED_IDX1_MASK, WF_UWTBL_RELATED_IDX1_SHIFT, false}, |
| + {"RELATED_BAND1", WF_UWTBL_RELATED_BAND1_MASK, WF_UWTBL_RELATED_BAND1_SHIFT, false}, |
| + {"SEC_MLD_BAND", WF_UWTBL_SECONDARY_MLD_BAND_MASK, WF_UWTBL_SECONDARY_MLD_BAND_SHIFT, true}, |
| + {NULL,} |
| +}; |
| + |
| +static void parse_fmac_uwtbl_mlo_info(struct seq_file *s, u8 *uwtbl) |
| +{ |
| + u32 *addr = 0; |
| + u32 dw_value = 0; |
| + u16 i = 0; |
| + |
| + seq_printf(s, "\t\n"); |
| + seq_printf(s, "MldAddr: %02x:%02x:%02x:%02x:%02x:%02x(D0[B0~15], D1[B0~31])\n", |
| + uwtbl[4], uwtbl[5], uwtbl[6], uwtbl[7], uwtbl[0], uwtbl[1]); |
| + |
| + /* UMAC WTBL DW 0 */ |
| + seq_printf(s, "\t\n"); |
| + seq_printf(s, "UWTBL DW 0\n"); |
| + addr = (u32 *)&(uwtbl[WF_UWTBL_OWN_MLD_ID_DW*4]); |
| + dw_value = *addr; |
| + |
| + seq_printf(s, "\t%s:%u\n", "OMLD_ID", |
| + (dw_value & WF_UWTBL_OWN_MLD_ID_MASK) >> WF_UWTBL_OWN_MLD_ID_SHIFT); |
| + |
| + /* UMAC WTBL DW 9 */ |
| + seq_printf(s, "\t\n"); |
| + seq_printf(s, "UWTBL DW 9\n"); |
| + addr = (u32 *)&(uwtbl[WF_UWTBL_RELATED_IDX0_DW*4]); |
| + dw_value = *addr; |
| + |
| + while (WTBL_UMAC_DW9[i].name) { |
| + |
| + if (WTBL_UMAC_DW9[i].shift == NO_SHIFT_DEFINE) |
| + seq_printf(s, "\t%s:%d\n", WTBL_UMAC_DW9[i].name, |
| + (dw_value & WTBL_UMAC_DW9[i].mask) ? 1 : 0); |
| + else |
| + seq_printf(s, "\t%s:%u\n", WTBL_UMAC_DW9[i].name, |
| + (dw_value & WTBL_UMAC_DW9[i].mask) >> |
| + WTBL_UMAC_DW9[i].shift); |
| + i++; |
| + } |
| +} |
| + |
| +static bool |
| +is_wtbl_bigtk_exist(u8 *lwtbl) |
| +{ |
| + u32 *addr = 0; |
| + u32 dw_value = 0; |
| + |
| + addr = (u32 *)&(lwtbl[WF_LWTBL_MUAR_DW*4]); |
| + dw_value = *addr; |
| + if (((dw_value & WF_LWTBL_MUAR_MASK) >> WF_LWTBL_MUAR_SHIFT) == |
| + MUAR_INDEX_OWN_MAC_ADDR_BC_MC) { |
| + addr = (u32 *)&(lwtbl[WF_LWTBL_CIPHER_SUIT_BIGTK_DW*4]); |
| + dw_value = *addr; |
| + if (((dw_value & WF_LWTBL_CIPHER_SUIT_BIGTK_MASK) >> |
| + WF_LWTBL_CIPHER_SUIT_BIGTK_SHIFT) != IGTK_CIPHER_SUIT_NONE) |
| + return true; |
| + } |
| + |
| + return false; |
| +} |
| + |
| +static const struct berse_wtbl_parse WTBL_UMAC_DW2[] = { |
| + {"PN0", WTBL_PN0_MASK, WTBL_PN0_OFFSET, false}, |
| + {"PN1", WTBL_PN1_MASK, WTBL_PN1_OFFSET, false}, |
| + {"PN2", WTBL_PN2_MASK, WTBL_PN2_OFFSET, true}, |
| + {"PN3", WTBL_PN3_MASK, WTBL_PN3_OFFSET, false}, |
| + {NULL,} |
| +}; |
| + |
| +static const struct berse_wtbl_parse WTBL_UMAC_DW3[] = { |
| + {"PN4", WTBL_PN4_MASK, WTBL_PN4_OFFSET, false}, |
| + {"PN5", WTBL_PN5_MASK, WTBL_PN5_OFFSET, true}, |
| + {NULL,} |
| +}; |
| + |
| +static const struct berse_wtbl_parse WTBL_UMAC_DW4_BIPN[] = { |
| + {"BIPN0", WTBL_BIPN0_MASK, WTBL_BIPN0_OFFSET, false}, |
| + {"BIPN1", WTBL_BIPN1_MASK, WTBL_BIPN1_OFFSET, false}, |
| + {"BIPN2", WTBL_BIPN2_MASK, WTBL_BIPN2_OFFSET, true}, |
| + {"BIPN3", WTBL_BIPN3_MASK, WTBL_BIPN3_OFFSET, false}, |
| + {NULL,} |
| +}; |
| + |
| +static const struct berse_wtbl_parse WTBL_UMAC_DW5_BIPN[] = { |
| + {"BIPN4", WTBL_BIPN0_MASK, WTBL_BIPN0_OFFSET, false}, |
| + {"BIPN5", WTBL_BIPN1_MASK, WTBL_BIPN1_OFFSET, true}, |
| + {NULL,} |
| +}; |
| + |
| +static void parse_fmac_uwtbl_pn(struct seq_file *s, u8 *uwtbl, u8 *lwtbl) |
| +{ |
| + u32 *addr = 0; |
| + u32 dw_value = 0; |
| + u16 i = 0; |
| + |
| + seq_printf(s, "\t\n"); |
| + seq_printf(s, "UWTBL PN\n"); |
| + |
| + /* UMAC WTBL DW 2/3 */ |
| + addr = (u32 *)&(uwtbl[WF_UWTBL_PN_31_0__DW*4]); |
| + dw_value = *addr; |
| + |
| + while (WTBL_UMAC_DW2[i].name) { |
| + seq_printf(s, "\t%s:%u\n", WTBL_UMAC_DW2[i].name, |
| + (dw_value & WTBL_UMAC_DW2[i].mask) >> |
| + WTBL_UMAC_DW2[i].shift); |
| + i++; |
| + } |
| + |
| + i = 0; |
| + addr = (u32 *)&(uwtbl[WF_UWTBL_PN_47_32__DW*4]); |
| + dw_value = *addr; |
| + |
| + while (WTBL_UMAC_DW3[i].name) { |
| + seq_printf(s, "\t%s:%u\n", WTBL_UMAC_DW3[i].name, |
| + (dw_value & WTBL_UMAC_DW3[i].mask) >> |
| + WTBL_UMAC_DW3[i].shift); |
| + i++; |
| + } |
| + |
| + |
| + /* UMAC WTBL DW 4/5 for BIGTK */ |
| + if (is_wtbl_bigtk_exist(lwtbl) == true) { |
| + i = 0; |
| + addr = (u32 *)&(uwtbl[WF_UWTBL_RX_BIPN_31_0__DW*4]); |
| + dw_value = *addr; |
| + |
| + while (WTBL_UMAC_DW4_BIPN[i].name) { |
| + seq_printf(s, "\t%s:%u\n", WTBL_UMAC_DW4_BIPN[i].name, |
| + (dw_value & WTBL_UMAC_DW4_BIPN[i].mask) >> |
| + WTBL_UMAC_DW4_BIPN[i].shift); |
| + i++; |
| + } |
| + |
| + i = 0; |
| + addr = (u32 *)&(uwtbl[WF_UWTBL_RX_BIPN_47_32__DW*4]); |
| + dw_value = *addr; |
| + |
| + while (WTBL_UMAC_DW5_BIPN[i].name) { |
| + seq_printf(s, "\t%s:%u\n", WTBL_UMAC_DW5_BIPN[i].name, |
| + (dw_value & WTBL_UMAC_DW5_BIPN[i].mask) >> |
| + WTBL_UMAC_DW5_BIPN[i].shift); |
| + i++; |
| + } |
| + } |
| +} |
| + |
| +static void parse_fmac_uwtbl_sn(struct seq_file *s, u8 *uwtbl) |
| +{ |
| + u32 *addr = 0; |
| + u32 u2SN = 0; |
| + |
| + /* UMAC WTBL DW SN part */ |
| + seq_printf(s, "\t\n"); |
| + seq_printf(s, "UWTBL SN\n"); |
| + |
| + addr = (u32 *)&(uwtbl[WF_UWTBL_TID0_SN_DW*4]); |
| + u2SN = ((*addr) & WF_UWTBL_TID0_SN_MASK) >> WF_UWTBL_TID0_SN_SHIFT; |
| + seq_printf(s, "\t%s:%u\n", "TID0_AC0_SN", u2SN); |
| + |
| + addr = (u32 *)&(uwtbl[WF_UWTBL_TID1_SN_DW*4]); |
| + u2SN = ((*addr) & WF_UWTBL_TID1_SN_MASK) >> WF_UWTBL_TID1_SN_SHIFT; |
| + seq_printf(s, "\t%s:%u\n", "TID1_AC1_SN", u2SN); |
| + |
| + addr = (u32 *)&(uwtbl[WF_UWTBL_TID2_SN_7_0__DW*4]); |
| + u2SN = ((*addr) & WF_UWTBL_TID2_SN_7_0__MASK) >> |
| + WF_UWTBL_TID2_SN_7_0__SHIFT; |
| + addr = (u32 *)&(uwtbl[WF_UWTBL_TID2_SN_11_8__DW*4]); |
| + u2SN |= (((*addr) & WF_UWTBL_TID2_SN_11_8__MASK) >> |
| + WF_UWTBL_TID2_SN_11_8__SHIFT) << 8; |
| + seq_printf(s, "\t%s:%u\n", "TID2_AC2_SN", u2SN); |
| + |
| + addr = (u32 *)&(uwtbl[WF_UWTBL_TID3_SN_DW*4]); |
| + u2SN = ((*addr) & WF_UWTBL_TID3_SN_MASK) >> WF_UWTBL_TID3_SN_SHIFT; |
| + seq_printf(s, "\t%s:%u\n", "TID3_AC3_SN", u2SN); |
| + |
| + addr = (u32 *)&(uwtbl[WF_UWTBL_TID4_SN_DW*4]); |
| + u2SN = ((*addr) & WF_UWTBL_TID4_SN_MASK) >> WF_UWTBL_TID4_SN_SHIFT; |
| + seq_printf(s, "\t%s:%u\n", "TID4_SN", u2SN); |
| + |
| + addr = (u32 *)&(uwtbl[WF_UWTBL_TID5_SN_3_0__DW*4]); |
| + u2SN = ((*addr) & WF_UWTBL_TID5_SN_3_0__MASK) >> |
| + WF_UWTBL_TID5_SN_3_0__SHIFT; |
| + addr = (u32 *)&(uwtbl[WF_UWTBL_TID5_SN_11_4__DW*4]); |
| + u2SN |= (((*addr) & WF_UWTBL_TID5_SN_11_4__MASK) >> |
| + WF_UWTBL_TID5_SN_11_4__SHIFT) << 4; |
| + seq_printf(s, "\t%s:%u\n", "TID5_SN", u2SN); |
| + |
| + addr = (u32 *)&(uwtbl[WF_UWTBL_TID6_SN_DW*4]); |
| + u2SN = ((*addr) & WF_UWTBL_TID6_SN_MASK) >> WF_UWTBL_TID6_SN_SHIFT; |
| + seq_printf(s, "\t%s:%u\n", "TID6_SN", u2SN); |
| + |
| + addr = (u32 *)&(uwtbl[WF_UWTBL_TID7_SN_DW*4]); |
| + u2SN = ((*addr) & WF_UWTBL_TID7_SN_MASK) >> WF_UWTBL_TID7_SN_SHIFT; |
| + seq_printf(s, "\t%s:%u\n", "TID7_SN", u2SN); |
| + |
| + addr = (u32 *)&(uwtbl[WF_UWTBL_COM_SN_DW*4]); |
| + u2SN = ((*addr) & WF_UWTBL_COM_SN_MASK) >> WF_UWTBL_COM_SN_SHIFT; |
| + seq_printf(s, "\t%s:%u\n", "COM_SN", u2SN); |
| +} |
| + |
| +static void dump_key_table( |
| + struct seq_file *s, |
| + uint16_t keyloc0, |
| + uint16_t keyloc1, |
| + uint16_t keyloc2 |
| +) |
| +{ |
| +#define ONE_KEY_ENTRY_LEN_IN_DW 8 |
| + struct besra_dev *dev = dev_get_drvdata(s->private); |
| + u8 keytbl[ONE_KEY_ENTRY_LEN_IN_DW*4] = {0}; |
| + uint16_t x; |
| + |
| + seq_printf(s, "\t\n"); |
| + seq_printf(s, "\t%s:%d\n", "keyloc0", keyloc0); |
| + if (keyloc0 != INVALID_KEY_ENTRY) { |
| + |
| + /* Don't swap below two lines, halWtblReadRaw will |
| + * write new value WF_WTBLON_TOP_WDUCR_ADDR |
| + */ |
| + besra_wtbl_read_raw(dev, keyloc0, |
| + WTBL_TYPE_KEY, 0, ONE_KEY_ENTRY_LEN_IN_DW, keytbl); |
| + seq_printf(s, "\t\tKEY WTBL Addr: group:0x%x=0x%x addr: 0x%x\n", |
| + MT_DBG_UWTBL_TOP_WDUCR_ADDR, |
| + mt76_rr(dev, MT_DBG_UWTBL_TOP_WDUCR_ADDR), |
| + KEYTBL_IDX2BASE(keyloc0, 0)); |
| + for (x = 0; x < ONE_KEY_ENTRY_LEN_IN_DW; x++) { |
| + seq_printf(s, "\t\tDW%02d: %02x %02x %02x %02x\n", |
| + x, |
| + keytbl[x * 4 + 3], |
| + keytbl[x * 4 + 2], |
| + keytbl[x * 4 + 1], |
| + keytbl[x * 4]); |
| + } |
| + } |
| + |
| + seq_printf(s, "\t%s:%d\n", "keyloc1", keyloc1); |
| + if (keyloc1 != INVALID_KEY_ENTRY) { |
| + /* Don't swap below two lines, halWtblReadRaw will |
| + * write new value WF_WTBLON_TOP_WDUCR_ADDR |
| + */ |
| + besra_wtbl_read_raw(dev, keyloc1, |
| + WTBL_TYPE_KEY, 0, ONE_KEY_ENTRY_LEN_IN_DW, keytbl); |
| + seq_printf(s, "\t\tKEY WTBL Addr: group:0x%x=0x%x addr: 0x%x\n", |
| + MT_DBG_UWTBL_TOP_WDUCR_ADDR, |
| + mt76_rr(dev, MT_DBG_UWTBL_TOP_WDUCR_ADDR), |
| + KEYTBL_IDX2BASE(keyloc1, 0)); |
| + for (x = 0; x < ONE_KEY_ENTRY_LEN_IN_DW; x++) { |
| + seq_printf(s, "\t\tDW%02d: %02x %02x %02x %02x\n", |
| + x, |
| + keytbl[x * 4 + 3], |
| + keytbl[x * 4 + 2], |
| + keytbl[x * 4 + 1], |
| + keytbl[x * 4]); |
| + } |
| + } |
| + |
| + seq_printf(s, "\t%s:%d\n", "keyloc2", keyloc2); |
| + if (keyloc2 != INVALID_KEY_ENTRY) { |
| + /* Don't swap below two lines, halWtblReadRaw will |
| + * write new value WF_WTBLON_TOP_WDUCR_ADDR |
| + */ |
| + besra_wtbl_read_raw(dev, keyloc2, |
| + WTBL_TYPE_KEY, 0, ONE_KEY_ENTRY_LEN_IN_DW, keytbl); |
| + seq_printf(s, "\t\tKEY WTBL Addr: group:0x%x=0x%x addr: 0x%x\n", |
| + MT_DBG_UWTBL_TOP_WDUCR_ADDR, |
| + mt76_rr(dev, MT_DBG_UWTBL_TOP_WDUCR_ADDR), |
| + KEYTBL_IDX2BASE(keyloc2, 0)); |
| + for (x = 0; x < ONE_KEY_ENTRY_LEN_IN_DW; x++) { |
| + seq_printf(s, "\t\tDW%02d: %02x %02x %02x %02x\n", |
| + x, |
| + keytbl[x * 4 + 3], |
| + keytbl[x * 4 + 2], |
| + keytbl[x * 4 + 1], |
| + keytbl[x * 4]); |
| + } |
| + } |
| +} |
| + |
| +static void parse_fmac_uwtbl_key_info(struct seq_file *s, u8 *uwtbl, u8 *lwtbl) |
| +{ |
| + u32 *addr = 0; |
| + u32 dw_value = 0; |
| + uint16_t keyloc0 = INVALID_KEY_ENTRY; |
| + uint16_t keyloc1 = INVALID_KEY_ENTRY; |
| + uint16_t keyloc2 = INVALID_KEY_ENTRY; |
| + |
| + /* UMAC WTBL DW 7 */ |
| + seq_printf(s, "\t\n"); |
| + seq_printf(s, "UWTBL key info\n"); |
| + |
| + addr = (u32 *)&(uwtbl[WF_UWTBL_KEY_LOC0_DW*4]); |
| + dw_value = *addr; |
| + keyloc0 = (dw_value & WF_UWTBL_KEY_LOC0_MASK) >> WF_UWTBL_KEY_LOC0_SHIFT; |
| + keyloc1 = (dw_value & WF_UWTBL_KEY_LOC1_MASK) >> WF_UWTBL_KEY_LOC1_SHIFT; |
| + |
| + seq_printf(s, "\t%s:%u/%u\n", "Key Loc 0/1", keyloc0, keyloc1); |
| + |
| + /* UMAC WTBL DW 6 for BIGTK */ |
| + if (is_wtbl_bigtk_exist(lwtbl) == true) { |
| + keyloc2 = (dw_value & WF_UWTBL_KEY_LOC2_MASK) >> |
| + WF_UWTBL_KEY_LOC2_SHIFT; |
| + seq_printf(s, "\t%s:%u\n", "Key Loc 2", keyloc2); |
| + } |
| + |
| + /* Parse KEY link */ |
| + dump_key_table(s, keyloc0, keyloc1, keyloc2); |
| +} |
| + |
| +static const struct berse_wtbl_parse WTBL_UMAC_DW8[] = { |
| + {"UWTBL_WMM_Q", WF_UWTBL_WMM_Q_MASK, WF_UWTBL_WMM_Q_SHIFT, false}, |
| + {"UWTBL_QOS", WF_UWTBL_QOS_MASK, NO_SHIFT_DEFINE, false}, |
| + {"UWTBL_HT_VHT_HE", WF_UWTBL_HT_MASK, NO_SHIFT_DEFINE, false}, |
| + {"UWTBL_HDRT_MODE", WF_UWTBL_HDRT_MODE_MASK, NO_SHIFT_DEFINE, true}, |
| + {NULL,} |
| +}; |
| + |
| +static void parse_fmac_uwtbl_msdu_info(struct seq_file *s, u8 *uwtbl) |
| +{ |
| + u32 *addr = 0; |
| + u32 dw_value = 0; |
| + u32 amsdu_len = 0; |
| + u16 i = 0; |
| + |
| + /* UMAC WTBL DW 8 */ |
| + seq_printf(s, "\t\n"); |
| + seq_printf(s, "UWTBL DW8\n"); |
| + |
| + addr = (u32 *)&(uwtbl[WF_UWTBL_AMSDU_CFG_DW*4]); |
| + dw_value = *addr; |
| + |
| + while (WTBL_UMAC_DW8[i].name) { |
| + |
| + if (WTBL_UMAC_DW8[i].shift == NO_SHIFT_DEFINE) |
| + seq_printf(s, "\t%s:%d\n", WTBL_UMAC_DW8[i].name, |
| + (dw_value & WTBL_UMAC_DW8[i].mask) ? 1 : 0); |
| + else |
| + seq_printf(s, "\t%s:%u\n", WTBL_UMAC_DW8[i].name, |
| + (dw_value & WTBL_UMAC_DW8[i].mask) >> |
| + WTBL_UMAC_DW8[i].shift); |
| + i++; |
| + } |
| + |
| + /* UMAC WTBL DW 8 - AMSDU_CFG */ |
| + seq_printf(s, "\t%s:%d\n", "HW AMSDU Enable", |
| + (dw_value & WTBL_AMSDU_EN_MASK) ? 1 : 0); |
| + |
| + amsdu_len = (dw_value & WTBL_AMSDU_LEN_MASK) >> WTBL_AMSDU_LEN_OFFSET; |
| + if (amsdu_len == 0) |
| + seq_printf(s, "\t%s:invalid (WTBL value=0x%x)\n", "HW AMSDU Len", |
| + amsdu_len); |
| + else if (amsdu_len == 1) |
| + seq_printf(s, "\t%s:%d~%d (WTBL value=0x%x)\n", "HW AMSDU Len", |
| + 1, |
| + 255, |
| + amsdu_len); |
| + else if (amsdu_len == 2) |
| + seq_printf(s, "\t%s:%d~%d (WTBL value=0x%x)\n", "HW AMSDU Len", |
| + 256, |
| + 511, |
| + amsdu_len); |
| + else if (amsdu_len == 3) |
| + seq_printf(s, "\t%s:%d~%d (WTBL value=0x%x)\n", "HW AMSDU Len", |
| + 512, |
| + 767, |
| + amsdu_len); |
| + else |
| + seq_printf(s, "\t%s:%d~%d (WTBL value=0x%x)\n", "HW AMSDU Len", |
| + 256 * (amsdu_len - 1), |
| + 256 * (amsdu_len - 1) + 255, |
| + amsdu_len); |
| + |
| + seq_printf(s, "\t%s:%lu (WTBL value=0x%lx)\n", "HW AMSDU Num", |
| + ((dw_value & WTBL_AMSDU_NUM_MASK) >> WTBL_AMSDU_NUM_OFFSET) + 1, |
| + (dw_value & WTBL_AMSDU_NUM_MASK) >> WTBL_AMSDU_NUM_OFFSET); |
| +} |
| + |
| +static int besra_wtbl_read(struct seq_file *s, void *data) |
| +{ |
| + struct besra_dev *dev = dev_get_drvdata(s->private); |
| + u8 lwtbl[LWTBL_LEN_IN_DW * 4] = {0}; |
| + u8 uwtbl[UWTBL_LEN_IN_DW * 4] = {0}; |
| + int x; |
| + |
| + besra_wtbl_read_raw(dev, dev->wlan_idx, WTBL_TYPE_LMAC, 0, |
| + LWTBL_LEN_IN_DW, lwtbl); |
| + seq_printf(s, "Dump WTBL info of WLAN_IDX:%d\n", dev->wlan_idx); |
| + seq_printf(s, "LMAC WTBL Addr: group:0x%x=0x%x addr: 0x%lx\n", |
| + MT_DBG_WTBLON_TOP_WDUCR_ADDR, |
| + mt76_rr(dev, MT_DBG_WTBLON_TOP_WDUCR_ADDR), |
| + LWTBL_IDX2BASE(dev->wlan_idx, 0)); |
| + for (x = 0; x < LWTBL_LEN_IN_DW; x++) { |
| + seq_printf(s, "DW%02d: %02x %02x %02x %02x\n", |
| + x, |
| + lwtbl[x * 4 + 3], |
| + lwtbl[x * 4 + 2], |
| + lwtbl[x * 4 + 1], |
| + lwtbl[x * 4]); |
| + } |
| + |
| + /* Parse LWTBL */ |
| + parse_fmac_lwtbl_dw0_1(s, lwtbl); |
| + parse_fmac_lwtbl_dw2(s, lwtbl); |
| + parse_fmac_lwtbl_dw3(s, lwtbl); |
| + parse_fmac_lwtbl_dw4(s, lwtbl); |
| + parse_fmac_lwtbl_dw5(s, lwtbl); |
| + parse_fmac_lwtbl_dw6(s, lwtbl); |
| + parse_fmac_lwtbl_dw7(s, lwtbl); |
| + parse_fmac_lwtbl_dw8(s, lwtbl); |
| + parse_fmac_lwtbl_dw9(s, lwtbl); |
| + parse_fmac_lwtbl_dw10(s, lwtbl); |
| + parse_fmac_lwtbl_dw11(s, lwtbl); |
| + parse_fmac_lwtbl_dw12(s, lwtbl); |
| + parse_fmac_lwtbl_dw13(s, lwtbl); |
| + parse_fmac_lwtbl_dw14(s, lwtbl); |
| + parse_fmac_lwtbl_mlo_info(s, lwtbl); |
| + parse_fmac_lwtbl_dw31(s, lwtbl); |
| + parse_fmac_lwtbl_dw32(s, lwtbl); |
| + parse_fmac_lwtbl_rx_stats(s, lwtbl); |
| + |
| + besra_wtbl_read_raw(dev, dev->wlan_idx, WTBL_TYPE_UMAC, 0, |
| + UWTBL_LEN_IN_DW, uwtbl); |
| + seq_printf(s, "Dump WTBL info of WLAN_IDX:%d\n", dev->wlan_idx); |
| + seq_printf(s, "UMAC WTBL Addr: group:0x%x=0x%x addr: 0x%lx\n", |
| + MT_DBG_UWTBL_TOP_WDUCR_ADDR, |
| + mt76_rr(dev, MT_DBG_UWTBL_TOP_WDUCR_ADDR), |
| + UWTBL_IDX2BASE(dev->wlan_idx, 0)); |
| + for (x = 0; x < UWTBL_LEN_IN_DW; x++) { |
| + seq_printf(s, "DW%02d: %02x %02x %02x %02x\n", |
| + x, |
| + uwtbl[x * 4 + 3], |
| + uwtbl[x * 4 + 2], |
| + uwtbl[x * 4 + 1], |
| + uwtbl[x * 4]); |
| + } |
| + |
| + /* Parse UWTBL */ |
| + parse_fmac_uwtbl_mlo_info(s, uwtbl); |
| + parse_fmac_uwtbl_pn(s, uwtbl, lwtbl); |
| + parse_fmac_uwtbl_sn(s, uwtbl); |
| + parse_fmac_uwtbl_key_info(s, uwtbl, lwtbl); |
| + parse_fmac_uwtbl_msdu_info(s, uwtbl); |
| + |
| + return 0; |
| +} |
| + |
| +/* dma info dump */ |
| +const struct queue_desc mt7902_tx_ring_layout[] = { |
| + { |
| + .hw_desc_base = WF_WFDMA_HOST_DMA0_WPDMA_TX_RING18_CTRL0_ADDR, |
| + .ring_size = 2048, |
| + .ring_info = "band0 TXD" |
| + }, |
| + { |
| + .hw_desc_base = WF_WFDMA_HOST_DMA0_WPDMA_TX_RING19_CTRL0_ADDR, |
| + .ring_size = 2048, |
| + .ring_info = "band1 TXD" |
| + }, |
| + { |
| + .hw_desc_base = WF_WFDMA_HOST_DMA0_WPDMA_TX_RING21_CTRL0_ADDR, |
| + .ring_size = 2048, |
| + .ring_info = "band2 TXD" |
| + }, |
| + { |
| + .hw_desc_base = WF_WFDMA_HOST_DMA0_WPDMA_TX_RING16_CTRL0_ADDR, |
| + .ring_size = 128, |
| + .ring_info = "FWDL" |
| + }, |
| + { |
| + .hw_desc_base = WF_WFDMA_HOST_DMA0_WPDMA_TX_RING17_CTRL0_ADDR, |
| + .ring_size = 256, |
| + .ring_info = "cmd to WM" |
| + }, |
| + { |
| + .hw_desc_base = WF_WFDMA_HOST_DMA0_WPDMA_TX_RING20_CTRL0_ADDR, |
| + .ring_size = 256, |
| + .ring_info = "cmd to WA" |
| + } |
| +}; |
| + |
| +const struct queue_desc mt7902_rx_ring_layout[] = { |
| + { |
| + .hw_desc_base = WF_WFDMA_HOST_DMA0_WPDMA_RX_RING4_CTRL0_ADDR, |
| + .ring_size = 1536, |
| + .ring_info = "band0 RX data" |
| + }, |
| + { |
| + .hw_desc_base = WF_WFDMA_HOST_DMA0_WPDMA_RX_RING5_CTRL0_ADDR, |
| + .ring_size = 1536, |
| + .ring_info = "band1 RX data" |
| + }, |
| + { |
| + .hw_desc_base = WF_WFDMA_HOST_DMA0_WPDMA_RX_RING8_CTRL0_ADDR, |
| + .ring_size = 1536, |
| + .ring_info = "band2 RX data" |
| + }, |
| + { |
| + .hw_desc_base = WF_WFDMA_HOST_DMA0_WPDMA_RX_RING0_CTRL0_ADDR, |
| + .ring_size = 512, |
| + .ring_info = "event from WM" |
| + }, |
| + { |
| + .hw_desc_base = WF_WFDMA_HOST_DMA0_WPDMA_RX_RING1_CTRL0_ADDR, |
| + .ring_size = 1024, |
| + .ring_info = "event from WA" |
| + }, |
| + { |
| + .hw_desc_base = WF_WFDMA_HOST_DMA0_WPDMA_RX_RING2_CTRL0_ADDR, |
| + .ring_size = 1024, |
| + .ring_info = "band0/1/2 tx free done" |
| + }, |
| +}; |
| + |
| +static void |
| +dump_dma_tx_ring_info(struct seq_file *s, struct besra_dev *dev, char *str1, char *str2, u32 ring_base) |
| +{ |
| + u32 base, cnt, cidx, didx, queue_cnt; |
| + |
| + base= mt76_rr(dev, ring_base); |
| + cnt = mt76_rr(dev, ring_base + 4); |
| + cidx = mt76_rr(dev, ring_base + 8); |
| + didx = mt76_rr(dev, ring_base + 12); |
| + queue_cnt = (cidx >= didx) ? (cidx - didx) : (cidx - didx + cnt); |
| + |
| + seq_printf(s, "%20s %6s %10x %10x %10x %10x %10x\n", str1, str2, base, cnt, cidx, didx, queue_cnt); |
| +} |
| + |
| +static void |
| +dump_dma_rx_ring_info(struct seq_file *s, struct besra_dev *dev, char *str1, char *str2, u32 ring_base) |
| +{ |
| + u32 base, cnt, cidx, didx, queue_cnt; |
| + |
| + base= mt76_rr(dev, ring_base); |
| + cnt = mt76_rr(dev, ring_base + 4); |
| + cidx = mt76_rr(dev, ring_base + 8); |
| + didx = mt76_rr(dev, ring_base + 12); |
| + queue_cnt = (didx > cidx) ? (didx - cidx - 1) : (didx - cidx + cnt - 1); |
| + |
| + seq_printf(s, "%20s %6s %10x %10x %10x %10x %10x\n", str1, str2, base, cnt, cidx, didx, queue_cnt); |
| +} |
| + |
| +static void |
| +besra_show_dma_info(struct seq_file *s, struct besra_dev *dev) |
| +{ |
| + u32 sys_ctrl[10]; |
| + |
| + /* HOST DMA information */ |
| + sys_ctrl[0] = mt76_rr(dev, WF_WFDMA_HOST_DMA0_HOST_INT_STA_ADDR); |
| + sys_ctrl[1] = mt76_rr(dev, WF_WFDMA_HOST_DMA0_HOST_INT_ENA_ADDR); |
| + sys_ctrl[2] = mt76_rr(dev, WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_ADDR); |
| + |
| + seq_printf(s, "HOST_DMA Configuration\n"); |
| + seq_printf(s, "%10s %10s %10s %10s %10s %10s\n", |
| + "DMA", "IntCSR", "IntMask", "Glocfg", "Tx/RxEn", "Tx/RxBusy"); |
| + seq_printf(s, "%10s %10x %10x %10x %4x/%5x %4x/%5x\n", |
| + "DMA0", sys_ctrl[0], sys_ctrl[1], sys_ctrl[2], |
| + (sys_ctrl[2] & WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_TX_DMA_EN_MASK) |
| + >> WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_TX_DMA_EN_SHFT, |
| + (sys_ctrl[2] & WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_RX_DMA_EN_MASK) |
| + >> WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_RX_DMA_EN_SHFT, |
| + (sys_ctrl[2] & WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK) |
| + >> WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT, |
| + (sys_ctrl[2] & WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK) |
| + >> WF_WFDMA_HOST_DMA0_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT); |
| + |
| + seq_printf(s, "HOST_DMA0 Ring Configuration\n"); |
| + seq_printf(s, "%20s %6s %10s %10s %10s %10s %10s\n", |
| + "Name", "Used", "Base", "Cnt", "CIDX", "DIDX", "QCnt"); |
| + dump_dma_tx_ring_info(s, dev, "T0:TXD0(H2MAC)", "STA", |
| + WF_WFDMA_HOST_DMA0_WPDMA_TX_RING0_CTRL0_ADDR); |
| + dump_dma_tx_ring_info(s, dev, "T1:TXD1(H2MAC)", "STA", |
| + WF_WFDMA_HOST_DMA0_WPDMA_TX_RING1_CTRL0_ADDR); |
| + dump_dma_tx_ring_info(s, dev, "T2:TXD2(H2MAC)", "STA", |
| + WF_WFDMA_HOST_DMA0_WPDMA_TX_RING2_CTRL0_ADDR); |
| + dump_dma_tx_ring_info(s, dev, "T3:", "STA", |
| + WF_WFDMA_HOST_DMA0_WPDMA_TX_RING3_CTRL0_ADDR); |
| + dump_dma_tx_ring_info(s, dev, "T4:", "STA", |
| + WF_WFDMA_HOST_DMA0_WPDMA_TX_RING4_CTRL0_ADDR); |
| + dump_dma_tx_ring_info(s, dev, "T5:", "STA", |
| + WF_WFDMA_HOST_DMA0_WPDMA_TX_RING5_CTRL0_ADDR); |
| + dump_dma_tx_ring_info(s, dev, "T6:", "STA", |
| + WF_WFDMA_HOST_DMA0_WPDMA_TX_RING6_CTRL0_ADDR); |
| + dump_dma_tx_ring_info(s, dev, "T16:FWDL", "Both", |
| + WF_WFDMA_HOST_DMA0_WPDMA_TX_RING16_CTRL0_ADDR); |
| + dump_dma_tx_ring_info(s, dev, "T17:Cmd(H2WM)", "Both", |
| + WF_WFDMA_HOST_DMA0_WPDMA_TX_RING17_CTRL0_ADDR); |
| + dump_dma_tx_ring_info(s, dev, "T18:TXD0(H2WA)", "AP", |
| + WF_WFDMA_HOST_DMA0_WPDMA_TX_RING18_CTRL0_ADDR); |
| + dump_dma_tx_ring_info(s, dev, "T19:TXD1(H2WA)", "AP", |
| + WF_WFDMA_HOST_DMA0_WPDMA_TX_RING19_CTRL0_ADDR); |
| + dump_dma_tx_ring_info(s, dev, "T20:Cmd(H2WA)", "AP", |
| + WF_WFDMA_HOST_DMA0_WPDMA_TX_RING20_CTRL0_ADDR); |
| + dump_dma_tx_ring_info(s, dev, "T21:TXD2(H2WA)", "AP", |
| + WF_WFDMA_HOST_DMA0_WPDMA_TX_RING21_CTRL0_ADDR); |
| + dump_dma_rx_ring_info(s, dev, "R0:Event(WM2H)", "Both", |
| + WF_WFDMA_HOST_DMA0_WPDMA_RX_RING0_CTRL0_ADDR); |
| + dump_dma_rx_ring_info(s, dev, "R1:Event(WA2H)", "AP", |
| + WF_WFDMA_HOST_DMA0_WPDMA_RX_RING1_CTRL0_ADDR); |
| + dump_dma_rx_ring_info(s, dev, "R2:TxDone0(WA2H)", "AP", |
| + WF_WFDMA_HOST_DMA0_WPDMA_RX_RING2_CTRL0_ADDR); |
| + dump_dma_rx_ring_info(s, dev, "R3:TxDone1(WA2H)", "AP", |
| + WF_WFDMA_HOST_DMA0_WPDMA_RX_RING3_CTRL0_ADDR); |
| + dump_dma_rx_ring_info(s, dev, "R4:Data0(MAC2H)", "Both", |
| + WF_WFDMA_HOST_DMA0_WPDMA_RX_RING4_CTRL0_ADDR); |
| + dump_dma_rx_ring_info(s, dev, "R5:Data1(MAC2H)", "Both", |
| + WF_WFDMA_HOST_DMA0_WPDMA_RX_RING5_CTRL0_ADDR); |
| + dump_dma_rx_ring_info(s, dev, "R6:TxDone0(MAC2H)", "STA", |
| + WF_WFDMA_HOST_DMA0_WPDMA_RX_RING6_CTRL0_ADDR); |
| + dump_dma_rx_ring_info(s, dev, "R7:TxDone1(MAC2H)", "STA", |
| + WF_WFDMA_HOST_DMA0_WPDMA_RX_RING7_CTRL0_ADDR); |
| + dump_dma_rx_ring_info(s, dev, "R8:Data2(MAC2H)", "Both", |
| + WF_WFDMA_HOST_DMA0_WPDMA_RX_RING8_CTRL0_ADDR); |
| + dump_dma_rx_ring_info(s, dev, "R9:TxDone2(MAC2H)", "STA", |
| + WF_WFDMA_HOST_DMA0_WPDMA_RX_RING9_CTRL0_ADDR); |
| + |
| + /* MCU DMA information */ |
| + sys_ctrl[0] = mt76_rr(dev, WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_ADDR); |
| + sys_ctrl[1] = mt76_rr(dev, WF_WFDMA_MCU_DMA0_HOST_INT_STA_ADDR); |
| + sys_ctrl[2] = mt76_rr(dev, WF_WFDMA_MCU_DMA0_HOST_INT_ENA_ADDR); |
| + |
| + seq_printf(s, "MCU_DMA Configuration\n"); |
| + seq_printf(s, "%10s %10s %10s %10s %10s %10s\n", |
| + "DMA", "IntCSR", "IntMask", "Glocfg", "Tx/RxEn", "Tx/RxBusy"); |
| + seq_printf(s, "%10s %10x %10x %10x %4x/%5x %4x/%5x\n", |
| + "DMA0", sys_ctrl[1], sys_ctrl[2], sys_ctrl[0], |
| + (sys_ctrl[0] & WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_EN_MASK) |
| + >> WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_EN_SHFT, |
| + (sys_ctrl[0] & WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_EN_MASK) |
| + >> WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_EN_SHFT, |
| + (sys_ctrl[0] & WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK) |
| + >> WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT, |
| + (sys_ctrl[0] & WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK) |
| + >> WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT); |
| + |
| + seq_printf(s, "MCU_DMA0 Ring Configuration\n"); |
| + seq_printf(s, "%20s %6s %10s %10s %10s %10s %10s\n", |
| + "Name", "Used", "Base", "Cnt", "CIDX", "DIDX", "QCnt"); |
| + dump_dma_tx_ring_info(s, dev, "T0:Event(WM2H)", "Both", |
| + WF_WFDMA_MCU_DMA0_WPDMA_TX_RING0_CTRL0_ADDR); |
| + dump_dma_tx_ring_info(s, dev, "T1:Event(WA2H)", "AP", |
| + WF_WFDMA_MCU_DMA0_WPDMA_TX_RING1_CTRL0_ADDR); |
| + dump_dma_tx_ring_info(s, dev, "T2:TxDone0(WA2H)", "AP", |
| + WF_WFDMA_MCU_DMA0_WPDMA_TX_RING2_CTRL0_ADDR); |
| + dump_dma_tx_ring_info(s, dev, "T3:TxDone1(WA2H)", "AP", |
| + WF_WFDMA_MCU_DMA0_WPDMA_TX_RING3_CTRL0_ADDR); |
| + dump_dma_tx_ring_info(s, dev, "T4:TXD(WM2MAC)", "Both", |
| + WF_WFDMA_MCU_DMA0_WPDMA_TX_RING4_CTRL0_ADDR); |
| + dump_dma_tx_ring_info(s, dev, "T5:TXCMD(WM2MAC)", "Both", |
| + WF_WFDMA_MCU_DMA0_WPDMA_TX_RING5_CTRL0_ADDR); |
| + dump_dma_tx_ring_info(s, dev, "T6:TXD(WA2MAC)", "AP", |
| + WF_WFDMA_MCU_DMA0_WPDMA_TX_RING6_CTRL0_ADDR); |
| + dump_dma_rx_ring_info(s, dev, "R0:FWDL", "Both", |
| + WF_WFDMA_MCU_DMA0_WPDMA_RX_RING0_CTRL0_ADDR); |
| + dump_dma_rx_ring_info(s, dev, "R1:Cmd(H2WM)", "Both", |
| + WF_WFDMA_MCU_DMA0_WPDMA_RX_RING1_CTRL0_ADDR); |
| + dump_dma_rx_ring_info(s, dev, "R2:TXD0(H2WA)", "AP", |
| + WF_WFDMA_MCU_DMA0_WPDMA_RX_RING2_CTRL0_ADDR); |
| + dump_dma_rx_ring_info(s, dev, "R3:TXD1(H2WA)", "AP", |
| + WF_WFDMA_MCU_DMA0_WPDMA_RX_RING3_CTRL0_ADDR); |
| + dump_dma_rx_ring_info(s, dev, "R4:Cmd(H2WA)", "AP", |
| + WF_WFDMA_MCU_DMA0_WPDMA_RX_RING4_CTRL0_ADDR); |
| + dump_dma_rx_ring_info(s, dev, "R5:Data0(MAC2WM)", "Both", |
| + WF_WFDMA_MCU_DMA0_WPDMA_RX_RING5_CTRL0_ADDR); |
| + dump_dma_rx_ring_info(s, dev, "R6:TxDone(MAC2WM)", "Both", |
| + WF_WFDMA_MCU_DMA0_WPDMA_RX_RING6_CTRL0_ADDR); |
| + dump_dma_rx_ring_info(s, dev, "R7:SPL/RPT(MAC2WM)", "Both", |
| + WF_WFDMA_MCU_DMA0_WPDMA_RX_RING7_CTRL0_ADDR); |
| + dump_dma_rx_ring_info(s, dev, "R8:TxDone(MAC2WA)", "AP", |
| + WF_WFDMA_MCU_DMA0_WPDMA_RX_RING8_CTRL0_ADDR); |
| + dump_dma_rx_ring_info(s, dev, "R9:Data1(MAC2WM)", "Both", |
| + WF_WFDMA_MCU_DMA0_WPDMA_RX_RING9_CTRL0_ADDR); |
| + dump_dma_rx_ring_info(s, dev, "R10:TXD2(H2WA)", "AP", |
| + WF_WFDMA_MCU_DMA0_WPDMA_RX_RING10_CTRL0_ADDR); |
| + |
| + /* MEM DMA information */ |
| + sys_ctrl[0] = mt76_rr(dev, WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_ADDR); |
| + sys_ctrl[1] = mt76_rr(dev, WF_WFDMA_MEM_DMA_HOST_INT_STA_ADDR); |
| + sys_ctrl[2] = mt76_rr(dev, WF_WFDMA_MEM_DMA_HOST_INT_ENA_ADDR); |
| + |
| + seq_printf(s, "MEM_DMA Configuration\n"); |
| + seq_printf(s, "%10s %10s %10s %10s %10s %10s\n", |
| + "DMA", "IntCSR", "IntMask", "Glocfg", "Tx/RxEn", "Tx/RxBusy"); |
| + seq_printf(s, "%10s %10x %10x %10x %4x/%5x %4x/%5x\n", |
| + "MEM", sys_ctrl[1], sys_ctrl[2], sys_ctrl[0], |
| + (sys_ctrl[0] & WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_EN_MASK) |
| + >> WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_EN_SHFT, |
| + (sys_ctrl[0] & WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_EN_MASK) |
| + >> WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_EN_SHFT, |
| + (sys_ctrl[0] & WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK) |
| + >> WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT, |
| + (sys_ctrl[0] & WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK) |
| + >> WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT); |
| + |
| + seq_printf(s, "MEM_DMA Ring Configuration\n"); |
| + seq_printf(s, "%20s %6s %10s %10s %10s %10s %10s\n", |
| + "Name", "Used", "Base", "Cnt", "CIDX", "DIDX", "QCnt"); |
| + dump_dma_tx_ring_info(s, dev, "T0:CmdEvent(WM2WA)", "AP", |
| + WF_WFDMA_MEM_DMA_WPDMA_TX_RING0_CTRL0_ADDR); |
| + dump_dma_tx_ring_info(s, dev, "T1:CmdEvent(WA2WM)", "AP", |
| + WF_WFDMA_MEM_DMA_WPDMA_TX_RING1_CTRL0_ADDR); |
| + dump_dma_rx_ring_info(s, dev, "R0:CmdEvent(WM2WA)", "AP", |
| + WF_WFDMA_MEM_DMA_WPDMA_RX_RING0_CTRL0_ADDR); |
| + dump_dma_rx_ring_info(s, dev, "R1:CmdEvent(WA2WM)", "AP", |
| + WF_WFDMA_MEM_DMA_WPDMA_RX_RING1_CTRL0_ADDR); |
| +} |
| + |
| +static int besra_trinfo_read(struct seq_file *s, void *data) |
| +{ |
| + struct besra_dev *dev = dev_get_drvdata(s->private); |
| + const struct queue_desc *tx_ring_layout; |
| + const struct queue_desc *rx_ring_layout; |
| + u32 tx_ring_num, rx_ring_num; |
| + u32 tbase[10], tcnt[10]; |
| + u32 tcidx[10], tdidx[10]; |
| + u32 rbase[10], rcnt[10]; |
| + u32 rcidx[10], rdidx[10]; |
| + int idx; |
| + |
| + tx_ring_layout = &mt7902_tx_ring_layout[0]; |
| + rx_ring_layout = &mt7902_rx_ring_layout[0]; |
| + tx_ring_num = ARRAY_SIZE(mt7902_tx_ring_layout); |
| + rx_ring_num = ARRAY_SIZE(mt7902_rx_ring_layout); |
| + |
| + for (idx = 0; idx < tx_ring_num; idx++) { |
| + tbase[idx] = mt76_rr(dev, tx_ring_layout[idx].hw_desc_base); |
| + tcnt[idx] = mt76_rr(dev, tx_ring_layout[idx].hw_desc_base + 0x04); |
| + tcidx[idx] = mt76_rr(dev, tx_ring_layout[idx].hw_desc_base + 0x08); |
| + tdidx[idx] = mt76_rr(dev, tx_ring_layout[idx].hw_desc_base + 0x0c); |
| + } |
| + |
| + for (idx = 0; idx < rx_ring_num; idx++) { |
| + rbase[idx] = mt76_rr(dev, rx_ring_layout[idx].hw_desc_base); |
| + rcnt[idx] = mt76_rr(dev, rx_ring_layout[idx].hw_desc_base + 0x04); |
| + rcidx[idx] = mt76_rr(dev, rx_ring_layout[idx].hw_desc_base + 0x08); |
| + rdidx[idx] = mt76_rr(dev, rx_ring_layout[idx].hw_desc_base + 0x0c); |
| + } |
| + |
| + seq_printf(s, "=================================================\n"); |
| + seq_printf(s, "TxRing Configuration\n"); |
| + seq_printf(s, "%4s %10s %8s %1s %6s %6s %6s %6s\n", |
| + "Idx", "Attr", "Reg", "Base", "Cnt", "CIDX", "DIDX", |
| + "QCnt"); |
| + for (idx = 0; idx < tx_ring_num; idx++) { |
| + u32 queue_cnt; |
| + |
| + queue_cnt = (tcidx[idx] >= tdidx[idx]) ? |
| + (tcidx[idx] - tdidx[idx]) : |
| + (tcidx[idx] - tdidx[idx] + tcnt[idx]); |
| + seq_printf(s, "%4d %8s %8x %10x %6x %6x %6x %6x\n", |
| + idx, tx_ring_layout[idx].ring_info, |
| + tx_ring_layout[idx].hw_desc_base, tbase[idx], |
| + tcnt[idx], tcidx[idx], tdidx[idx], queue_cnt); |
| + } |
| + |
| + seq_printf(s, "RxRing Configuration\n"); |
| + seq_printf(s, "%4s %10s %8s %10s %6s %6s %6s %6s\n", |
| + "Idx", "Attr", "Reg", "Base", "Cnt", "CIDX", "DIDX", |
| + "QCnt"); |
| + |
| + for (idx = 0; idx < rx_ring_num; idx++) { |
| + u32 queue_cnt; |
| + |
| + queue_cnt = (rdidx[idx] > rcidx[idx]) ? |
| + (rdidx[idx] - rcidx[idx] - 1) : |
| + (rdidx[idx] - rcidx[idx] + rcnt[idx] - 1); |
| + seq_printf(s, "%4d %8s %8x %10x %6x %6x %6x %6x\n", |
| + idx, rx_ring_layout[idx].ring_info, |
| + rx_ring_layout[idx].hw_desc_base, |
| + rbase[idx], rcnt[idx], rcidx[idx], rdidx[idx], queue_cnt); |
| + } |
| + |
| + besra_show_dma_info(s, dev); |
| + return 0; |
| +} |
| + |
| +/* MIB INFO */ |
| +static int besra_mibinfo_read_per_band(struct seq_file *s, int band_idx) |
| +{ |
| +#define BSS_NUM 4 |
| + struct besra_dev *dev = dev_get_drvdata(s->private); |
| + u8 bss_nums = BSS_NUM; |
| + u32 idx; |
| + u32 mac_val, band_offset = 0, band_offset_umib = 0; |
| + u32 msdr6, msdr9, msdr18; |
| + u32 rvsr0, rscr26, rscr35, mctr5, mctr6, msr0, msr1, msr2; |
| + u32 tbcr0, tbcr1, tbcr2, tbcr3, tbcr4; |
| + u32 btscr[7]; |
| + u32 tdrcr[5]; |
| + u32 mbtocr[16], mbtbcr[16], mbrocr[16], mbrbcr[16]; |
| + u32 btcr, btbcr, brocr, brbcr, btdcr, brdcr; |
| + u32 mu_cnt[5]; |
| + u32 ampdu_cnt[3]; |
| + u64 per; |
| + |
| + switch (band_idx) { |
| + case 0: |
| + band_offset = 0; |
| + band_offset_umib = 0; |
| + break; |
| + case 1: |
| + band_offset = BN1_WF_MIB_TOP_BASE - BN0_WF_MIB_TOP_BASE; |
| + band_offset_umib = WF_UMIB_TOP_B1BROCR_ADDR - WF_UMIB_TOP_B0BROCR_ADDR; |
| + break; |
| + case 2: |
| + band_offset = IP1_BN0_WF_MIB_TOP_BASE - BN0_WF_MIB_TOP_BASE; |
| + band_offset_umib = WF_UMIB_TOP_B2BROCR_ADDR - WF_UMIB_TOP_B0BROCR_ADDR; |
| + break; |
| + default: |
| + return true; |
| + } |
| + |
| + seq_printf(s, "Band %d MIB Status\n", band_idx); |
| + seq_printf(s, "===============================\n"); |
| + mac_val = mt76_rr(dev, BN0_WF_MIB_TOP_M0SCR0_ADDR + band_offset); |
| + seq_printf(s, "MIB Status Control=0x%x\n", mac_val); |
| + |
| + msdr6 = mt76_rr(dev, BN0_WF_MIB_TOP_M0SDR6_ADDR + band_offset); |
| + rvsr0 = mt76_rr(dev, BN0_WF_MIB_TOP_RVSR0_ADDR + band_offset); |
| + rscr35 = mt76_rr(dev, BN0_WF_MIB_TOP_RSCR35_ADDR + band_offset); |
| + msdr9 = mt76_rr(dev, BN0_WF_MIB_TOP_M0SDR9_ADDR + band_offset); |
| + rscr26 = mt76_rr(dev, BN0_WF_MIB_TOP_RSCR26_ADDR + band_offset); |
| + mctr5 = mt76_rr(dev, BN0_WF_MIB_TOP_MCTR5_ADDR + band_offset); |
| + mctr6 = mt76_rr(dev, BN0_WF_MIB_TOP_MCTR6_ADDR + band_offset); |
| + msdr18 = mt76_rr(dev, BN0_WF_MIB_TOP_M0SDR18_ADDR + band_offset); |
| + msr0 = mt76_rr(dev, BN0_WF_MIB_TOP_MSR0_ADDR + band_offset); |
| + msr1 = mt76_rr(dev, BN0_WF_MIB_TOP_MSR1_ADDR + band_offset); |
| + msr2 = mt76_rr(dev, BN0_WF_MIB_TOP_MSR2_ADDR + band_offset); |
| + ampdu_cnt[0] = mt76_rr(dev, BN0_WF_MIB_TOP_TSCR0_ADDR + band_offset); |
| + ampdu_cnt[1] = mt76_rr(dev, BN0_WF_MIB_TOP_TSCR3_ADDR + band_offset); |
| + ampdu_cnt[2] = mt76_rr(dev, BN0_WF_MIB_TOP_TSCR4_ADDR + band_offset); |
| + ampdu_cnt[1] &= BN0_WF_MIB_TOP_TSCR3_AMPDU_MPDU_COUNT_MASK; |
| + ampdu_cnt[2] &= BN0_WF_MIB_TOP_TSCR4_AMPDU_ACKED_COUNT_MASK; |
| + |
| + seq_printf(s, "===Phy/Timing Related Counters===\n"); |
| + seq_printf(s, "\tChannelIdleCnt=0x%x\n", |
| + msdr6 & BN0_WF_MIB_TOP_M0SDR6_CHANNEL_IDLE_COUNT_MASK); |
| + seq_printf(s, "\tCCA_NAV_Tx_Time=0x%x\n", |
| + msdr9 & BN0_WF_MIB_TOP_M0SDR9_CCA_NAV_TX_TIME_MASK); |
| + seq_printf(s, "\tRx_MDRDY_CNT=0x%x\n", |
| + rscr26 & BN0_WF_MIB_TOP_RSCR26_RX_MDRDY_COUNT_MASK); |
| + seq_printf(s, "\tCCK_MDRDY_TIME=0x%x, OFDM_MDRDY_TIME=0x%x", |
| + msr0 & BN0_WF_MIB_TOP_MSR0_CCK_MDRDY_TIME_MASK, |
| + msr1 & BN0_WF_MIB_TOP_MSR1_OFDM_LG_MIXED_VHT_MDRDY_TIME_MASK); |
| + seq_printf(s, ", OFDM_GREEN_MDRDY_TIME=0x%x\n", |
| + msr2 & BN0_WF_MIB_TOP_MSR2_OFDM_GREEN_MDRDY_TIME_MASK); |
| + seq_printf(s, "\tPrim CCA Time=0x%x\n", |
| + mctr5 & BN0_WF_MIB_TOP_MCTR5_P_CCA_TIME_MASK); |
| + seq_printf(s, "\tSec CCA Time=0x%x\n", |
| + mctr6 & BN0_WF_MIB_TOP_MCTR6_S_CCA_TIME_MASK); |
| + seq_printf(s, "\tPrim ED Time=0x%x\n", |
| + msdr18 & BN0_WF_MIB_TOP_M0SDR18_P_ED_TIME_MASK); |
| + |
| + seq_printf(s, "===Tx Related Counters(Generic)===\n"); |
| + mac_val = mt76_rr(dev, BN0_WF_MIB_TOP_TSCR18_ADDR + band_offset); |
| + dev->dbg.bcn_total_cnt[band_idx] += |
| + (mac_val & BN0_WF_MIB_TOP_TSCR18_BEACONTXCOUNT_MASK); |
| + seq_printf(s, "\tBeaconTxCnt=0x%x\n", dev->dbg.bcn_total_cnt[band_idx]); |
| + dev->dbg.bcn_total_cnt[band_idx] = 0; |
| + |
| + tbcr0 = mt76_rr(dev, BN0_WF_MIB_TOP_TBCR0_ADDR + band_offset); |
| + seq_printf(s, "\tTx 20MHz Cnt=0x%x\n", |
| + tbcr0 & BN0_WF_MIB_TOP_TBCR0_TX_20MHZ_CNT_MASK); |
| + tbcr1 = mt76_rr(dev, BN0_WF_MIB_TOP_TBCR1_ADDR + band_offset); |
| + seq_printf(s, "\tTx 40MHz Cnt=0x%x\n", |
| + tbcr1 & BN0_WF_MIB_TOP_TBCR1_TX_40MHZ_CNT_MASK); |
| + tbcr2 = mt76_rr(dev, BN0_WF_MIB_TOP_TBCR2_ADDR + band_offset); |
| + seq_printf(s, "\tTx 80MHz Cnt=0x%x\n", |
| + tbcr2 & BN0_WF_MIB_TOP_TBCR2_TX_80MHZ_CNT_MASK); |
| + tbcr3 = mt76_rr(dev, BN0_WF_MIB_TOP_TBCR3_ADDR + band_offset); |
| + seq_printf(s, "\tTx 160MHz Cnt=0x%x\n", |
| + tbcr3 & BN0_WF_MIB_TOP_TBCR3_TX_160MHZ_CNT_MASK); |
| + tbcr4 = mt76_rr(dev, BN0_WF_MIB_TOP_TBCR4_ADDR + band_offset); |
| + seq_printf(s, "\tTx 320MHz Cnt=0x%x\n", |
| + tbcr4 & BN0_WF_MIB_TOP_TBCR4_TX_320MHZ_CNT_MASK); |
| + seq_printf(s, "\tAMPDU Cnt=0x%x\n", ampdu_cnt[0]); |
| + seq_printf(s, "\tAMPDU MPDU Cnt=0x%x\n", ampdu_cnt[1]); |
| + seq_printf(s, "\tAMPDU MPDU Ack Cnt=0x%x\n", ampdu_cnt[2]); |
| + per = (ampdu_cnt[2] == 0 ? |
| + 0 : 1000 * (ampdu_cnt[1] - ampdu_cnt[2]) / ampdu_cnt[1]); |
| + seq_printf(s, "\tAMPDU MPDU PER=%ld.%1ld%%\n", per / 10, per % 10); |
| + |
| + seq_printf(s, "===MU Related Counters===\n"); |
| + mu_cnt[0] = mt76_rr(dev, BN0_WF_MIB_TOP_BSCR2_ADDR + band_offset); |
| + mu_cnt[1] = mt76_rr(dev, BN0_WF_MIB_TOP_TSCR5_ADDR + band_offset); |
| + mu_cnt[2] = mt76_rr(dev, BN0_WF_MIB_TOP_TSCR6_ADDR + band_offset); |
| + mu_cnt[3] = mt76_rr(dev, BN0_WF_MIB_TOP_TSCR8_ADDR + band_offset); |
| + mu_cnt[4] = mt76_rr(dev, BN0_WF_MIB_TOP_TSCR7_ADDR + band_offset); |
| + |
| + seq_printf(s, "\tMUBF_TX_COUNT=0x%x\n", |
| + mu_cnt[0] & BN0_WF_MIB_TOP_BSCR2_MUBF_TX_COUNT_MASK); |
| + seq_printf(s, "\tMU_TX_MPDU_COUNT(Ok+Fail)=0x%x\n", mu_cnt[1]); |
| + seq_printf(s, "\tMU_TX_OK_MPDU_COUNT=0x%x\n", mu_cnt[2]); |
| + seq_printf(s, "\tMU_TO_MU_FAIL_PPDU_COUNT=0x%x\n", mu_cnt[3]); |
| + seq_printf(s, "\tSU_TX_OK_MPDU_COUNT=0x%x\n", mu_cnt[4]); |
| + |
| + seq_printf(s, "===Rx Related Counters(Generic)===\n"); |
| + seq_printf(s, "\tVector Mismacth Cnt=0x%x\n", |
| + rvsr0 & BN0_WF_MIB_TOP_RVSR0_VEC_MISS_COUNT_MASK); |
| + seq_printf(s, "\tDelimiter Fail Cnt=0x%x\n", |
| + rscr35 & BN0_WF_MIB_TOP_RSCR35_DELIMITER_FAIL_COUNT_MASK); |
| + |
| + mac_val = mt76_rr(dev, BN0_WF_MIB_TOP_RSCR1_ADDR + band_offset); |
| + seq_printf(s, "\tRxFCSErrCnt=0x%x\n", |
| + (mac_val & BN0_WF_MIB_TOP_RSCR1_RX_FCS_ERROR_COUNT_MASK)); |
| + mac_val = mt76_rr(dev, BN0_WF_MIB_TOP_RSCR33_ADDR + band_offset); |
| + seq_printf(s, "\tRxFifoFullCnt=0x%x\n", |
| + (mac_val & BN0_WF_MIB_TOP_RSCR33_RX_FIFO_FULL_COUNT_MASK)); |
| + mac_val = mt76_rr(dev, BN0_WF_MIB_TOP_RSCR36_ADDR + band_offset); |
| + seq_printf(s, "\tRxLenMismatch=0x%x\n", |
| + (mac_val & BN0_WF_MIB_TOP_RSCR36_RX_LEN_MISMATCH_MASK)); |
| + mac_val = mt76_rr(dev, BN0_WF_MIB_TOP_RSCR31_ADDR + band_offset); |
| + seq_printf(s, "\tRxMPDUCnt=0x%x\n", |
| + (mac_val & BN0_WF_MIB_TOP_RSCR31_RX_MPDU_COUNT_MASK)); |
| + mac_val = mt76_rr(dev, BN0_WF_MIB_TOP_RSCR27_ADDR + band_offset); |
| + seq_printf(s, "\tRx AMPDU Cnt=0x%x\n", mac_val); |
| + mac_val = mt76_rr(dev, BN0_WF_MIB_TOP_RSCR28_ADDR + band_offset); |
| + seq_printf(s, "\tRx Total ByteCnt=0x%x\n", mac_val); |
| + |
| + |
| + /* Per-BSS T/RX Counters */ |
| + seq_printf(s, "===Per-BSS Related Tx/Rx Counters===\n"); |
| + seq_printf(s, "BSS Idx TxCnt/DataCnt TxByteCnt RxOkCnt/DataCnt RxByteCnt\n"); |
| + for (idx = 0; idx < bss_nums; idx++) { |
| + btcr = mt76_rr(dev, BN0_WF_MIB_TOP_BTCR_ADDR + band_offset + idx * 4); |
| + btdcr = mt76_rr(dev, BN0_WF_MIB_TOP_BTDCR_ADDR + band_offset + idx * 4); |
| + btbcr = mt76_rr(dev, BN0_WF_MIB_TOP_BTBCR_ADDR + band_offset + idx * 4); |
| + |
| + brocr = mt76_rr(dev, WF_UMIB_TOP_B0BROCR_ADDR + band_offset_umib + idx * 4); |
| + brdcr = mt76_rr(dev, WF_UMIB_TOP_B0BRDCR_ADDR + band_offset_umib + idx * 4); |
| + brbcr = mt76_rr(dev, WF_UMIB_TOP_B0BRBCR_ADDR + band_offset_umib + idx * 4); |
| + |
| + seq_printf(s, "%d\t 0x%x/0x%x\t 0x%x \t 0x%x/0x%x \t 0x%x\n", |
| + idx, btcr, btdcr, btbcr, brocr, brdcr, brbcr); |
| + } |
| + |
| + seq_printf(s, "===Per-BSS Related MIB Counters===\n"); |
| + seq_printf(s, "BSS Idx RTSTx/RetryCnt BAMissCnt AckFailCnt FrmRetry1/2/3Cnt\n"); |
| + |
| + /* Per-BSS TX Status */ |
| + for (idx = 0; idx < bss_nums; idx++) { |
| + btscr[0] = mt76_rr(dev, BN0_WF_MIB_TOP_BTSCR5_ADDR + band_offset + idx * 4); |
| + btscr[1] = mt76_rr(dev, BN0_WF_MIB_TOP_BTSCR6_ADDR + band_offset + idx * 4); |
| + btscr[2] = mt76_rr(dev, BN0_WF_MIB_TOP_BTSCR0_ADDR + band_offset + idx * 4); |
| + btscr[3] = mt76_rr(dev, BN0_WF_MIB_TOP_BTSCR1_ADDR + band_offset + idx * 4); |
| + btscr[4] = mt76_rr(dev, BN0_WF_MIB_TOP_BTSCR2_ADDR + band_offset + idx * 4); |
| + btscr[5] = mt76_rr(dev, BN0_WF_MIB_TOP_BTSCR3_ADDR + band_offset + idx * 4); |
| + btscr[6] = mt76_rr(dev, BN0_WF_MIB_TOP_BTSCR4_ADDR + band_offset + idx * 4); |
| + |
| + seq_printf(s, "%d:\t0x%x/0x%x 0x%x \t 0x%x \t 0x%x/0x%x/0x%x\n", |
| + idx, (btscr[0] & BN0_WF_MIB_TOP_BTSCR5_RTSTXCOUNTn_MASK), |
| + (btscr[1] & BN0_WF_MIB_TOP_BTSCR6_RTSRETRYCOUNTn_MASK), |
| + (btscr[2] & BN0_WF_MIB_TOP_BTSCR0_BAMISSCOUNTn_MASK), |
| + (btscr[3] & BN0_WF_MIB_TOP_BTSCR1_ACKFAILCOUNTn_MASK), |
| + (btscr[4] & BN0_WF_MIB_TOP_BTSCR2_FRAMERETRYCOUNTn_MASK), |
| + (btscr[5] & BN0_WF_MIB_TOP_BTSCR3_FRAMERETRY2COUNTn_MASK), |
| + (btscr[6] & BN0_WF_MIB_TOP_BTSCR4_FRAMERETRY3COUNTn_MASK)); |
| + } |
| + |
| + /* Dummy delimiter insertion result */ |
| + seq_printf(s, "===Dummy delimiter insertion result===\n"); |
| + tdrcr[0] = mt76_rr(dev, BN0_WF_MIB_TOP_TDRCR0_ADDR + band_offset); |
| + tdrcr[1] = mt76_rr(dev, BN0_WF_MIB_TOP_TDRCR1_ADDR + band_offset); |
| + tdrcr[2] = mt76_rr(dev, BN0_WF_MIB_TOP_TDRCR2_ADDR + band_offset); |
| + tdrcr[3] = mt76_rr(dev, BN0_WF_MIB_TOP_TDRCR3_ADDR + band_offset); |
| + tdrcr[4] = mt76_rr(dev, BN0_WF_MIB_TOP_TDRCR4_ADDR + band_offset); |
| + |
| + seq_printf(s, "Range0 = %d\t Range1 = %d\t Range2 = %d\t Range3 = %d\t Range4 = %d\n", |
| + tdrcr[0], |
| + tdrcr[1], |
| + tdrcr[2], |
| + tdrcr[3], |
| + tdrcr[4]); |
| + |
| + /* Per-MBSS T/RX Counters */ |
| + seq_printf(s, "===Per-MBSS Related Tx/Rx Counters===\n"); |
| + seq_printf(s, "MBSSIdx TxOkCnt TxByteCnt RxOkCnt RxByteCnt\n"); |
| + |
| + for (idx = 0; idx < 16; idx++) { |
| + mbtocr[idx] = mt76_rr(dev, BN0_WF_MIB_TOP_BTOCR_ADDR + band_offset + (bss_nums + idx) * 4); |
| + mbtbcr[idx] = mt76_rr(dev, BN0_WF_MIB_TOP_BTBCR_ADDR + band_offset + (bss_nums + idx) * 4); |
| + |
| + mbrocr[idx] = mt76_rr(dev, WF_UMIB_TOP_B0BROCR_ADDR + band_offset_umib + (bss_nums + idx) * 4); |
| + mbrbcr[idx] = mt76_rr(dev, WF_UMIB_TOP_B0BRBCR_ADDR + band_offset_umib + (bss_nums + idx) * 4); |
| + } |
| + |
| + for (idx = 0; idx < 16; idx++) { |
| + seq_printf(s, "%d\t 0x%x\t 0x%x \t 0x%x \t 0x%x\n", |
| + idx, mbtocr[idx], mbtbcr[idx], mbrocr[idx], mbrbcr[idx]); |
| + } |
| + |
| + return 0; |
| +} |
| + |
| +static int besra_mibinfo_band0(struct seq_file *s, void *data) |
| +{ |
| + besra_mibinfo_read_per_band(s, MT_BAND0); |
| + return 0; |
| +} |
| + |
| +static int besra_mibinfo_band1(struct seq_file *s, void *data) |
| +{ |
| + besra_mibinfo_read_per_band(s, MT_BAND1); |
| + return 0; |
| +} |
| + |
| +static int besra_mibinfo_band2(struct seq_file *s, void *data) |
| +{ |
| + besra_mibinfo_read_per_band(s, MT_BAND2); |
| + return 0; |
| +} |
| + |
| +//bmac dump txp |
| +void besra_dump_bmac_txp_info(struct besra_dev *dev, __le32 *txp) |
| +{ |
| + int i, j = 0; |
| + u32 dw; |
| + |
| + printk("txp raw data: size=%d\n", HIF_TXP_V2_SIZE); |
| + print_hex_dump(KERN_ERR , "", DUMP_PREFIX_OFFSET, 16, 1, (u8 *)txp, HIF_TXP_V2_SIZE, false); |
| + |
| + printk("BMAC_TXP Fields:\n"); |
| + |
| + /* dw0 */ |
| + dw = le32_to_cpu(txp[0]); |
| + printk("HIF_TXP_PRIORITY = %d\n", |
| + GET_FIELD(HIF_TXP_PRIORITY, dw)); |
| + printk("HIF_TXP_FIXED_RATE = %d\n", |
| + GET_FIELD(HIF_TXP_FIXED_RATE, dw)); |
| + printk("HIF_TXP_TCP = %d\n", |
| + GET_FIELD(HIF_TXP_TCP, dw)); |
| + printk("HIF_TXP_NON_CIPHER = %d\n", |
| + GET_FIELD(HIF_TXP_NON_CIPHER, dw)); |
| + printk("HIF_TXP_VLAN = %d\n", |
| + GET_FIELD(HIF_TXP_VLAN, dw)); |
| + printk("HIF_TXP_BC_MC_FLAG = %d\n", |
| + GET_FIELD(HIF_TXP_BC_MC_FLAG, dw)); |
| + printk("HIF_TXP_FR_HOST = %d\n", |
| + GET_FIELD(HIF_TXP_FR_HOST, dw)); |
| + printk("HIF_TXP_ETYPE = %d\n", |
| + GET_FIELD(HIF_TXP_ETYPE, dw)); |
| + printk("HIF_TXP_TXP_AMSDU = %d\n", |
| + GET_FIELD(HIF_TXP_TXP_AMSDU, dw)); |
| + printk("HIF_TXP_TXP_MC_CLONE = %d\n", |
| + GET_FIELD(HIF_TXP_TXP_MC_CLONE, dw)); |
| + printk("HIF_TXP_TOKEN_ID = %d\n", |
| + GET_FIELD(HIF_TXP_TOKEN_ID, dw)); |
| + |
| + /* dw1 */ |
| + dw = le32_to_cpu(txp[1]); |
| + printk("HIF_TXP_BSS_IDX = %d\n", |
| + GET_FIELD(HIF_TXP_BSS_IDX, dw)); |
| + printk("HIF_TXP_USER_PRIORITY = %d\n", |
| + GET_FIELD(HIF_TXP_USER_PRIORITY, dw)); |
| + printk("HIF_TXP_BUF_NUM = %d\n", |
| + GET_FIELD(HIF_TXP_BUF_NUM, dw)); |
| + printk("HIF_TXP_MSDU_CNT = %d\n", |
| + GET_FIELD(HIF_TXP_MSDU_CNT, dw)); |
| + printk("HIF_TXP_SRC = %d\n", |
| + GET_FIELD(HIF_TXP_SRC, dw)); |
| + |
| + /* dw2 */ |
| + dw = le32_to_cpu(txp[2]); |
| + printk("HIF_TXP_ETH_TYPE(network-endian) = 0x%x\n", |
| + GET_FIELD(HIF_TXP_ETH_TYPE, dw)); |
| + printk("HIF_TXP_WLAN_IDX = %d\n", |
| + GET_FIELD(HIF_TXP_WLAN_IDX, dw)); |
| + |
| + /* dw3 */ |
| + dw = le32_to_cpu(txp[3]); |
| + printk("HIF_TXP_PPE_INFO = 0x%x\n", |
| + GET_FIELD(HIF_TXP_PPE_INFO, dw)); |
| + |
| + for (i = 0; i < 13; i++) { |
| + if (i % 2 == 0) { |
| + printk("HIF_TXP_BUF_PTR%d_L = 0x%x\n", |
| + i, GET_FIELD(HIF_TXP_BUF_PTR0_L, |
| + le32_to_cpu(txp[4 + j]))); |
| + j++; |
| + printk("HIF_TXP_BUF_LEN%d = %d\n", |
| + i, GET_FIELD(HIF_TXP_BUF_LEN0, le32_to_cpu(txp[4 + j]))); |
| + printk("HIF_TXP_BUF_PTR%d_H = 0x%x\n", |
| + i, GET_FIELD(HIF_TXP_BUF_PTR0_H, le32_to_cpu(txp[4 + j]))); |
| + if (i <= 10) { |
| + printk("HIF_TXP_BUF_LEN%d = %d\n", |
| + i + 1, GET_FIELD(HIF_TXP_BUF_LEN1, le32_to_cpu(txp[4 + j]))); |
| + printk("HIF_TXP_BUF_PTR%d_H = 0x%x\n", |
| + i + 1, GET_FIELD(HIF_TXP_BUF_PTR1_H, le32_to_cpu(txp[4 + j]))); |
| + } |
| + j++; |
| + } else { |
| + printk("HIF_TXP_BUF_PTR%d_L = 0x%x\n", |
| + i, GET_FIELD(HIF_TXP_BUF_PTR1_L, |
| + le32_to_cpu(txp[4 + j]))); |
| + j++; |
| + } |
| + } |
| + |
| + printk("ml = 0x%x\n", |
| + GET_FIELD(HIF_TXP_ML, le32_to_cpu(txp[23]))); |
| +} |
| + |
| +/* bmac txd dump */ |
| +void besra_dump_bmac_txd_info(struct besra_dev *dev, __le32 *txd, bool dump_txp) |
| +{ |
| + /* dump stop */ |
| + if (!dev->dbg.txd_read_cnt) |
| + return; |
| + |
| + /* force dump */ |
| + if (dev->dbg.txd_read_cnt > 8) |
| + dev->dbg.txd_read_cnt = 8; |
| + |
| + /* dump txd_read_cnt times */ |
| + if (dev->dbg.txd_read_cnt != 8) |
| + dev->dbg.txd_read_cnt--; |
| + |
| + printk("txd raw data: size=%d\n", MT_TXD_SIZE); |
| + print_hex_dump(KERN_ERR , "", DUMP_PREFIX_OFFSET, 16, 1, (u8 *)txd, MT_TXD_SIZE, false); |
| + |
| + printk("BMAC_TXD Fields:\n"); |
| + /* dw0 */ |
| + printk("TX_BYTE_COUNT = %d\n", |
| + GET_FIELD(WF_TX_DESCRIPTOR_TX_BYTE_COUNT, txd[0])); |
| + printk("ETHER_TYPE_OFFSET(word) = %d\n", |
| + GET_FIELD(WF_TX_DESCRIPTOR_ETHER_TYPE_OFFSET, txd[0])); |
| + printk("PKT_FT = %d%s%s%s%s\n", |
| + GET_FIELD(WF_TX_DESCRIPTOR_PKT_FT, txd[0]), |
| + GET_FIELD(WF_TX_DESCRIPTOR_PKT_FT, txd[0]) == 0 ? "(ct)" : "", |
| + GET_FIELD(WF_TX_DESCRIPTOR_PKT_FT, txd[0]) == 1 ? "(s&f)" : "", |
| + GET_FIELD(WF_TX_DESCRIPTOR_PKT_FT, txd[0]) == 2 ? "(cmd)" : "", |
| + GET_FIELD(WF_TX_DESCRIPTOR_PKT_FT, txd[0]) == 3 ? "(redirect)" : ""); |
| + printk("Q_IDX = %d%s%s%s\n", |
| + GET_FIELD(WF_TX_DESCRIPTOR_Q_IDX, txd[0]), |
| + GET_FIELD(WF_TX_DESCRIPTOR_Q_IDX, txd[0]) == 0x10 ? "(ALTX)" : "", |
| + GET_FIELD(WF_TX_DESCRIPTOR_Q_IDX, txd[0]) == 0x11 ? "(BMC)" : "", |
| + GET_FIELD(WF_TX_DESCRIPTOR_Q_IDX, txd[0]) == 0x12 ? "(BCN)" : ""); |
| + |
| + /* dw1 */ |
| + printk("MLD_ID = %d\n", |
| + GET_FIELD(WF_TX_DESCRIPTOR_MLD_ID, txd[1])); |
| + printk("TGID = %d\n", |
| + GET_FIELD(WF_TX_DESCRIPTOR_TGID, txd[1])); |
| + printk("HF = %d%s%s%s%s\n", |
| + GET_FIELD(WF_TX_DESCRIPTOR_HF, txd[1]), |
| + GET_FIELD(WF_TX_DESCRIPTOR_HF, txd[1]) == 0 ? "(eth/802.3)" : "", |
| + GET_FIELD(WF_TX_DESCRIPTOR_HF, txd[1]) == 1 ? "(cmd)" : "", |
| + GET_FIELD(WF_TX_DESCRIPTOR_HF, txd[1]) == 2 ? "(802.11)" : "", |
| + GET_FIELD(WF_TX_DESCRIPTOR_HF, txd[1]) == 3 ? "(802.11 enhanced" : ""); |
| + printk("802.11 HEADER_LENGTH = %d\n", |
| + GET_FIELD(WF_TX_DESCRIPTOR_HF, txd[1]) == 2 ? |
| + GET_FIELD(WF_TX_DESCRIPTOR_HEADER_LENGTH, txd[1]) : 0); |
| + printk("MRD = %d\n", |
| + GET_FIELD(WF_TX_DESCRIPTOR_HF, txd[1]) == 0 ? |
| + GET_FIELD(WF_TX_DESCRIPTOR_MRD, txd[1]) : 0); |
| + printk("EOSP = %d\n", |
| + GET_FIELD(WF_TX_DESCRIPTOR_HF, txd[1]) == 0 ? |
| + GET_FIELD(WF_TX_DESCRIPTOR_EOSP, txd[1]) : 0); |
| + printk("AMS = %d\n", |
| + GET_FIELD(WF_TX_DESCRIPTOR_HF, txd[1]) == 3 ? |
| + GET_FIELD(WF_TX_DESCRIPTOR_AMS, txd[1]) : 0); |
| + printk("RMVL = %d\n", |
| + GET_FIELD(WF_TX_DESCRIPTOR_HF, txd[1]) == 0 ? |
| + GET_FIELD(WF_TX_DESCRIPTOR_RMVL, txd[1]): 0); |
| + printk("VLAN = %d\n", |
| + GET_FIELD(WF_TX_DESCRIPTOR_HF, txd[1]) == 0 ? |
| + GET_FIELD(WF_TX_DESCRIPTOR_VLAN, txd[1]) : 0); |
| + printk("ETYP = %d\n", |
| + GET_FIELD(WF_TX_DESCRIPTOR_HF, txd[1]) == 0 ? |
| + GET_FIELD(WF_TX_DESCRIPTOR_ETYP, txd[1]) : 0); |
| + printk("TID_MGMT_TYPE = %d\n", |
| + GET_FIELD(WF_TX_DESCRIPTOR_TID_MGMT_TYPE, txd[1])); |
| + printk("OM = %d\n", |
| + GET_FIELD(WF_TX_DESCRIPTOR_OM, txd[1])); |
| + printk("FR = %d\n", |
| + GET_FIELD(WF_TX_DESCRIPTOR_FR, txd[1])); |
| + |
| + /* dw2 */ |
| + printk("SUBTYPE = %d%s%s%s%s\n", |
| + GET_FIELD(WF_TX_DESCRIPTOR_SUBTYPE, txd[2]), |
| + (GET_FIELD(WF_TX_DESCRIPTOR_FTYPE, txd[2]) == 0) && |
| + (GET_FIELD(WF_TX_DESCRIPTOR_SUBTYPE, txd[2]) == 13) ? |
| + "(action)" : "", |
| + (GET_FIELD(WF_TX_DESCRIPTOR_FTYPE, txd[2]) == 1) && |
| + (GET_FIELD(WF_TX_DESCRIPTOR_SUBTYPE, txd[2]) == 8) ? |
| + "(bar)" : "", |
| + (GET_FIELD(WF_TX_DESCRIPTOR_FTYPE, txd[2]) == 2) && |
| + (GET_FIELD(WF_TX_DESCRIPTOR_SUBTYPE, txd[2]) == 4) ? |
| + "(null)" : "", |
| + (GET_FIELD(WF_TX_DESCRIPTOR_FTYPE, txd[2]) == 2) && |
| + (GET_FIELD(WF_TX_DESCRIPTOR_SUBTYPE, txd[2]) == 12) ? |
| + "(qos null)" : ""); |
| + |
| + printk("FTYPE = %d%s\n", |
| + GET_FIELD(WF_TX_DESCRIPTOR_FTYPE, txd[2]), |
| + GET_FIELD(WF_TX_DESCRIPTOR_FTYPE, txd[2]) == 0 ? "(mgmt)" : "", |
| + GET_FIELD(WF_TX_DESCRIPTOR_FTYPE, txd[2]) == 1 ? "(ctl)" : "", |
| + GET_FIELD(WF_TX_DESCRIPTOR_FTYPE, txd[2]) == 2 ? "(data)" : ""); |
| + printk("BF_TYPE = %d\n", |
| + GET_FIELD(WF_TX_DESCRIPTOR_BF_TYPE, txd[2])); |
| + printk("OM_MAP = %d\n", |
| + GET_FIELD(WF_TX_DESCRIPTOR_OM_MAP, txd[2])); |
| + printk("RTS = %d\n", |
| + GET_FIELD(WF_TX_DESCRIPTOR_RTS, txd[2])); |
| + printk("HEADER_PADDING = %d\n", |
| + GET_FIELD(WF_TX_DESCRIPTOR_HEADER_PADDING, txd[2])); |
| + printk("DU = %d\n", |
| + GET_FIELD(WF_TX_DESCRIPTOR_DU, txd[2])); |
| + printk("HE = %d\n", |
| + GET_FIELD(WF_TX_DESCRIPTOR_HE, txd[2])); |
| + printk("FRAG = %d\n", |
| + GET_FIELD(WF_TX_DESCRIPTOR_FRAG, txd[2])); |
| + printk("REMAINING_TX_TIME = %d\n", |
| + GET_FIELD(WF_TX_DESCRIPTOR_REMAINING_TX_TIME, txd[2])); |
| + printk("POWER_OFFSET = %d\n", |
| + GET_FIELD(WF_TX_DESCRIPTOR_POWER_OFFSET, txd[2])); |
| + |
| + /* dw3 */ |
| + printk("NA = %d\n", |
| + GET_FIELD(WF_TX_DESCRIPTOR_NA, txd[3])); |
| + printk("PF = %d\n", |
| + GET_FIELD(WF_TX_DESCRIPTOR_PF, txd[3])); |
| + printk("EMRD = %d\n", |
| + GET_FIELD(WF_TX_DESCRIPTOR_EMRD, txd[3])); |
| + printk("EEOSP = %d\n", |
| + GET_FIELD(WF_TX_DESCRIPTOR_EEOSP, txd[3])); |
| + printk("BM = %d\n", |
| + GET_FIELD(WF_TX_DESCRIPTOR_BM, txd[3])); |
| + printk("HW_AMSDU_CAP = %d\n", |
| + GET_FIELD(WF_TX_DESCRIPTOR_HW_AMSDU_CAP, txd[3])); |
| + printk("TX_COUNT = %d\n", |
| + GET_FIELD(WF_TX_DESCRIPTOR_TX_COUNT, txd[3])); |
| + printk("REMAINING_TX_COUNT = %d\n", |
| + GET_FIELD(WF_TX_DESCRIPTOR_REMAINING_TX_COUNT, txd[3])); |
| + printk("SN = %d\n", |
| + GET_FIELD(WF_TX_DESCRIPTOR_SN, txd[3])); |
| + printk("BA_DIS = %d\n", |
| + GET_FIELD(WF_TX_DESCRIPTOR_BA_DIS, txd[3])); |
| + printk("PM = %d\n", |
| + GET_FIELD(WF_TX_DESCRIPTOR_PM, txd[3])); |
| + printk("PN_VLD = %d\n", |
| + GET_FIELD(WF_TX_DESCRIPTOR_PN_VLD, txd[3])); |
| + printk("SN_VLD = %d\n", |
| + GET_FIELD(WF_TX_DESCRIPTOR_SN_VLD, txd[3])); |
| + |
| + /* dw4 */ |
| + printk("PN_31_0 = 0x%x\n", |
| + GET_FIELD(WF_TX_DESCRIPTOR_PN_31_0_, txd[4])); |
| + |
| + /* dw5 */ |
| + printk("PID = %d\n", |
| + GET_FIELD(WF_TX_DESCRIPTOR_PID, txd[5])); |
| + printk("TXSFM = %d\n", |
| + GET_FIELD(WF_TX_DESCRIPTOR_TXSFM, txd[5])); |
| + printk("TXS2M = %d\n", |
| + GET_FIELD(WF_TX_DESCRIPTOR_TXS2M, txd[5])); |
| + printk("TXS2H = %d\n", |
| + GET_FIELD(WF_TX_DESCRIPTOR_TXS2H, txd[5])); |
| + printk("FBCZ = %d\n", |
| + GET_FIELD(WF_TX_DESCRIPTOR_FBCZ, txd[5])); |
| + printk("BYPASS_RBB = %d\n", |
| + GET_FIELD(WF_TX_DESCRIPTOR_BYPASS_RBB, txd[5])); |
| + |
| + printk("FL = %d\n", |
| + GET_FIELD(WF_TX_DESCRIPTOR_FL, txd[5])); |
| + printk("PN_47_32 = 0x%x\n", |
| + GET_FIELD(WF_TX_DESCRIPTOR_PN_47_32_, txd[5])); |
| + |
| + /* dw6 */ |
| + printk("AMSDU_CAP_UTXB = %d\n", |
| + GET_FIELD(WF_TX_DESCRIPTOR_AMSDU_CAP_UTXB, txd[6])); |
| + printk("DAS = %d\n", |
| + GET_FIELD(WF_TX_DESCRIPTOR_DAS, txd[6])); |
| + printk("DIS_MAT = %d\n", |
| + GET_FIELD(WF_TX_DESCRIPTOR_DIS_MAT, txd[6])); |
| + printk("MSDU_COUNT = %d\n", |
| + GET_FIELD(WF_TX_DESCRIPTOR_MSDU_COUNT, txd[6])); |
| + printk("TIMESTAMP_OFFSET = %d\n", |
| + GET_FIELD(WF_TX_DESCRIPTOR_TIMESTAMP_OFFSET_IDX, txd[6])); |
| + printk("FIXED_RATE_IDX = %d\n", |
| + GET_FIELD(WF_TX_DESCRIPTOR_FIXED_RATE_IDX, txd[6])); |
| + printk("BW = %d\n", |
| + GET_FIELD(WF_TX_DESCRIPTOR_BW, txd[6])); |
| + printk("VTA = %d\n", |
| + GET_FIELD(WF_TX_DESCRIPTOR_VTA, txd[6])); |
| + printk("SRC = %d\n", |
| + GET_FIELD(WF_TX_DESCRIPTOR_SRC, txd[6])); |
| + |
| + /* dw7 */ |
| + printk("SW_TX_TIME(unit:65536ns) = d%\n", |
| + GET_FIELD(WF_TX_DESCRIPTOR_SW_TX_TIME , txd[7])); |
| + printk("UT = %d\n", |
| + GET_FIELD(WF_TX_DESCRIPTOR_UT, txd[7])); |
| + printk("CTXD_CNT = %d\n", |
| + GET_FIELD(WF_TX_DESCRIPTOR_CTXD_CNT, txd[7])); |
| + printk("HM = %d\n", |
| + GET_FIELD(WF_TX_DESCRIPTOR_HM, txd[7])); |
| + printk("DP = %d\n", |
| + GET_FIELD(WF_TX_DESCRIPTOR_DP, txd[7])); |
| + printk("IP = %d\n", |
| + GET_FIELD(WF_TX_DESCRIPTOR_IP, txd[7])); |
| + printk("TXD_LEN = %d\n", |
| + GET_FIELD(WF_TX_DESCRIPTOR_TXD_LEN, txd[7])); |
| + |
| + if (dump_txp) { |
| + __le32 *txp = txd + 8; |
| + |
| + besra_dump_bmac_txp_info(dev, txp); |
| + } |
| +} |
| + |
| +static void |
| +besra_dump_bmac_txd_by_fid(u32 fid) |
| +{ |
| + //TDO |
| +} |
| + |
| +void besra_dump_bmac_rxd_info(struct besra_dev *dev, __le32 *rxd) |
| +{ |
| + /* dump stop */ |
| + if (!dev->dbg.rxd_read_cnt) |
| + return; |
| + |
| + /* force dump */ |
| + if (dev->dbg.rxd_read_cnt > 8) |
| + dev->dbg.rxd_read_cnt = 8; |
| + |
| + /* dump txd_read_cnt times */ |
| + if (dev->dbg.rxd_read_cnt != 8) |
| + dev->dbg.rxd_read_cnt--; |
| + |
| + printk("rxd raw data: size=%d\n", MT_TXD_SIZE); |
| + print_hex_dump(KERN_ERR , "", DUMP_PREFIX_OFFSET, 16, 1, (u8 *)rxd, 96, false); |
| + |
| + printk("BMAC_RXD Fields:\n"); |
| + |
| + /* group0 */ |
| + /* dw0 */ |
| + printk("RX_BYTE_COUNT = %d\n", |
| + GET_FIELD(WF_RX_DESCRIPTOR_RX_BYTE_COUNT, le32_to_cpu(rxd[0]))); |
| + printk("PACKET_TYPE = %d\n", |
| + GET_FIELD(WF_RX_DESCRIPTOR_PACKET_TYPE, le32_to_cpu(rxd[0]))); |
| + |
| + /* dw1 */ |
| + printk("MLD_ID = %d\n", |
| + GET_FIELD(WF_RX_DESCRIPTOR_MLD_ID, le32_to_cpu(rxd[1]))); |
| + printk("GROUP_VLD = 0x%x%s%s%s%s%s\n", |
| + GET_FIELD(WF_RX_DESCRIPTOR_GROUP_VLD, le32_to_cpu(rxd[1])), |
| + GET_FIELD(WF_RX_DESCRIPTOR_GROUP_VLD, le32_to_cpu(rxd[1])) |
| + & BMAC_GROUP_VLD_1 ? "[group1]" : "", |
| + GET_FIELD(WF_RX_DESCRIPTOR_GROUP_VLD, le32_to_cpu(rxd[1])) |
| + & BMAC_GROUP_VLD_2 ? "[group2]" : "", |
| + GET_FIELD(WF_RX_DESCRIPTOR_GROUP_VLD, le32_to_cpu(rxd[1])) |
| + & BMAC_GROUP_VLD_3 ? "[group3]" : "", |
| + GET_FIELD(WF_RX_DESCRIPTOR_GROUP_VLD, le32_to_cpu(rxd[1])) |
| + & BMAC_GROUP_VLD_4 ? "[group4]" : "", |
| + GET_FIELD(WF_RX_DESCRIPTOR_GROUP_VLD, le32_to_cpu(rxd[1])) |
| + & BMAC_GROUP_VLD_5 ? "[group5]" : ""); |
| + printk("KID = %d\n", |
| + GET_FIELD(WF_RX_DESCRIPTOR_KID, le32_to_cpu(rxd[1]))); |
| + printk("CM = %d\n", |
| + GET_FIELD(WF_RX_DESCRIPTOR_CM, le32_to_cpu(rxd[1]))); |
| + printk("CLM = %d\n", |
| + GET_FIELD(WF_RX_DESCRIPTOR_CLM, le32_to_cpu(rxd[1]))); |
| + printk("I = %d\n", |
| + GET_FIELD(WF_RX_DESCRIPTOR_I, le32_to_cpu(rxd[1]))); |
| + printk("T = %d\n", |
| + GET_FIELD(WF_RX_DESCRIPTOR_T, le32_to_cpu(rxd[1]))); |
| + printk("BN = %d\n", |
| + GET_FIELD(WF_RX_DESCRIPTOR_BN, le32_to_cpu(rxd[1]))); |
| + printk("BIPN_FAIL = %d\n", |
| + GET_FIELD(WF_RX_DESCRIPTOR_BIPN_FAIL, le32_to_cpu(rxd[1]))); |
| + |
| + /* dw2 */ |
| + printk("BSSID = %d\n", |
| + GET_FIELD(WF_RX_DESCRIPTOR_BSSID, le32_to_cpu(rxd[2]))); |
| + printk("H = %d%s\n", |
| + GET_FIELD(WF_RX_DESCRIPTOR_H, le32_to_cpu(rxd[2])), |
| + GET_FIELD(WF_RX_DESCRIPTOR_H, le32_to_cpu(rxd[2])) == 0 ? |
| + "802.11 frame" : "eth/802.3 frame"); |
| + printk("HEADER_LENGTH(word) = %d\n", |
| + GET_FIELD(WF_RX_DESCRIPTOR_HEADER_LENGTH, le32_to_cpu(rxd[2]))); |
| + printk("HO(word) = %d\n", |
| + GET_FIELD(WF_RX_DESCRIPTOR_HO, le32_to_cpu(rxd[2]))); |
| + printk("SEC_MODE = %d\n", |
| + GET_FIELD(WF_RX_DESCRIPTOR_SEC_MODE, le32_to_cpu(rxd[2]))); |
| + printk("MUBAR = %d\n", |
| + GET_FIELD(WF_RX_DESCRIPTOR_MUBAR, le32_to_cpu(rxd[2]))); |
| + printk("SWBIT = %d\n", |
| + GET_FIELD(WF_RX_DESCRIPTOR_SWBIT, le32_to_cpu(rxd[2]))); |
| + printk("DAF = %d\n", |
| + GET_FIELD(WF_RX_DESCRIPTOR_DAF, le32_to_cpu(rxd[2]))); |
| + printk("EL = %d\n", |
| + GET_FIELD(WF_RX_DESCRIPTOR_EL, le32_to_cpu(rxd[2]))); |
| + printk("HTF = %d\n", |
| + GET_FIELD(WF_RX_DESCRIPTOR_HTF, le32_to_cpu(rxd[2]))); |
| + printk("INTF = %d\n", |
| + GET_FIELD(WF_RX_DESCRIPTOR_INTF, le32_to_cpu(rxd[2]))); |
| + printk("FRAG = %d\n", |
| + GET_FIELD(WF_RX_DESCRIPTOR_FRAG, le32_to_cpu(rxd[2]))); |
| + printk("NUL = %d\n", |
| + GET_FIELD(WF_RX_DESCRIPTOR_NUL, le32_to_cpu(rxd[2]))); |
| + printk("NDATA = %d%s\n", |
| + GET_FIELD(WF_RX_DESCRIPTOR_NDATA, le32_to_cpu(rxd[2])), |
| + GET_FIELD(WF_RX_DESCRIPTOR_NDATA, le32_to_cpu(rxd[2])) == 0 ? |
| + "[data frame]" : "[mgmt/ctl frame]"); |
| + printk("NAMP = %d%s\n", |
| + GET_FIELD(WF_RX_DESCRIPTOR_NAMP, le32_to_cpu(rxd[2])), |
| + GET_FIELD(WF_RX_DESCRIPTOR_NAMP, le32_to_cpu(rxd[2])) == 0 ? |
| + "[ampdu frame]" : "[mpdu frame]"); |
| + printk("BF_RPT = %d\n", |
| + GET_FIELD(WF_RX_DESCRIPTOR_BF_RPT, le32_to_cpu(rxd[2]))); |
| + |
| + /* dw3 */ |
| + printk("RXV_SN = %d\n", |
| + GET_FIELD(WF_RX_DESCRIPTOR_RXV_SN, le32_to_cpu(rxd[3]))); |
| + printk("CH_FREQUENCY = %d\n", |
| + GET_FIELD(WF_RX_DESCRIPTOR_CH_FREQUENCY, le32_to_cpu(rxd[3]))); |
| + printk("A1_TYPE = %d%s%s%s%s\n", |
| + GET_FIELD(WF_RX_DESCRIPTOR_A1_TYPE, le32_to_cpu(rxd[3])), |
| + GET_FIELD(WF_RX_DESCRIPTOR_A1_TYPE, le32_to_cpu(rxd[3])) == 0 ? |
| + "[reserved]" : "", |
| + GET_FIELD(WF_RX_DESCRIPTOR_A1_TYPE, le32_to_cpu(rxd[3])) == 1 ? |
| + "[uc2me]" : "", |
| + GET_FIELD(WF_RX_DESCRIPTOR_A1_TYPE, le32_to_cpu(rxd[3])) == 2 ? |
| + "[mc]" : "", |
| + GET_FIELD(WF_RX_DESCRIPTOR_A1_TYPE, le32_to_cpu(rxd[3])) == 3 ? |
| + "[bc]" : ""); |
| + printk("HTC = %d\n", |
| + GET_FIELD(WF_RX_DESCRIPTOR_HTC, le32_to_cpu(rxd[3]))); |
| + printk("TCL = %d\n", |
| + GET_FIELD(WF_RX_DESCRIPTOR_TCL, le32_to_cpu(rxd[3]))); |
| + printk("BBM = %d\n", |
| + GET_FIELD(WF_RX_DESCRIPTOR_BBM, le32_to_cpu(rxd[3]))); |
| + printk("BU = %d\n", |
| + GET_FIELD(WF_RX_DESCRIPTOR_BU, le32_to_cpu(rxd[3]))); |
| + printk("CO_ANT = %d\n", |
| + GET_FIELD(WF_RX_DESCRIPTOR_CO_ANT, le32_to_cpu(rxd[3]))); |
| + printk("BF_CQI = %d\n", |
| + GET_FIELD(WF_RX_DESCRIPTOR_BF_CQI, le32_to_cpu(rxd[3]))); |
| + printk("FC = %d\n", |
| + GET_FIELD(WF_RX_DESCRIPTOR_FC, le32_to_cpu(rxd[3]))); |
| + printk("VLAN = %d\n", |
| + GET_FIELD(WF_RX_DESCRIPTOR_VLAN, le32_to_cpu(rxd[3]))); |
| + |
| + /* dw4 */ |
| + printk("PF = %d%s%s%s%s\n", |
| + GET_FIELD(WF_RX_DESCRIPTOR_PF, le32_to_cpu(rxd[4])), |
| + GET_FIELD(WF_RX_DESCRIPTOR_PF, le32_to_cpu(rxd[4])) == 0 ? |
| + "[msdu]" : "", |
| + GET_FIELD(WF_RX_DESCRIPTOR_PF, le32_to_cpu(rxd[4])) == 1 ? |
| + "[final amsdu]" : "", |
| + GET_FIELD(WF_RX_DESCRIPTOR_PF, le32_to_cpu(rxd[4])) == 2 ? |
| + "[middle amsdu]" : "", |
| + GET_FIELD(WF_RX_DESCRIPTOR_PF, le32_to_cpu(rxd[4])) == 3 ? |
| + "[first amsdu]" : ""); |
| + printk("MAC = %d\n", |
| + GET_FIELD(WF_RX_DESCRIPTOR_MAC, le32_to_cpu(rxd[4]))); |
| + printk("TID = %d\n", |
| + GET_FIELD(WF_RX_DESCRIPTOR_TID, le32_to_cpu(rxd[4]))); |
| + printk("ETHER_TYPE_OFFSET = %d\n", |
| + GET_FIELD(WF_RX_DESCRIPTOR_ETHER_TYPE_OFFSET, le32_to_cpu(rxd[4]))); |
| + printk("IP = %d\n", |
| + GET_FIELD(WF_RX_DESCRIPTOR_IP, le32_to_cpu(rxd[4]))); |
| + printk("UT = %d\n", |
| + GET_FIELD(WF_RX_DESCRIPTOR_UT, le32_to_cpu(rxd[4]))); |
| + printk("PSE_FID = %d\n", |
| + GET_FIELD(WF_RX_DESCRIPTOR_PSE_FID, le32_to_cpu(rxd[4]))); |
| + |
| + /* group4 */ |
| + /* dw0 */ |
| + printk("FRAME_CONTROL_FIELD = 0x%x\n", |
| + GET_FIELD(WF_RX_DESCRIPTOR_GROUP_VLD, le32_to_cpu(rxd[1])) |
| + & BMAC_GROUP_VLD_4 ? |
| + GET_FIELD(WF_RX_DESCRIPTOR_FRAME_CONTROL_FIELD, le32_to_cpu(rxd[8])) : 0); |
| + printk("PEER_MLD_ADDRESS_15_0 = 0x%x\n", |
| + GET_FIELD(WF_RX_DESCRIPTOR_GROUP_VLD, le32_to_cpu(rxd[1])) |
| + & BMAC_GROUP_VLD_4 ? |
| + GET_FIELD(WF_RX_DESCRIPTOR_PEER_MLD_ADDRESS_15_0_, |
| + le32_to_cpu(rxd[8])) : 0); |
| + |
| + /* dw1 */ |
| + printk("PEER_MLD_ADDRESS_47_16 = 0x%x\n", |
| + GET_FIELD(WF_RX_DESCRIPTOR_GROUP_VLD, le32_to_cpu(rxd[1])) |
| + & BMAC_GROUP_VLD_4 ? |
| + GET_FIELD(WF_RX_DESCRIPTOR_PEER_MLD_ADDRESS_47_16_, |
| + le32_to_cpu(rxd[9])) : 0); |
| + |
| + /* dw2 */ |
| + printk("FRAGMENT_NUMBER = %d\n", |
| + GET_FIELD(WF_RX_DESCRIPTOR_GROUP_VLD, le32_to_cpu(rxd[1])) |
| + & BMAC_GROUP_VLD_4 ? |
| + GET_FIELD(WF_RX_DESCRIPTOR_FRAGMENT_NUMBER, |
| + le32_to_cpu(rxd[10])) : 0); |
| + printk("SEQUENCE_NUMBER = %d\n", |
| + GET_FIELD(WF_RX_DESCRIPTOR_GROUP_VLD, le32_to_cpu(rxd[1])) |
| + & BMAC_GROUP_VLD_4 ? |
| + GET_FIELD(WF_RX_DESCRIPTOR_SEQUENCE_NUMBER, |
| + le32_to_cpu(rxd[10])) : 0); |
| + printk("QOS_CONTROL_FIELD = 0x%x\n", |
| + GET_FIELD(WF_RX_DESCRIPTOR_GROUP_VLD, le32_to_cpu(rxd[1])) |
| + & BMAC_GROUP_VLD_4 ? |
| + GET_FIELD(WF_RX_DESCRIPTOR_QOS_CONTROL_FIELD, |
| + le32_to_cpu(rxd[10])) : 0); |
| + |
| + /* dw3 */ |
| + printk("HT_CONTROL_FIELD = 0x%x\n", |
| + GET_FIELD(WF_RX_DESCRIPTOR_GROUP_VLD, le32_to_cpu(rxd[1])) |
| + & BMAC_GROUP_VLD_4 ? |
| + GET_FIELD(WF_RX_DESCRIPTOR_HT_CONTROL_FIELD, |
| + le32_to_cpu(rxd[11])) : 0); |
| +} |
| + |
| +static int besra_token_read(struct seq_file *s, void *data) |
| +{ |
| + struct besra_dev *dev = dev_get_drvdata(s->private); |
| + int id, count = 0; |
| + struct mt76_txwi_cache *txwi; |
| + |
| + seq_printf(s, "Cut through token:\n"); |
| + spin_lock_bh(&dev->mt76.token_lock); |
| + idr_for_each_entry(&dev->mt76.token, txwi, id) { |
| + seq_printf(s, "%4d ", id); |
| + count++; |
| + if (count % 8 == 0) |
| + seq_printf(s, "\n"); |
| + } |
| + spin_unlock_bh(&dev->mt76.token_lock); |
| + seq_printf(s, "\n"); |
| + |
| + return 0; |
| +} |
| + |
| +static int besra_token_txd_read(struct seq_file *s, void *data) |
| +{ |
| + struct besra_dev *dev = dev_get_drvdata(s->private); |
| + struct mt76_txwi_cache *t; |
| + u8* txwi; |
| + |
| + printk("\n"); |
| + spin_lock_bh(&dev->mt76.token_lock); |
| + |
| + t = idr_find(&dev->mt76.token, dev->dbg.token_idx); |
| + |
| + spin_unlock_bh(&dev->mt76.token_lock); |
| + if (t != NULL) { |
| + struct mt76_dev *mdev = &dev->mt76; |
| + txwi = ((u8*)(t)) - (mdev->drv->txwi_size); |
| + /* dump one txd info */ |
| + dev->dbg.txd_read_cnt = 1; |
| + besra_dump_bmac_txd_info(dev, (__le32 *)txwi, false); |
| + printk("\n"); |
| + printk("[SKB]\n"); |
| + print_hex_dump(KERN_ERR , "", DUMP_PREFIX_OFFSET, 16, 1, (u8 *)t->skb->data, t->skb->len, false); |
| + printk("\n"); |
| + } |
| + return 0; |
| +} |
| + |
| +/* AMSDU INFO */ |
| +static int besra_amsdu_read(struct seq_file *s, void *data) |
| +{ |
| + struct besra_dev *dev = dev_get_drvdata(s->private); |
| + u32 ple_stat[8] = {0}, total_amsdu = 0; |
| + u8 i; |
| + |
| + for (i = 0; i < 8; i++) |
| + ple_stat[i] = mt76_rr(dev, WF_PLE_TOP_AMSDU_PACK_1_MSDU_CNT_ADDR + i * 0x04); |
| + |
| + seq_printf(s, "TXD counter status of MSDU:\n"); |
| + |
| + for (i = 0; i < 8; i++) |
| + total_amsdu += ple_stat[i]; |
| + |
| + for (i = 0; i < 8; i++) { |
| + seq_printf(s, "AMSDU pack count of %d MSDU in TXD: 0x%x ", i+1, ple_stat[i]); |
| + if (total_amsdu != 0) |
| + seq_printf(s, "(%d%%)\n", ple_stat[i] * 100 / total_amsdu); |
| + else |
| + seq_printf(s, "\n"); |
| + } |
| + |
| + return 0; |
| +} |
| + |
| +/* AGG INFO */ |
| +static int |
| +besra_agginfo_read_per_band(struct seq_file *s, int band_idx) |
| +{ |
| + struct besra_dev *dev = dev_get_drvdata(s->private); |
| + u64 total_burst, total_ampdu, ampdu_cnt[16]; |
| + u32 value, idx, row_idx, col_idx, start_range, agg_rang_sel[16], burst_cnt[16], band_offset = 0; |
| + u8 readFW = 0, partial_str[16] = {}, full_str[64] = {}; |
| + |
| + switch (band_idx) { |
| + case 0: |
| + band_offset = 0; |
| + break; |
| + case 1: |
| + band_offset = BN1_WF_AGG_TOP_BASE - BN0_WF_AGG_TOP_BASE; |
| + break; |
| + case 2: |
| + band_offset = IP1_BN0_WF_AGG_TOP_BASE - BN0_WF_AGG_TOP_BASE; |
| + break; |
| + default: |
| + return 0; |
| + } |
| + |
| + seq_printf(s, "Band %d AGG Status\n", band_idx); |
| + seq_printf(s, "===============================\n"); |
| + value = mt76_rr(dev, BN0_WF_AGG_TOP_AALCR0_ADDR + band_offset); |
| + seq_printf(s, "AC00 Agg limit = %d\t", (value & BN0_WF_AGG_TOP_AALCR0_AC00_AGG_LIMIT_MASK) >> BN0_WF_AGG_TOP_AALCR0_AC00_AGG_LIMIT_SHFT); |
| + seq_printf(s, "AC01 Agg limit = %d\t", (value & BN0_WF_AGG_TOP_AALCR0_AC01_AGG_LIMIT_MASK) >> BN0_WF_AGG_TOP_AALCR0_AC01_AGG_LIMIT_SHFT); |
| + value = mt76_rr(dev, BN0_WF_AGG_TOP_AALCR1_ADDR + band_offset); |
| + seq_printf(s, "AC02 Agg limit = %d\t", (value & BN0_WF_AGG_TOP_AALCR1_AC02_AGG_LIMIT_MASK) >> BN0_WF_AGG_TOP_AALCR1_AC02_AGG_LIMIT_SHFT); |
| + seq_printf(s, "AC03 Agg limit = %d\t", (value & BN0_WF_AGG_TOP_AALCR1_AC03_AGG_LIMIT_MASK) >> BN0_WF_AGG_TOP_AALCR1_AC03_AGG_LIMIT_SHFT); |
| + value = mt76_rr(dev, BN0_WF_AGG_TOP_AALCR2_ADDR + band_offset); |
| + seq_printf(s, "AC10 Agg limit = %d\t", (value & BN0_WF_AGG_TOP_AALCR2_AC10_AGG_LIMIT_MASK) >> BN0_WF_AGG_TOP_AALCR2_AC10_AGG_LIMIT_SHFT); |
| + seq_printf(s, "AC11 Agg limit = %d\t", (value & BN0_WF_AGG_TOP_AALCR2_AC11_AGG_LIMIT_MASK) >> BN0_WF_AGG_TOP_AALCR2_AC11_AGG_LIMIT_SHFT); |
| + value = mt76_rr(dev, BN0_WF_AGG_TOP_AALCR3_ADDR + band_offset); |
| + seq_printf(s, "AC12 Agg limit = %d\t", (value & BN0_WF_AGG_TOP_AALCR3_AC12_AGG_LIMIT_MASK) >> BN0_WF_AGG_TOP_AALCR3_AC12_AGG_LIMIT_SHFT); |
| + seq_printf(s, "AC13 Agg limit = %d\t", (value & BN0_WF_AGG_TOP_AALCR3_AC13_AGG_LIMIT_MASK) >> BN0_WF_AGG_TOP_AALCR3_AC13_AGG_LIMIT_SHFT); |
| + value = mt76_rr(dev, BN0_WF_AGG_TOP_AALCR4_ADDR + band_offset); |
| + seq_printf(s, "AC20 Agg limit = %d\t", (value & BN0_WF_AGG_TOP_AALCR4_AC20_AGG_LIMIT_MASK) >> BN0_WF_AGG_TOP_AALCR4_AC20_AGG_LIMIT_SHFT); |
| + seq_printf(s, "AC21 Agg limit = %d\t", (value & BN0_WF_AGG_TOP_AALCR4_AC21_AGG_LIMIT_MASK) >> BN0_WF_AGG_TOP_AALCR4_AC21_AGG_LIMIT_SHFT); |
| + value = mt76_rr(dev, BN0_WF_AGG_TOP_AALCR5_ADDR + band_offset); |
| + seq_printf(s, "AC22 Agg limit = %d\t", (value & BN0_WF_AGG_TOP_AALCR5_AC22_AGG_LIMIT_MASK) >> BN0_WF_AGG_TOP_AALCR5_AC22_AGG_LIMIT_SHFT); |
| + seq_printf(s, "AC23 Agg limit = %d\t", (value & BN0_WF_AGG_TOP_AALCR5_AC23_AGG_LIMIT_MASK) >> BN0_WF_AGG_TOP_AALCR5_AC23_AGG_LIMIT_SHFT); |
| + value = mt76_rr(dev, BN0_WF_AGG_TOP_AALCR6_ADDR + band_offset); |
| + seq_printf(s, "AC30 Agg limit = %d\t", (value & BN0_WF_AGG_TOP_AALCR6_AC30_AGG_LIMIT_MASK) >> BN0_WF_AGG_TOP_AALCR6_AC30_AGG_LIMIT_SHFT); |
| + seq_printf(s, "AC31 Agg limit = %d\t", (value & BN0_WF_AGG_TOP_AALCR6_AC31_AGG_LIMIT_MASK) >> BN0_WF_AGG_TOP_AALCR6_AC31_AGG_LIMIT_SHFT); |
| + value = mt76_rr(dev, BN0_WF_AGG_TOP_AALCR7_ADDR + band_offset); |
| + seq_printf(s, "AC32 Agg limit = %d\t", (value & BN0_WF_AGG_TOP_AALCR7_AC32_AGG_LIMIT_MASK) >> BN0_WF_AGG_TOP_AALCR7_AC32_AGG_LIMIT_SHFT); |
| + seq_printf(s, "AC33 Agg limit = %d\t", (value & BN0_WF_AGG_TOP_AALCR7_AC33_AGG_LIMIT_MASK) >> BN0_WF_AGG_TOP_AALCR7_AC33_AGG_LIMIT_SHFT); |
| + |
| + switch (band_idx) { |
| + case 0: |
| + band_offset = 0; |
| + break; |
| + case 1: |
| + band_offset = BN1_WF_MIB_TOP_BASE - BN0_WF_MIB_TOP_BASE; |
| + break; |
| + case 2: |
| + band_offset = IP1_BN0_WF_MIB_TOP_BASE - BN0_WF_MIB_TOP_BASE; |
| + break; |
| + default: |
| + return 0; |
| + } |
| + |
| + seq_printf(s, "===AMPDU Related Counters===\n"); |
| + |
| + if (readFW) { |
| + /* BELLWETHER TODO: Wait MIB counter API implement complete */ |
| + } else { |
| + value = mt76_rr(dev, BN0_WF_MIB_TOP_TRARC0_ADDR + band_offset); |
| + agg_rang_sel[0] = (value & BN0_WF_MIB_TOP_TRARC0_AGG_RANG_SEL_0_MASK) >> BN0_WF_MIB_TOP_TRARC0_AGG_RANG_SEL_0_SHFT; |
| + agg_rang_sel[1] = (value & BN0_WF_MIB_TOP_TRARC0_AGG_RANG_SEL_1_MASK) >> BN0_WF_MIB_TOP_TRARC0_AGG_RANG_SEL_1_SHFT; |
| + value = mt76_rr(dev, BN0_WF_MIB_TOP_TRARC1_ADDR + band_offset); |
| + agg_rang_sel[2] = (value & BN0_WF_MIB_TOP_TRARC1_AGG_RANG_SEL_2_MASK) >> BN0_WF_MIB_TOP_TRARC1_AGG_RANG_SEL_2_SHFT; |
| + agg_rang_sel[3] = (value & BN0_WF_MIB_TOP_TRARC1_AGG_RANG_SEL_3_MASK) >> BN0_WF_MIB_TOP_TRARC1_AGG_RANG_SEL_3_SHFT; |
| + value = mt76_rr(dev, BN0_WF_MIB_TOP_TRARC2_ADDR + band_offset); |
| + agg_rang_sel[4] = (value & BN0_WF_MIB_TOP_TRARC2_AGG_RANG_SEL_4_MASK) >> BN0_WF_MIB_TOP_TRARC2_AGG_RANG_SEL_4_SHFT; |
| + agg_rang_sel[5] = (value & BN0_WF_MIB_TOP_TRARC2_AGG_RANG_SEL_5_MASK) >> BN0_WF_MIB_TOP_TRARC2_AGG_RANG_SEL_5_SHFT; |
| + value = mt76_rr(dev, BN0_WF_MIB_TOP_TRARC3_ADDR + band_offset); |
| + agg_rang_sel[6] = (value & BN0_WF_MIB_TOP_TRARC3_AGG_RANG_SEL_6_MASK) >> BN0_WF_MIB_TOP_TRARC3_AGG_RANG_SEL_6_SHFT; |
| + agg_rang_sel[7] = (value & BN0_WF_MIB_TOP_TRARC3_AGG_RANG_SEL_7_MASK) >> BN0_WF_MIB_TOP_TRARC3_AGG_RANG_SEL_7_SHFT; |
| + value = mt76_rr(dev, BN0_WF_MIB_TOP_TRARC4_ADDR + band_offset); |
| + agg_rang_sel[8] = (value & BN0_WF_MIB_TOP_TRARC4_AGG_RANG_SEL_8_MASK) >> BN0_WF_MIB_TOP_TRARC4_AGG_RANG_SEL_8_SHFT; |
| + agg_rang_sel[9] = (value & BN0_WF_MIB_TOP_TRARC4_AGG_RANG_SEL_9_MASK) >> BN0_WF_MIB_TOP_TRARC4_AGG_RANG_SEL_9_SHFT; |
| + value = mt76_rr(dev, BN0_WF_MIB_TOP_TRARC5_ADDR + band_offset); |
| + agg_rang_sel[10] = (value & BN0_WF_MIB_TOP_TRARC5_AGG_RANG_SEL_10_MASK) >> BN0_WF_MIB_TOP_TRARC5_AGG_RANG_SEL_10_SHFT; |
| + agg_rang_sel[11] = (value & BN0_WF_MIB_TOP_TRARC5_AGG_RANG_SEL_11_MASK) >> BN0_WF_MIB_TOP_TRARC5_AGG_RANG_SEL_11_SHFT; |
| + value = mt76_rr(dev, BN0_WF_MIB_TOP_TRARC6_ADDR + band_offset); |
| + agg_rang_sel[12] = (value & BN0_WF_MIB_TOP_TRARC6_AGG_RANG_SEL_12_MASK) >> BN0_WF_MIB_TOP_TRARC6_AGG_RANG_SEL_12_SHFT; |
| + agg_rang_sel[13] = (value & BN0_WF_MIB_TOP_TRARC6_AGG_RANG_SEL_13_MASK) >> BN0_WF_MIB_TOP_TRARC6_AGG_RANG_SEL_13_SHFT; |
| + value = mt76_rr(dev, BN0_WF_MIB_TOP_TRARC7_ADDR + band_offset); |
| + agg_rang_sel[14] = (value & BN0_WF_MIB_TOP_TRARC7_AGG_RANG_SEL_14_MASK) >> BN0_WF_MIB_TOP_TRARC7_AGG_RANG_SEL_14_SHFT; |
| + |
| + burst_cnt[0] = mt76_rr(dev, BN0_WF_MIB_TOP_TRDR0_ADDR + band_offset); |
| + burst_cnt[1] = mt76_rr(dev, BN0_WF_MIB_TOP_TRDR1_ADDR + band_offset); |
| + burst_cnt[2] = mt76_rr(dev, BN0_WF_MIB_TOP_TRDR2_ADDR + band_offset); |
| + burst_cnt[3] = mt76_rr(dev, BN0_WF_MIB_TOP_TRDR3_ADDR + band_offset); |
| + burst_cnt[4] = mt76_rr(dev, BN0_WF_MIB_TOP_TRDR4_ADDR + band_offset); |
| + burst_cnt[5] = mt76_rr(dev, BN0_WF_MIB_TOP_TRDR5_ADDR + band_offset); |
| + burst_cnt[6] = mt76_rr(dev, BN0_WF_MIB_TOP_TRDR6_ADDR + band_offset); |
| + burst_cnt[7] = mt76_rr(dev, BN0_WF_MIB_TOP_TRDR7_ADDR + band_offset); |
| + burst_cnt[8] = mt76_rr(dev, BN0_WF_MIB_TOP_TRDR8_ADDR + band_offset); |
| + burst_cnt[9] = mt76_rr(dev, BN0_WF_MIB_TOP_TRDR9_ADDR + band_offset); |
| + burst_cnt[10] = mt76_rr(dev, BN0_WF_MIB_TOP_TRDR10_ADDR + band_offset); |
| + burst_cnt[11] = mt76_rr(dev, BN0_WF_MIB_TOP_TRDR11_ADDR + band_offset); |
| + burst_cnt[12] = mt76_rr(dev, BN0_WF_MIB_TOP_TRDR12_ADDR + band_offset); |
| + burst_cnt[13] = mt76_rr(dev, BN0_WF_MIB_TOP_TRDR13_ADDR + band_offset); |
| + burst_cnt[14] = mt76_rr(dev, BN0_WF_MIB_TOP_TRDR14_ADDR + band_offset); |
| + burst_cnt[15] = mt76_rr(dev, BN0_WF_MIB_TOP_TRDR15_ADDR + band_offset); |
| + } |
| + |
| + start_range = 1; |
| + total_burst = 0; |
| + total_ampdu = 0; |
| + agg_rang_sel[15] = 1023; |
| + |
| + /* Need to add 1 after read from AGG_RANG_SEL CR */ |
| + for (idx = 0; idx < 16; idx++) { |
| + agg_rang_sel[idx]++; |
| + total_burst += burst_cnt[idx]; |
| + |
| + if (start_range == agg_rang_sel[idx]) |
| + ampdu_cnt[idx] = (u64) start_range * burst_cnt[idx]; |
| + else |
| + ampdu_cnt[idx] = (u64) ((start_range + agg_rang_sel[idx]) >> 1) * burst_cnt[idx]; |
| + |
| + start_range = agg_rang_sel[idx] + 1; |
| + total_ampdu += ampdu_cnt[idx]; |
| + } |
| + |
| + start_range = 1; |
| + sprintf(full_str, "%13s ", "Tx Agg Range:"); |
| + |
| + for (row_idx = 0; row_idx < 4; row_idx++) { |
| + for (col_idx = 0; col_idx < 4; col_idx++, idx++) { |
| + idx = 4 * row_idx + col_idx; |
| + |
| + if (start_range == agg_rang_sel[idx]) |
| + sprintf(partial_str, "%d", agg_rang_sel[idx]); |
| + else |
| + sprintf(partial_str, "%d~%d", start_range, agg_rang_sel[idx]); |
| + |
| + start_range = agg_rang_sel[idx] + 1; |
| + sprintf(full_str + strlen(full_str), "%-11s ", partial_str); |
| + } |
| + |
| + idx = 4 * row_idx; |
| + |
| + seq_printf(s, "%s\n", full_str); |
| + seq_printf(s, "%13s 0x%-9x 0x%-9x 0x%-9x 0x%-9x\n", |
| + row_idx ? "" : "Burst count:", |
| + burst_cnt[idx], burst_cnt[idx + 1], |
| + burst_cnt[idx + 2], burst_cnt[idx + 3]); |
| + |
| + if (total_burst != 0) { |
| + if (row_idx == 0) |
| + sprintf(full_str, "%13s ", |
| + "Burst ratio:"); |
| + else |
| + sprintf(full_str, "%13s ", ""); |
| + |
| + for (col_idx = 0; col_idx < 4; col_idx++) { |
| + u64 count = (u64) burst_cnt[idx + col_idx] * 100; |
| + |
| + sprintf(partial_str, "(%llu%%)", |
| + div64_u64(count, total_burst)); |
| + sprintf(full_str + strlen(full_str), |
| + "%-11s ", partial_str); |
| + } |
| + |
| + seq_printf(s, "%s\n", full_str); |
| + |
| + if (row_idx == 0) |
| + sprintf(full_str, "%13s ", |
| + "MDPU ratio:"); |
| + else |
| + sprintf(full_str, "%13s ", ""); |
| + |
| + for (col_idx = 0; col_idx < 4; col_idx++) { |
| + u64 count = ampdu_cnt[idx + col_idx] * 100; |
| + |
| + sprintf(partial_str, "(%llu%%)", |
| + div64_u64(count, total_ampdu)); |
| + sprintf(full_str + strlen(full_str), |
| + "%-11s ", partial_str); |
| + } |
| + |
| + seq_printf(s, "%s\n", full_str); |
| + } |
| + |
| + sprintf(full_str, "%13s ", ""); |
| + } |
| + |
| + return 0; |
| +} |
| + |
| +static int besra_agginfo_read_band0(struct seq_file *s, void *data) |
| +{ |
| + besra_agginfo_read_per_band(s, MT_BAND0); |
| + return 0; |
| +} |
| + |
| +static int besra_agginfo_read_band1(struct seq_file *s, void *data) |
| +{ |
| + besra_agginfo_read_per_band(s, MT_BAND1); |
| + return 0; |
| +} |
| + |
| +static int besra_agginfo_read_band2(struct seq_file *s, void *data) |
| +{ |
| + besra_agginfo_read_per_band(s, MT_BAND2); |
| + return 0; |
| +} |
| + |
| +/* PSE INFO */ |
| +static struct bmac_queue_info_t pse_queue_empty_info[] = { |
| + {"CPU Q0", ENUM_UMAC_CPU_PORT_1, ENUM_UMAC_CTX_Q_0}, |
| + {"CPU Q1", ENUM_UMAC_CPU_PORT_1, ENUM_UMAC_CTX_Q_1}, |
| + {"CPU Q2", ENUM_UMAC_CPU_PORT_1, ENUM_UMAC_CTX_Q_2}, |
| + {"CPU Q3", ENUM_UMAC_CPU_PORT_1, ENUM_UMAC_CTX_Q_3}, |
| + {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, /* 4~7 not defined */ |
| + {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, |
| + {NULL, 0, 0}, {NULL, 0, 0}, /* 14~15 not defined */ |
| + {"LMAC Q", ENUM_UMAC_LMAC_PORT_2, 0}, |
| + {"MDP TX Q0", ENUM_UMAC_LMAC_PORT_2, 1}, |
| + {"MDP RX Q", ENUM_UMAC_LMAC_PORT_2, 2}, |
| + {"SEC TX Q0", ENUM_UMAC_LMAC_PORT_2, 3}, |
| + {"SEC RX Q", ENUM_UMAC_LMAC_PORT_2, 4}, |
| + {"SFD_PARK Q", ENUM_UMAC_LMAC_PORT_2, 5}, |
| + {"MDP_TXIOC Q0", ENUM_UMAC_LMAC_PORT_2, 6}, |
| + {"MDP_RXIOC Q0", ENUM_UMAC_LMAC_PORT_2, 7}, |
| + {"MDP TX Q1", ENUM_UMAC_LMAC_PORT_2, 0x11}, |
| + {"SEC TX Q1", ENUM_UMAC_LMAC_PORT_2, 0x13}, |
| + {"MDP_TXIOC Q1", ENUM_UMAC_LMAC_PORT_2, 0x16}, |
| + {"MDP_RXIOC Q1", ENUM_UMAC_LMAC_PORT_2, 0x17}, |
| + {"CPU Q3", ENUM_UMAC_CPU_PORT_1, 4}, |
| + {NULL, 0, 0}, {NULL, 0, 0}, |
| + {"RLS Q", ENUM_PLE_CTRL_PSE_PORT_3, ENUM_UMAC_PLE_CTRL_P3_Q_0X1F} |
| +}; |
| + |
| +static struct bmac_queue_info_t pse_queue_empty2_info[] = { |
| + {"MDP_TDPIOC Q0", ENUM_UMAC_LMAC_PORT_2, 0x8}, |
| + {"MDP_RDPIOC Q0", ENUM_UMAC_LMAC_PORT_2, 0x9}, |
| + {"MDP_TDPIOC Q1", ENUM_UMAC_LMAC_PORT_2, 0x18}, |
| + {"MDP_RDPIOC Q1", ENUM_UMAC_LMAC_PORT_2, 0x19}, |
| + {"MDP_TDPIOC Q2", ENUM_UMAC_LMAC_PORT_2, 0x28}, |
| + {"MDP_RDPIOC Q2", ENUM_UMAC_LMAC_PORT_2, 0x29}, |
| + {NULL, 0, 0}, |
| + {"MDP_RDPIOC Q3", ENUM_UMAC_LMAC_PORT_2, 0x39}, |
| + {"MDP TX Q2", ENUM_UMAC_LMAC_PORT_2, 0x21}, |
| + {"SEC TX Q2", ENUM_UMAC_LMAC_PORT_2, 0x23}, |
| + {"MDP_TXIOC Q2", ENUM_UMAC_LMAC_PORT_2, 0x26}, |
| + {"MDP_RXIOC Q2", ENUM_UMAC_LMAC_PORT_2, 0x27}, |
| + {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, |
| + {"MDP_RXIOC Q3", ENUM_UMAC_LMAC_PORT_2, 0x37}, |
| + {"HIF Q0", ENUM_UMAC_HIF_PORT_0, 0}, |
| + {"HIF Q1", ENUM_UMAC_HIF_PORT_0, 1}, |
| + {"HIF Q2", ENUM_UMAC_HIF_PORT_0, 2}, |
| + {"HIF Q3", ENUM_UMAC_HIF_PORT_0, 3}, |
| + {"HIF Q4", ENUM_UMAC_HIF_PORT_0, 4}, |
| + {"HIF Q5", ENUM_UMAC_HIF_PORT_0, 5}, |
| + {"HIF Q6", ENUM_UMAC_HIF_PORT_0, 6}, |
| + {"HIF Q7", ENUM_UMAC_HIF_PORT_0, 7}, |
| + {"HIF Q8", ENUM_UMAC_HIF_PORT_0, 8}, |
| + {"HIF Q9", ENUM_UMAC_HIF_PORT_0, 9}, |
| + {"HIF Q10", ENUM_UMAC_HIF_PORT_0, 10}, |
| + {"HIF Q11", ENUM_UMAC_HIF_PORT_0, 11}, |
| + {"HIF Q12", ENUM_UMAC_HIF_PORT_0, 12}, |
| + {"HIF Q13", ENUM_UMAC_HIF_PORT_0, 13}, |
| + {NULL, 0, 0}, {NULL, 0, 0} |
| +}; |
| + |
| +static int |
| +besra_pseinfo_read(struct seq_file *s, void *data) |
| +{ |
| + struct besra_dev *dev = dev_get_drvdata(s->private); |
| + u32 pse_buf_ctrl, pg_sz, pg_num; |
| + u32 pse_stat[2], pg_flow_ctrl[28] = {0}; |
| + u32 fpg_cnt, ffa_cnt, fpg_head, fpg_tail; |
| + u32 max_q, min_q, rsv_pg, used_pg; |
| + int i; |
| + |
| + pse_buf_ctrl = mt76_rr(dev, WF_PSE_TOP_PBUF_CTRL_ADDR); |
| + pse_stat[0] = mt76_rr(dev, WF_PSE_TOP_QUEUE_EMPTY_ADDR); |
| + pse_stat[1] = mt76_rr(dev, WF_PSE_TOP_QUEUE_EMPTY_1_ADDR); |
| + pg_flow_ctrl[0] = mt76_rr(dev, WF_PSE_TOP_FREEPG_CNT_ADDR); |
| + pg_flow_ctrl[1] = mt76_rr(dev, WF_PSE_TOP_FREEPG_HEAD_TAIL_ADDR); |
| + pg_flow_ctrl[2] = mt76_rr(dev, WF_PSE_TOP_PG_HIF0_GROUP_ADDR); |
| + pg_flow_ctrl[3] = mt76_rr(dev, WF_PSE_TOP_HIF0_PG_INFO_ADDR); |
| + pg_flow_ctrl[4] = mt76_rr(dev, WF_PSE_TOP_PG_HIF1_GROUP_ADDR); |
| + pg_flow_ctrl[5] = mt76_rr(dev, WF_PSE_TOP_HIF1_PG_INFO_ADDR); |
| + pg_flow_ctrl[6] = mt76_rr(dev, WF_PSE_TOP_PG_CPU_GROUP_ADDR); |
| + pg_flow_ctrl[7] = mt76_rr(dev, WF_PSE_TOP_CPU_PG_INFO_ADDR); |
| + pg_flow_ctrl[8] = mt76_rr(dev, WF_PSE_TOP_PG_LMAC0_GROUP_ADDR); |
| + pg_flow_ctrl[9] = mt76_rr(dev, WF_PSE_TOP_LMAC0_PG_INFO_ADDR); |
| + pg_flow_ctrl[10] = mt76_rr(dev, WF_PSE_TOP_PG_LMAC1_GROUP_ADDR); |
| + pg_flow_ctrl[11] = mt76_rr(dev, WF_PSE_TOP_LMAC1_PG_INFO_ADDR); |
| + pg_flow_ctrl[12] = mt76_rr(dev, WF_PSE_TOP_PG_LMAC2_GROUP_ADDR); |
| + pg_flow_ctrl[13] = mt76_rr(dev, WF_PSE_TOP_LMAC2_PG_INFO_ADDR); |
| + pg_flow_ctrl[14] = mt76_rr(dev, WF_PSE_TOP_PG_PLE_GROUP_ADDR); |
| + pg_flow_ctrl[15] = mt76_rr(dev, WF_PSE_TOP_PLE_PG_INFO_ADDR); |
| + pg_flow_ctrl[16] = mt76_rr(dev, WF_PSE_TOP_PG_LMAC3_GROUP_ADDR); |
| + pg_flow_ctrl[17] = mt76_rr(dev, WF_PSE_TOP_LMAC3_PG_INFO_ADDR); |
| + pg_flow_ctrl[18] = mt76_rr(dev, WF_PSE_TOP_PG_MDP_GROUP_ADDR); |
| + pg_flow_ctrl[19] = mt76_rr(dev, WF_PSE_TOP_MDP_PG_INFO_ADDR); |
| + pg_flow_ctrl[20] = mt76_rr(dev, WF_PSE_TOP_PG_PLE1_GROUP_ADDR); |
| + pg_flow_ctrl[21] = mt76_rr(dev, WF_PSE_TOP_PLE1_PG_INFO_ADDR); |
| + pg_flow_ctrl[22] = mt76_rr(dev, WF_PSE_TOP_PG_MDP2_GROUP_ADDR); |
| + pg_flow_ctrl[23] = mt76_rr(dev, WF_PSE_TOP_MDP2_PG_INFO_ADDR); |
| + pg_flow_ctrl[24] = mt76_rr(dev, WF_PSE_TOP_PG_MDP3_GROUP_ADDR); |
| + pg_flow_ctrl[25] = mt76_rr(dev, WF_PSE_TOP_MDP3_PG_INFO_ADDR); |
| + pg_flow_ctrl[26] = mt76_rr(dev, WF_PSE_TOP_PG_HIF2_GROUP_ADDR); |
| + pg_flow_ctrl[27] = mt76_rr(dev, WF_PSE_TOP_HIF2_PG_INFO_ADDR); |
| + /* Configuration Info */ |
| + printk("PSE Configuration Info:\n"); |
| + printk("\tPacket Buffer Control: 0x%08x\n", pse_buf_ctrl); |
| + pg_sz = (pse_buf_ctrl & WF_PSE_TOP_PBUF_CTRL_PAGE_SIZE_CFG_MASK) >> WF_PSE_TOP_PBUF_CTRL_PAGE_SIZE_CFG_SHFT; |
| + printk("\t\tPage Size=%d(%d bytes per page)\n", pg_sz, (pg_sz == 1 ? 256 : 128)); |
| + printk("\t\tPage Offset=%d(in unit of 64KB)\n", |
| + (pse_buf_ctrl & WF_PSE_TOP_PBUF_CTRL_PBUF_OFFSET_MASK) >> WF_PSE_TOP_PBUF_CTRL_PBUF_OFFSET_SHFT); |
| + pg_num = (pse_buf_ctrl & WF_PSE_TOP_PBUF_CTRL_TOTAL_PAGE_NUM_MASK) >> WF_PSE_TOP_PBUF_CTRL_TOTAL_PAGE_NUM_SHFT; |
| + printk("\t\tTotal page numbers=%d pages\n", pg_num); |
| + /* Page Flow Control */ |
| + printk("PSE Page Flow Control:\n"); |
| + printk("\tFree page counter: 0x%08x\n", pg_flow_ctrl[0]); |
| + fpg_cnt = (pg_flow_ctrl[0] & WF_PSE_TOP_FREEPG_CNT_FREEPG_CNT_MASK) >> WF_PSE_TOP_FREEPG_CNT_FREEPG_CNT_SHFT; |
| + printk("\t\tThe toal page number of free=0x%03x\n", fpg_cnt); |
| + ffa_cnt = (pg_flow_ctrl[0] & WF_PSE_TOP_FREEPG_CNT_FFA_CNT_MASK) >> WF_PSE_TOP_FREEPG_CNT_FFA_CNT_SHFT; |
| + printk("\t\tThe free page numbers of free for all=0x%03x\n", ffa_cnt); |
| + printk("\tFree page head and tail: 0x%08x\n", pg_flow_ctrl[1]); |
| + fpg_head = (pg_flow_ctrl[1] & WF_PSE_TOP_FREEPG_HEAD_TAIL_FREEPG_HEAD_MASK) >> WF_PSE_TOP_FREEPG_HEAD_TAIL_FREEPG_HEAD_SHFT; |
| + fpg_tail = (pg_flow_ctrl[1] & WF_PSE_TOP_FREEPG_HEAD_TAIL_FREEPG_TAIL_MASK) >> WF_PSE_TOP_FREEPG_HEAD_TAIL_FREEPG_TAIL_SHFT; |
| + printk("\t\tThe tail/head page of free page list=0x%03x/0x%03x\n", fpg_tail, fpg_head); |
| + printk("\tReserved page counter of HIF0 group: 0x%08x\n", pg_flow_ctrl[2]); |
| + printk("\tHIF0 group page status: 0x%08x\n", pg_flow_ctrl[3]); |
| + min_q = (pg_flow_ctrl[2] & WF_PSE_TOP_PG_HIF0_GROUP_HIF0_MIN_QUOTA_MASK) >> WF_PSE_TOP_PG_HIF0_GROUP_HIF0_MIN_QUOTA_SHFT; |
| + max_q = (pg_flow_ctrl[2] & WF_PSE_TOP_PG_HIF0_GROUP_HIF0_MAX_QUOTA_MASK) >> WF_PSE_TOP_PG_HIF0_GROUP_HIF0_MAX_QUOTA_SHFT; |
| + printk("\t\tThe max/min quota pages of HIF0 group=0x%03x/0x%03x\n", max_q, min_q); |
| + rsv_pg = (pg_flow_ctrl[3] & WF_PSE_TOP_HIF0_PG_INFO_HIF0_RSV_CNT_MASK) >> WF_PSE_TOP_HIF0_PG_INFO_HIF0_RSV_CNT_SHFT; |
| + used_pg = (pg_flow_ctrl[3] & WF_PSE_TOP_HIF0_PG_INFO_HIF0_SRC_CNT_MASK) >> WF_PSE_TOP_HIF0_PG_INFO_HIF0_SRC_CNT_SHFT; |
| + printk("\t\tThe used/reserved pages of HIF0 group=0x%03x/0x%03x\n", used_pg, rsv_pg); |
| + printk("\tReserved page counter of HIF1 group: 0x%08x\n", pg_flow_ctrl[4]); |
| + printk("\tHIF1 group page status: 0x%08x\n", pg_flow_ctrl[5]); |
| + min_q = (pg_flow_ctrl[4] & WF_PSE_TOP_PG_HIF1_GROUP_HIF1_MIN_QUOTA_MASK) >> WF_PSE_TOP_PG_HIF1_GROUP_HIF1_MIN_QUOTA_SHFT; |
| + max_q = (pg_flow_ctrl[4] & WF_PSE_TOP_PG_HIF1_GROUP_HIF1_MAX_QUOTA_MASK) >> WF_PSE_TOP_PG_HIF1_GROUP_HIF1_MAX_QUOTA_SHFT; |
| + printk("\t\tThe max/min quota pages of HIF1 group=0x%03x/0x%03x\n", max_q, min_q); |
| + rsv_pg = (pg_flow_ctrl[5] & WF_PSE_TOP_HIF1_PG_INFO_HIF1_RSV_CNT_MASK) >> WF_PSE_TOP_HIF1_PG_INFO_HIF1_RSV_CNT_SHFT; |
| + used_pg = (pg_flow_ctrl[5] & WF_PSE_TOP_HIF1_PG_INFO_HIF1_SRC_CNT_MASK) >> WF_PSE_TOP_HIF1_PG_INFO_HIF1_SRC_CNT_SHFT; |
| + printk("\t\tThe used/reserved pages of HIF1 group=0x%03x/0x%03x\n", used_pg, rsv_pg); |
| + printk("\tReserved page counter of HIF2 group: 0x%08x\n", pg_flow_ctrl[26]); |
| + printk("\tHIF2 group page status: 0x%08x\n", pg_flow_ctrl[27]); |
| + min_q = (pg_flow_ctrl[26] & WF_PSE_TOP_PG_HIF2_GROUP_HIF2_MIN_QUOTA_MASK) >> WF_PSE_TOP_PG_HIF2_GROUP_HIF2_MIN_QUOTA_SHFT; |
| + max_q = (pg_flow_ctrl[26] & WF_PSE_TOP_PG_HIF2_GROUP_HIF2_MAX_QUOTA_MASK) >> WF_PSE_TOP_PG_HIF2_GROUP_HIF2_MAX_QUOTA_SHFT; |
| + printk("\t\tThe max/min quota pages of HIF2 group=0x%03x/0x%03x\n", max_q, min_q); |
| + rsv_pg = (pg_flow_ctrl[27] & WF_PSE_TOP_HIF2_PG_INFO_HIF2_RSV_CNT_MASK) >> WF_PSE_TOP_HIF2_PG_INFO_HIF2_RSV_CNT_SHFT; |
| + used_pg = (pg_flow_ctrl[27] & WF_PSE_TOP_HIF2_PG_INFO_HIF2_SRC_CNT_MASK) >> WF_PSE_TOP_HIF2_PG_INFO_HIF2_SRC_CNT_SHFT; |
| + printk("\t\tThe used/reserved pages of HIF2 group=0x%03x/0x%03x\n", used_pg, rsv_pg); |
| + printk("\tReserved page counter of CPU group: 0x%08x\n", pg_flow_ctrl[6]); |
| + printk("\tCPU group page status: 0x%08x\n", pg_flow_ctrl[7]); |
| + min_q = (pg_flow_ctrl[6] & WF_PSE_TOP_PG_CPU_GROUP_CPU_MIN_QUOTA_MASK) >> WF_PSE_TOP_PG_CPU_GROUP_CPU_MIN_QUOTA_SHFT; |
| + max_q = (pg_flow_ctrl[6] & WF_PSE_TOP_PG_CPU_GROUP_CPU_MAX_QUOTA_MASK) >> WF_PSE_TOP_PG_CPU_GROUP_CPU_MAX_QUOTA_SHFT; |
| + printk("\t\tThe max/min quota pages of CPU group=0x%03x/0x%03x\n", max_q, min_q); |
| + rsv_pg = (pg_flow_ctrl[7] & WF_PSE_TOP_CPU_PG_INFO_CPU_RSV_CNT_MASK) >> WF_PSE_TOP_CPU_PG_INFO_CPU_RSV_CNT_SHFT; |
| + used_pg = (pg_flow_ctrl[7] & WF_PSE_TOP_CPU_PG_INFO_CPU_SRC_CNT_MASK) >> WF_PSE_TOP_CPU_PG_INFO_CPU_SRC_CNT_SHFT; |
| + printk("\t\tThe used/reserved pages of CPU group=0x%03x/0x%03x\n", used_pg, rsv_pg); |
| + printk("\tReserved page counter of LMAC0 group: 0x%08x\n", pg_flow_ctrl[8]); |
| + printk("\tLMAC0 group page status: 0x%08x\n", pg_flow_ctrl[9]); |
| + min_q = (pg_flow_ctrl[8] & WF_PSE_TOP_PG_LMAC0_GROUP_LMAC0_MIN_QUOTA_MASK) >> WF_PSE_TOP_PG_LMAC0_GROUP_LMAC0_MIN_QUOTA_SHFT; |
| + max_q = (pg_flow_ctrl[8] & WF_PSE_TOP_PG_LMAC0_GROUP_LMAC0_MAX_QUOTA_MASK) >> WF_PSE_TOP_PG_LMAC0_GROUP_LMAC0_MAX_QUOTA_SHFT; |
| + printk("\t\tThe max/min quota pages of LMAC0 group=0x%03x/0x%03x\n", max_q, min_q); |
| + rsv_pg = (pg_flow_ctrl[9] & WF_PSE_TOP_LMAC0_PG_INFO_LMAC0_RSV_CNT_MASK) >> WF_PSE_TOP_LMAC0_PG_INFO_LMAC0_RSV_CNT_SHFT; |
| + used_pg = (pg_flow_ctrl[9] & WF_PSE_TOP_LMAC0_PG_INFO_LMAC0_SRC_CNT_MASK) >> WF_PSE_TOP_LMAC0_PG_INFO_LMAC0_SRC_CNT_SHFT; |
| + printk("\t\tThe used/reserved pages of LMAC0 group=0x%03x/0x%03x\n", used_pg, rsv_pg); |
| + printk("\tReserved page counter of LMAC1 group: 0x%08x\n", pg_flow_ctrl[10]); |
| + printk("\tLMAC1 group page status: 0x%08x\n", pg_flow_ctrl[11]); |
| + min_q = (pg_flow_ctrl[10] & WF_PSE_TOP_PG_LMAC1_GROUP_LMAC1_MIN_QUOTA_MASK) >> WF_PSE_TOP_PG_LMAC1_GROUP_LMAC1_MIN_QUOTA_SHFT; |
| + max_q = (pg_flow_ctrl[10] & WF_PSE_TOP_PG_LMAC1_GROUP_LMAC1_MAX_QUOTA_MASK) >> WF_PSE_TOP_PG_LMAC1_GROUP_LMAC1_MAX_QUOTA_SHFT; |
| + printk("\t\tThe max/min quota pages of LMAC1 group=0x%03x/0x%03x\n", max_q, min_q); |
| + rsv_pg = (pg_flow_ctrl[11] & WF_PSE_TOP_LMAC1_PG_INFO_LMAC1_RSV_CNT_MASK) >> WF_PSE_TOP_LMAC1_PG_INFO_LMAC1_RSV_CNT_SHFT; |
| + used_pg = (pg_flow_ctrl[11] & WF_PSE_TOP_LMAC1_PG_INFO_LMAC1_SRC_CNT_MASK) >> WF_PSE_TOP_LMAC1_PG_INFO_LMAC1_SRC_CNT_SHFT; |
| + printk("\t\tThe used/reserved pages of LMAC1 group=0x%03x/0x%03x\n", used_pg, rsv_pg); |
| + printk("\tReserved page counter of LMAC2 group: 0x%08x\n", pg_flow_ctrl[11]); |
| + printk("\tLMAC2 group page status: 0x%08x\n", pg_flow_ctrl[12]); |
| + min_q = (pg_flow_ctrl[12] & WF_PSE_TOP_PG_LMAC2_GROUP_LMAC2_MIN_QUOTA_MASK) >> WF_PSE_TOP_PG_LMAC2_GROUP_LMAC2_MIN_QUOTA_SHFT; |
| + max_q = (pg_flow_ctrl[12] & WF_PSE_TOP_PG_LMAC2_GROUP_LMAC2_MAX_QUOTA_MASK) >> WF_PSE_TOP_PG_LMAC2_GROUP_LMAC2_MAX_QUOTA_SHFT; |
| + printk("\t\tThe max/min quota pages of LMAC2 group=0x%03x/0x%03x\n", max_q, min_q); |
| + rsv_pg = (pg_flow_ctrl[13] & WF_PSE_TOP_LMAC2_PG_INFO_LMAC2_RSV_CNT_MASK) >> WF_PSE_TOP_LMAC2_PG_INFO_LMAC2_RSV_CNT_SHFT; |
| + used_pg = (pg_flow_ctrl[13] & WF_PSE_TOP_LMAC2_PG_INFO_LMAC2_SRC_CNT_MASK) >> WF_PSE_TOP_LMAC2_PG_INFO_LMAC2_SRC_CNT_SHFT; |
| + printk("\t\tThe used/reserved pages of LMAC2 group=0x%03x/0x%03x\n", used_pg, rsv_pg); |
| + |
| + printk("\tReserved page counter of LMAC3 group: 0x%08x\n", pg_flow_ctrl[16]); |
| + printk("\tLMAC3 group page status: 0x%08x\n", pg_flow_ctrl[17]); |
| + min_q = (pg_flow_ctrl[16] & WF_PSE_TOP_PG_LMAC3_GROUP_LMAC3_MIN_QUOTA_MASK) >> WF_PSE_TOP_PG_LMAC3_GROUP_LMAC3_MIN_QUOTA_SHFT; |
| + max_q = (pg_flow_ctrl[16] & WF_PSE_TOP_PG_LMAC3_GROUP_LMAC3_MAX_QUOTA_MASK) >> WF_PSE_TOP_PG_LMAC3_GROUP_LMAC3_MAX_QUOTA_SHFT; |
| + printk("\t\tThe max/min quota pages of LMAC3 group=0x%03x/0x%03x\n", max_q, min_q); |
| + rsv_pg = (pg_flow_ctrl[17] & WF_PSE_TOP_LMAC3_PG_INFO_LMAC3_RSV_CNT_MASK) >> WF_PSE_TOP_LMAC3_PG_INFO_LMAC3_RSV_CNT_SHFT; |
| + used_pg = (pg_flow_ctrl[17] & WF_PSE_TOP_LMAC3_PG_INFO_LMAC3_SRC_CNT_MASK) >> WF_PSE_TOP_LMAC3_PG_INFO_LMAC3_SRC_CNT_SHFT; |
| + printk("\t\tThe used/reserved pages of LMAC3 group=0x%03x/0x%03x\n", used_pg, rsv_pg); |
| + |
| + printk("\tReserved page counter of PLE group: 0x%08x\n", pg_flow_ctrl[14]); |
| + printk("\tPLE group page status: 0x%08x\n", pg_flow_ctrl[15]); |
| + min_q = (pg_flow_ctrl[14] & WF_PSE_TOP_PG_PLE_GROUP_PLE_MIN_QUOTA_MASK) >> WF_PSE_TOP_PG_PLE_GROUP_PLE_MIN_QUOTA_SHFT; |
| + max_q = (pg_flow_ctrl[14] & WF_PSE_TOP_PG_PLE_GROUP_PLE_MAX_QUOTA_MASK) >> WF_PSE_TOP_PG_PLE_GROUP_PLE_MAX_QUOTA_SHFT; |
| + printk("\t\tThe max/min quota pages of PLE group=0x%03x/0x%03x\n", max_q, min_q); |
| + rsv_pg = (pg_flow_ctrl[15] & WF_PSE_TOP_PLE_PG_INFO_PLE_RSV_CNT_MASK) >> WF_PSE_TOP_PLE_PG_INFO_PLE_RSV_CNT_SHFT; |
| + used_pg = (pg_flow_ctrl[15] & WF_PSE_TOP_PLE_PG_INFO_PLE_SRC_CNT_MASK) >> WF_PSE_TOP_PLE_PG_INFO_PLE_SRC_CNT_SHFT; |
| + printk("\t\tThe used/reserved pages of PLE group=0x%03x/0x%03x\n", used_pg, rsv_pg); |
| + |
| + printk("\tReserved page counter of PLE1 group: 0x%08x\n", pg_flow_ctrl[14]); |
| + printk("\tPLE1 group page status: 0x%08x\n", pg_flow_ctrl[15]); |
| + min_q = (pg_flow_ctrl[20] & WF_PSE_TOP_PG_PLE_GROUP_PLE_MIN_QUOTA_MASK) >> WF_PSE_TOP_PG_PLE_GROUP_PLE_MIN_QUOTA_SHFT; |
| + max_q = (pg_flow_ctrl[20] & WF_PSE_TOP_PG_PLE_GROUP_PLE_MAX_QUOTA_MASK) >> WF_PSE_TOP_PG_PLE_GROUP_PLE_MAX_QUOTA_SHFT; |
| + printk("\t\tThe max/min quota pages of PLE1 group=0x%03x/0x%03x\n", max_q, min_q); |
| + rsv_pg = (pg_flow_ctrl[21] & WF_PSE_TOP_PLE_PG_INFO_PLE_RSV_CNT_MASK) >> WF_PSE_TOP_PLE_PG_INFO_PLE_RSV_CNT_SHFT; |
| + used_pg = (pg_flow_ctrl[21] & WF_PSE_TOP_PLE_PG_INFO_PLE_SRC_CNT_MASK) >> WF_PSE_TOP_PLE_PG_INFO_PLE_SRC_CNT_SHFT; |
| + printk("\t\tThe used/reserved pages of PLE1 group=0x%03x/0x%03x\n", used_pg, rsv_pg); |
| + |
| + printk("\tReserved page counter of MDP group: 0x%08x\n", pg_flow_ctrl[18]); |
| + printk("\tMDP group page status: 0x%08x\n", pg_flow_ctrl[19]); |
| + min_q = (pg_flow_ctrl[18] & WF_PSE_TOP_PG_MDP_GROUP_MDP_MIN_QUOTA_MASK) >> WF_PSE_TOP_PG_MDP_GROUP_MDP_MIN_QUOTA_SHFT; |
| + max_q = (pg_flow_ctrl[18] & WF_PSE_TOP_PG_MDP_GROUP_MDP_MAX_QUOTA_MASK) >> WF_PSE_TOP_PG_MDP_GROUP_MDP_MAX_QUOTA_SHFT; |
| + printk("\t\tThe max/min quota pages of MDP group=0x%03x/0x%03x\n", max_q, min_q); |
| + rsv_pg = (pg_flow_ctrl[19] & WF_PSE_TOP_MDP_PG_INFO_MDP_RSV_CNT_MASK) >> WF_PSE_TOP_MDP_PG_INFO_MDP_RSV_CNT_SHFT; |
| + used_pg = (pg_flow_ctrl[19] & WF_PSE_TOP_MDP_PG_INFO_MDP_SRC_CNT_MASK) >> WF_PSE_TOP_MDP_PG_INFO_MDP_SRC_CNT_SHFT; |
| + printk("\t\tThe used/reserved pages of MDP group=0x%03x/0x%03x\n", used_pg, rsv_pg); |
| + printk("\tReserved page counter of MDP2 group: 0x%08x\n", pg_flow_ctrl[22]); |
| + printk("\tMDP2 group page status: 0x%08x\n", pg_flow_ctrl[23]); |
| + min_q = (pg_flow_ctrl[22] & WF_PSE_TOP_PG_MDP2_GROUP_MDP2_MIN_QUOTA_MASK) >> WF_PSE_TOP_PG_MDP2_GROUP_MDP2_MIN_QUOTA_SHFT; |
| + max_q = (pg_flow_ctrl[22] & WF_PSE_TOP_PG_MDP2_GROUP_MDP2_MAX_QUOTA_MASK) >> WF_PSE_TOP_PG_MDP2_GROUP_MDP2_MAX_QUOTA_SHFT; |
| + printk("\t\tThe max/min quota pages of MDP2 group=0x%03x/0x%03x\n", max_q, min_q); |
| + rsv_pg = (pg_flow_ctrl[23] & WF_PSE_TOP_MDP2_PG_INFO_MDP2_RSV_CNT_MASK) >> WF_PSE_TOP_MDP2_PG_INFO_MDP2_RSV_CNT_SHFT; |
| + used_pg = (pg_flow_ctrl[23] & WF_PSE_TOP_MDP2_PG_INFO_MDP2_SRC_CNT_MASK) >> WF_PSE_TOP_MDP2_PG_INFO_MDP2_SRC_CNT_SHFT; |
| + printk("\t\tThe used/reserved pages of MDP2 group=0x%03x/0x%03x\n", used_pg, rsv_pg); |
| + printk("\tReserved page counter of MDP3 group: 0x%08x\n", pg_flow_ctrl[24]); |
| + printk("\tMDP3 group page status: 0x%08x\n", pg_flow_ctrl[25]); |
| + min_q = (pg_flow_ctrl[24] & WF_PSE_TOP_PG_MDP3_GROUP_MDP3_MIN_QUOTA_MASK) >> WF_PSE_TOP_PG_MDP3_GROUP_MDP3_MIN_QUOTA_SHFT; |
| + max_q = (pg_flow_ctrl[24] & WF_PSE_TOP_PG_MDP3_GROUP_MDP3_MAX_QUOTA_MASK) >> WF_PSE_TOP_PG_MDP3_GROUP_MDP3_MAX_QUOTA_SHFT; |
| + printk("\t\tThe max/min quota pages of MDP3 group=0x%03x/0x%03x\n", max_q, min_q); |
| + rsv_pg = (pg_flow_ctrl[25] & WF_PSE_TOP_MDP3_PG_INFO_MDP3_RSV_CNT_MASK) >> WF_PSE_TOP_MDP3_PG_INFO_MDP3_RSV_CNT_SHFT; |
| + used_pg = (pg_flow_ctrl[25] & WF_PSE_TOP_MDP3_PG_INFO_MDP3_SRC_CNT_MASK) >> WF_PSE_TOP_MDP3_PG_INFO_MDP3_SRC_CNT_SHFT; |
| + printk("\t\tThe used/reserved pages of MDP3 group=0x%03x/0x%03x\n", used_pg, rsv_pg); |
| + /* Queue Empty Status */ |
| + printk("PSE Queue Empty Status:\n"); |
| + printk("\tQUEUE_EMPTY: 0x%08x, QUEUE_EMPTY2: 0x%08x\n", pse_stat[0], pse_stat[1]); |
| + printk("\t\tCPU Q0/1/2/3/4 empty=%d/%d/%d/%d/%d\n", |
| + (pse_stat[0] & WF_PSE_TOP_QUEUE_EMPTY_CPU_Q0_EMPTY_MASK) >> WF_PSE_TOP_QUEUE_EMPTY_CPU_Q0_EMPTY_SHFT, |
| + ((pse_stat[0] & WF_PSE_TOP_QUEUE_EMPTY_CPU_Q1_EMPTY_MASK) >> WF_PSE_TOP_QUEUE_EMPTY_CPU_Q1_EMPTY_SHFT), |
| + ((pse_stat[0] & WF_PSE_TOP_QUEUE_EMPTY_CPU_Q2_EMPTY_MASK) >> WF_PSE_TOP_QUEUE_EMPTY_CPU_Q2_EMPTY_SHFT), |
| + ((pse_stat[0] & WF_PSE_TOP_QUEUE_EMPTY_CPU_Q3_EMPTY_MASK) >> WF_PSE_TOP_QUEUE_EMPTY_CPU_Q3_EMPTY_SHFT), |
| + ((pse_stat[0] & WF_PSE_TOP_QUEUE_EMPTY_CPU_Q4_EMPTY_MASK) >> WF_PSE_TOP_QUEUE_EMPTY_CPU_Q4_EMPTY_SHFT)); |
| + printk("\t\tHIF Q0/1/2/3/4/5/6/7/8/9/10/11/12/13 empty=%d/%d/%d/%d/%d/%d/%d/%d/%d/%d/%d/%d/%d/%d\n", |
| + ((pse_stat[1] & WF_PSE_TOP_QUEUE_EMPTY_1_HIF_0_EMPTY_MASK) >> WF_PSE_TOP_QUEUE_EMPTY_1_HIF_0_EMPTY_SHFT), |
| + ((pse_stat[1] & WF_PSE_TOP_QUEUE_EMPTY_1_HIF_1_EMPTY_MASK) >> WF_PSE_TOP_QUEUE_EMPTY_1_HIF_1_EMPTY_SHFT), |
| + ((pse_stat[1] & WF_PSE_TOP_QUEUE_EMPTY_1_HIF_2_EMPTY_MASK) >> WF_PSE_TOP_QUEUE_EMPTY_1_HIF_2_EMPTY_SHFT), |
| + ((pse_stat[1] & WF_PSE_TOP_QUEUE_EMPTY_1_HIF_3_EMPTY_MASK) >> WF_PSE_TOP_QUEUE_EMPTY_1_HIF_3_EMPTY_SHFT), |
| + ((pse_stat[1] & WF_PSE_TOP_QUEUE_EMPTY_1_HIF_4_EMPTY_MASK) >> WF_PSE_TOP_QUEUE_EMPTY_1_HIF_4_EMPTY_SHFT), |
| + ((pse_stat[1] & WF_PSE_TOP_QUEUE_EMPTY_1_HIF_5_EMPTY_MASK) >> WF_PSE_TOP_QUEUE_EMPTY_1_HIF_5_EMPTY_SHFT), |
| + ((pse_stat[1] & WF_PSE_TOP_QUEUE_EMPTY_1_HIF_6_EMPTY_MASK) >> WF_PSE_TOP_QUEUE_EMPTY_1_HIF_6_EMPTY_SHFT), |
| + ((pse_stat[1] & WF_PSE_TOP_QUEUE_EMPTY_1_HIF_7_EMPTY_MASK) >> WF_PSE_TOP_QUEUE_EMPTY_1_HIF_7_EMPTY_SHFT), |
| + ((pse_stat[1] & WF_PSE_TOP_QUEUE_EMPTY_1_HIF_8_EMPTY_MASK) >> WF_PSE_TOP_QUEUE_EMPTY_1_HIF_8_EMPTY_SHFT), |
| + ((pse_stat[1] & WF_PSE_TOP_QUEUE_EMPTY_1_HIF_9_EMPTY_MASK) >> WF_PSE_TOP_QUEUE_EMPTY_1_HIF_9_EMPTY_SHFT), |
| + ((pse_stat[1] & WF_PSE_TOP_QUEUE_EMPTY_1_HIF_10_EMPTY_MASK) >> WF_PSE_TOP_QUEUE_EMPTY_1_HIF_10_EMPTY_SHFT), |
| + ((pse_stat[1] & WF_PSE_TOP_QUEUE_EMPTY_1_HIF_11_EMPTY_MASK) >> WF_PSE_TOP_QUEUE_EMPTY_1_HIF_11_EMPTY_SHFT), |
| + ((pse_stat[1] & WF_PSE_TOP_QUEUE_EMPTY_1_HIF_12_EMPTY_MASK) >> WF_PSE_TOP_QUEUE_EMPTY_1_HIF_12_EMPTY_SHFT), |
| + ((pse_stat[1] & WF_PSE_TOP_QUEUE_EMPTY_1_HIF_13_EMPTY_MASK) >> WF_PSE_TOP_QUEUE_EMPTY_1_HIF_13_EMPTY_SHFT)); |
| + printk("\t\tLMAC TX Q empty=%d\n", |
| + ((pse_stat[0] & WF_PSE_TOP_QUEUE_EMPTY_LMAC_TX_QUEUE_EMPTY_MASK) >> WF_PSE_TOP_QUEUE_EMPTY_LMAC_TX_QUEUE_EMPTY_SHFT)); |
| + printk("\t\tMDP TX Q0/Q1/Q2/RX Q empty=%d/%d/%d/%d\n", |
| + ((pse_stat[0] & WF_PSE_TOP_QUEUE_EMPTY_MDP_TX_QUEUE_EMPTY_MASK) >> WF_PSE_TOP_QUEUE_EMPTY_MDP_TX_QUEUE_EMPTY_SHFT), |
| + ((pse_stat[0] & WF_PSE_TOP_QUEUE_EMPTY_MDP_TX1_QUEUE_EMPTY_MASK) >> WF_PSE_TOP_QUEUE_EMPTY_MDP_TX1_QUEUE_EMPTY_SHFT), |
| + ((pse_stat[1] & WF_PSE_TOP_QUEUE_EMPTY_1_MDP_TX2_QUEUE_EMPTY_MASK) >> WF_PSE_TOP_QUEUE_EMPTY_1_MDP_TX2_QUEUE_EMPTY_SHFT), |
| + ((pse_stat[0] & WF_PSE_TOP_QUEUE_EMPTY_MDP_RX_QUEUE_EMPTY_MASK) >> WF_PSE_TOP_QUEUE_EMPTY_MDP_RX_QUEUE_EMPTY_SHFT)); |
| + printk("\t\tSEC TX Q0/Q1/Q2/RX Q empty=%d/%d/%d/%d\n", |
| + ((pse_stat[0] & WF_PSE_TOP_QUEUE_EMPTY_SEC_TX_QUEUE_EMPTY_MASK) >> WF_PSE_TOP_QUEUE_EMPTY_SEC_TX_QUEUE_EMPTY_SHFT), |
| + ((pse_stat[0] & WF_PSE_TOP_QUEUE_EMPTY_SEC_TX1_QUEUE_EMPTY_MASK) >> WF_PSE_TOP_QUEUE_EMPTY_SEC_TX1_QUEUE_EMPTY_SHFT), |
| + ((pse_stat[1] & WF_PSE_TOP_QUEUE_EMPTY_1_SEC_TX2_QUEUE_EMPTY_MASK) >> WF_PSE_TOP_QUEUE_EMPTY_1_SEC_TX2_QUEUE_EMPTY_SHFT), |
| + ((pse_stat[0] & WF_PSE_TOP_QUEUE_EMPTY_SEC_RX_QUEUE_EMPTY_MASK) >> WF_PSE_TOP_QUEUE_EMPTY_SEC_RX_QUEUE_EMPTY_SHFT)); |
| + printk("\t\tSFD PARK Q empty=%d\n", |
| + ((pse_stat[0] & WF_PSE_TOP_QUEUE_EMPTY_SFD_PARK_QUEUE_EMPTY_MASK) >> WF_PSE_TOP_QUEUE_EMPTY_SFD_PARK_QUEUE_EMPTY_SHFT)); |
| + printk("\t\tMDP TXIOC Q0/Q1/Q2 empty=%d/%d/%d\n", |
| + ((pse_stat[0] & WF_PSE_TOP_QUEUE_EMPTY_MDP_TXIOC_QUEUE_EMPTY_MASK) >> WF_PSE_TOP_QUEUE_EMPTY_MDP_TXIOC_QUEUE_EMPTY_SHFT), |
| + ((pse_stat[0] & WF_PSE_TOP_QUEUE_EMPTY_MDP_TXIOC1_QUEUE_EMPTY_MASK) >> WF_PSE_TOP_QUEUE_EMPTY_MDP_TXIOC1_QUEUE_EMPTY_SHFT), |
| + ((pse_stat[1] & WF_PSE_TOP_QUEUE_EMPTY_1_MDP_TXIOC2_QUEUE_EMPTY_MASK) >> WF_PSE_TOP_QUEUE_EMPTY_1_MDP_TXIOC2_QUEUE_EMPTY_SHFT)); |
| + printk("\t\tMDP RXIOC Q0/Q1/Q2/Q3 empty=%d/%d/%d/%d\n", |
| + ((pse_stat[0] & WF_PSE_TOP_QUEUE_EMPTY_MDP_RXIOC_QUEUE_EMPTY_MASK) >> WF_PSE_TOP_QUEUE_EMPTY_MDP_RXIOC_QUEUE_EMPTY_SHFT), |
| + ((pse_stat[0] & WF_PSE_TOP_QUEUE_EMPTY_MDP_RXIOC1_QUEUE_EMPTY_MASK) >> WF_PSE_TOP_QUEUE_EMPTY_MDP_RXIOC1_QUEUE_EMPTY_SHFT), |
| + ((pse_stat[1] & WF_PSE_TOP_QUEUE_EMPTY_1_MDP_RXIOC2_QUEUE_EMPTY_MASK) >> WF_PSE_TOP_QUEUE_EMPTY_1_MDP_RXIOC2_QUEUE_EMPTY_SHFT), |
| + ((pse_stat[1] & WF_PSE_TOP_QUEUE_EMPTY_1_MDP_RXIOC3_QUEUE_EMPTY_MASK) >> WF_PSE_TOP_QUEUE_EMPTY_1_MDP_RXIOC3_QUEUE_EMPTY_SHFT)); |
| + printk("\t\tRLS Q empty=%d\n", |
| + ((pse_stat[0] & WF_PSE_TOP_QUEUE_EMPTY_RLS_Q_EMTPY_MASK) >> WF_PSE_TOP_QUEUE_EMPTY_RLS_Q_EMTPY_SHFT)); |
| + printk("Nonempty Q info:\n"); |
| + |
| + for (i = 0; i < 31; i++) { |
| + if (((pse_stat[0] & (0x1 << i)) >> i) == 0) { |
| + u32 hfid, tfid, pktcnt, fl_que_ctrl[3] = {0}; |
| + |
| + if (pse_queue_empty_info[i].QueueName != NULL) { |
| + printk("\t%s: ", pse_queue_empty_info[i].QueueName); |
| + fl_que_ctrl[0] |= WF_PSE_TOP_FL_QUE_CTRL_0_EXECUTE_MASK; |
| + fl_que_ctrl[1] |= (pse_queue_empty_info[i].Portid << WF_PSE_TOP_FL_QUE_CTRL_1_Q_BUF_PID_SHFT); |
| + fl_que_ctrl[0] |= (pse_queue_empty_info[i].Queueid << WF_PSE_TOP_FL_QUE_CTRL_0_Q_BUF_QID_SHFT); |
| + } else |
| + continue; |
| + |
| + fl_que_ctrl[0] |= (0x1 << 31); |
| + mt76_wr(dev, WF_PSE_TOP_FL_QUE_CTRL_1_ADDR, fl_que_ctrl[1]); |
| + mt76_wr(dev, WF_PSE_TOP_FL_QUE_CTRL_0_ADDR, fl_que_ctrl[0]); |
| + fl_que_ctrl[1] = mt76_rr(dev, WF_PSE_TOP_FL_QUE_CTRL_2_ADDR); |
| + fl_que_ctrl[2] = mt76_rr(dev, WF_PSE_TOP_FL_QUE_CTRL_3_ADDR); |
| + hfid = (fl_que_ctrl[1] & WF_PSE_TOP_FL_QUE_CTRL_2_QUEUE_HEAD_FID_MASK) >> WF_PSE_TOP_FL_QUE_CTRL_2_QUEUE_HEAD_FID_SHFT; |
| + tfid = (fl_que_ctrl[1] & WF_PSE_TOP_FL_QUE_CTRL_2_QUEUE_TAIL_FID_MASK) >> WF_PSE_TOP_FL_QUE_CTRL_2_QUEUE_TAIL_FID_SHFT; |
| + pktcnt = (fl_que_ctrl[2] & WF_PSE_TOP_FL_QUE_CTRL_3_QUEUE_PKT_NUM_MASK) >> WF_PSE_TOP_FL_QUE_CTRL_3_QUEUE_PKT_NUM_SHFT; |
| + printk("tail/head fid = 0x%03x/0x%03x, pkt cnt = 0x%03x\n", |
| + tfid, hfid, pktcnt); |
| + } |
| + } |
| + |
| + for (i = 0; i < 31; i++) { |
| + if (((pse_stat[1] & (0x1 << i)) >> i) == 0) { |
| + u32 hfid, tfid, pktcnt, fl_que_ctrl[3] = {0}; |
| + |
| + if (pse_queue_empty2_info[i].QueueName != NULL) { |
| + printk("\t%s: ", pse_queue_empty2_info[i].QueueName); |
| + fl_que_ctrl[0] |= WF_PSE_TOP_FL_QUE_CTRL_0_EXECUTE_MASK; |
| + fl_que_ctrl[1] |= (pse_queue_empty2_info[i].Portid << WF_PSE_TOP_FL_QUE_CTRL_1_Q_BUF_PID_SHFT); |
| + fl_que_ctrl[0] |= (pse_queue_empty2_info[i].Queueid << WF_PSE_TOP_FL_QUE_CTRL_0_Q_BUF_QID_SHFT); |
| + } else |
| + continue; |
| + |
| + fl_que_ctrl[0] |= (0x1 << 31); |
| + mt76_wr(dev, WF_PSE_TOP_FL_QUE_CTRL_1_ADDR, fl_que_ctrl[1]); |
| + mt76_wr(dev, WF_PSE_TOP_FL_QUE_CTRL_0_ADDR, fl_que_ctrl[0]); |
| + fl_que_ctrl[1] = mt76_rr(dev, WF_PSE_TOP_FL_QUE_CTRL_2_ADDR); |
| + fl_que_ctrl[2] = mt76_rr(dev, WF_PSE_TOP_FL_QUE_CTRL_3_ADDR); |
| + hfid = (fl_que_ctrl[1] & WF_PSE_TOP_FL_QUE_CTRL_2_QUEUE_HEAD_FID_MASK) >> WF_PSE_TOP_FL_QUE_CTRL_2_QUEUE_HEAD_FID_SHFT; |
| + tfid = (fl_que_ctrl[1] & WF_PSE_TOP_FL_QUE_CTRL_2_QUEUE_TAIL_FID_MASK) >> WF_PSE_TOP_FL_QUE_CTRL_2_QUEUE_TAIL_FID_SHFT; |
| + pktcnt = (fl_que_ctrl[2] & WF_PSE_TOP_FL_QUE_CTRL_3_QUEUE_PKT_NUM_MASK) >> WF_PSE_TOP_FL_QUE_CTRL_3_QUEUE_PKT_NUM_SHFT; |
| + printk("tail/head fid = 0x%03x/0x%03x, pkt cnt = 0x%03x\n", |
| + tfid, hfid, pktcnt); |
| + } |
| + } |
| + |
| + return true; |
| +} |
| + |
| +/* PLE INFO */ |
| +static char *sta_ctrl_reg[] = {"ENABLE", "DISABLE", "PAUSE"}; |
| +static struct bmac_queue_info ple_queue_empty_info[] = { |
| + {"CPU Q0", ENUM_UMAC_CPU_PORT_1, ENUM_UMAC_CTX_Q_0, 0}, |
| + {"CPU Q1", ENUM_UMAC_CPU_PORT_1, ENUM_UMAC_CTX_Q_1, 0}, |
| + {"CPU Q2", ENUM_UMAC_CPU_PORT_1, ENUM_UMAC_CTX_Q_2, 0}, |
| + {"CPU Q3", ENUM_UMAC_CPU_PORT_1, ENUM_UMAC_CTX_Q_3, 0}, |
| + {"ALTX Q0", ENUM_UMAC_LMAC_PORT_2, 0x10, 0}, |
| + {"BMC Q0", ENUM_UMAC_LMAC_PORT_2, 0x11, 0}, |
| + {"BCN Q0", ENUM_UMAC_LMAC_PORT_2, 0x12, 0}, |
| + {"PSMP Q0", ENUM_UMAC_LMAC_PORT_2, 0x13, 0}, |
| + {"ALTX Q1", ENUM_UMAC_LMAC_PORT_2, 0x10, 1}, |
| + {"BMC Q1", ENUM_UMAC_LMAC_PORT_2, 0x11, 1}, |
| + {"BCN Q1", ENUM_UMAC_LMAC_PORT_2, 0x12, 1}, |
| + {"PSMP Q1", ENUM_UMAC_LMAC_PORT_2, 0x13, 1}, |
| + {"ALTX Q2", ENUM_UMAC_LMAC_PORT_2, 0x10, 2}, |
| + {"BMC Q2", ENUM_UMAC_LMAC_PORT_2, 0x11, 2}, |
| + {"BCN Q2", ENUM_UMAC_LMAC_PORT_2, 0x12, 2}, |
| + {"PSMP Q2", ENUM_UMAC_LMAC_PORT_2, 0x13, 2}, |
| + {"NAF Q", ENUM_UMAC_LMAC_PORT_2, 0x18, 0}, |
| + {"NBCN Q", ENUM_UMAC_LMAC_PORT_2, 0x19, 0}, |
| + {NULL, 0, 0, 0}, {NULL, 0, 0, 0}, /* 18, 19 not defined */ |
| + {"FIXFID Q", ENUM_UMAC_LMAC_PORT_2, 0x1a, 0}, |
| + {NULL, 0, 0, 0}, {NULL, 0, 0, 0}, {NULL, 0, 0, 0}, {NULL, 0, 0, 0}, {NULL, 0, 0, 0}, |
| + {NULL, 0, 0, 0}, {NULL, 0, 0, 0}, |
| + {"RLS4 Q", ENUM_PLE_CTRL_PSE_PORT_3, 0x7c, 0}, |
| + {"RLS3 Q", ENUM_PLE_CTRL_PSE_PORT_3, 0x7d, 0}, |
| + {"RLS2 Q", ENUM_PLE_CTRL_PSE_PORT_3, 0x7e, 0}, |
| + {"RLS Q", ENUM_PLE_CTRL_PSE_PORT_3, 0x7f, 0} |
| +}; |
| + |
| +static struct bmac_queue_info_t ple_txcmd_queue_empty_info[] = { |
| + {"AC00Q", ENUM_UMAC_LMAC_PORT_2, 0x40}, |
| + {"AC01Q", ENUM_UMAC_LMAC_PORT_2, 0x41}, |
| + {"AC02Q", ENUM_UMAC_LMAC_PORT_2, 0x42}, |
| + {"AC03Q", ENUM_UMAC_LMAC_PORT_2, 0x43}, |
| + {"AC10Q", ENUM_UMAC_LMAC_PORT_2, 0x44}, |
| + {"AC11Q", ENUM_UMAC_LMAC_PORT_2, 0x45}, |
| + {"AC12Q", ENUM_UMAC_LMAC_PORT_2, 0x46}, |
| + {"AC13Q", ENUM_UMAC_LMAC_PORT_2, 0x47}, |
| + {"AC20Q", ENUM_UMAC_LMAC_PORT_2, 0x48}, |
| + {"AC21Q", ENUM_UMAC_LMAC_PORT_2, 0x49}, |
| + {"AC22Q", ENUM_UMAC_LMAC_PORT_2, 0x4a}, |
| + {"AC23Q", ENUM_UMAC_LMAC_PORT_2, 0x4b}, |
| + {"AC30Q", ENUM_UMAC_LMAC_PORT_2, 0x4c}, |
| + {"AC31Q", ENUM_UMAC_LMAC_PORT_2, 0x4d}, |
| + {"AC32Q", ENUM_UMAC_LMAC_PORT_2, 0x4e}, |
| + {"AC33Q", ENUM_UMAC_LMAC_PORT_2, 0x4f}, |
| + {"ALTX Q0", ENUM_UMAC_LMAC_PORT_2, 0x50}, |
| + {"TF Q0", ENUM_UMAC_LMAC_PORT_2, 0x51}, |
| + {"TWT TSF-TF Q0", ENUM_UMAC_LMAC_PORT_2, 0x52}, |
| + {"TWT DL Q0", ENUM_UMAC_LMAC_PORT_2, 0x53}, |
| + {"TWT UL Q0", ENUM_UMAC_LMAC_PORT_2, 0x54}, |
| + {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, |
| + {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, |
| +}; |
| + |
| +static void |
| +besra_get_ple_acq_stat(struct besra_dev *dev, u32 *ple_stat) |
| +{ |
| + ple_stat[0] = mt76_rr(dev, WF_PLE_TOP_QUEUE_EMPTY_ADDR); |
| + |
| + ple_stat[1] = mt76_rr(dev, WF_PLE_TOP_AC0_QUEUE_EMPTY0_ADDR); |
| + ple_stat[2] = mt76_rr(dev, WF_PLE_TOP_AC0_QUEUE_EMPTY1_ADDR); |
| + ple_stat[3] = mt76_rr(dev, WF_PLE_TOP_AC0_QUEUE_EMPTY2_ADDR); |
| + ple_stat[4] = mt76_rr(dev, WF_PLE_TOP_AC0_QUEUE_EMPTY3_ADDR); |
| + ple_stat[5] = mt76_rr(dev, WF_PLE_TOP_AC0_QUEUE_EMPTY4_ADDR); |
| + ple_stat[6] = mt76_rr(dev, WF_PLE_TOP_AC0_QUEUE_EMPTY5_ADDR); |
| + ple_stat[7] = mt76_rr(dev, WF_PLE_TOP_AC0_QUEUE_EMPTY6_ADDR); |
| + ple_stat[8] = mt76_rr(dev, WF_PLE_TOP_AC0_QUEUE_EMPTY7_ADDR); |
| + ple_stat[9] = mt76_rr(dev, WF_PLE_TOP_AC0_QUEUE_EMPTY8_ADDR); |
| + |
| + ple_stat[10] = mt76_rr(dev, WF_PLE_TOP_AC1_QUEUE_EMPTY0_ADDR); |
| + ple_stat[11] = mt76_rr(dev, WF_PLE_TOP_AC1_QUEUE_EMPTY1_ADDR); |
| + ple_stat[12] = mt76_rr(dev, WF_PLE_TOP_AC1_QUEUE_EMPTY2_ADDR); |
| + ple_stat[13] = mt76_rr(dev, WF_PLE_TOP_AC1_QUEUE_EMPTY3_ADDR); |
| + ple_stat[14] = mt76_rr(dev, WF_PLE_TOP_AC1_QUEUE_EMPTY4_ADDR); |
| + ple_stat[15] = mt76_rr(dev, WF_PLE_TOP_AC1_QUEUE_EMPTY5_ADDR); |
| + ple_stat[16] = mt76_rr(dev, WF_PLE_TOP_AC1_QUEUE_EMPTY6_ADDR); |
| + ple_stat[17] = mt76_rr(dev, WF_PLE_TOP_AC1_QUEUE_EMPTY7_ADDR); |
| + ple_stat[18] = mt76_rr(dev, WF_PLE_TOP_AC1_QUEUE_EMPTY8_ADDR); |
| + |
| + ple_stat[19] = mt76_rr(dev, WF_PLE_TOP_AC2_QUEUE_EMPTY0_ADDR); |
| + ple_stat[20] = mt76_rr(dev, WF_PLE_TOP_AC2_QUEUE_EMPTY1_ADDR); |
| + ple_stat[21] = mt76_rr(dev, WF_PLE_TOP_AC2_QUEUE_EMPTY2_ADDR); |
| + ple_stat[22] = mt76_rr(dev, WF_PLE_TOP_AC2_QUEUE_EMPTY3_ADDR); |
| + ple_stat[23] = mt76_rr(dev, WF_PLE_TOP_AC2_QUEUE_EMPTY4_ADDR); |
| + ple_stat[24] = mt76_rr(dev, WF_PLE_TOP_AC2_QUEUE_EMPTY5_ADDR); |
| + ple_stat[25] = mt76_rr(dev, WF_PLE_TOP_AC2_QUEUE_EMPTY6_ADDR); |
| + ple_stat[26] = mt76_rr(dev, WF_PLE_TOP_AC2_QUEUE_EMPTY7_ADDR); |
| + ple_stat[27] = mt76_rr(dev, WF_PLE_TOP_AC2_QUEUE_EMPTY8_ADDR); |
| + |
| + ple_stat[28] = mt76_rr(dev, WF_PLE_TOP_AC3_QUEUE_EMPTY0_ADDR); |
| + ple_stat[29] = mt76_rr(dev, WF_PLE_TOP_AC3_QUEUE_EMPTY1_ADDR); |
| + ple_stat[30] = mt76_rr(dev, WF_PLE_TOP_AC3_QUEUE_EMPTY2_ADDR); |
| + ple_stat[31] = mt76_rr(dev, WF_PLE_TOP_AC3_QUEUE_EMPTY3_ADDR); |
| + ple_stat[32] = mt76_rr(dev, WF_PLE_TOP_AC3_QUEUE_EMPTY4_ADDR); |
| + ple_stat[33] = mt76_rr(dev, WF_PLE_TOP_AC3_QUEUE_EMPTY5_ADDR); |
| + ple_stat[34] = mt76_rr(dev, WF_PLE_TOP_AC3_QUEUE_EMPTY6_ADDR); |
| + ple_stat[35] = mt76_rr(dev, WF_PLE_TOP_AC3_QUEUE_EMPTY7_ADDR); |
| + ple_stat[36] = mt76_rr(dev, WF_PLE_TOP_AC3_QUEUE_EMPTY8_ADDR); |
| +} |
| + |
| +static void |
| +besra_get_ple_txcmd_stat(struct besra_dev *dev, u32 *ple_txcmd_stat) |
| +{ |
| + *ple_txcmd_stat = mt76_rr(dev, WF_PLE_TOP_NATIVE_TXCMD_QUEUE_EMPTY_ADDR); |
| +} |
| + |
| +static void |
| +besra_get_dis_sta_map(struct besra_dev *dev, u32 *dis_sta_map) |
| +{ |
| + dis_sta_map[0] = mt76_rr(dev, WF_PLE_TOP_DIS_STA_MAP0_ADDR); |
| + dis_sta_map[1] = mt76_rr(dev, WF_PLE_TOP_DIS_STA_MAP1_ADDR); |
| + dis_sta_map[2] = mt76_rr(dev, WF_PLE_TOP_DIS_STA_MAP2_ADDR); |
| + dis_sta_map[3] = mt76_rr(dev, WF_PLE_TOP_DIS_STA_MAP3_ADDR); |
| + dis_sta_map[4] = mt76_rr(dev, WF_PLE_TOP_DIS_STA_MAP4_ADDR); |
| + dis_sta_map[5] = mt76_rr(dev, WF_PLE_TOP_DIS_STA_MAP5_ADDR); |
| + dis_sta_map[6] = mt76_rr(dev, WF_PLE_TOP_DIS_STA_MAP6_ADDR); |
| + dis_sta_map[7] = mt76_rr(dev, WF_PLE_TOP_DIS_STA_MAP7_ADDR); |
| + dis_sta_map[8] = mt76_rr(dev, WF_PLE_TOP_DIS_STA_MAP8_ADDR); |
| +} |
| + |
| +static void |
| +besra_get_sta_pause(struct besra_dev *dev, u32 *sta_pause) |
| +{ |
| + /* BELLWETHER TODO: Wait MIB counter API implement complete */ |
| +} |
| + |
| +static int |
| +besra_show_sta_acq_info(struct seq_file *s, u32 *ple_stat, |
| + u32 *sta_pause, u32 *dis_sta_map, |
| + u32 dumptxd) |
| +{ |
| + struct besra_dev *dev = dev_get_drvdata(s->private); |
| + int i, j; |
| + u32 total_nonempty_cnt = 0; |
| + |
| + for (j = 0; j < ALL_CR_NUM_OF_ALL_AC; j++) { /* show AC Q info */ |
| + for (i = 0; i < 32; i++) { |
| + if (((ple_stat[j + 1] & (0x1 << i)) >> i) == 0) { |
| + u32 hfid, tfid, pktcnt, ac_num = j / CR_NUM_OF_AC, ctrl = 0; |
| + u32 sta_num = i + (j % CR_NUM_OF_AC) * 32, fl_que_ctrl[3] = {0}; |
| + u32 wmmidx = 0; |
| + struct besra_sta *msta; |
| + struct mt76_wcid *wcid; |
| + struct ieee80211_sta *sta = NULL; |
| + |
| + wcid = rcu_dereference(dev->mt76.wcid[sta_num]); |
| + sta = wcid_to_sta(wcid); |
| + if (!sta) { |
| + printk("ERROR!! no found STA wcid=%d\n", sta_num); |
| + return 0; |
| + } |
| + msta = container_of(wcid, struct besra_sta, wcid); |
| + wmmidx = msta->vif->mt76.wmm_idx; |
| + |
| + printk("\tSTA%d AC%d: ", sta_num, ac_num); |
| + |
| + fl_que_ctrl[0] |= WF_PLE_TOP_FL_QUE_CTRL_0_EXECUTE_MASK; |
| + fl_que_ctrl[1] |= (ENUM_UMAC_LMAC_PORT_2 << WF_PLE_TOP_FL_QUE_CTRL_1_Q_BUF_PID_SHFT); |
| + fl_que_ctrl[0] |= (ac_num << WF_PLE_TOP_FL_QUE_CTRL_0_Q_BUF_QID_SHFT); |
| + fl_que_ctrl[0] |= (sta_num << WF_PLE_TOP_FL_QUE_CTRL_0_Q_BUF_WLANID_SHFT); |
| + mt76_wr(dev, WF_PLE_TOP_FL_QUE_CTRL_1_ADDR, fl_que_ctrl[1]); |
| + mt76_wr(dev, WF_PLE_TOP_FL_QUE_CTRL_0_ADDR, fl_que_ctrl[0]); |
| + fl_que_ctrl[1] = mt76_rr(dev, WF_PLE_TOP_FL_QUE_CTRL_2_ADDR); |
| + fl_que_ctrl[2] = mt76_rr(dev, WF_PLE_TOP_FL_QUE_CTRL_3_ADDR); |
| + hfid = (fl_que_ctrl[1] & WF_PLE_TOP_FL_QUE_CTRL_2_QUEUE_HEAD_FID_MASK) >> |
| + WF_PLE_TOP_FL_QUE_CTRL_2_QUEUE_HEAD_FID_SHFT; |
| + tfid = (fl_que_ctrl[1] & WF_PLE_TOP_FL_QUE_CTRL_2_QUEUE_TAIL_FID_MASK) >> |
| + WF_PLE_TOP_FL_QUE_CTRL_2_QUEUE_TAIL_FID_SHFT; |
| + pktcnt = (fl_que_ctrl[2] & WF_PLE_TOP_FL_QUE_CTRL_3_QUEUE_PKT_NUM_MASK) >> |
| + WF_PLE_TOP_FL_QUE_CTRL_3_QUEUE_PKT_NUM_SHFT; |
| + printk("tail/head fid = 0x%03x/0x%03x, pkt cnt = 0x%03x", |
| + tfid, hfid, pktcnt); |
| + |
| + if (((sta_pause[j % CR_NUM_OF_AC] & 0x1 << i) >> i) == 1) |
| + ctrl = 2; |
| + |
| + if (((dis_sta_map[j % CR_NUM_OF_AC] & 0x1 << i) >> i) == 1) |
| + ctrl = 1; |
| + |
| + printk(" ctrl = %s", sta_ctrl_reg[ctrl]); |
| + printk(" (wmmidx=%d)\n", wmmidx); |
| + |
| + total_nonempty_cnt++; |
| + |
| + if (pktcnt > 0 && dumptxd > 0) |
| + besra_dump_bmac_txd_by_fid(hfid); |
| + } |
| + } |
| + } |
| + |
| + return total_nonempty_cnt; |
| +} |
| + |
| +static void |
| +besra_show_txcmdq_info(struct seq_file *s, u32 ple_txcmd_stat) |
| +{ |
| + struct besra_dev *dev = dev_get_drvdata(s->private); |
| + int i; |
| + |
| + printk("Nonempty TXCMD Q info:\n"); |
| + for (i = 0; i < 32 ; i++) { |
| + if (((ple_txcmd_stat & (0x1 << i)) >> i) == 0) { |
| + u32 hfid, tfid, pktcnt, fl_que_ctrl[3] = {0}; |
| + |
| + if (ple_txcmd_queue_empty_info[i].QueueName != NULL) { |
| + printk("\t%s: ", ple_txcmd_queue_empty_info[i].QueueName); |
| + fl_que_ctrl[0] |= WF_PLE_TOP_FL_QUE_CTRL_0_EXECUTE_MASK; |
| + fl_que_ctrl[1] |= (ple_txcmd_queue_empty_info[i].Portid << |
| + WF_PLE_TOP_FL_QUE_CTRL_1_Q_BUF_PID_SHFT); |
| + fl_que_ctrl[0] |= (ple_txcmd_queue_empty_info[i].Queueid << |
| + WF_PLE_TOP_FL_QUE_CTRL_0_Q_BUF_QID_SHFT); |
| + } else |
| + continue; |
| + |
| + mt76_wr(dev, WF_PLE_TOP_FL_QUE_CTRL_1_ADDR, fl_que_ctrl[1]); |
| + mt76_wr(dev, WF_PLE_TOP_FL_QUE_CTRL_0_ADDR, fl_que_ctrl[0]); |
| + fl_que_ctrl[1] = mt76_rr(dev, WF_PLE_TOP_FL_QUE_CTRL_2_ADDR); |
| + fl_que_ctrl[2] = mt76_rr(dev, WF_PLE_TOP_FL_QUE_CTRL_3_ADDR); |
| + hfid = (fl_que_ctrl[1] & WF_PLE_TOP_FL_QUE_CTRL_2_QUEUE_HEAD_FID_MASK) >> |
| + WF_PLE_TOP_FL_QUE_CTRL_2_QUEUE_HEAD_FID_SHFT; |
| + tfid = (fl_que_ctrl[1] & WF_PLE_TOP_FL_QUE_CTRL_2_QUEUE_TAIL_FID_MASK) >> |
| + WF_PLE_TOP_FL_QUE_CTRL_2_QUEUE_TAIL_FID_SHFT; |
| + pktcnt = (fl_que_ctrl[2] & WF_PLE_TOP_FL_QUE_CTRL_3_QUEUE_PKT_NUM_MASK) >> |
| + WF_PLE_TOP_FL_QUE_CTRL_3_QUEUE_PKT_NUM_SHFT; |
| + printk("tail/head fid = 0x%03x/0x%03x, pkt cnt = 0x%03x\n", |
| + tfid, hfid, pktcnt); |
| + } |
| + } |
| +} |
| + |
| +static int |
| +besra_pleinfo_read(struct seq_file *s, void *data) |
| +{ |
| + struct besra_dev *dev = dev_get_drvdata(s->private); |
| + u32 ple_buf_ctrl, pg_sz, pg_num; |
| + u32 ple_stat[ALL_CR_NUM_OF_ALL_AC + 1] = {0}, pg_flow_ctrl[10] = {0}; |
| + u32 ple_native_txcmd_stat; |
| + u32 ple_txcmd_stat; |
| + u32 sta_pause[CR_NUM_OF_AC] = {0}, dis_sta_map[CR_NUM_OF_AC] = {0}; |
| + u32 fpg_cnt, ffa_cnt, fpg_head, fpg_tail, hif_max_q, hif_min_q; |
| + u32 rpg_hif, upg_hif, cpu_max_q, cpu_min_q, rpg_cpu, upg_cpu; |
| + int i, j; |
| + u32 dumptxd = 1; |
| + |
| + ple_buf_ctrl = mt76_rr(dev, WF_PLE_TOP_PBUF_CTRL_ADDR); |
| + besra_get_ple_acq_stat(dev, ple_stat); |
| + ple_txcmd_stat = mt76_rr(dev, WF_PLE_TOP_TXCMD_QUEUE_EMPTY_ADDR); |
| + besra_get_ple_txcmd_stat(dev, &ple_native_txcmd_stat); |
| + pg_flow_ctrl[0] = mt76_rr(dev, WF_PLE_TOP_FREEPG_CNT_ADDR); |
| + pg_flow_ctrl[1] = mt76_rr(dev, WF_PLE_TOP_FREEPG_HEAD_TAIL_ADDR); |
| + pg_flow_ctrl[2] = mt76_rr(dev, WF_PLE_TOP_PG_HIF_GROUP_ADDR); |
| + pg_flow_ctrl[3] = mt76_rr(dev, WF_PLE_TOP_HIF_PG_INFO_ADDR); |
| + pg_flow_ctrl[4] = mt76_rr(dev, WF_PLE_TOP_PG_CPU_GROUP_ADDR); |
| + pg_flow_ctrl[5] = mt76_rr(dev, WF_PLE_TOP_CPU_PG_INFO_ADDR); |
| + pg_flow_ctrl[6] = mt76_rr(dev, WF_PLE_TOP_PG_HIF_TXCMD_GROUP_ADDR); |
| + pg_flow_ctrl[7] = mt76_rr(dev, WF_PLE_TOP_HIF_TXCMD_PG_INFO_ADDR); |
| + pg_flow_ctrl[8] = mt76_rr(dev, WF_PLE_TOP_PG_HIF_WMTXD_GROUP_ADDR); |
| + pg_flow_ctrl[9] = mt76_rr(dev, WF_PLE_TOP_HIF_WMTXD_PG_INFO_ADDR); |
| + besra_get_dis_sta_map(dev, dis_sta_map); |
| + besra_get_sta_pause(dev, sta_pause); |
| + |
| + /* Configuration Info */ |
| + printk("PLE Configuration Info:\n"); |
| + printk("\tPacket Buffer Control(0x82060014): 0x%08x\n", ple_buf_ctrl); |
| + pg_sz = (ple_buf_ctrl & WF_PLE_TOP_PBUF_CTRL_PAGE_SIZE_CFG_MASK) >> WF_PLE_TOP_PBUF_CTRL_PAGE_SIZE_CFG_SHFT; |
| + printk("\t\tPage Size=%d(%d bytes per page)\n", pg_sz, (pg_sz == 1 ? 128 : 64)); |
| + printk("\t\tPage Offset=%d(in unit of 2KB)\n", |
| + (ple_buf_ctrl & WF_PLE_TOP_PBUF_CTRL_PBUF_OFFSET_MASK) >> WF_PLE_TOP_PBUF_CTRL_PBUF_OFFSET_SHFT); |
| + pg_num = (ple_buf_ctrl & WF_PLE_TOP_PBUF_CTRL_TOTAL_PAGE_NUM_MASK) >> WF_PLE_TOP_PBUF_CTRL_TOTAL_PAGE_NUM_SHFT; |
| + printk("\t\tTotal Page=%d pages\n", pg_num); |
| + |
| + /* Page Flow Control */ |
| + printk("PLE Page Flow Control:\n"); |
| + printk("\tFree page counter: 0x%08x\n", pg_flow_ctrl[0]); |
| + fpg_cnt = (pg_flow_ctrl[0] & WF_PLE_TOP_FREEPG_CNT_FREEPG_CNT_MASK) >> WF_PLE_TOP_FREEPG_CNT_FREEPG_CNT_SHFT; |
| + printk("\t\tThe toal page number of free=0x%03x\n", fpg_cnt); |
| + ffa_cnt = (pg_flow_ctrl[0] & WF_PLE_TOP_FREEPG_CNT_FFA_CNT_MASK) >> WF_PLE_TOP_FREEPG_CNT_FFA_CNT_SHFT; |
| + printk("\t\tThe free page numbers of free for all=0x%03x\n", ffa_cnt); |
| + printk("\tFree page head and tail: 0x%08x\n", pg_flow_ctrl[1]); |
| + fpg_head = (pg_flow_ctrl[1] & WF_PLE_TOP_FREEPG_HEAD_TAIL_FREEPG_HEAD_MASK) >> WF_PLE_TOP_FREEPG_HEAD_TAIL_FREEPG_HEAD_SHFT; |
| + fpg_tail = (pg_flow_ctrl[1] & WF_PLE_TOP_FREEPG_HEAD_TAIL_FREEPG_TAIL_MASK) >> WF_PLE_TOP_FREEPG_HEAD_TAIL_FREEPG_TAIL_SHFT; |
| + printk("\t\tThe tail/head page of free page list=0x%03x/0x%03x\n", fpg_tail, fpg_head); |
| + printk("\tReserved page counter of HIF group: 0x%08x\n", pg_flow_ctrl[2]); |
| + printk("\tHIF group page status: 0x%08x\n", pg_flow_ctrl[3]); |
| + hif_min_q = (pg_flow_ctrl[2] & WF_PLE_TOP_PG_HIF_GROUP_HIF_MIN_QUOTA_MASK) >> WF_PLE_TOP_PG_HIF_GROUP_HIF_MIN_QUOTA_SHFT; |
| + hif_max_q = (pg_flow_ctrl[2] & WF_PLE_TOP_PG_HIF_GROUP_HIF_MAX_QUOTA_MASK) >> WF_PLE_TOP_PG_HIF_GROUP_HIF_MAX_QUOTA_SHFT; |
| + printk("\t\tThe max/min quota pages of HIF group=0x%03x/0x%03x\n", hif_max_q, hif_min_q); |
| + rpg_hif = (pg_flow_ctrl[3] & WF_PLE_TOP_HIF_PG_INFO_HIF_RSV_CNT_MASK) >> WF_PLE_TOP_HIF_PG_INFO_HIF_RSV_CNT_SHFT; |
| + upg_hif = (pg_flow_ctrl[3] & WF_PLE_TOP_HIF_PG_INFO_HIF_SRC_CNT_MASK) >> WF_PLE_TOP_HIF_PG_INFO_HIF_SRC_CNT_SHFT; |
| + printk("\t\tThe used/reserved pages of HIF group=0x%03x/0x%03x\n", upg_hif, rpg_hif); |
| + |
| + printk("\tReserved page counter of WMTXD group: 0x%08x\n", pg_flow_ctrl[8]); |
| + printk("\tWMTXD group page status: 0x%08x\n", pg_flow_ctrl[9]); |
| + cpu_min_q = (pg_flow_ctrl[8] & WF_PLE_TOP_PG_HIF_WMTXD_GROUP_HIF_WMTXD_MIN_QUOTA_MASK) >> WF_PLE_TOP_PG_HIF_WMTXD_GROUP_HIF_WMTXD_MIN_QUOTA_SHFT; |
| + cpu_max_q = (pg_flow_ctrl[8] & WF_PLE_TOP_PG_HIF_WMTXD_GROUP_HIF_WMTXD_MAX_QUOTA_MASK) >> WF_PLE_TOP_PG_HIF_WMTXD_GROUP_HIF_WMTXD_MAX_QUOTA_SHFT; |
| + printk("\t\tThe max/min quota pages of WMTXD group=0x%03x/0x%03x\n", cpu_max_q, cpu_min_q); |
| + rpg_cpu = (pg_flow_ctrl[9] & WF_PLE_TOP_HIF_WMTXD_PG_INFO_HIF_WMTXD_RSV_CNT_MASK) >> WF_PLE_TOP_HIF_WMTXD_PG_INFO_HIF_WMTXD_RSV_CNT_SHFT; |
| + upg_cpu = (pg_flow_ctrl[9] & WF_PLE_TOP_HIF_WMTXD_PG_INFO_HIF_WMTXD_SRC_CNT_MASK) >> WF_PLE_TOP_HIF_WMTXD_PG_INFO_HIF_WMTXD_SRC_CNT_SHFT; |
| + printk("\t\tThe used/reserved pages of WMTXD group=0x%03x/0x%03x\n", upg_cpu, rpg_cpu); |
| + |
| + printk("\tReserved page counter of HIF_TXCMD group: 0x%08x\n", pg_flow_ctrl[6]); |
| + printk("\tHIF_TXCMD group page status: 0x%08x\n", pg_flow_ctrl[7]); |
| + cpu_min_q = (pg_flow_ctrl[6] & WF_PLE_TOP_PG_HIF_TXCMD_GROUP_HIF_TXCMD_MIN_QUOTA_MASK) >> WF_PLE_TOP_PG_HIF_TXCMD_GROUP_HIF_TXCMD_MIN_QUOTA_SHFT; |
| + cpu_max_q = (pg_flow_ctrl[6] & WF_PLE_TOP_PG_HIF_TXCMD_GROUP_HIF_TXCMD_MAX_QUOTA_MASK) >> WF_PLE_TOP_PG_HIF_TXCMD_GROUP_HIF_TXCMD_MAX_QUOTA_SHFT; |
| + printk("\t\tThe max/min quota pages of HIF_TXCMD group=0x%03x/0x%03x\n", cpu_max_q, cpu_min_q); |
| + rpg_cpu = (pg_flow_ctrl[7] & WF_PLE_TOP_HIF_TXCMD_PG_INFO_HIF_TXCMD_RSV_CNT_MASK) >> WF_PLE_TOP_HIF_TXCMD_PG_INFO_HIF_TXCMD_RSV_CNT_SHFT; |
| + upg_cpu = (pg_flow_ctrl[7] & WF_PLE_TOP_HIF_TXCMD_PG_INFO_HIF_TXCMD_SRC_CNT_MASK) >> WF_PLE_TOP_HIF_TXCMD_PG_INFO_HIF_TXCMD_SRC_CNT_SHFT; |
| + printk("\t\tThe used/reserved pages of HIF_TXCMD group=0x%03x/0x%03x\n", upg_cpu, rpg_cpu); |
| + |
| + printk("\tReserved page counter of CPU group(0x820c0150): 0x%08x\n", pg_flow_ctrl[4]); |
| + printk("\tCPU group page status(0x820c0154): 0x%08x\n", pg_flow_ctrl[5]); |
| + cpu_min_q = (pg_flow_ctrl[4] & WF_PLE_TOP_PG_CPU_GROUP_CPU_MIN_QUOTA_MASK) >> WF_PLE_TOP_PG_CPU_GROUP_CPU_MIN_QUOTA_SHFT; |
| + cpu_max_q = (pg_flow_ctrl[4] & WF_PLE_TOP_PG_CPU_GROUP_CPU_MAX_QUOTA_MASK) >> WF_PLE_TOP_PG_CPU_GROUP_CPU_MAX_QUOTA_SHFT; |
| + printk("\t\tThe max/min quota pages of CPU group=0x%03x/0x%03x\n", cpu_max_q, cpu_min_q); |
| + rpg_cpu = (pg_flow_ctrl[5] & WF_PLE_TOP_CPU_PG_INFO_CPU_RSV_CNT_MASK) >> WF_PLE_TOP_CPU_PG_INFO_CPU_RSV_CNT_SHFT; |
| + upg_cpu = (pg_flow_ctrl[5] & WF_PLE_TOP_CPU_PG_INFO_CPU_SRC_CNT_MASK) >> WF_PLE_TOP_CPU_PG_INFO_CPU_SRC_CNT_SHFT; |
| + printk("\t\tThe used/reserved pages of CPU group=0x%03x/0x%03x\n", upg_cpu, rpg_cpu); |
| + |
| + if ((ple_stat[0] & WF_PLE_TOP_QUEUE_EMPTY_ALL_AC_EMPTY_MASK) == 0) { |
| + for (j = 0; j < ALL_CR_NUM_OF_ALL_AC; j++) { |
| + if (j % CR_NUM_OF_AC == 0) { |
| + printk("\n\tNonempty AC%d Q of STA#: ", j / CR_NUM_OF_AC); |
| + } |
| + |
| + for (i = 0; i < 32; i++) { |
| + if (((ple_stat[j + 1] & (0x1 << i)) >> i) == 0) { |
| + printk("%d ", i + (j % CR_NUM_OF_AC) * 32); |
| + } |
| + } |
| + } |
| + |
| + printk("\n"); |
| + } |
| + |
| + printk("non-native/native txcmd queue empty = %d/%d\n", ple_txcmd_stat, ple_native_txcmd_stat); |
| + |
| + printk("Nonempty Q info:\n"); |
| + |
| + for (i = 0; i < 32; i++) { |
| + if (((ple_stat[0] & (0x1 << i)) >> i) == 0) { |
| + u32 hfid, tfid, pktcnt, waitcnt = 3, fl_que_ctrl[3] = {0}; |
| + |
| + if (ple_queue_empty_info[i].QueueName != NULL) { |
| + printk("\t%s: ", ple_queue_empty_info[i].QueueName); |
| + fl_que_ctrl[0] |= WF_PLE_TOP_FL_QUE_CTRL_0_EXECUTE_MASK; |
| + fl_que_ctrl[1] |= (ple_queue_empty_info[i].Portid << WF_PLE_TOP_FL_QUE_CTRL_1_Q_BUF_PID_SHFT); |
| + fl_que_ctrl[1] |= (ple_queue_empty_info[i].tgid << WF_PLE_TOP_FL_QUE_CTRL_1_Q_BUF_TGID_SHFT); |
| + /* Bellwether HW issue, Queueid need + (4 * band_idx) */ |
| + fl_que_ctrl[0] |= ((ple_queue_empty_info[i].Queueid + 4 * ple_queue_empty_info[i].tgid) |
| + << WF_PLE_TOP_FL_QUE_CTRL_0_Q_BUF_QID_SHFT); |
| + } else |
| + continue; |
| + |
| + mt76_wr(dev, WF_PLE_TOP_FL_QUE_CTRL_1_ADDR, fl_que_ctrl[1]); |
| + mt76_wr(dev, WF_PLE_TOP_FL_QUE_CTRL_0_ADDR, fl_que_ctrl[0]); |
| + |
| + do { |
| + /* Polling if HW done (0 = Done, 1 = Not done) */ |
| + fl_que_ctrl[0] = mt76_rr(dev, WF_PLE_TOP_FL_QUE_CTRL_0_ADDR); |
| + fl_que_ctrl[0] &= WF_PLE_TOP_FL_QUE_CTRL_0_EXECUTE_MASK; |
| + waitcnt -= 1; |
| + } while (fl_que_ctrl[0] && waitcnt); |
| + |
| + if (fl_que_ctrl[0] && waitcnt == 0) { |
| + printk("Polling HW too many times, drop information\n"); |
| + continue; |
| + } |
| + |
| + fl_que_ctrl[1] = mt76_rr(dev, WF_PLE_TOP_FL_QUE_CTRL_2_ADDR); |
| + fl_que_ctrl[2] = mt76_rr(dev, WF_PLE_TOP_FL_QUE_CTRL_3_ADDR); |
| + hfid = (fl_que_ctrl[1] & WF_PLE_TOP_FL_QUE_CTRL_2_QUEUE_HEAD_FID_MASK) >> WF_PLE_TOP_FL_QUE_CTRL_2_QUEUE_HEAD_FID_SHFT; |
| + tfid = (fl_que_ctrl[1] & WF_PLE_TOP_FL_QUE_CTRL_2_QUEUE_TAIL_FID_MASK) >> WF_PLE_TOP_FL_QUE_CTRL_2_QUEUE_TAIL_FID_SHFT; |
| + pktcnt = (fl_que_ctrl[2] & WF_PLE_TOP_FL_QUE_CTRL_3_QUEUE_PKT_NUM_MASK) >> WF_PLE_TOP_FL_QUE_CTRL_3_QUEUE_PKT_NUM_SHFT; |
| + printk("tail/head fid = 0x%03x/0x%03x, pkt cnt = 0x%03x\n", |
| + tfid, hfid, pktcnt); |
| + |
| + if (pktcnt > 0 && dumptxd > 0) |
| + besra_dump_bmac_txd_by_fid(hfid); |
| + } |
| + } |
| + |
| + besra_show_sta_acq_info(s, ple_stat, sta_pause, dis_sta_map, dumptxd); |
| + besra_show_txcmdq_info(s, ple_native_txcmd_stat); |
| + |
| + return true; |
| +} |
| + |
| +/* DRR */ |
| +static int |
| +besra_drr_info(struct seq_file *s, void *data) |
| +{ |
| + /* BELLWETHER TODO: Wait MIB counter API implement complete */ |
| + return 0; |
| +} |
| + |
| +int besra_mtk_init_debugfs(struct besra_phy *phy, struct dentry *dir) |
| +{ |
| + struct besra_dev *dev = phy->dev; |
| + |
| + besra_mcu_fw_log_2_host(dev, MCU_FW_LOG_WM, 0); |
| + |
| + debugfs_create_file("fw_debug_module", 0600, dir, dev, |
| + &fops_fw_debug_module); |
| + debugfs_create_file("fw_debug_level", 0600, dir, dev, |
| + &fops_fw_debug_level); |
| + |
| + debugfs_create_devm_seqfile(dev->mt76.dev, "wtbl_info", dir, |
| + besra_wtbl_read); |
| + |
| + debugfs_create_devm_seqfile(dev->mt76.dev, "tr_info", dir, |
| + besra_trinfo_read); |
| + |
| + debugfs_create_devm_seqfile(dev->mt76.dev, "drr_info", dir, |
| + besra_drr_info); |
| + |
| + debugfs_create_devm_seqfile(dev->mt76.dev, "ple_info", dir, |
| + besra_pleinfo_read); |
| + |
| + debugfs_create_devm_seqfile(dev->mt76.dev, "pse_info", dir, |
| + besra_pseinfo_read); |
| + |
| + debugfs_create_devm_seqfile(dev->mt76.dev, "mib_info0", dir, |
| + besra_mibinfo_band0); |
| + debugfs_create_devm_seqfile(dev->mt76.dev, "mib_info1", dir, |
| + besra_mibinfo_band1); |
| + debugfs_create_devm_seqfile(dev->mt76.dev, "mib_info2", dir, |
| + besra_mibinfo_band2); |
| + |
| + debugfs_create_u32("token_idx", 0600, dir, &dev->dbg.token_idx); |
| + debugfs_create_devm_seqfile(dev->mt76.dev, "token", dir, |
| + besra_token_read); |
| + debugfs_create_devm_seqfile(dev->mt76.dev, "token_txd", dir, |
| + besra_token_txd_read); |
| + debugfs_create_u32("txd_dump", 0600, dir, &dev->dbg.txd_read_cnt); |
| + debugfs_create_u32("rxd_dump", 0600, dir, &dev->dbg.rxd_read_cnt); |
| + |
| + debugfs_create_devm_seqfile(dev->mt76.dev, "amsdu_info", dir, |
| + besra_amsdu_read); |
| + |
| + debugfs_create_devm_seqfile(dev->mt76.dev, "agg_info0", dir, |
| + besra_agginfo_read_band0); |
| + debugfs_create_devm_seqfile(dev->mt76.dev, "agg_info1", dir, |
| + besra_agginfo_read_band1); |
| + debugfs_create_devm_seqfile(dev->mt76.dev, "agg_info2", dir, |
| + besra_agginfo_read_band2); |
| + |
| + return 0; |
| +} |
| + |
| +#endif |
| diff --git a/tools/fwlog.c b/tools/fwlog.c |
| index e5d4a105..3c6a61d7 100644 |
| --- a/tools/fwlog.c |
| +++ b/tools/fwlog.c |
| @@ -26,7 +26,7 @@ static const char *debugfs_path(const char *phyname, const char *file) |
| return path; |
| } |
| |
| -static int mt76_set_fwlog_en(const char *phyname, bool en) |
| +static int mt76_set_fwlog_en(const char *phyname, bool en, char *val) |
| { |
| FILE *f = fopen(debugfs_path(phyname, "fw_debug_bin"), "w"); |
| |
| @@ -35,7 +35,13 @@ static int mt76_set_fwlog_en(const char *phyname, bool en) |
| return 1; |
| } |
| |
| - fprintf(f, "7"); |
| + if (en && val) |
| + fprintf(f, "%s", val); |
| + else if (en) |
| + fprintf(f, "7"); |
| + else |
| + fprintf(f, "0"); |
| + |
| fclose(f); |
| |
| return 0; |
| @@ -76,6 +82,7 @@ static void handle_signal(int sig) |
| |
| int mt76_fwlog(const char *phyname, int argc, char **argv) |
| { |
| +#define BUF_SIZE 1504 |
| struct sockaddr_in local = { |
| .sin_family = AF_INET, |
| .sin_addr.s_addr = INADDR_ANY, |
| @@ -84,9 +91,9 @@ int mt76_fwlog(const char *phyname, int argc, char **argv) |
| .sin_family = AF_INET, |
| .sin_port = htons(55688), |
| }; |
| - char buf[1504]; |
| + char *buf = calloc(BUF_SIZE, sizeof(char)); |
| int ret = 0; |
| - int yes = 1; |
| + /* int yes = 1; */ |
| int s, fd; |
| |
| if (argc < 1) { |
| @@ -105,13 +112,13 @@ int mt76_fwlog(const char *phyname, int argc, char **argv) |
| return 1; |
| } |
| |
| - setsockopt(s, SOL_SOCKET, SO_BROADCAST, &yes, sizeof(yes)); |
| + /* setsockopt(s, SOL_SOCKET, SO_BROADCAST, &yes, sizeof(yes)); */ |
| if (bind(s, (struct sockaddr *)&local, sizeof(local)) < 0) { |
| perror("bind"); |
| return 1; |
| } |
| |
| - if (mt76_set_fwlog_en(phyname, true)) |
| + if (mt76_set_fwlog_en(phyname, true, argv[1])) |
| return 1; |
| |
| fd = open(debugfs_path(phyname, "fwlog_data"), O_RDONLY); |
| @@ -145,8 +152,8 @@ int mt76_fwlog(const char *phyname, int argc, char **argv) |
| if (!r) |
| continue; |
| |
| - if (len > sizeof(buf)) { |
| - fprintf(stderr, "Length error: %d > %d\n", len, (int)sizeof(buf)); |
| + if (len > BUF_SIZE) { |
| + fprintf(stderr, "Length error: %d > %d\n", len, BUF_SIZE); |
| ret = 1; |
| break; |
| } |
| @@ -171,7 +178,7 @@ int mt76_fwlog(const char *phyname, int argc, char **argv) |
| close(fd); |
| |
| out: |
| - mt76_set_fwlog_en(phyname, false); |
| + mt76_set_fwlog_en(phyname, false, NULL); |
| |
| return ret; |
| } |
| -- |
| 2.18.0 |
| |