commit 77bbf4315da5d8cdba105759e428b1e11048981d
author developer <developer@mediatek.com> Mon Jun 28 18:39:08 2021 +0800
committer developer <developer@mediatek.com> Tue Jun 29 10:23:41 2021 +0800
tree 8db00f80f19071faec55edf069e89dbfdc47a807
parent fbbf02b1eb0535196d0c8dc427ce9cc2a2f76c52

[][Change mtk eth to enable clk by its own dts node instead of global clk]

[Description]
Change mtk eth to enable clk by its own dts node instead of global clk

[Release-log]
N/A

Change-Id: Ib03f389453a88053f7edb2b2dad064c43077f650
Reviewed-on: https://gerrit.mediatek.inc/c/openwrt/feeds/mtk_openwrt_feeds/+/4687906

target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986b.dtsi

diff --git a/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986b.dtsi b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986b.dtsi
index a795e83..adc55b8 100644
--- a/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986b.dtsi
+++ b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986b.dtsi
@@ -357,14 +357,14 @@
                          <&ethsys CK_ETH_GP1_EN>,
                          <&ethsys CK_ETH_WOCPU1_EN>,
                          <&ethsys CK_ETH_WOCPU0_EN>,
-                         <&ethsys CK_SGM0_TX_EN>,
-                         <&ethsys CK_SGM0_RX_EN>,
-                         <&ethsys CK_SGM0_CK0_EN>,
-                         <&ethsys CK_SGM0_CDR_CK0_EN>,
-                         <&ethsys CK_SGM1_TX_EN>,
-                         <&ethsys CK_SGM1_RX_EN>,
-                         <&ethsys CK_SGM1_CK1_EN>,
-                         <&ethsys CK_SGM1_CDR_CK1_EN>;
+                         <&sgmiisys0 CK_SGM0_TX_EN>,
+                         <&sgmiisys0 CK_SGM0_RX_EN>,
+                         <&sgmiisys0 CK_SGM0_CK0_EN>,
+                         <&sgmiisys0 CK_SGM0_CDR_CK0_EN>,
+                         <&sgmiisys1 CK_SGM1_TX_EN>,
+                         <&sgmiisys1 CK_SGM1_RX_EN>,
+                         <&sgmiisys1 CK_SGM1_CK1_EN>,
+                         <&sgmiisys1 CK_SGM1_CDR_CK1_EN>;
                 clock-names = "fe", "gp2", "gp1", "wocpu1", "wocpu0",
                          "sgmii_tx250m", "sgmii_rx250m",
                          "sgmii_cdr_ref", "sgmii_cdr_fb",