[][Change mtk eth to enable clk by its own dts node instead of global clk]
[Description]
Change mtk eth to enable clk by its own dts node instead of global clk
[Release-log]
N/A
Change-Id: Ib03f389453a88053f7edb2b2dad064c43077f650
Reviewed-on: https://gerrit.mediatek.inc/c/openwrt/feeds/mtk_openwrt_feeds/+/4687906
diff --git a/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986-clkitg.dtsi b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986-clkitg.dtsi
index a01d8f3..9a59273 100644
--- a/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986-clkitg.dtsi
+++ b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986-clkitg.dtsi
@@ -1,243 +1,243 @@
-/*
- * Copyright (c) 2018 MediaTek Inc.
- * Author: Wenzhen.Yu <Wenzhen.Yu@mediatek.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-&clkitg {
- bring-up {
- compatible = "mediatek,clk-bring-up";
- clocks =
- <&apmixedsys CK_APMIXED_ARMPLL>,
- <&apmixedsys CK_APMIXED_NET2PLL>,
- <&apmixedsys CK_APMIXED_MMPLL>,
- <&apmixedsys CK_APMIXED_SGMPLL>,
- <&apmixedsys CK_APMIXED_WEDMCUPLL>,
- <&apmixedsys CK_APMIXED_NET1PLL>,
- <&apmixedsys CK_APMIXED_MPLL>,
- <&apmixedsys CK_APMIXED_APLL2>,
- <&infracfg CK_INFRA_CK_F26M>,
- <&infracfg CK_INFRA_UART>,
- <&infracfg CK_INFRA_ISPI0>,
- <&infracfg CK_INFRA_I2C>,
- <&infracfg CK_INFRA_ISPI1>,
- <&infracfg CK_INFRA_PWM>,
- <&infracfg CK_INFRA_66M_MCK>,
- <&infracfg CK_INFRA_CK_F32K>,
- <&infracfg CK_INFRA_PCIE_CK>,
- <&infracfg CK_INFRA_PWM_BCK>,
- <&infracfg CK_INFRA_PWM_CK1>,
- <&infracfg CK_INFRA_PWM_CK2>,
- <&infracfg CK_INFRA_133M_HCK>,
- <&infracfg CK_INFRA_EIP_CK>,
- <&infracfg CK_INFRA_66M_PHCK>,
- <&infracfg CK_INFRA_FAUD_L_CK >,
- <&infracfg CK_INFRA_FAUD_AUD_CK>,
- <&infracfg CK_INFRA_FAUD_EG2_CK>,
- <&infracfg CK_INFRA_I2CS_CK>,
- <&infracfg CK_INFRA_MUX_UART0>,
- <&infracfg CK_INFRA_MUX_UART1>,
- <&infracfg CK_INFRA_MUX_UART2>,
- <&infracfg CK_INFRA_NFI_CK>,
- <&infracfg CK_INFRA_SPINFI_CK>,
- <&infracfg CK_INFRA_MUX_SPI0>,
- <&infracfg CK_INFRA_MUX_SPI1>,
- <&infracfg CK_INFRA_RTC_32K>,
- <&infracfg CK_INFRA_FMSDC_CK>,
- <&infracfg CK_INFRA_FMSDC_HCK_CK>,
- <&infracfg CK_INFRA_PERI_133M>,
- <&infracfg CK_INFRA_133M_PHCK>,
- <&infracfg CK_INFRA_USB_SYS_CK>,
- <&infracfg CK_INFRA_USB_CK>,
- <&infracfg CK_INFRA_USB_XHCI_CK>,
- <&infracfg CK_INFRA_PCIE_GFMUX_TL_O_PRE>,
- <&infracfg CK_INFRA_F26M_CK0>,
- <&infracfg_ao CK_INFRA_UART0_SEL>,
- <&infracfg_ao CK_INFRA_UART1_SEL>,
- <&infracfg_ao CK_INFRA_UART2_SEL>,
- <&infracfg_ao CK_INFRA_SPI0_SEL>,
- <&infracfg_ao CK_INFRA_SPI1_SEL>,
- <&infracfg_ao CK_INFRA_PWM1_SEL>,
- <&infracfg_ao CK_INFRA_PWM2_SEL>,
- <&infracfg_ao CK_INFRA_PWM_BSEL>,
- <&infracfg_ao CK_INFRA_PCIE_SEL>,
- <&infracfg_ao CK_INFRA_GPT_STA>,
- <&infracfg_ao CK_INFRA_PWM_HCK>,
- <&infracfg_ao CK_INFRA_PWM_STA>,
- <&infracfg_ao CK_INFRA_PWM1_CK>,
- <&infracfg_ao CK_INFRA_PWM2_CK>,
- <&infracfg_ao CK_INFRA_CQ_DMA_CK>,
- <&infracfg_ao CK_INFRA_EIP97_CK>,
- <&infracfg_ao CK_INFRA_AUD_BUS_CK>,
- <&infracfg_ao CK_INFRA_AUD_26M_CK>,
- <&infracfg_ao CK_INFRA_AUD_L_CK>,
- <&infracfg_ao CK_INFRA_AUD_AUD_CK>,
- <&infracfg_ao CK_INFRA_AUD_EG2_CK>,
- <&infracfg_ao CK_INFRA_DRAMC_26M_CK>,
- <&infracfg_ao CK_INFRA_DBG_CK>,
- <&infracfg_ao CK_INFRA_AP_DMA_CK>,
- <&infracfg_ao CK_INFRA_SEJ_CK>,
- <&infracfg_ao CK_INFRA_SEJ_13M_CK>,
- <&infracfg_ao CK_INFRA_THERM_CK>,
- <&infracfg_ao CK_INFRA_I2CO_CK>,
- <&infracfg_ao CK_INFRA_UART0_CK>,
- <&infracfg_ao CK_INFRA_UART1_CK>,
- <&infracfg_ao CK_INFRA_UART2_CK>,
- <&infracfg_ao CK_INFRA_NFI1_CK>,
- <&infracfg_ao CK_INFRA_SPINFI1_CK>,
- <&infracfg_ao CK_INFRA_NFI_HCK_CK>,
- <&infracfg_ao CK_INFRA_SPI0_CK>,
- <&infracfg_ao CK_INFRA_SPI1_CK>,
- <&infracfg_ao CK_INFRA_SPI0_HCK_CK>,
- <&infracfg_ao CK_INFRA_SPI1_HCK_CK>,
- <&infracfg_ao CK_INFRA_FRTC_CK>,
- <&infracfg_ao CK_INFRA_MSDC_CK>,
- <&infracfg_ao CK_INFRA_MSDC_HCK_CK>,
- <&infracfg_ao CK_INFRA_MSDC_133M_CK>,
- <&infracfg_ao CK_INFRA_MSDC_66M_CK>,
- <&infracfg_ao CK_INFRA_ADC_26M_CK>,
- <&infracfg_ao CK_INFRA_ADC_FRC_CK>,
- <&infracfg_ao CK_INFRA_FBIST2FPC_CK>,
- <&infracfg_ao CK_INFRA_IUSB_133_CK>,
- <&infracfg_ao CK_INFRA_IUSB_66M_CK>,
- <&infracfg_ao CK_INFRA_IUSB_SYS_CK>,
- <&infracfg_ao CK_INFRA_IUSB_CK>,
- <&infracfg_ao CK_INFRA_IPCIE_CK>,
- <&infracfg_ao CK_INFRA_IPCIER_CK>,
- <&infracfg_ao CK_INFRA_IPCIEB_CK>,
- <&infracfg_ao CK_INFRA_TRNG_CK>,
- <&topckgen CK_TOP_CB_M_416M>,
- <&topckgen CK_TOP_CB_M_D2>,
- <&topckgen CK_TOP_CB_M_D4>,
- <&topckgen CK_TOP_CB_M_D8>,
- <&topckgen CK_TOP_M_D8_D2>,
- <&topckgen CK_TOP_M_D3_D2>,
- <&topckgen CK_TOP_CB_MM_D2>,
- <&topckgen CK_TOP_CB_MM_D4>,
- <&topckgen CK_TOP_CB_MM_D8>,
- <&topckgen CK_TOP_MM_D8_D2>,
- <&topckgen CK_TOP_MM_D3_D8>,
- <&topckgen CK_TOP_CB_U2_PHYD_CK>,
- <&topckgen CK_TOP_CB_APLL2_196M>,
- <&topckgen CK_TOP_APLL2_D4>,
- <&topckgen CK_TOP_CB_NET1_D4>,
- <&topckgen CK_TOP_CB_NET1_D5>,
- <&topckgen CK_TOP_NET1_D5_D2>,
- <&topckgen CK_TOP_NET1_D5_D4>,
- <&topckgen CK_TOP_NET1_D8_D2>,
- <&topckgen CK_TOP_NET1_D8_D4>,
- <&topckgen CK_TOP_CB_NET2_800M>,
- <&topckgen CK_TOP_CB_NET2_D4>,
- <&topckgen CK_TOP_NET2_D4_D2>,
- <&topckgen CK_TOP_NET2_D3_D2>,
- <&topckgen CK_TOP_CB_WEDMCU_760M>,
- <&topckgen CK_TOP_WEDMCU_D5_D2 >,
- <&topckgen CK_TOP_CB_SGM_325M>,
- <&topckgen CK_TOP_CB_CKSQ_40M_D2>,
- <&topckgen CK_TOP_CB_RTC_32K>,
- <&topckgen CK_TOP_CB_RTC_32P7K>,
- <&topckgen CK_TOP_NFI1X>,
- <&topckgen CK_TOP_USB_EQ_RX250M>,
- <&topckgen CK_TOP_USB_TX250M>,
- <&topckgen CK_TOP_USB_LN0_CK>,
- <&topckgen CK_TOP_USB_CDR_CK>,
- <&topckgen CK_TOP_SPINFI_BCK>,
- <&topckgen CK_TOP_I2C_BCK>,
- <&topckgen CK_TOP_PEXTP_TL>,
- <&topckgen CK_TOP_EMMC_250M>,
- <&topckgen CK_TOP_EMMC_416M>,
- <&topckgen CK_TOP_F_26M_ADC_CK>,
- <&topckgen CK_TOP_SYSAXI>,
- <&topckgen CK_TOP_NETSYS_WED_MCU>,
- <&topckgen CK_TOP_NETSYS_2X>,
- <&topckgen CK_TOP_SGM_325M>,
- <&topckgen CK_TOP_A1SYS>,
- <&topckgen CK_TOP_EIP_B>,
- <&topckgen CK_TOP_F26M>,
- <&topckgen CK_TOP_AUD_L>,
- <&topckgen CK_TOP_A_TUNER>,
- <&topckgen CK_TOP_U2U3_REF>,
- <&topckgen CK_TOP_U2U3_SYS>,
- <&topckgen CK_TOP_U2U3_XHCI>,
- <&topckgen CK_TOP_AP2CNN_HOST>,
- <&topckgen CK_TOP_NFI1X_SEL>,
- <&topckgen CK_TOP_SPINFI_SEL>,
- <&topckgen CK_TOP_SPI_SEL>,
- <&topckgen CK_TOP_SPIM_MST_SEL>,
- <&topckgen CK_TOP_UART_SEL>,
- <&topckgen CK_TOP_PWM_SEL>,
- <&topckgen CK_TOP_I2C_SEL>,
- <&topckgen CK_TOP_PEXTP_TL_SEL>,
- <&topckgen CK_TOP_EMMC_250M_SEL >,
- <&topckgen CK_TOP_EMMC_416M_SEL >,
- <&topckgen CK_TOP_F_26M_ADC_SEL>,
- <&topckgen CK_TOP_DRAMC_SEL>,
- <&topckgen CK_TOP_DRAMC_MD32_SEL>,
- <&topckgen CK_TOP_SYSAXI_SEL>,
- <&topckgen CK_TOP_SYSAPB_SEL>,
- <&topckgen CK_TOP_ARM_DB_MAIN_SEL>,
- <&topckgen CK_TOP_ARM_DB_JTSEL>,
- <&topckgen CK_TOP_NETSYS_SEL>,
- <&topckgen CK_TOP_NETSYS_500M_SEL>,
- <&topckgen CK_TOP_NETSYS_MCU_SEL>,
- <&topckgen CK_TOP_NETSYS_2X_SEL>,
- <&topckgen CK_TOP_SGM_325M_SEL>,
- <&topckgen CK_TOP_SGM_REG_SEL>,
- <&topckgen CK_TOP_A1SYS_SEL>,
- <&topckgen CK_TOP_CONN_MCUSYS_SEL>,
- <&topckgen CK_TOP_EIP_B_SEL>,
- <&topckgen CK_TOP_PCIE_PHY_SEL>,
- <&topckgen CK_TOP_USB3_PHY_SEL>,
- <&topckgen CK_TOP_F26M_SEL>,
- <&topckgen CK_TOP_AUD_L_SEL>,
- <&topckgen CK_TOP_A_TUNER_SEL>,
- <&topckgen CK_TOP_U2U3_SEL>,
- <&topckgen CK_TOP_U2U3_SYS_SEL>,
- <&topckgen CK_TOP_U2U3_XHCI_SEL>,
- <&topckgen CK_TOP_DA_U2_REFSEL>,
- <&topckgen CK_TOP_DA_U2_CK_1P_SEL>,
- <&topckgen CK_TOP_AP2CNN_HOST_SEL>,
- <ðsys CK_ETH_FE_EN>,
- <ðsys CK_ETH_GP2_EN>,
- <ðsys CK_ETH_GP1_EN>,
- <ðsys CK_ETH_WOCPU1_EN>,
- <ðsys CK_ETH_WOCPU0_EN>,
- <&sgmiisys0 CK_SGM0_TX_EN>,
- <&sgmiisys0 CK_SGM0_RX_EN>,
- <&sgmiisys0 CK_SGM0_CK0_EN>,
- <&sgmiisys0 CK_SGM0_CDR_CK0_EN>,
- <&sgmiisys1 CK_SGM1_TX_EN>,
- <&sgmiisys1 CK_SGM1_RX_EN>,
- <&sgmiisys1 CK_SGM1_CK1_EN>,
- <&sgmiisys1 CK_SGM1_CDR_CK1_EN>;
-
-
- clock-names = "0", "1", "2", "3", "4", "5", "6", "7", "8", "9", "10", "11",
- "12", "13", "14", "15", "16", "17", "18", "19", "20", "21", "22", "23",
- "24", "25", "26", "27", "28", "29", "30", "31", "32", "33", "34", "35",
- "36", "37", "38", "39", "40", "41", "42", "43", "44", "45", "46", "47",
- "48", "49", "50", "51", "52", "53", "54", "55", "56", "57", "58", "59",
- "60", "61", "62", "63", "64", "65", "66", "67", "68", "69", "70", "71",
- "72", "73", "74", "75", "76", "77", "78", "79", "80", "81", "82", "83",
- "84", "85", "86", "87", "88", "89", "90", "91", "92", "93", "94", "95",
- "96", "97", "98", "99", "100", "101", "102", "103", "104", "105", "106", "107",
- "108", "109", "110", "111", "112", "113", "114", "115", "116", "117",
- "118", "119", "120", "121", "122", "123",
- "124", "125", "126", "127", "128", "129", "130", "131", "132", "133", "134", "135",
- "136", "137", "138", "139", "140", "141", "142", "143", "144", "145", "146", "147",
- "148", "149", "150", "151", "152", "153", "154", "155", "156", "157", "158", "159",
- "160", "161", "162", "163", "164", "165", "166", "167", "168", "169", "170", "171",
- "172", "173", "174", "175", "176", "177", "178", "179", "180", "181", "182", "183",
- "184", "185", "186", "187", "188", "189", "190", "191", "192", "193", "194", "195",
- "196", "197", "198", "199", "200", "201", "202", "203", "204", "205", "206", "207",
- "208", "209", "210", "211", "212", "213", "214", "215", "216", "217", "218", "219", "220", "221";
- };
-};
+/*
+ * Copyright (c) 2018 MediaTek Inc.
+ * Author: Wenzhen.Yu <Wenzhen.Yu@mediatek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+&clkitg {
+ bring-up {
+ compatible = "mediatek,clk-bring-up";
+ clocks =
+ <&apmixedsys CK_APMIXED_ARMPLL>,
+ <&apmixedsys CK_APMIXED_NET2PLL>,
+ <&apmixedsys CK_APMIXED_MMPLL>,
+ <&apmixedsys CK_APMIXED_SGMPLL>,
+ <&apmixedsys CK_APMIXED_WEDMCUPLL>,
+ <&apmixedsys CK_APMIXED_NET1PLL>,
+ <&apmixedsys CK_APMIXED_MPLL>,
+ <&apmixedsys CK_APMIXED_APLL2>,
+ <&infracfg CK_INFRA_CK_F26M>,
+ <&infracfg CK_INFRA_UART>,
+ <&infracfg CK_INFRA_ISPI0>,
+ <&infracfg CK_INFRA_I2C>,
+ <&infracfg CK_INFRA_ISPI1>,
+ <&infracfg CK_INFRA_PWM>,
+ <&infracfg CK_INFRA_66M_MCK>,
+ <&infracfg CK_INFRA_CK_F32K>,
+ <&infracfg CK_INFRA_PCIE_CK>,
+ <&infracfg CK_INFRA_PWM_BCK>,
+ <&infracfg CK_INFRA_PWM_CK1>,
+ <&infracfg CK_INFRA_PWM_CK2>,
+ <&infracfg CK_INFRA_133M_HCK>,
+ <&infracfg CK_INFRA_EIP_CK>,
+ <&infracfg CK_INFRA_66M_PHCK>,
+ <&infracfg CK_INFRA_FAUD_L_CK >,
+ <&infracfg CK_INFRA_FAUD_AUD_CK>,
+ <&infracfg CK_INFRA_FAUD_EG2_CK>,
+ <&infracfg CK_INFRA_I2CS_CK>,
+ <&infracfg CK_INFRA_MUX_UART0>,
+ <&infracfg CK_INFRA_MUX_UART1>,
+ <&infracfg CK_INFRA_MUX_UART2>,
+ <&infracfg CK_INFRA_NFI_CK>,
+ <&infracfg CK_INFRA_SPINFI_CK>,
+ <&infracfg CK_INFRA_MUX_SPI0>,
+ <&infracfg CK_INFRA_MUX_SPI1>,
+ <&infracfg CK_INFRA_RTC_32K>,
+ <&infracfg CK_INFRA_FMSDC_CK>,
+ <&infracfg CK_INFRA_FMSDC_HCK_CK>,
+ <&infracfg CK_INFRA_PERI_133M>,
+ <&infracfg CK_INFRA_133M_PHCK>,
+ <&infracfg CK_INFRA_USB_SYS_CK>,
+ <&infracfg CK_INFRA_USB_CK>,
+ <&infracfg CK_INFRA_USB_XHCI_CK>,
+ <&infracfg CK_INFRA_PCIE_GFMUX_TL_O_PRE>,
+ <&infracfg CK_INFRA_F26M_CK0>,
+ <&infracfg_ao CK_INFRA_UART0_SEL>,
+ <&infracfg_ao CK_INFRA_UART1_SEL>,
+ <&infracfg_ao CK_INFRA_UART2_SEL>,
+ <&infracfg_ao CK_INFRA_SPI0_SEL>,
+ <&infracfg_ao CK_INFRA_SPI1_SEL>,
+ <&infracfg_ao CK_INFRA_PWM1_SEL>,
+ <&infracfg_ao CK_INFRA_PWM2_SEL>,
+ <&infracfg_ao CK_INFRA_PWM_BSEL>,
+ <&infracfg_ao CK_INFRA_PCIE_SEL>,
+ <&infracfg_ao CK_INFRA_GPT_STA>,
+ <&infracfg_ao CK_INFRA_PWM_HCK>,
+ <&infracfg_ao CK_INFRA_PWM_STA>,
+ <&infracfg_ao CK_INFRA_PWM1_CK>,
+ <&infracfg_ao CK_INFRA_PWM2_CK>,
+ <&infracfg_ao CK_INFRA_CQ_DMA_CK>,
+ <&infracfg_ao CK_INFRA_EIP97_CK>,
+ <&infracfg_ao CK_INFRA_AUD_BUS_CK>,
+ <&infracfg_ao CK_INFRA_AUD_26M_CK>,
+ <&infracfg_ao CK_INFRA_AUD_L_CK>,
+ <&infracfg_ao CK_INFRA_AUD_AUD_CK>,
+ <&infracfg_ao CK_INFRA_AUD_EG2_CK>,
+ <&infracfg_ao CK_INFRA_DRAMC_26M_CK>,
+ <&infracfg_ao CK_INFRA_DBG_CK>,
+ <&infracfg_ao CK_INFRA_AP_DMA_CK>,
+ <&infracfg_ao CK_INFRA_SEJ_CK>,
+ <&infracfg_ao CK_INFRA_SEJ_13M_CK>,
+ <&infracfg_ao CK_INFRA_THERM_CK>,
+ <&infracfg_ao CK_INFRA_I2CO_CK>,
+ <&infracfg_ao CK_INFRA_UART0_CK>,
+ <&infracfg_ao CK_INFRA_UART1_CK>,
+ <&infracfg_ao CK_INFRA_UART2_CK>,
+ <&infracfg_ao CK_INFRA_NFI1_CK>,
+ <&infracfg_ao CK_INFRA_SPINFI1_CK>,
+ <&infracfg_ao CK_INFRA_NFI_HCK_CK>,
+ <&infracfg_ao CK_INFRA_SPI0_CK>,
+ <&infracfg_ao CK_INFRA_SPI1_CK>,
+ <&infracfg_ao CK_INFRA_SPI0_HCK_CK>,
+ <&infracfg_ao CK_INFRA_SPI1_HCK_CK>,
+ <&infracfg_ao CK_INFRA_FRTC_CK>,
+ <&infracfg_ao CK_INFRA_MSDC_CK>,
+ <&infracfg_ao CK_INFRA_MSDC_HCK_CK>,
+ <&infracfg_ao CK_INFRA_MSDC_133M_CK>,
+ <&infracfg_ao CK_INFRA_MSDC_66M_CK>,
+ <&infracfg_ao CK_INFRA_ADC_26M_CK>,
+ <&infracfg_ao CK_INFRA_ADC_FRC_CK>,
+ <&infracfg_ao CK_INFRA_FBIST2FPC_CK>,
+ <&infracfg_ao CK_INFRA_IUSB_133_CK>,
+ <&infracfg_ao CK_INFRA_IUSB_66M_CK>,
+ <&infracfg_ao CK_INFRA_IUSB_SYS_CK>,
+ <&infracfg_ao CK_INFRA_IUSB_CK>,
+ <&infracfg_ao CK_INFRA_IPCIE_CK>,
+ <&infracfg_ao CK_INFRA_IPCIER_CK>,
+ <&infracfg_ao CK_INFRA_IPCIEB_CK>,
+ <&infracfg_ao CK_INFRA_TRNG_CK>,
+ <&topckgen CK_TOP_CB_M_416M>,
+ <&topckgen CK_TOP_CB_M_D2>,
+ <&topckgen CK_TOP_CB_M_D4>,
+ <&topckgen CK_TOP_CB_M_D8>,
+ <&topckgen CK_TOP_M_D8_D2>,
+ <&topckgen CK_TOP_M_D3_D2>,
+ <&topckgen CK_TOP_CB_MM_D2>,
+ <&topckgen CK_TOP_CB_MM_D4>,
+ <&topckgen CK_TOP_CB_MM_D8>,
+ <&topckgen CK_TOP_MM_D8_D2>,
+ <&topckgen CK_TOP_MM_D3_D8>,
+ <&topckgen CK_TOP_CB_U2_PHYD_CK>,
+ <&topckgen CK_TOP_CB_APLL2_196M>,
+ <&topckgen CK_TOP_APLL2_D4>,
+ <&topckgen CK_TOP_CB_NET1_D4>,
+ <&topckgen CK_TOP_CB_NET1_D5>,
+ <&topckgen CK_TOP_NET1_D5_D2>,
+ <&topckgen CK_TOP_NET1_D5_D4>,
+ <&topckgen CK_TOP_NET1_D8_D2>,
+ <&topckgen CK_TOP_NET1_D8_D4>,
+ <&topckgen CK_TOP_CB_NET2_800M>,
+ <&topckgen CK_TOP_CB_NET2_D4>,
+ <&topckgen CK_TOP_NET2_D4_D2>,
+ <&topckgen CK_TOP_NET2_D3_D2>,
+ <&topckgen CK_TOP_CB_WEDMCU_760M>,
+ <&topckgen CK_TOP_WEDMCU_D5_D2 >,
+ <&topckgen CK_TOP_CB_SGM_325M>,
+ <&topckgen CK_TOP_CB_CKSQ_40M_D2>,
+ <&topckgen CK_TOP_CB_RTC_32K>,
+ <&topckgen CK_TOP_CB_RTC_32P7K>,
+ <&topckgen CK_TOP_NFI1X>,
+ <&topckgen CK_TOP_USB_EQ_RX250M>,
+ <&topckgen CK_TOP_USB_TX250M>,
+ <&topckgen CK_TOP_USB_LN0_CK>,
+ <&topckgen CK_TOP_USB_CDR_CK>,
+ <&topckgen CK_TOP_SPINFI_BCK>,
+ <&topckgen CK_TOP_I2C_BCK>,
+ <&topckgen CK_TOP_PEXTP_TL>,
+ <&topckgen CK_TOP_EMMC_250M>,
+ <&topckgen CK_TOP_EMMC_416M>,
+ <&topckgen CK_TOP_F_26M_ADC_CK>,
+ <&topckgen CK_TOP_SYSAXI>,
+ <&topckgen CK_TOP_NETSYS_WED_MCU>,
+ <&topckgen CK_TOP_NETSYS_2X>,
+ <&topckgen CK_TOP_SGM_325M>,
+ <&topckgen CK_TOP_A1SYS>,
+ <&topckgen CK_TOP_EIP_B>,
+ <&topckgen CK_TOP_F26M>,
+ <&topckgen CK_TOP_AUD_L>,
+ <&topckgen CK_TOP_A_TUNER>,
+ <&topckgen CK_TOP_U2U3_REF>,
+ <&topckgen CK_TOP_U2U3_SYS>,
+ <&topckgen CK_TOP_U2U3_XHCI>,
+ <&topckgen CK_TOP_AP2CNN_HOST>,
+ <&topckgen CK_TOP_NFI1X_SEL>,
+ <&topckgen CK_TOP_SPINFI_SEL>,
+ <&topckgen CK_TOP_SPI_SEL>,
+ <&topckgen CK_TOP_SPIM_MST_SEL>,
+ <&topckgen CK_TOP_UART_SEL>,
+ <&topckgen CK_TOP_PWM_SEL>,
+ <&topckgen CK_TOP_I2C_SEL>,
+ <&topckgen CK_TOP_PEXTP_TL_SEL>,
+ <&topckgen CK_TOP_EMMC_250M_SEL >,
+ <&topckgen CK_TOP_EMMC_416M_SEL >,
+ <&topckgen CK_TOP_F_26M_ADC_SEL>,
+ <&topckgen CK_TOP_DRAMC_SEL>,
+ <&topckgen CK_TOP_DRAMC_MD32_SEL>,
+ <&topckgen CK_TOP_SYSAXI_SEL>,
+ <&topckgen CK_TOP_SYSAPB_SEL>,
+ <&topckgen CK_TOP_ARM_DB_MAIN_SEL>,
+ <&topckgen CK_TOP_ARM_DB_JTSEL>,
+ <&topckgen CK_TOP_NETSYS_SEL>,
+ <&topckgen CK_TOP_NETSYS_500M_SEL>,
+ <&topckgen CK_TOP_NETSYS_MCU_SEL>,
+ <&topckgen CK_TOP_NETSYS_2X_SEL>,
+ <&topckgen CK_TOP_SGM_325M_SEL>,
+ <&topckgen CK_TOP_SGM_REG_SEL>,
+ <&topckgen CK_TOP_A1SYS_SEL>,
+ <&topckgen CK_TOP_CONN_MCUSYS_SEL>,
+ <&topckgen CK_TOP_EIP_B_SEL>,
+ <&topckgen CK_TOP_PCIE_PHY_SEL>,
+ <&topckgen CK_TOP_USB3_PHY_SEL>,
+ <&topckgen CK_TOP_F26M_SEL>,
+ <&topckgen CK_TOP_AUD_L_SEL>,
+ <&topckgen CK_TOP_A_TUNER_SEL>,
+ <&topckgen CK_TOP_U2U3_SEL>,
+ <&topckgen CK_TOP_U2U3_SYS_SEL>,
+ <&topckgen CK_TOP_U2U3_XHCI_SEL>,
+ <&topckgen CK_TOP_DA_U2_REFSEL>,
+ <&topckgen CK_TOP_DA_U2_CK_1P_SEL>,
+ <&topckgen CK_TOP_AP2CNN_HOST_SEL>,
+ <&clk40m>,
+ <&clk40m>,
+ <&clk40m>,
+ <&clk40m>,
+ <&clk40m>,
+ <&clk40m>,
+ <&clk40m>,
+ <&clk40m>,
+ <&clk40m>,
+ <&clk40m>,
+ <&clk40m>,
+ <&clk40m>,
+ <&clk40m>;
+
+
+ clock-names = "0", "1", "2", "3", "4", "5", "6", "7", "8", "9", "10", "11",
+ "12", "13", "14", "15", "16", "17", "18", "19", "20", "21", "22", "23",
+ "24", "25", "26", "27", "28", "29", "30", "31", "32", "33", "34", "35",
+ "36", "37", "38", "39", "40", "41", "42", "43", "44", "45", "46", "47",
+ "48", "49", "50", "51", "52", "53", "54", "55", "56", "57", "58", "59",
+ "60", "61", "62", "63", "64", "65", "66", "67", "68", "69", "70", "71",
+ "72", "73", "74", "75", "76", "77", "78", "79", "80", "81", "82", "83",
+ "84", "85", "86", "87", "88", "89", "90", "91", "92", "93", "94", "95",
+ "96", "97", "98", "99", "100", "101", "102", "103", "104", "105", "106", "107",
+ "108", "109", "110", "111", "112", "113", "114", "115", "116", "117",
+ "118", "119", "120", "121", "122", "123",
+ "124", "125", "126", "127", "128", "129", "130", "131", "132", "133", "134", "135",
+ "136", "137", "138", "139", "140", "141", "142", "143", "144", "145", "146", "147",
+ "148", "149", "150", "151", "152", "153", "154", "155", "156", "157", "158", "159",
+ "160", "161", "162", "163", "164", "165", "166", "167", "168", "169", "170", "171",
+ "172", "173", "174", "175", "176", "177", "178", "179", "180", "181", "182", "183",
+ "184", "185", "186", "187", "188", "189", "190", "191", "192", "193", "194", "195",
+ "196", "197", "198", "199", "200", "201", "202", "203", "204", "205", "206", "207",
+ "208", "209", "210", "211", "212", "213", "214", "215", "216", "217", "218", "219", "220", "221";
+ };
+};
diff --git a/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986a.dtsi b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
index e957f5c..7801a8e 100644
--- a/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
+++ b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
@@ -389,14 +389,14 @@
<ðsys CK_ETH_GP1_EN>,
<ðsys CK_ETH_WOCPU1_EN>,
<ðsys CK_ETH_WOCPU0_EN>,
- <ðsys CK_SGM0_TX_EN>,
- <ðsys CK_SGM0_RX_EN>,
- <ðsys CK_SGM0_CK0_EN>,
- <ðsys CK_SGM0_CDR_CK0_EN>,
- <ðsys CK_SGM1_TX_EN>,
- <ðsys CK_SGM1_RX_EN>,
- <ðsys CK_SGM1_CK1_EN>,
- <ðsys CK_SGM1_CDR_CK1_EN>;
+ <&sgmiisys0 CK_SGM0_TX_EN>,
+ <&sgmiisys0 CK_SGM0_RX_EN>,
+ <&sgmiisys0 CK_SGM0_CK0_EN>,
+ <&sgmiisys0 CK_SGM0_CDR_CK0_EN>,
+ <&sgmiisys1 CK_SGM1_TX_EN>,
+ <&sgmiisys1 CK_SGM1_RX_EN>,
+ <&sgmiisys1 CK_SGM1_CK1_EN>,
+ <&sgmiisys1 CK_SGM1_CDR_CK1_EN>;
clock-names = "fe", "gp2", "gp1", "wocpu1", "wocpu0",
"sgmii_tx250m", "sgmii_rx250m",
"sgmii_cdr_ref", "sgmii_cdr_fb",
diff --git a/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986b.dtsi b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986b.dtsi
index a795e83..adc55b8 100644
--- a/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986b.dtsi
+++ b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986b.dtsi
@@ -357,14 +357,14 @@
<ðsys CK_ETH_GP1_EN>,
<ðsys CK_ETH_WOCPU1_EN>,
<ðsys CK_ETH_WOCPU0_EN>,
- <ðsys CK_SGM0_TX_EN>,
- <ðsys CK_SGM0_RX_EN>,
- <ðsys CK_SGM0_CK0_EN>,
- <ðsys CK_SGM0_CDR_CK0_EN>,
- <ðsys CK_SGM1_TX_EN>,
- <ðsys CK_SGM1_RX_EN>,
- <ðsys CK_SGM1_CK1_EN>,
- <ðsys CK_SGM1_CDR_CK1_EN>;
+ <&sgmiisys0 CK_SGM0_TX_EN>,
+ <&sgmiisys0 CK_SGM0_RX_EN>,
+ <&sgmiisys0 CK_SGM0_CK0_EN>,
+ <&sgmiisys0 CK_SGM0_CDR_CK0_EN>,
+ <&sgmiisys1 CK_SGM1_TX_EN>,
+ <&sgmiisys1 CK_SGM1_RX_EN>,
+ <&sgmiisys1 CK_SGM1_CK1_EN>,
+ <&sgmiisys1 CK_SGM1_CDR_CK1_EN>;
clock-names = "fe", "gp2", "gp1", "wocpu1", "wocpu0",
"sgmii_tx250m", "sgmii_rx250m",
"sgmii_cdr_ref", "sgmii_cdr_fb",