blob: b6a4255fc8c15738aca23c0c96f81a43d0e7a423 [file] [log] [blame]
From f392188951839efae7807b6287a62c78d1ed0088 Mon Sep 17 00:00:00 2001
From: Sam Shih <sam.shih@mediatek.com>
Date: Fri, 2 Jun 2023 13:06:17 +0800
Subject: [PATCH]
[spi-and-storage][999-2340-drivers-mtd-spi-nor-Add-calibration-support-for-spi-nor.patch]
---
drivers/mtd/spi-nor/spi-nor.c | 40 +++++++++++++++++++++++++++++++++++
1 file changed, 40 insertions(+)
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index 8d2bc03cd..198b57a92 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -4899,6 +4899,35 @@ static void spi_nor_debugfs_init(struct spi_nor *nor,
info->id_len, info->id);
}
+static int spi_nor_cal_read(void *priv, u32 *addr, int addrlen, u8 *buf, int readlen)
+{
+ int ret;
+ struct spi_nor *nor = (struct spi_nor *)priv;
+
+ nor->reg_proto = SNOR_PROTO_1_1_1;
+ nor->read_proto = SNOR_PROTO_1_1_1;
+ nor->read_opcode = SPINOR_OP_READ;
+ nor->addr_width = 3;
+ nor->read_dummy = 0;
+
+ return spi_nor_read_raw(nor, *addr, readlen, buf);
+}
+
+static int spi_nor_cal_read_4B(void *priv, u32 *addr, int addrlen, u8 *buf,
+ int readlen)
+{
+ int ret;
+ struct spi_nor *nor = (struct spi_nor *)priv;
+
+ nor->reg_proto = SNOR_PROTO_1_1_1;
+ nor->read_proto = SNOR_PROTO_1_1_1;
+ nor->read_opcode = SPINOR_OP_READ_4B;
+ nor->addr_width = 4;
+ nor->read_dummy = 0;
+
+ return spi_nor_read_raw(nor, *addr, readlen, buf);
+}
+
static const struct flash_info *spi_nor_get_flash_info(struct spi_nor *nor,
const char *name)
{
@@ -4973,6 +5002,17 @@ int spi_nor_scan(struct spi_nor *nor, const char *name,
if (!nor->bouncebuf)
return -ENOMEM;
+ if(nor->spimem) {
+ ret = spi_mem_do_calibration(nor->spimem,
+ spi_nor_cal_read, nor);
+ if (ret) {
+ ret = spi_mem_do_calibration(nor->spimem,
+ spi_nor_cal_read_4B, nor);
+ if (ret)
+ return ret;
+ }
+ }
+
info = spi_nor_get_flash_info(nor, name);
if (IS_ERR(info))
return PTR_ERR(info);
--
2.34.1