[][kernel][common][eth][Add AMDA TX/RX ring index to the dbg_regs command]
[Description]
Add AMDA TX/RX ring index to the dbg_regs command.
Without this patch, users are unable to retrieve the values of
all ADMA CPU/DMA TX/RX indexes using the dbg_regs command.
[Release-log]
N/A
Change-Id: I4c3b1f1e6ce0faedc936ae52a0348d57522c4667
Reviewed-on: https://gerrit.mediatek.inc/c/openwrt/feeds/mtk_openwrt_feeds/+/8669288
diff --git a/21.02/files/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_dbg.c b/21.02/files/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_dbg.c
index 8af4c9a..f902989 100755
--- a/21.02/files/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_dbg.c
+++ b/21.02/files/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_dbg.c
@@ -1027,6 +1027,7 @@
int dbg_regs_read(struct seq_file *seq, void *v)
{
struct mtk_eth *eth = g_eth;
+ u32 i;
seq_puts(seq, " <<DEBUG REG DUMP>>\n");
@@ -1085,16 +1086,43 @@
mtk_r32(eth, MTK_PRX_CRX_IDX0));
seq_printf(seq, "| PDMA_DRX_IDX : %08x |\n",
mtk_r32(eth, MTK_PRX_DRX_IDX0));
- seq_printf(seq, "| QDMA_CTX_IDX : %08x |\n",
- mtk_r32(eth, MTK_QTX_CTX_PTR));
- seq_printf(seq, "| QDMA_DTX_IDX : %08x |\n",
- mtk_r32(eth, MTK_QTX_DTX_PTR));
- seq_printf(seq, "| QDMA_FQ_CNT : %08x |\n",
- mtk_r32(eth, MTK_QDMA_FQ_CNT));
- seq_printf(seq, "| QDMA_FWD_CNT : %08x |\n",
- mtk_r32(eth, MTK_QDMA_FWD_CNT));
- seq_printf(seq, "| QDMA_FSM : %08x |\n",
- mtk_r32(eth, MTK_QDMA_FSM));
+ if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSS)) {
+ for (i = 1; i < eth->soc->rss_num; i++) {
+ seq_printf(seq, "| PDMA_CRX_IDX%d : %08x |\n",
+ i, mtk_r32(eth, MTK_PRX_CRX_IDX_CFG(i)));
+ seq_printf(seq, "| PDMA_DRX_IDX%d : %08x |\n",
+ i, mtk_r32(eth, MTK_PRX_DRX_IDX_CFG(i)));
+ }
+ }
+ if (MTK_HAS_CAPS(eth->soc->caps, MTK_HWLRO)) {
+ for (i = 0; i < MTK_HW_LRO_RING_NUM; i++) {
+ seq_printf(seq, "| PDMA_CRX_IDX%d : %08x |\n",
+ MTK_HW_LRO_RING(i),
+ mtk_r32(eth, MTK_PRX_CRX_IDX_CFG(MTK_HW_LRO_RING(i))));
+ seq_printf(seq, "| PDMA_DRX_IDX%d : %08x |\n",
+ MTK_HW_LRO_RING(i),
+ mtk_r32(eth, MTK_PRX_DRX_IDX_CFG(MTK_HW_LRO_RING(i))));
+ }
+ }
+
+ if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) {
+ seq_printf(seq, "| QDMA_CTX_IDX : %08x |\n",
+ mtk_r32(eth, MTK_QTX_CTX_PTR));
+ seq_printf(seq, "| QDMA_DTX_IDX : %08x |\n",
+ mtk_r32(eth, MTK_QTX_DTX_PTR));
+ seq_printf(seq, "| QDMA_FQ_CNT : %08x |\n",
+ mtk_r32(eth, MTK_QDMA_FQ_CNT));
+ seq_printf(seq, "| QDMA_FWD_CNT : %08x |\n",
+ mtk_r32(eth, MTK_QDMA_FWD_CNT));
+ seq_printf(seq, "| QDMA_FSM : %08x |\n",
+ mtk_r32(eth, MTK_QDMA_FSM));
+ } else {
+ seq_printf(seq, "| PDMA_CTX_IDX : %08x |\n",
+ mtk_r32(eth, MTK_PTX_CTX_IDX0));
+ seq_printf(seq, "| PDMA_DTX_IDX : %08x |\n",
+ mtk_r32(eth, MTK_PTX_DTX_IDX0));
+ }
+
seq_printf(seq, "| FE_PSE_FREE : %08x |\n",
mtk_r32(eth, MTK_FE_PSE_FREE));
seq_printf(seq, "| FE_DROP_FQ : %08x |\n",
diff --git a/21.02/files/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/21.02/files/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.h
index 08fe13b..c32a0ee 100644
--- a/21.02/files/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+++ b/21.02/files/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.h
@@ -203,6 +203,12 @@
#define WDMA_BASE(x) (0x2800 + ((x) * 0x400))
#define PPE_BASE(x) (0xE00 + ((x) * 0x400))
#endif
+/* PDMA TX CPU Pointer Register */
+#define MTK_PTX_CTX_IDX0 (PDMA_BASE + 0x08)
+
+/* PDMA TX DMA Pointer Register */
+#define MTK_PTX_DTX_IDX0 (PDMA_BASE + 0x0c)
+
/* PDMA RX Base Pointer Register */
#define MTK_PRX_BASE_PTR0 (PDMA_BASE + 0x100)
#define MTK_PRX_BASE_PTR_CFG(x) (MTK_PRX_BASE_PTR0 + (x * 0x10))