[][openwrt][update the patches in accordance with the new naming rules]
[Description]
Change all mtk patches in accordance with the new naming rules
"999-20xx-" : Basic Part
"999-21xx-" : Slow Speed I/O
"999-22xx-" : Slow Speed I/O
"999-23xx-" : SPI & Storage
"999-24xx-" : SPI & Storage
"999-25xx-" : Advanced features
"999-26xx-" : High Speed I/O
"999-27xx-" : Networking
"999-28xx-" : MISC
"999-29xx-" : Uncategorized
[Release-log]
N/A
Change-Id: I245da3b0e5b7299b42473c20cc6f0899cffc1ad2
Reviewed-on: https://gerrit.mediatek.inc/c/openwrt/feeds/mtk_openwrt_feeds/+/7530987
diff --git a/target/linux/generic/backport-5.4/999-2327-mtd-spinand-toshiba-Support-for-new-Kioxia-Serial-NAND.patch b/target/linux/generic/backport-5.4/999-2327-mtd-spinand-toshiba-Support-for-new-Kioxia-Serial-NAND.patch
new file mode 100644
index 0000000..12a55cb
--- /dev/null
+++ b/target/linux/generic/backport-5.4/999-2327-mtd-spinand-toshiba-Support-for-new-Kioxia-Serial-NAND.patch
@@ -0,0 +1,201 @@
+From 1d16ff587875717c950c983af8eaa474d0a855ca Mon Sep 17 00:00:00 2001
+From: Sam Shih <sam.shih@mediatek.com>
+Date: Fri, 2 Jun 2023 13:06:13 +0800
+Subject: [PATCH]
+ [spi-and-storage][999-2327-mtd-spinand-toshiba-Support-for-new-Kioxia-Serial-NAND.patch]
+
+---
+ drivers/mtd/nand/spi/toshiba.c | 128 ++++++++++++++++++++++++++++-----
+ 1 file changed, 111 insertions(+), 17 deletions(-)
+
+diff --git a/drivers/mtd/nand/spi/toshiba.c b/drivers/mtd/nand/spi/toshiba.c
+index 7ce5997dd..be51a2eaf 100644
+--- a/drivers/mtd/nand/spi/toshiba.c
++++ b/drivers/mtd/nand/spi/toshiba.c
+@@ -19,6 +19,18 @@ static SPINAND_OP_VARIANTS(read_cache_variants,
+ SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
+
++static SPINAND_OP_VARIANTS(write_cache_x4_variants,
++ SPINAND_PROG_LOAD_X4(true, 0, NULL, 0),
++ SPINAND_PROG_LOAD(true, 0, NULL, 0));
++
++static SPINAND_OP_VARIANTS(update_cache_x4_variants,
++ SPINAND_PROG_LOAD_X4(false, 0, NULL, 0),
++ SPINAND_PROG_LOAD(false, 0, NULL, 0));
++
++/**
++ * Backward compatibility for 1st generation Serial NAND devices
++ * which don't support Quad Program Load operation.
++ */
+ static SPINAND_OP_VARIANTS(write_cache_variants,
+ SPINAND_PROG_LOAD(true, 0, NULL, 0));
+
+@@ -94,7 +106,7 @@ static int tx58cxgxsxraix_ecc_get_status(struct spinand_device *spinand,
+ }
+
+ static const struct spinand_info toshiba_spinand_table[] = {
+- /* 3.3V 1Gb */
++ /* 3.3V 1Gb (1st generation) */
+ SPINAND_INFO("TC58CVG0S3HRAIG",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xC2),
+ NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
+@@ -105,7 +117,7 @@ static const struct spinand_info toshiba_spinand_table[] = {
+ 0,
+ SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
+ tx58cxgxsxraix_ecc_get_status)),
+- /* 3.3V 2Gb */
++ /* 3.3V 2Gb (1st generation) */
+ SPINAND_INFO("TC58CVG1S3HRAIG",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xCB),
+ NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
+@@ -116,7 +128,7 @@ static const struct spinand_info toshiba_spinand_table[] = {
+ 0,
+ SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
+ tx58cxgxsxraix_ecc_get_status)),
+- /* 3.3V 4Gb */
++ /* 3.3V 4Gb (1st generation) */
+ SPINAND_INFO("TC58CVG2S0HRAIG",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xCD),
+ NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1),
+@@ -127,18 +139,7 @@ static const struct spinand_info toshiba_spinand_table[] = {
+ 0,
+ SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
+ tx58cxgxsxraix_ecc_get_status)),
+- /* 3.3V 4Gb */
+- SPINAND_INFO("TC58CVG2S0HRAIJ",
+- SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xED),
+- NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1),
+- NAND_ECCREQ(8, 512),
+- SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+- &write_cache_variants,
+- &update_cache_variants),
+- 0,
+- SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
+- tx58cxgxsxraix_ecc_get_status)),
+- /* 1.8V 1Gb */
++ /* 1.8V 1Gb (1st generation) */
+ SPINAND_INFO("TC58CYG0S3HRAIG",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xB2),
+ NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
+@@ -149,7 +150,7 @@ static const struct spinand_info toshiba_spinand_table[] = {
+ 0,
+ SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
+ tx58cxgxsxraix_ecc_get_status)),
+- /* 1.8V 2Gb */
++ /* 1.8V 2Gb (1st generation) */
+ SPINAND_INFO("TC58CYG1S3HRAIG",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xBB),
+ NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
+@@ -160,7 +161,7 @@ static const struct spinand_info toshiba_spinand_table[] = {
+ 0,
+ SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
+ tx58cxgxsxraix_ecc_get_status)),
+- /* 1.8V 4Gb */
++ /* 1.8V 4Gb (1st generation) */
+ SPINAND_INFO("TC58CYG2S0HRAIG",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xBD),
+ NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1),
+@@ -171,6 +172,99 @@ static const struct spinand_info toshiba_spinand_table[] = {
+ 0,
+ SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
+ tx58cxgxsxraix_ecc_get_status)),
++
++ /*
++ * 2nd generation serial nand has HOLD_D which is equivalent to
++ * QE_BIT.
++ */
++ /* 3.3V 1Gb (2nd generation) */
++ SPINAND_INFO("TC58CVG0S3HRAIJ",
++ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xE2),
++ NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
++ NAND_ECCREQ(8, 512),
++ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
++ &write_cache_x4_variants,
++ &update_cache_x4_variants),
++ SPINAND_HAS_QE_BIT,
++ SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
++ tx58cxgxsxraix_ecc_get_status)),
++ /* 3.3V 2Gb (2nd generation) */
++ SPINAND_INFO("TC58CVG1S3HRAIJ",
++ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xEB),
++ NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
++ NAND_ECCREQ(8, 512),
++ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
++ &write_cache_x4_variants,
++ &update_cache_x4_variants),
++ SPINAND_HAS_QE_BIT,
++ SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
++ tx58cxgxsxraix_ecc_get_status)),
++ /* 3.3V 4Gb (2nd generation) */
++ SPINAND_INFO("TC58CVG2S0HRAIJ",
++ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xED),
++ NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1),
++ NAND_ECCREQ(8, 512),
++ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
++ &write_cache_x4_variants,
++ &update_cache_x4_variants),
++ SPINAND_HAS_QE_BIT,
++ SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
++ tx58cxgxsxraix_ecc_get_status)),
++ /* 3.3V 8Gb (2nd generation) */
++ SPINAND_INFO("TH58CVG3S0HRAIJ",
++ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xE4),
++ NAND_MEMORG(1, 4096, 256, 64, 4096, 80, 1, 1, 1),
++ NAND_ECCREQ(8, 512),
++ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
++ &write_cache_x4_variants,
++ &update_cache_x4_variants),
++ SPINAND_HAS_QE_BIT,
++ SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
++ tx58cxgxsxraix_ecc_get_status)),
++ /* 1.8V 1Gb (2nd generation) */
++ SPINAND_INFO("TC58CYG0S3HRAIJ",
++ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xD2),
++ NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
++ NAND_ECCREQ(8, 512),
++ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
++ &write_cache_x4_variants,
++ &update_cache_x4_variants),
++ SPINAND_HAS_QE_BIT,
++ SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
++ tx58cxgxsxraix_ecc_get_status)),
++ /* 1.8V 2Gb (2nd generation) */
++ SPINAND_INFO("TC58CYG1S3HRAIJ",
++ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xDB),
++ NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
++ NAND_ECCREQ(8, 512),
++ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
++ &write_cache_x4_variants,
++ &update_cache_x4_variants),
++ SPINAND_HAS_QE_BIT,
++ SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
++ tx58cxgxsxraix_ecc_get_status)),
++ /* 1.8V 4Gb (2nd generation) */
++ SPINAND_INFO("TC58CYG2S0HRAIJ",
++ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xDD),
++ NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1),
++ NAND_ECCREQ(8, 512),
++ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
++ &write_cache_x4_variants,
++ &update_cache_x4_variants),
++ SPINAND_HAS_QE_BIT,
++ SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
++ tx58cxgxsxraix_ecc_get_status)),
++ /* 1.8V 8Gb (2nd generation) */
++ SPINAND_INFO("TH58CYG3S0HRAIJ",
++ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xD4),
++ NAND_MEMORG(1, 4096, 256, 64, 4096, 80, 1, 1, 1),
++ NAND_ECCREQ(8, 512),
++ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
++ &write_cache_x4_variants,
++ &update_cache_x4_variants),
++ SPINAND_HAS_QE_BIT,
++ SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
++ tx58cxgxsxraix_ecc_get_status)),
+ };
+
+ static const struct spinand_manufacturer_ops toshiba_spinand_manuf_ops = {
+--
+2.34.1
+