[][mt7981/mt7988][eth][phy: mediatek-ge: Fix conflict default settings]
[Description]
Fix conflict default settings:
1. VgaDecRate is 1 at default on Jaguar. We don't set it again.
2. Move TR_OPEN_LOOP_EN=1, lpf_x_average = 9 to common part.
3. InhibitDisableDfeTail1000 is clear at EEE function, set it back.
[Release-log]
N/A
Change-Id: I2e46cd9fa996b91378a47d0c3d685ca767ac11a5
Reviewed-on: https://gerrit.mediatek.inc/c/openwrt/feeds/mtk_openwrt_feeds/+/7329924
diff --git a/target/linux/mediatek/files-5.4/drivers/net/phy/mediatek-ge.c b/target/linux/mediatek/files-5.4/drivers/net/phy/mediatek-ge.c
index fd0bc8e..2140945 100644
--- a/target/linux/mediatek/files-5.4/drivers/net/phy/mediatek-ge.c
+++ b/target/linux/mediatek/files-5.4/drivers/net/phy/mediatek-ge.c
@@ -837,11 +837,6 @@
__phy_write(phydev, 0x12, 0x0);
__phy_write(phydev, 0x10, 0x83aa);
- /* InhibitDisableDfeTail1000 = 1 */
- __phy_write(phydev, 0x11, 0x2b);
- __phy_write(phydev, 0x12, 0x0);
- __phy_write(phydev, 0x10, 0x8f80);
-
/* SSTrKp1000Slv = 5 */
__phy_write(phydev, 0x11, 0xbaef);
__phy_write(phydev, 0x12, 0x2e);
@@ -860,6 +855,11 @@
__phy_write(phydev, 0x10, 0x8ec0);
phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
+ /* TR_OPEN_LOOP_EN = 1, lpf_x_average = 9*/
+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG234,
+ MTK_PHY_TR_OPEN_LOOP_EN_MASK | MTK_PHY_LPF_X_AVERAGE_MASK,
+ BIT(0) | FIELD_PREP(MTK_PHY_LPF_X_AVERAGE_MASK, 0x9));
+
/* rg_tr_lpf_cnt_val = 512 */
phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LPF_CNT_VAL, 0x200);
@@ -947,10 +947,6 @@
__phy_write(phydev, 0x10, 0x9680);
phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
- /* TR_OPEN_LOOP_EN = 1, lpf_x_average = 9*/
- phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG234,
- MTK_PHY_TR_OPEN_LOOP_EN_MASK | MTK_PHY_LPF_X_AVERAGE_MASK,
- BIT(0) | FIELD_PREP(MTK_PHY_LPF_X_AVERAGE_MASK, 0x9));
}
static inline void mt7988_phy_finetune(struct phy_device *phydev)
@@ -981,6 +977,9 @@
__phy_write(phydev, 0x11, 0x500);
__phy_write(phydev, 0x12, 0x0);
__phy_write(phydev, 0x10, 0x8fc0);
+
+ /* VgaDecRate is 1 at default on mt7988 */
+
phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_2A30);
@@ -988,11 +987,6 @@
__phy_modify(phydev, MTK_PHY_ANARG_RG, MTK_PHY_TCLKOFFSET_MASK,
FIELD_PREP(MTK_PHY_TCLKOFFSET_MASK, 0x2));
phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
-
- /* TR_OPEN_LOOP_EN = 1, lpf_x_average = 9*/
- phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG234,
- MTK_PHY_TR_OPEN_LOOP_EN_MASK | MTK_PHY_LPF_X_AVERAGE_MASK,
- BIT(0) | FIELD_PREP(MTK_PHY_LPF_X_AVERAGE_MASK, 0x9));
}
static inline void mt798x_phy_eee(struct phy_device *phydev)
@@ -1094,7 +1088,8 @@
__phy_write(phydev, 0x10, 0x96ca);
/* DfeTailEnableVgaThresh1000 = 27 */
- __phy_write(phydev, 0x11, 0x36);
+ /* InhibitDisableDfeTail1000 = 1 */
+ __phy_write(phydev, 0x11, 0x37);
__phy_write(phydev, 0x12, 0x0);
__phy_write(phydev, 0x10, 0x8f80);
phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);