| /* |
| * Copyright (c) 2022 MediaTek Inc. |
| * Author: Xiufeng Li <Xiufeng.Li@mediatek.com> |
| * |
| * This program is free software; you can redistribute it and/or modify |
| * it under the terms of the GNU General Public License version 2 as |
| * published by the Free Software Foundation. |
| * |
| * This program is distributed in the hope that it will be useful, |
| * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| * GNU General Public License for more details. |
| */ |
| |
| #ifndef _DT_BINDINGS_CLK_MT7988_H |
| #define _DT_BINDINGS_CLK_MT7988_H |
| |
| /* INFRACFG */ |
| |
| #define CK_INFRA_CK_F26M 0 |
| #define CK_INFRA_PWM_O 1 |
| #define CK_INFRA_PCIE_OCC_P0 2 |
| #define CK_INFRA_PCIE_OCC_P1 3 |
| #define CK_INFRA_PCIE_OCC_P2 4 |
| #define CK_INFRA_PCIE_OCC_P3 5 |
| #define CK_INFRA_133M_HCK 6 |
| #define CK_INFRA_133M_PHCK 7 |
| #define CK_INFRA_66M_PHCK 8 |
| #define CK_INFRA_FAUD_L_O 9 |
| #define CK_INFRA_FAUD_AUD_O 10 |
| #define CK_INFRA_FAUD_EG2_O 11 |
| #define CK_INFRA_I2C_O 12 |
| #define CK_INFRA_UART_O0 13 |
| #define CK_INFRA_UART_O1 14 |
| #define CK_INFRA_UART_O2 15 |
| #define CK_INFRA_NFI_O 16 |
| #define CK_INFRA_SPINFI_O 17 |
| #define CK_INFRA_SPI0_O 18 |
| #define CK_INFRA_SPI1_O 19 |
| #define CK_INFRA_LB_MUX_FRTC 20 |
| #define CK_INFRA_FRTC 21 |
| #define CK_INFRA_FMSDC400_O 22 |
| #define CK_INFRA_FMSDC2_HCK_OCC 23 |
| #define CK_INFRA_PERI_133M 24 |
| #define CK_INFRA_USB_O 25 |
| #define CK_INFRA_USB_O_P1 26 |
| #define CK_INFRA_USB_FRMCNT_O 27 |
| #define CK_INFRA_USB_FRMCNT_O_P1 28 |
| #define CK_INFRA_USB_XHCI_O 29 |
| #define CK_INFRA_USB_XHCI_O_P1 30 |
| #define CK_INFRA_USB_PIPE_O 31 |
| #define CK_INFRA_USB_PIPE_O_P1 32 |
| #define CK_INFRA_USB_UTMI_O 33 |
| #define CK_INFRA_USB_UTMI_O_P1 34 |
| #define CK_INFRA_PCIE_PIPE_OCC_P0 35 |
| #define CK_INFRA_PCIE_PIPE_OCC_P1 36 |
| #define CK_INFRA_PCIE_PIPE_OCC_P2 37 |
| #define CK_INFRA_PCIE_PIPE_OCC_P3 38 |
| #define CK_INFRA_F26M_O0 39 |
| #define CK_INFRA_F26M_O1 40 |
| #define CK_INFRA_133M_MCK 41 |
| #define CK_INFRA_66M_MCK 42 |
| #define CK_INFRA_PERI_66M_O 43 |
| #define CK_INFRA_USB_SYS_O 44 |
| #define CK_INFRA_USB_SYS_O_P1 45 |
| #define CLK_INFRA_NR_CLK 46 |
| |
| |
| /* INFRACFG_AO */ |
| |
| #define CK_INFRA_MUX_UART0_SEL 0 |
| #define CK_INFRA_MUX_UART1_SEL 1 |
| #define CK_INFRA_MUX_UART2_SEL 2 |
| #define CK_INFRA_MUX_SPI0_SEL 3 |
| #define CK_INFRA_MUX_SPI1_SEL 4 |
| #define CK_INFRA_MUX_SPI2_SEL 5 |
| #define CK_INFRA_PWM_SEL 6 |
| #define CK_INFRA_PWM_CK1_SEL 7 |
| #define CK_INFRA_PWM_CK2_SEL 8 |
| #define CK_INFRA_PWM_CK3_SEL 9 |
| #define CK_INFRA_PWM_CK4_SEL 10 |
| #define CK_INFRA_PWM_CK5_SEL 11 |
| #define CK_INFRA_PWM_CK6_SEL 12 |
| #define CK_INFRA_PWM_CK7_SEL 13 |
| #define CK_INFRA_PWM_CK8_SEL 14 |
| #define CK_INFRA_PCIE_GFMUX_TL_O_P0_SEL 15 |
| #define CK_INFRA_PCIE_GFMUX_TL_O_P1_SEL 16 |
| #define CK_INFRA_PCIE_GFMUX_TL_O_P2_SEL 17 |
| #define CK_INFRA_PCIE_GFMUX_TL_O_P3_SEL 18 |
| #define CK_INFRA_66M_GPT_BCK 19 |
| #define CK_INFRA_66M_PWM_HCK 20 |
| #define CK_INFRA_66M_PWM_BCK 21 |
| #define CK_INFRA_66M_PWM_CK1 22 |
| #define CK_INFRA_66M_PWM_CK2 23 |
| #define CK_INFRA_66M_PWM_CK3 24 |
| #define CK_INFRA_66M_PWM_CK4 25 |
| #define CK_INFRA_66M_PWM_CK5 26 |
| #define CK_INFRA_66M_PWM_CK6 27 |
| #define CK_INFRA_66M_PWM_CK7 28 |
| #define CK_INFRA_66M_PWM_CK8 29 |
| #define CK_INFRA_133M_CQDMA_BCK 30 |
| #define CK_INFRA_66M_AUD_SLV_BCK 31 |
| #define CK_INFRA_AUD_26M 32 |
| #define CK_INFRA_AUD_L 33 |
| #define CK_INFRA_AUD_AUD 34 |
| #define CK_INFRA_AUD_EG2 35 |
| #define CK_INFRA_DRAMC_F26M 36 |
| #define CK_INFRA_133M_DBG_ACKM 37 |
| #define CK_INFRA_66M_AP_DMA_BCK 38 |
| #define CK_INFRA_66M_SEJ_BCK 39 |
| #define CK_INFRA_PRE_CK_SEJ_F13M 40 |
| #define CK_INFRA_66M_TRNG 41 |
| #define CK_INFRA_26M_THERM_SYSTEM 42 |
| #define CK_INFRA_I2C_BCK 43 |
| #define CK_INFRA_66M_UART0_PCK 44 |
| #define CK_INFRA_66M_UART1_PCK 45 |
| #define CK_INFRA_66M_UART2_PCK 46 |
| #define CK_INFRA_52M_UART0_CK 47 |
| #define CK_INFRA_52M_UART1_CK 48 |
| #define CK_INFRA_52M_UART2_CK 49 |
| #define CK_INFRA_NFI 50 |
| #define CK_INFRA_SPINFI 51 |
| #define CK_INFRA_66M_NFI_HCK 52 |
| #define CK_INFRA_104M_SPI0 53 |
| #define CK_INFRA_104M_SPI1 54 |
| #define CK_INFRA_104M_SPI2_BCK 55 |
| #define CK_INFRA_66M_SPI0_HCK 56 |
| #define CK_INFRA_66M_SPI1_HCK 57 |
| #define CK_INFRA_66M_SPI2_HCK 58 |
| #define CK_INFRA_66M_FLASHIF_AXI 59 |
| #define CK_INFRA_RTC 60 |
| #define CK_INFRA_26M_ADC_BCK 61 |
| #define CK_INFRA_RC_ADC 62 |
| #define CK_INFRA_MSDC400 63 |
| #define CK_INFRA_MSDC2_HCK 64 |
| #define CK_INFRA_133M_MSDC_0_HCK 65 |
| #define CK_INFRA_66M_MSDC_0_HCK 66 |
| #define CK_INFRA_133M_CPUM_BCK 67 |
| #define CK_INFRA_BIST2FPC 68 |
| #define CK_INFRA_I2C_X16W_MCK_CK_P1 69 |
| #define CK_INFRA_I2C_X16W_PCK_CK_P1 70 |
| #define CK_INFRA_133M_USB_HCK 71 |
| #define CK_INFRA_133M_USB_HCK_CK_P1 72 |
| #define CK_INFRA_66M_USB_HCK 73 |
| #define CK_INFRA_66M_USB_HCK_CK_P1 74 |
| #define CK_INFRA_USB_SYS 75 |
| #define CK_INFRA_USB_SYS_CK_P1 76 |
| #define CK_INFRA_USB_REF 77 |
| #define CK_INFRA_USB_CK_P1 78 |
| #define CK_INFRA_USB_FRMCNT 79 |
| #define CK_INFRA_USB_FRMCNT_CK_P1 80 |
| #define CK_INFRA_USB_PIPE 81 |
| #define CK_INFRA_USB_PIPE_CK_P1 82 |
| #define CK_INFRA_USB_UTMI 83 |
| #define CK_INFRA_USB_UTMI_CK_P1 84 |
| #define CK_INFRA_USB_XHCI 85 |
| #define CK_INFRA_USB_XHCI_CK_P1 86 |
| #define CK_INFRA_PCIE_GFMUX_TL_P0 87 |
| #define CK_INFRA_PCIE_GFMUX_TL_P1 88 |
| #define CK_INFRA_PCIE_GFMUX_TL_P2 89 |
| #define CK_INFRA_PCIE_GFMUX_TL_P3 90 |
| #define CK_INFRA_PCIE_PIPE_P0 91 |
| #define CK_INFRA_PCIE_PIPE_P1 92 |
| #define CK_INFRA_PCIE_PIPE_P2 93 |
| #define CK_INFRA_PCIE_PIPE_P3 94 |
| #define CK_INFRA_133M_PCIE_CK_P0 95 |
| #define CK_INFRA_133M_PCIE_CK_P1 96 |
| #define CK_INFRA_133M_PCIE_CK_P2 97 |
| #define CK_INFRA_133M_PCIE_CK_P3 98 |
| #define CK_INFRA_PCIE_PERI_26M_CK_P0 99 |
| #define CK_INFRA_PCIE_PERI_26M_CK_P1 100 |
| #define CK_INFRA_PCIE_PERI_26M_CK_P2 101 |
| #define CK_INFRA_PCIE_PERI_26M_CK_P3 102 |
| #define CLK_INFRA_AO_NR_CLK 103 |
| |
| /* TOPCKGEN */ |
| |
| #define CK_TOP_NETSYS_SEL 0 |
| #define CK_TOP_NETSYS_500M_SEL 1 |
| #define CK_TOP_NETSYS_2X_SEL 2 |
| #define CK_TOP_NETSYS_GSW_SEL 3 |
| #define CK_TOP_ETH_GMII_SEL 4 |
| #define CK_TOP_NETSYS_MCU_SEL 5 |
| #define CK_TOP_NETSYS_PAO_2X_SEL 6 |
| #define CK_TOP_EIP197_SEL 7 |
| #define CK_TOP_AXI_INFRA_SEL 8 |
| #define CK_TOP_UART_SEL 9 |
| #define CK_TOP_EMMC_250M_SEL 10 |
| #define CK_TOP_EMMC_400M_SEL 11 |
| #define CK_TOP_SPI_SEL 12 |
| #define CK_TOP_SPIM_MST_SEL 13 |
| #define CK_TOP_NFI1X_SEL 14 |
| #define CK_TOP_SPINFI_SEL 15 |
| #define CK_TOP_PWM_SEL 16 |
| #define CK_TOP_I2C_SEL 17 |
| #define CK_TOP_PCIE_MBIST_250M_SEL 18 |
| #define CK_TOP_PEXTP_TL_SEL 19 |
| #define CK_TOP_PEXTP_TL_P1_SEL 20 |
| #define CK_TOP_PEXTP_TL_P2_SEL 21 |
| #define CK_TOP_PEXTP_TL_P3_SEL 22 |
| #define CK_TOP_USB_SYS_SEL 23 |
| #define CK_TOP_USB_SYS_P1_SEL 24 |
| #define CK_TOP_USB_XHCI_SEL 25 |
| #define CK_TOP_USB_XHCI_P1_SEL 26 |
| #define CK_TOP_USB_FRMCNT_SEL 27 |
| #define CK_TOP_USB_FRMCNT_P1_SEL 28 |
| #define CK_TOP_AUD_SEL 29 |
| #define CK_TOP_A1SYS_SEL 30 |
| #define CK_TOP_AUD_L_SEL 31 |
| #define CK_TOP_A_TUNER_SEL 32 |
| #define CK_TOP_SSPXTP_SEL 33 |
| #define CK_TOP_USB_PHY_SEL 34 |
| #define CK_TOP_USXGMII_SBUS_0_SEL 35 |
| #define CK_TOP_USXGMII_SBUS_1_SEL 36 |
| #define CK_TOP_SGM_0_SEL 37 |
| #define CK_TOP_SGM_SBUS_0_SEL 38 |
| #define CK_TOP_SGM_1_SEL 39 |
| #define CK_TOP_SGM_SBUS_1_SEL 40 |
| #define CK_TOP_XFI_PHY_0_XTAL_SEL 41 |
| #define CK_TOP_XFI_PHY_1_XTAL_SEL 42 |
| #define CK_TOP_SYSAXI_SEL 43 |
| #define CK_TOP_SYSAPB_SEL 44 |
| #define CK_TOP_ETH_REFCK_50M_SEL 45 |
| #define CK_TOP_ETH_SYS_200M_SEL 46 |
| #define CK_TOP_ETH_SYS_SEL 47 |
| #define CK_TOP_ETH_XGMII_SEL 48 |
| #define CK_TOP_BUS_TOPS_SEL 49 |
| #define CK_TOP_NPU_TOPS_SEL 50 |
| #define CK_TOP_DRAMC_SEL 51 |
| #define CK_TOP_DRAMC_MD32_SEL 52 |
| #define CK_TOP_INFRA_F26M_SEL 53 |
| #define CK_TOP_PEXTP_P0_SEL 54 |
| #define CK_TOP_PEXTP_P1_SEL 55 |
| #define CK_TOP_PEXTP_P2_SEL 56 |
| #define CK_TOP_PEXTP_P3_SEL 57 |
| #define CK_TOP_DA_XTP_GLB_P0_SEL 58 |
| #define CK_TOP_DA_XTP_GLB_P1_SEL 59 |
| #define CK_TOP_DA_XTP_GLB_P2_SEL 60 |
| #define CK_TOP_DA_XTP_GLB_P3_SEL 61 |
| #define CK_TOP_CKM_SEL 62 |
| #define CK_TOP_DA_SELM_XTAL_SEL 63 |
| #define CK_TOP_PEXTP_SEL 64 |
| #define CK_TOP_TOPS_P2_26M_SEL 65 |
| #define CK_TOP_MCUSYS_BACKUP_625M_SEL 66 |
| #define CK_TOP_NETSYS_SYNC_250M_SEL 67 |
| #define CK_TOP_MACSEC_SEL 68 |
| #define CK_TOP_NETSYS_TOPS_400M_SEL 69 |
| #define CK_TOP_NETSYS_PPEFB_250M_SEL 70 |
| #define CK_TOP_NETSYS_WARP_SEL 71 |
| #define CK_TOP_ETH_MII_SEL 72 |
| #define CK_TOP_CK_NPU_SEL_CM_TOPS_SEL 73 |
| #define CK_TOP_CB_CKSQ_40M 74 |
| #define CK_TOP_CB_M_416M 75 |
| #define CK_TOP_CB_M_D2 76 |
| #define CK_TOP_M_D3_D2 77 |
| #define CK_TOP_CB_M_D4 78 |
| #define CK_TOP_CB_M_D8 79 |
| #define CK_TOP_M_D8_D2 80 |
| #define CK_TOP_CB_MM_720M 81 |
| #define CK_TOP_CB_MM_D2 82 |
| #define CK_TOP_CB_MM_D3_D5 83 |
| #define CK_TOP_CB_MM_D4 84 |
| #define CK_TOP_MM_D6_D2 85 |
| #define CK_TOP_CB_MM_D8 86 |
| #define CK_TOP_CB_APLL2_196M 87 |
| #define CK_TOP_CB_APLL2_D4 88 |
| #define CK_TOP_CB_NET1_D4 89 |
| #define CK_TOP_CB_NET1_D5 90 |
| #define CK_TOP_NET1_D5_D2 91 |
| #define CK_TOP_NET1_D5_D4 92 |
| #define CK_TOP_CB_NET1_D8 93 |
| #define CK_TOP_NET1_D8_D2 94 |
| #define CK_TOP_NET1_D8_D4 95 |
| #define CK_TOP_NET1_D8_D8 96 |
| #define CK_TOP_NET1_D8_D16 97 |
| #define CK_TOP_CB_NET2_800M 98 |
| #define CK_TOP_CB_NET2_D2 99 |
| #define CK_TOP_CB_NET2_D4 100 |
| #define CK_TOP_NET2_D4_D4 101 |
| #define CK_TOP_NET2_D4_D8 102 |
| #define CK_TOP_CB_NET2_D6 103 |
| #define CK_TOP_CB_NET2_D8 104 |
| #define CK_TOP_CB_WEDMCU_208M 105 |
| #define CK_TOP_CB_SGM_325M 106 |
| #define CK_TOP_CB_NETSYS_850M 107 |
| #define CK_TOP_CB_MSDC_400M 108 |
| #define CK_TOP_CKSQ_40M_D2 109 |
| #define CK_TOP_CB_RTC_32K 110 |
| #define CK_TOP_CB_RTC_32P7K 111 |
| #define CK_TOP_INFRA_F32K 112 |
| #define CK_TOP_CKSQ_SRC 113 |
| #define CK_TOP_NETSYS_2X 114 |
| #define CK_TOP_NETSYS_GSW 115 |
| #define CK_TOP_NETSYS_WED_MCU 116 |
| #define CK_TOP_EIP197 117 |
| #define CK_TOP_EMMC_250M 118 |
| #define CK_TOP_EMMC_400M 119 |
| #define CK_TOP_SPI 120 |
| #define CK_TOP_SPIM_MST 121 |
| #define CK_TOP_NFI1X 122 |
| #define CK_TOP_SPINFI_BCK 123 |
| #define CK_TOP_I2C_BCK 124 |
| #define CK_TOP_USB_SYS 125 |
| #define CK_TOP_USB_SYS_P1 126 |
| #define CK_TOP_USB_XHCI 127 |
| #define CK_TOP_USB_XHCI_P1 128 |
| #define CK_TOP_USB_FRMCNT 129 |
| #define CK_TOP_USB_FRMCNT_P1 130 |
| #define CK_TOP_AUD 131 |
| #define CK_TOP_A1SYS 132 |
| #define CK_TOP_AUD_L 133 |
| #define CK_TOP_A_TUNER 134 |
| #define CK_TOP_SYSAXI 135 |
| #define CK_TOP_INFRA_F26M 136 |
| #define CK_TOP_USB_REF 137 |
| #define CK_TOP_USB_CK_P1 138 |
| #define CK_TOP_AUD_I2S_M 139 |
| #define CLK_TOP_NR_CLK 140 |
| |
| /* APMIXEDSYS */ |
| |
| #define CK_APMIXED_NETSYSPLL 0 |
| #define CK_APMIXED_MPLL 1 |
| #define CK_APMIXED_MMPLL 2 |
| #define CK_APMIXED_APLL2 3 |
| #define CK_APMIXED_NET1PLL 4 |
| #define CK_APMIXED_NET2PLL 5 |
| #define CK_APMIXED_WEDMCUPLL 6 |
| #define CK_APMIXED_SGMPLL 7 |
| #define CK_APMIXED_ARM_B 8 |
| #define CK_APMIXED_CCIPLL2_B 9 |
| #define CK_APMIXED_USXGMIIPLL 10 |
| #define CK_APMIXED_MSDCPLL 11 |
| #define CLK_APMIXED_NR_CLK 12 |
| |
| /* MCUSYS */ |
| |
| #define CK_MCU_BUS_DIV_SEL 0 |
| #define CK_MCU_ARM_DIV_SEL 1 |
| #define CLK_MCU_NR_CLK 2 |
| |
| /* ETHDMA */ |
| |
| #define CK_ETHDMA_XGP1_EN 0 |
| #define CK_ETHDMA_XGP2_EN 1 |
| #define CK_ETHDMA_XGP3_EN 2 |
| #define CK_ETHDMA_FE_EN 3 |
| #define CK_ETHDMA_GP2_EN 4 |
| #define CK_ETHDMA_GP1_EN 5 |
| #define CK_ETHDMA_GP3_EN 6 |
| #define CK_ETHDMA_ESW_EN 7 |
| #define CK_ETHDMA_CRYPT0_EN 8 |
| #define CLK_ETHDMA_NR_CLK 9 |
| /* SGMIISYS_0 */ |
| |
| #define CK_SGM0_TX_EN 0 |
| #define CK_SGM0_RX_EN 1 |
| #define CLK_SGMII0_NR_CLK 2 |
| |
| /* SGMIISYS_1 */ |
| |
| #define CK_SGM1_TX_EN 0 |
| #define CK_SGM1_RX_EN 1 |
| #define CLK_SGMII1_NR_CLK 2 |
| |
| /* ETHWARP */ |
| |
| #define CK_ETHWARP_WOCPU2_EN 0 |
| #define CK_ETHWARP_WOCPU1_EN 1 |
| #define CK_ETHWARP_WOCPU0_EN 2 |
| #define CLK_ETHWARP_NR_CLK 3 |
| |
| #endif /* _DT_BINDINGS_CLK_MT7988_H */ |
| |