[][kernel][mt7988][eth][mediatek-ge-soc: Fix VCM K failure]
[Description]
Fix VCM K failure:
1. Disable TX power saving first, so that TX-VCM calibration can go on.
2. We don't calibrate Gphy twice. Remove calibration part in config_init().
Now, calibration will only take place at probe().
3. Print VCM calibration final result even it's successful.
Without this patch, TX-VCM won't work correctly on MT7988
[Release-log]
N/A
Change-Id: I83a5178ca1eaf43eccbdbd885b5c6223344807d9
Reviewed-on: https://gerrit.mediatek.inc/c/openwrt/feeds/mtk_openwrt_feeds/+/7678323
diff --git a/target/linux/mediatek/files-5.4/drivers/net/phy/mediatek-ge-soc.c b/target/linux/mediatek/files-5.4/drivers/net/phy/mediatek-ge-soc.c
index 489e524..40a5e0f 100644
--- a/target/linux/mediatek/files-5.4/drivers/net/phy/mediatek-ge-soc.c
+++ b/target/linux/mediatek/files-5.4/drivers/net/phy/mediatek-ge-soc.c
@@ -679,7 +679,7 @@
MTK_PHY_DA_RX_PSBN_LP_MASK,
upper_idx << 12 | upper_idx << 8 |
upper_idx << 4 | upper_idx);
- phydev_dbg(phydev, "TX-VCM SW cal result: 0x%x\n", upper_idx);
+ phydev_info(phydev, "TX-VCM SW cal result: 0x%x\n", upper_idx);
} else if (lower_idx == TXRESERVE_MIN && upper_ret == 1 &&
lower_ret == 1) {
ret = 0;
@@ -845,10 +845,6 @@
/* TCT finetune */
phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_TX_FILTER, 0x5);
- /* Disable TX power saving */
- phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG7,
- MTK_PHY_DA_AD_BUF_BIAS_LP_MASK, 0x3 << 8);
-
phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
/* ResetSyncOffset = 5 */
__phy_write(phydev, 0x11, 0x500);
@@ -1137,7 +1133,7 @@
mt798x_phy_common_finetune(phydev);
mt798x_phy_eee(phydev);
- return mt798x_phy_calibration(phydev);
+ return 0;
}
static int mt7988_phy_setup_led(struct phy_device *phydev)
@@ -1229,6 +1225,13 @@
return err;
}
+ /* Disable TX power saving at probing to:
+ * 1. Meet common mode compliance test criteria
+ * 2. Make sure that TX-VCM calibration works fine
+ */
+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG7,
+ MTK_PHY_DA_AD_BUF_BIAS_LP_MASK, 0x3 << 8);
+
mt7988_phy_setup_led(phydev);
return mt798x_phy_calibration(phydev);