| // SPDX-License-Identifier: (GPL-2.0 OR MIT) |
| /* |
| * Copyright (C) 2021 MediaTek Inc. |
| * Author: Sam.Shih <sam.shih@mediatek.com> |
| */ |
| |
| /dts-v1/; |
| #include "mt7988.dtsi" |
| |
| / { |
| model = "MediaTek MT7988D DSA 10G eMMC RFB"; |
| compatible = "mediatek,mt7988d-dsa-10g-emmc", |
| /* Reserve this for DVFS if creating new dts */ |
| "mediatek,mt7988"; |
| chosen { |
| bootargs = "console=ttyS0,115200n1 loglevel=8 \ |
| earlycon=uart8250,mmio32,0x11000000 \ |
| root=PARTLABEL=rootfs rootwait \ |
| rootfstype=squashfs,f2fs pci=pcie_bus_perf"; |
| }; |
| |
| memory { |
| reg = <0 0x40000000 0 0x10000000>; |
| }; |
| |
| wsys_adie: wsys_adie@0 { |
| // fpga cases need to manual change adie_id / sku_type for dvt only |
| compatible = "mediatek,rebb-mt7988-adie"; |
| adie_id = <7976>; |
| sku_type = <3000>; |
| }; |
| |
| reg_1p8v: regulator-1p8v { |
| compatible = "regulator-fixed"; |
| regulator-name = "fixed-1.8V"; |
| regulator-min-microvolt = <1800000>; |
| regulator-max-microvolt = <1800000>; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| |
| reg_3p3v: regulator-3p3v { |
| compatible = "regulator-fixed"; |
| regulator-name = "fixed-3.3V"; |
| regulator-min-microvolt = <3300000>; |
| regulator-max-microvolt = <3300000>; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| }; |
| |
| &fan { |
| pwms = <&pwm 0 50000 0>; |
| status = "okay"; |
| }; |
| |
| &pwm { |
| status = "okay"; |
| }; |
| |
| &uart0 { |
| status = "okay"; |
| }; |
| |
| &spi1 { |
| pinctrl-names = "default"; |
| /* pin shared with snfi */ |
| pinctrl-0 = <&spic_pins>; |
| status = "disabled"; |
| }; |
| |
| &pcie0 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pcie0_pins>; |
| status = "okay"; |
| }; |
| |
| &pcie1 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pcie1_pins>; |
| status = "disabled"; |
| }; |
| |
| &pcie2 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pcie2_pins>; |
| status = "disabled"; |
| }; |
| |
| &pcie3 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pcie3_pins>; |
| status = "okay"; |
| }; |
| |
| &pio { |
| mdio0_pins: mdio0-pins { |
| mux { |
| function = "mdio"; |
| groups = "mdc_mdio0"; |
| }; |
| |
| conf { |
| groups = "mdc_mdio0"; |
| drive-strength = <MTK_DRIVE_8mA>; |
| }; |
| }; |
| |
| gbe0_led0_pins: gbe0-pins { |
| mux { |
| function = "led"; |
| groups = "gbe0_led0"; |
| }; |
| }; |
| |
| gbe1_led0_pins: gbe1-pins { |
| mux { |
| function = "led"; |
| groups = "gbe1_led0"; |
| }; |
| }; |
| |
| gbe2_led0_pins: gbe2-pins { |
| mux { |
| function = "led"; |
| groups = "gbe2_led0"; |
| }; |
| }; |
| |
| gbe3_led0_pins: gbe3-pins { |
| mux { |
| function = "led"; |
| groups = "gbe3_led0"; |
| }; |
| }; |
| |
| i2p5gbe_led0_pins: 2p5gbe-pins { |
| mux { |
| function = "led"; |
| groups = "2p5gbe_led0"; |
| }; |
| }; |
| |
| pcie0_pins: pcie0-pins { |
| mux { |
| function = "pcie"; |
| groups = "pcie_2l_0_pereset", "pcie_clk_req_n0_0", |
| "pcie_wake_n0_0"; |
| }; |
| }; |
| |
| pcie1_pins: pcie1-pins { |
| mux { |
| function = "pcie"; |
| groups = "pcie_2l_1_pereset", "pcie_clk_req_n1", |
| "pcie_wake_n1_0"; |
| }; |
| }; |
| |
| pcie2_pins: pcie2-pins { |
| mux { |
| function = "pcie"; |
| groups = "pcie_1l_0_pereset", "pcie_clk_req_n2_0", |
| "pcie_wake_n2_0"; |
| }; |
| }; |
| |
| pcie3_pins: pcie3-pins { |
| mux { |
| function = "pcie"; |
| groups = "pcie_1l_1_pereset", "pcie_clk_req_n3", |
| "pcie_wake_n3_0"; |
| }; |
| }; |
| |
| spic_pins: spi1-pins { |
| mux { |
| function = "spi"; |
| groups = "spi1"; |
| }; |
| }; |
| |
| mmc0_pins_default: mmc0-pins-default { |
| mux { |
| function = "flash"; |
| groups = "emmc_51"; |
| }; |
| }; |
| |
| mmc0_pins_uhs: mmc0-pins-uhs { |
| mux { |
| function = "flash"; |
| groups = "emmc_51"; |
| }; |
| }; |
| }; |
| |
| &watchdog { |
| status = "disabled"; |
| }; |
| |
| ð { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&mdio0_pins>; |
| status = "okay"; |
| |
| gmac0: mac@0 { |
| compatible = "mediatek,eth-mac"; |
| reg = <0>; |
| mac-type = "xgdm"; |
| phy-mode = "10gbase-kr"; |
| |
| fixed-link { |
| speed = <10000>; |
| full-duplex; |
| pause; |
| }; |
| }; |
| |
| gmac1: mac@1 { |
| compatible = "mediatek,eth-mac"; |
| reg = <1>; |
| mac-type = "xgdm"; |
| phy-mode = "xgmii"; |
| phy-handle = <&phy0>; |
| }; |
| |
| gmac2: mac@2 { |
| compatible = "mediatek,eth-mac"; |
| reg = <2>; |
| mac-type = "xgdm"; |
| phy-mode = "usxgmii"; |
| phy-handle = <&phy1>; |
| }; |
| |
| mdio: mdio-bus { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clock-frequency = <10500000>; |
| |
| phy0: ethernet-phy@0 { |
| pinctrl-names = "i2p5gbe-led"; |
| pinctrl-0 = <&i2p5gbe_led0_pins>; |
| reg = <15>; |
| compatible = "ethernet-phy-ieee802.3-c45"; |
| phy-mode = "xgmii"; |
| }; |
| |
| phy1: ethernet-phy@8 { |
| reg = <8>; |
| compatible = "ethernet-phy-ieee802.3-c45"; |
| reset-gpios = <&pio 3 1>; |
| reset-assert-us = <100000>; |
| reset-deassert-us = <221000>; |
| }; |
| |
| switch@0 { |
| compatible = "mediatek,mt7988"; |
| reg = <31>; |
| ports { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| port@0 { |
| reg = <0>; |
| label = "lan0"; |
| phy-mode = "gmii"; |
| phy-handle = <&sphy0>; |
| }; |
| |
| port@1 { |
| reg = <1>; |
| label = "lan1"; |
| phy-mode = "gmii"; |
| phy-handle = <&sphy1>; |
| }; |
| |
| port@2 { |
| reg = <2>; |
| label = "lan2"; |
| phy-mode = "gmii"; |
| phy-handle = <&sphy2>; |
| }; |
| |
| port@3 { |
| reg = <3>; |
| label = "lan3"; |
| phy-mode = "gmii"; |
| phy-handle = <&sphy3>; |
| }; |
| |
| port@6 { |
| reg = <6>; |
| label = "cpu"; |
| ethernet = <&gmac0>; |
| phy-mode = "10gbase-kr"; |
| |
| fixed-link { |
| speed = <10000>; |
| full-duplex; |
| pause; |
| }; |
| }; |
| }; |
| |
| mdio { |
| compatible = "mediatek,dsa-slave-mdio"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| sphy0: switch_phy0@0 { |
| compatible = "ethernet-phy-id03a2.9481"; |
| reg = <0>; |
| pinctrl-names = "gbe-led"; |
| pinctrl-0 = <&gbe0_led0_pins>; |
| nvmem-cells = <&phy_calibration_p0>; |
| nvmem-cell-names = "phy-cal-data"; |
| }; |
| |
| sphy1: switch_phy1@1 { |
| compatible = "ethernet-phy-id03a2.9481"; |
| reg = <1>; |
| pinctrl-names = "gbe-led"; |
| pinctrl-0 = <&gbe1_led0_pins>; |
| nvmem-cells = <&phy_calibration_p1>; |
| nvmem-cell-names = "phy-cal-data"; |
| }; |
| |
| sphy2: switch_phy2@2 { |
| compatible = "ethernet-phy-id03a2.9481"; |
| reg = <2>; |
| pinctrl-names = "gbe-led"; |
| pinctrl-0 = <&gbe2_led0_pins>; |
| nvmem-cells = <&phy_calibration_p2>; |
| nvmem-cell-names = "phy-cal-data"; |
| }; |
| |
| sphy3: switch_phy3@3 { |
| compatible = "ethernet-phy-id03a2.9481"; |
| reg = <3>; |
| pinctrl-names = "gbe-led"; |
| pinctrl-0 = <&gbe3_led0_pins>; |
| nvmem-cells = <&phy_calibration_p3>; |
| nvmem-cell-names = "phy-cal-data"; |
| }; |
| }; |
| }; |
| }; |
| }; |
| |
| &hnat { |
| mtketh-wan = "eth1"; |
| mtketh-lan = "lan"; |
| mtketh-lan2 = "eth2"; |
| mtketh-max-gmac = <3>; |
| status = "okay"; |
| }; |
| |
| &mmc0 { |
| pinctrl-names = "default", "state_uhs"; |
| pinctrl-0 = <&mmc0_pins_default>; |
| pinctrl-1 = <&mmc0_pins_uhs>; |
| bus-width = <8>; |
| max-frequency = <200000000>; |
| cap-mmc-highspeed; |
| mmc-hs200-1_8v; |
| mmc-hs400-1_8v; |
| hs400-ds-delay = <0x12814>; |
| vqmmc-supply = <®_1p8v>; |
| vmmc-supply = <®_3p3v>; |
| non-removable; |
| no-sd; |
| no-sdio; |
| status = "okay"; |
| }; |