| commit | 2cd8fe806282810d5da5b993fec8f35daa9faa56 | [log] [tgz] |
|---|---|---|
| author | developer <developer@mediatek.com> | Tue Mar 19 23:10:37 2024 +0800 |
| committer | developer <developer@mediatek.com> | Wed Mar 20 17:48:21 2024 +0800 |
| tree | abf709e97ec952698fc3413dd70cc42ac552f805 | |
| parent | b72d6cba92bf9e29fb035c03052fa1e86664a25b [diff] |
[][kernel][mt7981][eth][Fix issue of GMAC RX hanging when internal GPHY connect to a legacy 10M/Half hub] [Description] Fix issue of GMAC RX hanging when internal GPHY connect to a legacy 10M/Half hub. Without this patch, the GMAC RX direction might be stalled due to irregular short packets. [Release-log] N/A Change-Id: I89b61fddf538e8035df86e5124e00b7b693321a5 Reviewed-on: https://gerrit.mediatek.inc/c/openwrt/feeds/mtk_openwrt_feeds/+/8821447
diff --git a/21.02/files/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/21.02/files/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.c index f3e0b06..d424cb8 100644 --- a/21.02/files/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.c +++ b/21.02/files/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.c
@@ -1140,6 +1140,8 @@ if (duplex == DUPLEX_FULL || interface == PHY_INTERFACE_MODE_SGMII) mcr |= MAC_MCR_FORCE_DPX; + else if (interface == PHY_INTERFACE_MODE_GMII) + mcr |= MAC_MCR_PRMBL_LMT_EN; /* Configure pause modes - * phylink will avoid these for half duplex
diff --git a/21.02/files/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/21.02/files/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.h index 23d384f..d6a68fb 100644 --- a/21.02/files/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.h +++ b/21.02/files/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.h
@@ -745,6 +745,7 @@ #define MAC_MCR_FORCE_MODE BIT(15) #define MAC_MCR_TX_EN BIT(14) #define MAC_MCR_RX_EN BIT(13) +#define MAC_MCR_PRMBL_LMT_EN BIT(10) #define MAC_MCR_BACKOFF_EN BIT(9) #define MAC_MCR_BACKPR_EN BIT(8) #define MAC_MCR_FORCE_EEE1000 BIT(7)