[][kernel][mt7988][i2.5gphy][net: phy: Fix RTL8156B 100Mbps EEE link down issue by setting lpi_SigEnLoThresh100 to 0]
[Description]
Fix RTL8156B 100Mbps EEE link down issue by setting lpi_SigEnLoThresh100
to 0. This fix will freeze parts of DSP states.
Without this patch, if testing internal 2.5gphy with RTL8156B cards,
you may suffer from link down during 100Mbps EEE.
[Release-log]
N/A
Change-Id: I10f7e8d11b0b794c475fb0eb2d86f8d530a39b1d
Reviewed-on: https://gerrit.mediatek.inc/c/openwrt/feeds/mtk_openwrt_feeds/+/8048257
diff --git a/target/linux/mediatek/files-5.4/drivers/net/phy/mediatek-2p5ge.c b/target/linux/mediatek/files-5.4/drivers/net/phy/mediatek-2p5ge.c
index 1047943..8cbe4ac 100644
--- a/target/linux/mediatek/files-5.4/drivers/net/phy/mediatek-2p5ge.c
+++ b/target/linux/mediatek/files-5.4/drivers/net/phy/mediatek-2p5ge.c
@@ -26,6 +26,9 @@
#define MTK_PHY_LINK_STATUS_MISC (0xa2)
#define MTK_PHY_FDX_ENABLE BIT(5)
+#define MTK_PHY_LPI_PCS_DSP_CTRL (0x121)
+#define MTK_PHY_LPI_SIG_EN_LO_THRESH100_MASK GENMASK(12, 8)
+
/* Registers on MDIO_MMD_VEND2 */
#define MTK_PHY_LED0_ON_CTRL (0x24)
#define MTK_PHY_LED0_ON_LINK1000 BIT(0)
@@ -98,6 +101,9 @@
writew(reg | MD32_EN, mcucsr_base + MD32_EN_CFG);
dev_info(dev, "Firmware loading/trigger ok.\n");
+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LPI_PCS_DSP_CTRL,
+ MTK_PHY_LPI_SIG_EN_LO_THRESH100_MASK, 0);
+
/* Setup LED */
phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED0_ON_CTRL,
MTK_PHY_LED0_POLARITY | MTK_PHY_LED0_ON_LINK10 |