| From 48b21966878b9b47925ce65008614d52117e2dba Mon Sep 17 00:00:00 2001 |
| From: "sujuan.chen" <sujuan.chen@mediatek.com> |
| Date: Thu, 6 Apr 2023 17:50:52 +0800 |
| Subject: [PATCH 2008/2009] wifi: mt76: mt7915: add ctxd support for mt7916 |
| |
| Signed-off-by: sujuan.chen <sujuan.chen@mediatek.com> |
| --- |
| mt7915/dma.c | 20 ++++++++++++++++++++ |
| mt7915/regs.h | 15 +++++++++++++++ |
| 2 files changed, 35 insertions(+) |
| |
| diff --git a/mt7915/dma.c b/mt7915/dma.c |
| index 326c8c8..f71ec55 100644 |
| --- a/mt7915/dma.c |
| +++ b/mt7915/dma.c |
| @@ -433,6 +433,26 @@ int mt7915_dma_init(struct mt7915_dev *dev, struct mt7915_phy *phy2) |
| if (is_mt7915(mdev)) |
| mt76_rmw(dev, MT_WFDMA0_EXT0_CFG, MT_WFDMA0_EXT0_RXWB_KEEP, |
| MT_WFDMA0_EXT0_RXWB_KEEP); |
| + else { |
| + if ((mt76_rr(dev, MT_CBTOP_RESV) & 0xff) == 2) { |
| + mt76_set(dev, MT_WFDMA0_GLO_CFG, MT_WFDMA0_GLO_CFG_DUMMY_REG); |
| + mt76_set(dev, MT_WFDMA0_CTXD_CFG, FIELD_PREP(MT_WFDMA0_CTXD_TIMEOUT, 0xa)); |
| + } else { |
| + mt76_set(dev, MT_WFDMA0_CTXD_CFG, FIELD_PREP(MT_WFDMA0_CTXD_TIMEOUT, 0xff)); |
| + |
| + /*Delay tick set to 0xFFFF, which is about 3449us*/ |
| + mt76_wr(dev, MT_WFDMA_WED_DLY_INT_TICK, 0xffff); |
| + } |
| + |
| + mt76_clear(dev, MT_WFDMA0_CTXD_CFG, MT_WFDMA0_CTXD_CASCADE_NUM); |
| + |
| + mt76_set(dev, MT_WFDMA0_CTXD_CFG, |
| + FIELD_PREP(MT_WFDMA0_BAND0_CTXD_RING_IDX, 18) | |
| + FIELD_PREP(MT_WFDMA0_BAND1_CTXD_RING_IDX, 19) | |
| + MT_WFDMA0_BAND0_CTXD_EN | MT_WFDMA0_BAND1_CTXD_EN); |
| + |
| + mt76_set(dev, MT_WFDMA0_CFG_EXT, MT_WFDMA0_EXT_TX_FCTRL_MODE); |
| + } |
| } |
| } else { |
| mt76_clear(dev, MT_WFDMA_HOST_CONFIG, MT_WFDMA_HOST_CONFIG_WED); |
| diff --git a/mt7915/regs.h b/mt7915/regs.h |
| index 44da7b8..bc963ac 100644 |
| --- a/mt7915/regs.h |
| +++ b/mt7915/regs.h |
| @@ -606,6 +606,7 @@ enum offs_rev { |
| #define MT_WFDMA0_GLO_CFG MT_WFDMA0(0x208) |
| #define MT_WFDMA0_GLO_CFG_TX_DMA_EN BIT(0) |
| #define MT_WFDMA0_GLO_CFG_RX_DMA_EN BIT(2) |
| +#define MT_WFDMA0_GLO_CFG_DUMMY_REG BIT(10) |
| #define MT_WFDMA0_GLO_CFG_OMIT_TX_INFO BIT(28) |
| #define MT_WFDMA0_GLO_CFG_OMIT_RX_INFO BIT(27) |
| #define MT_WFDMA0_GLO_CFG_OMIT_RX_INFO_PFET2 BIT(21) |
| @@ -615,6 +616,17 @@ enum offs_rev { |
| #define MT_WFDMA0_EXT0_CFG MT_WFDMA0(0x2b0) |
| #define MT_WFDMA0_EXT0_RXWB_KEEP BIT(10) |
| |
| +#define MT_WFDMA0_CFG_EXT MT_WFDMA0(0x2b4) |
| +#define MT_WFDMA0_EXT_TX_FCTRL_MODE BIT(28) |
| + |
| +#define MT_WFDMA0_CTXD_CFG MT_WFDMA0(0x2bc) |
| +#define MT_WFDMA0_BAND0_CTXD_EN BIT(0) |
| +#define MT_WFDMA0_BAND0_CTXD_RING_IDX GENMASK(5, 1) |
| +#define MT_WFDMA0_BAND1_CTXD_EN BIT(6) |
| +#define MT_WFDMA0_BAND1_CTXD_RING_IDX GENMASK(11, 7) |
| +#define MT_WFDMA0_CTXD_CASCADE_NUM GENMASK(15, 12) |
| +#define MT_WFDMA0_CTXD_TIMEOUT GENMASK(23, 16) |
| + |
| #define MT_WFDMA0_PRI_DLY_INT_CFG0 MT_WFDMA0(0x2f0) |
| #define MT_WFDMA0_PRI_DLY_INT_CFG1 MT_WFDMA0(0x2f4) |
| #define MT_WFDMA0_PRI_DLY_INT_CFG2 MT_WFDMA0(0x2f8) |
| @@ -658,6 +670,8 @@ enum offs_rev { |
| #define MT_WFDMA_WED_RING_CONTROL_TX1 GENMASK(12, 8) |
| #define MT_WFDMA_WED_RING_CONTROL_RX1 GENMASK(20, 16) |
| |
| +#define MT_WFDMA_WED_DLY_INT_TICK MT_WFDMA_EXT_CSR_PHYS(0x38) |
| + |
| #define MT_WFDMA_EXT_CSR_HIF_MISC MT_WFDMA_EXT_CSR_PHYS(0x44) |
| #define MT_WFDMA_EXT_CSR_HIF_MISC_BUSY BIT(0) |
| |
| @@ -1186,6 +1200,7 @@ enum offs_rev { |
| |
| #define MT_HW_BOUND 0x70010020 |
| #define MT_HW_REV 0x70010204 |
| +#define MT_CBTOP_RESV 0x70010210 |
| #define MT_WF_SUBSYS_RST 0x70002600 |
| |
| /* PCIE MAC */ |
| -- |
| 2.18.0 |
| |