[][kernel][common][eth][Remove SGMII_FIXED_2G5 from Maxlinear PHY driver]
[Description]
Remove SGMII_FIXED_2G5 from Maxlinear PHY driver.
We no longer need SGMII_FIXED_2G5 after applying DEL_RXFIFO_CLR patch.
[Release-log]
N/A
Change-Id: I6d2aea74bcee679210867580394001221f609d21
Reviewed-on: https://gerrit.mediatek.inc/c/openwrt/feeds/mtk_openwrt_feeds/+/6538171
diff --git a/target/linux/mediatek/patches-5.4/746-mxl-gpy-phy-support.patch b/target/linux/mediatek/patches-5.4/746-mxl-gpy-phy-support.patch
index 6812f0c..26bef5f 100644
--- a/target/linux/mediatek/patches-5.4/746-mxl-gpy-phy-support.patch
+++ b/target/linux/mediatek/patches-5.4/746-mxl-gpy-phy-support.patch
@@ -32,7 +32,7 @@
index 0000000..7304278
--- /dev/null
+++ b/drivers/net/phy/mxl-gpy.c
-@@ -0,0 +1,749 @@
+@@ -0,0 +1,738 @@
+// SPDX-License-Identifier: GPL-2.0+
+/* Copyright (C) 2021 Maxlinear Corporation
+ * Copyright (C) 2020 Intel Corporation
@@ -98,7 +98,6 @@
+#define VSPEC1_SGMII_CTRL_ANRS BIT(9) /* Restart Aneg */
+#define VSPEC1_SGMII_ANEN_ANRS (VSPEC1_SGMII_CTRL_ANEN | \
+ VSPEC1_SGMII_CTRL_ANRS)
-+#define VSPEC1_SGMII_FIXED_2G5 BIT(5)
+
+/* WoL */
+#define VPSPEC2_WOL_CTL 0x0E06
@@ -301,23 +300,13 @@
+ case SPEED_2500:
+ phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
+ ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL,
-+ VSPEC1_SGMII_CTRL_ANEN | VSPEC1_SGMII_FIXED_2G5,
-+ 0);
++ VSPEC1_SGMII_CTRL_ANEN, 0);
+ if (ret < 0)
+ phydev_err(phydev,
+ "Error: Disable of SGMII ANEG failed: %d\n",
+ ret);
+ break;
+ case SPEED_1000:
-+ phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
-+ ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL,
-+ VSPEC1_SGMII_CTRL_ANEN | VSPEC1_SGMII_FIXED_2G5,
-+ VSPEC1_SGMII_FIXED_2G5);
-+ if (ret < 0)
-+ phydev_err(phydev,
-+ "Error: Disable of SGMII ANEG failed: %d\n",
-+ ret);
-+ break;
+ case SPEED_100:
+ case SPEED_10:
+ phydev->interface = PHY_INTERFACE_MODE_SGMII;
@@ -327,7 +316,7 @@
+ * if ANEG is disabled (in 2500-BaseX mode).
+ */
+ ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL,
-+ VSPEC1_SGMII_ANEN_ANRS | VSPEC1_SGMII_FIXED_2G5,
++ VSPEC1_SGMII_ANEN_ANRS,
+ VSPEC1_SGMII_ANEN_ANRS);
+ if (ret < 0)
+ phydev_err(phydev,