| commit | 0fffed6e323ef7d8e280049666739e3986e1147f | [log] [tgz] |
|---|---|---|
| author | developer <developer@mediatek.com> | Tue Jun 29 14:17:11 2021 +0800 |
| committer | developer <developer@mediatek.com> | Wed Jun 30 10:24:06 2021 +0800 |
| tree | b98ae8a7426256a6c79bc8cfc5da4af2088af1aa | |
| parent | 691e73ff2765e8b90f4087a6a34efbe973d6f0e5 [diff] |
[][update pcie clk] [Description] Add pcie pipe clk and point it parent to xtal [Release-log] N/A Change-Id: I87defd2d5764b3c616aed21cecd28b4dbad3e82e Reviewed-on: https://gerrit.mediatek.inc/c/openwrt/feeds/mtk_openwrt_feeds/+/4691294