blob: 77cbc3929c14c21dfb459b4be13f6408d020297a [file] [log] [blame]
From a9cf0fd711fdccf35e6171dd4aba0eb7f6588148 Mon Sep 17 00:00:00 2001
From: Bo Jiao <Bo.Jiao@mediatek.com>
Date: Mon, 6 Jun 2022 20:08:58 +0800
Subject: [PATCH] mt76: mt7915: add mtk internal debug tools for mt76
---
mt76_connac_mcu.h | 6 +
mt7915/Makefile | 2 +-
mt7915/debugfs.c | 73 +-
mt7915/mac.c | 14 +
mt7915/mcu.c | 41 +
mt7915/mcu.h | 4 +
mt7915/mt7915.h | 41 +
mt7915/mt7915_debug.h | 1350 +++++++++++++++++++
mt7915/mtk_debugfs.c | 2921 +++++++++++++++++++++++++++++++++++++++++
mt7915/mtk_mcu.c | 51 +
tools/fwlog.c | 44 +-
11 files changed, 4534 insertions(+), 13 deletions(-)
mode change 100644 => 100755 mt7915/mcu.c
create mode 100644 mt7915/mt7915_debug.h
create mode 100644 mt7915/mtk_debugfs.c
create mode 100644 mt7915/mtk_mcu.c
diff --git a/mt76_connac_mcu.h b/mt76_connac_mcu.h
index aa14d2d4..03134066 100644
--- a/mt76_connac_mcu.h
+++ b/mt76_connac_mcu.h
@@ -968,6 +968,12 @@ enum {
MCU_EXT_CMD_TX_POWER_FEATURE_CTRL = 0x58,
MCU_EXT_CMD_RXDCOC_CAL = 0x59,
MCU_EXT_CMD_GET_MIB_INFO = 0x5a,
+#ifdef MTK_DEBUG
+ MCU_EXT_CMD_RED_ENABLE = 0x68,
+ MCU_EXT_CMD_RED_SHOW_STA = 0x69,
+ MCU_EXT_CMD_RED_TARGET_DELAY = 0x6A,
+ MCU_EXT_CMD_RED_TX_RPT = 0x6B,
+#endif
MCU_EXT_CMD_TXDPD_CAL = 0x60,
MCU_EXT_CMD_CAL_CACHE = 0x67,
MCU_EXT_CMD_SET_RADAR_TH = 0x7c,
diff --git a/mt7915/Makefile b/mt7915/Makefile
index b794ceb7..a3474e2f 100644
--- a/mt7915/Makefile
+++ b/mt7915/Makefile
@@ -3,7 +3,7 @@
obj-$(CONFIG_MT7915E) += mt7915e.o
mt7915e-y := pci.o init.o dma.o eeprom.o main.o mcu.o mac.o \
- debugfs.o mmio.o
+ debugfs.o mmio.o mtk_debugfs.o mtk_mcu.o
mt7915e-$(CONFIG_NL80211_TESTMODE) += testmode.o
mt7915e-$(CONFIG_MT7986_WMAC) += soc.o
\ No newline at end of file
diff --git a/mt7915/debugfs.c b/mt7915/debugfs.c
index 9f21d978..0cfb6068 100644
--- a/mt7915/debugfs.c
+++ b/mt7915/debugfs.c
@@ -8,6 +8,9 @@
#include "mac.h"
#define FW_BIN_LOG_MAGIC 0x44e98caf
+#ifdef MTK_DEBUG
+#define FW_BIN_LOG_MAGIC_V2 0x44d9c99a
+#endif
/** global debugfs **/
@@ -448,6 +451,9 @@ mt7915_fw_debug_wm_set(void *data, u64 val)
int ret;
dev->fw.debug_wm = val ? MCU_FW_LOG_TO_HOST : 0;
+#ifdef MTK_DEBUG
+ dev->fw.debug_wm = val;
+#endif
if (dev->fw.debug_bin)
val = 16;
@@ -472,6 +478,9 @@ mt7915_fw_debug_wm_set(void *data, u64 val)
if (ret)
goto out;
}
+#ifdef MTK_DEBUG
+ mt7915_mcu_fw_dbg_ctrl(dev, 68, !!val);
+#endif
/* WM CPU info record control */
mt76_clear(dev, MT_CPU_UTIL_CTRL, BIT(0));
@@ -479,6 +488,12 @@ mt7915_fw_debug_wm_set(void *data, u64 val)
mt76_wr(dev, MT_MCU_WM_CIRQ_IRQ_MASK_CLR_ADDR, BIT(5));
mt76_wr(dev, MT_MCU_WM_CIRQ_IRQ_SOFT_ADDR, BIT(5));
+#ifdef MTK_DEBUG
+ if (dev->fw.debug_bin & BIT(3))
+ /* use bit 7 to indicate v2 magic number */
+ dev->fw.debug_wm |= BIT(7);
+#endif
+
out:
if (ret)
dev->fw.debug_wm = 0;
@@ -491,7 +506,11 @@ mt7915_fw_debug_wm_get(void *data, u64 *val)
{
struct mt7915_dev *dev = data;
- *val = dev->fw.debug_wm;
+#ifdef MTK_DEBUG
+ *val = dev->fw.debug_wm & ~BIT(7);
+#else
+ val = dev->fw.debug_wm;
+#endif
return 0;
}
@@ -576,6 +595,17 @@ mt7915_fw_debug_bin_set(void *data, u64 val)
relay_reset(dev->relay_fwlog);
+#ifdef MTK_DEBUG
+ dev->dbg.dump_mcu_pkt = val & BIT(4) ? true : false;
+ dev->dbg.dump_txd = val & BIT(5) ? true : false;
+ dev->dbg.dump_tx_pkt = val & BIT(6) ? true : false;
+ dev->dbg.dump_rx_pkt = val & BIT(7) ? true : false;
+ dev->dbg.dump_rx_raw = val & BIT(8) ? true : false;
+ if (!(val & GENMASK(3, 0)))
+ return 0;
+#endif
+
+
return mt7915_fw_debug_wm_set(dev, dev->fw.debug_wm);
}
@@ -1038,6 +1068,11 @@ int mt7915_init_debugfs(struct mt7915_phy *phy)
if (!ext_phy)
dev->debugfs_dir = dir;
+#ifdef MTK_DEBUG
+ debugfs_create_u16("wlan_idx", 0600, dir, &dev->wlan_idx);
+ mt7915_mtk_init_debugfs(phy, dir);
+#endif
+
return 0;
}
@@ -1078,17 +1113,53 @@ void mt7915_debugfs_rx_fw_monitor(struct mt7915_dev *dev, const void *data, int
.msg_type = cpu_to_le16(PKT_TYPE_RX_FW_MONITOR),
};
+#ifdef MTK_DEBUG
+ struct {
+ __le32 magic;
+ u8 version;
+ u8 _rsv;
+ __le16 serial_id;
+ __le32 timestamp;
+ __le16 msg_type;
+ __le16 len;
+ } hdr2 = {
+ .version = 0x1,
+ .magic = cpu_to_le32(FW_BIN_LOG_MAGIC_V2),
+ .msg_type = PKT_TYPE_RX_FW_MONITOR,
+ };
+#endif
+
if (!dev->relay_fwlog)
return;
+#ifdef MTK_DEBUG
+ /* old magic num */
+ if (!(dev->fw.debug_wm & BIT(7))) {
+ hdr.timestamp = mt76_rr(dev, MT_LPON_FRCR(0));
+ hdr.len = *(__le16 *)data;
+ mt7915_debugfs_write_fwlog(dev, &hdr, sizeof(hdr), data, len);
+ } else {
+ hdr2.serial_id = dev->dbg.fwlog_seq++;
+ hdr2.timestamp = mt76_rr(dev, MT_LPON_FRCR(0));
+ hdr2.len = *(__le16 *)data;
+ mt7915_debugfs_write_fwlog(dev, &hdr2, sizeof(hdr2), data, len);
+ }
+#else
hdr.timestamp = cpu_to_le32(mt76_rr(dev, MT_LPON_FRCR(0)));
hdr.len = *(__le16 *)data;
mt7915_debugfs_write_fwlog(dev, &hdr, sizeof(hdr), data, len);
+#endif
}
bool mt7915_debugfs_rx_log(struct mt7915_dev *dev, const void *data, int len)
{
+#ifdef MTK_DEBUG
+ if (get_unaligned_le32(data) != FW_BIN_LOG_MAGIC &&
+ get_unaligned_le32(data) != FW_BIN_LOG_MAGIC_V2 &&
+ get_unaligned_le32(data) != PKT_BIN_DEBUG_MAGIC)
+#else
if (get_unaligned_le32(data) != FW_BIN_LOG_MAGIC)
+#endif
return false;
if (dev->relay_fwlog)
diff --git a/mt7915/mac.c b/mt7915/mac.c
index b0e86968..9e92b32f 100644
--- a/mt7915/mac.c
+++ b/mt7915/mac.c
@@ -596,6 +596,10 @@ mt7915_mac_fill_rx(struct mt7915_dev *dev, struct sk_buff *skb)
__le16 fc = 0;
int idx;
+#ifdef MTK_DEBUG
+ if (dev->dbg.dump_rx_raw)
+ mt7915_packet_log_to_host(dev, skb->data, skb->len, PKT_BIN_DEBUG_RX_RAW, 0);
+#endif
memset(status, 0, sizeof(*status));
if ((rxd1 & MT_RXD1_NORMAL_BAND_IDX) && !phy->band_idx) {
@@ -780,6 +784,10 @@ mt7915_mac_fill_rx(struct mt7915_dev *dev, struct sk_buff *skb)
}
hdr_gap = (u8 *)rxd - skb->data + 2 * remove_pad;
+#ifdef MTK_DEBUG
+ if (dev->dbg.dump_rx_pkt)
+ mt7915_packet_log_to_host(dev, skb->data, skb->len, PKT_BIN_DEBUG_RX, hdr_gap);
+#endif
if (hdr_trans && ieee80211_has_morefrags(fc)) {
if (mt7915_reverse_frag0_hdr_trans(skb, hdr_gap))
return -EINVAL;
@@ -1358,6 +1366,12 @@ int mt7915_tx_prepare_skb(struct mt76_dev *mdev, void *txwi_ptr,
tx_info->buf[1].skip_unmap = true;
tx_info->nbuf = MT_CT_DMA_BUF_NUM;
+#ifdef MTK_DEBUG
+ if (dev->dbg.dump_txd)
+ mt7915_packet_log_to_host(dev, txwi, MT_TXD_SIZE, PKT_BIN_DEBUG_TXD, 0);
+ if (dev->dbg.dump_tx_pkt)
+ mt7915_packet_log_to_host(dev, t->skb->data, t->skb->len, PKT_BIN_DEBUG_TX, 0);
+#endif
return 0;
}
diff --git a/mt7915/mcu.c b/mt7915/mcu.c
old mode 100644
new mode 100755
index 81559002..6ec321e1
--- a/mt7915/mcu.c
+++ b/mt7915/mcu.c
@@ -298,6 +298,10 @@ mt7915_mcu_send_message(struct mt76_dev *mdev, struct sk_buff *skb,
mcu_txd->s2d_index = MCU_S2D_H2N;
exit:
+#ifdef MTK_DEBUG
+ if (dev->dbg.dump_mcu_pkt)
+ mt7915_packet_log_to_host(dev, skb->data, skb->len, PKT_BIN_DEBUG_MCU, 0);
+#endif
if (wait_seq)
*wait_seq = seq;
@@ -3733,6 +3737,43 @@ int mt7915_mcu_twt_agrt_update(struct mt7915_dev *dev,
&req, sizeof(req), true);
}
+#ifdef MTK_DEBUG
+int mt7915_dbg_mcu_wa_cmd(struct mt7915_dev *dev, int cmd, u32 a1, u32 a2, u32 a3, bool wait_resp)
+{
+ struct {
+ __le32 args[3];
+ } req = {
+ .args = {
+ cpu_to_le32(a1),
+ cpu_to_le32(a2),
+ cpu_to_le32(a3),
+ },
+ };
+
+ return mt76_mcu_send_msg(&dev->mt76, cmd, &req, sizeof(req), wait_resp);
+}
+
+int mt7915_mcu_set_red(struct mt7915_dev *dev, bool enabled)
+{
+#define RED_DISABLE 0
+#define RED_BY_HOST_ENABLE 1
+#define RED_BY_WA_ENABLE 2
+ int ret;
+ u32 red_type = enabled > 0 ? RED_BY_WA_ENABLE : RED_DISABLE;
+ __le32 req = cpu_to_le32(red_type);
+
+ ret = mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(RED_ENABLE), &req,
+ sizeof(req), false);
+ if (ret < 0)
+ return ret;
+
+ mt7915_dbg_mcu_wa_cmd(dev, MCU_WA_PARAM_CMD(SET),
+ MCU_WA_PARAM_RED, enabled, 0, true);
+
+ return 0;
+}
+#endif
+
int mt7915_mcu_rf_regval(struct mt7915_dev *dev, u32 regidx, u32 *val, bool set)
{
struct {
diff --git a/mt7915/mcu.h b/mt7915/mcu.h
index d46c8da4..2f7007fd 100644
--- a/mt7915/mcu.h
+++ b/mt7915/mcu.h
@@ -296,6 +296,10 @@ enum {
MCU_WA_PARAM_PDMA_RX = 0x04,
MCU_WA_PARAM_CPU_UTIL = 0x0b,
MCU_WA_PARAM_RED = 0x0e,
+#ifdef MTK_DEBUG
+ MCU_WA_PARAM_RED_SHOW_STA = 0xf,
+ MCU_WA_PARAM_RED_TARGET_DELAY = 0x10,
+#endif
};
enum mcu_mmps_mode {
diff --git a/mt7915/mt7915.h b/mt7915/mt7915.h
index bd985e6c..001a6015 100644
--- a/mt7915/mt7915.h
+++ b/mt7915/mt7915.h
@@ -9,6 +9,7 @@
#include "../mt76_connac.h"
#include "regs.h"
+#define MTK_DEBUG 1
#define MT7915_MAX_INTERFACES 19
#define MT7915_MAX_WMM_SETS 4
#define MT7915_WTBL_SIZE 288
@@ -339,6 +340,27 @@ struct mt7915_dev {
struct reset_control *rstc;
void __iomem *dcm;
void __iomem *sku;
+
+#ifdef MTK_DEBUG
+ u16 wlan_idx;
+ struct {
+ u32 fixed_rate;
+ u32 l1debugfs_reg;
+ u32 l2debugfs_reg;
+ u32 mac_reg;
+ u32 fw_dbg_module;
+ u8 fw_dbg_lv;
+ u32 bcn_total_cnt[2];
+ u16 fwlog_seq;
+ bool dump_mcu_pkt;
+ bool dump_txd;
+ bool dump_tx_pkt;
+ bool dump_rx_pkt;
+ bool dump_rx_raw;
+ u32 token_idx;
+ } dbg;
+ const struct mt7915_dbg_reg_desc *dbg_reg;
+#endif
};
enum {
@@ -608,4 +630,23 @@ void mt7915_sta_add_debugfs(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
struct ieee80211_sta *sta, struct dentry *dir);
#endif
+#ifdef MTK_DEBUG
+int mt7915_mtk_init_debugfs(struct mt7915_phy *phy, struct dentry *dir);
+int mt7915_dbg_mcu_wa_cmd(struct mt7915_dev *dev, int cmd, u32 a1, u32 a2, u32 a3, bool wait_resp);
+int mt7915_mcu_set_red(struct mt7915_dev *dev, bool enabled);
+void mt7915_dump_tmac_info(u8 *tmac_info);
+int mt7915_mcu_set_txpower_level(struct mt7915_phy *phy, u8 drop_level);
+void mt7915_packet_log_to_host(struct mt7915_dev *dev, const void *data, int len, int type, int des_len);
+
+#define PKT_BIN_DEBUG_MAGIC 0xc8763123
+enum {
+ PKT_BIN_DEBUG_MCU,
+ PKT_BIN_DEBUG_TXD,
+ PKT_BIN_DEBUG_TX,
+ PKT_BIN_DEBUG_RX,
+ PKT_BIN_DEBUG_RX_RAW,
+};
+
+#endif
+
#endif
diff --git a/mt7915/mt7915_debug.h b/mt7915/mt7915_debug.h
new file mode 100644
index 00000000..58ba2cdf
--- /dev/null
+++ b/mt7915/mt7915_debug.h
@@ -0,0 +1,1350 @@
+#ifndef __MT7915_DEBUG_H
+#define __MT7915_DEBUG_H
+
+#ifdef MTK_DEBUG
+
+#define DBG_INVALID_BASE 0xffffffff
+#define DBG_INVALID_OFFSET 0x0
+
+struct __dbg_map {
+ u32 phys;
+ u32 maps;
+ u32 size;
+};
+
+struct __dbg_reg {
+ u32 base;
+ u32 offs;
+};
+
+struct __dbg_mask {
+ u32 end;
+ u32 start;
+};
+
+enum dbg_base_rev {
+ MT_DBG_WFDMA0_BASE,
+ MT_DBG_WFDMA1_BASE,
+ MT_DBG_WFDMA0_PCIE1_BASE,
+ MT_DBG_WFDMA1_PCIE1_BASE,
+ MT_DBG_WFDMA_EXT_CSR_BASE,
+ MT_DBG_SWDEF_BASE,
+ __MT_DBG_BASE_REV_MAX,
+};
+
+enum dbg_reg_rev {
+ DBG_INT_SOURCE_CSR,
+ DBG_INT_MASK_CSR,
+ DBG_INT1_SOURCE_CSR,
+ DBG_INT1_MASK_CSR,
+ DBG_TX_RING_BASE,
+ DBG_RX_EVENT_RING_BASE,
+ DBG_RX_STS_RING_BASE,
+ DBG_RX_DATA_RING_BASE,
+ DBG_DMA_ICSC_FR0,
+ DBG_DMA_ICSC_FR1,
+ DBG_TMAC_ICSCR0,
+ DBG_RMAC_RXICSRPT,
+ DBG_MIB_M0SDR0,
+ DBG_MIB_M0SDR3,
+ DBG_MIB_M0SDR4,
+ DBG_MIB_M0SDR5,
+ DBG_MIB_M0SDR7,
+ DBG_MIB_M0SDR8,
+ DBG_MIB_M0SDR9,
+ DBG_MIB_M0SDR10,
+ DBG_MIB_M0SDR11,
+ DBG_MIB_M0SDR12,
+ DBG_MIB_M0SDR14,
+ DBG_MIB_M0SDR15,
+ DBG_MIB_M0SDR16,
+ DBG_MIB_M0SDR17,
+ DBG_MIB_M0SDR18,
+ DBG_MIB_M0SDR19,
+ DBG_MIB_M0SDR20,
+ DBG_MIB_M0SDR21,
+ DBG_MIB_M0SDR22,
+ DBG_MIB_M0SDR23,
+ DBG_MIB_M0DR0,
+ DBG_MIB_M0DR1,
+ DBG_MIB_MUBF,
+ DBG_MIB_M0DR6,
+ DBG_MIB_M0DR7,
+ DBG_MIB_M0DR8,
+ DBG_MIB_M0DR9,
+ DBG_MIB_M0DR10,
+ DBG_MIB_M0DR11,
+ DBG_MIB_M0DR12,
+ DBG_WTBLON_WDUCR,
+ DBG_UWTBL_WDUCR,
+ DBG_PLE_DRR_TABLE_CTRL,
+ DBG_PLE_DRR_TABLE_RDATA,
+ DBG_PLE_PBUF_CTRL,
+ DBG_PLE_QUEUE_EMPTY,
+ DBG_PLE_FREEPG_CNT,
+ DBG_PLE_FREEPG_HEAD_TAIL,
+ DBG_PLE_PG_HIF_GROUP,
+ DBG_PLE_HIF_PG_INFO,
+ DBG_PLE_PG_HIF_TXCMD_GROUP,
+ DBG_PLE_HIF_TXCMD_PG_INFO,
+ DBG_PLE_PG_CPU_GROUP,
+ DBG_PLE_CPU_PG_INFO,
+ DBG_PLE_FL_QUE_CTRL,
+ DBG_PLE_NATIVE_TXCMD_Q_EMPTY,
+ DBG_PLE_TXCMD_Q_EMPTY,
+ DBG_PLE_AC_QEMPTY,
+ DBG_PLE_AC_OFFSET,
+ DBG_PLE_STATION_PAUSE,
+ DBG_PLE_DIS_STA_MAP,
+ DBG_PSE_PBUF_CTRL,
+ DBG_PSE_FREEPG_CNT,
+ DBG_PSE_FREEPG_HEAD_TAIL,
+ DBG_PSE_HIF0_PG_INFO,
+ DBG_PSE_PG_HIF1_GROUP,
+ DBG_PSE_HIF1_PG_INFO,
+ DBG_PSE_PG_CPU_GROUP,
+ DBG_PSE_CPU_PG_INFO,
+ DBG_PSE_PG_PLE_GROUP,
+ DBG_PSE_PLE_PG_INFO,
+ DBG_PSE_PG_LMAC0_GROUP,
+ DBG_PSE_LMAC0_PG_INFO,
+ DBG_PSE_PG_LMAC1_GROUP,
+ DBG_PSE_LMAC1_PG_INFO,
+ DBG_PSE_PG_LMAC2_GROUP,
+ DBG_PSE_LMAC2_PG_INFO,
+ DBG_PSE_PG_LMAC3_GROUP,
+ DBG_PSE_LMAC3_PG_INFO,
+ DBG_PSE_PG_MDP_GROUP,
+ DBG_PSE_MDP_PG_INFO,
+ DBG_PSE_PG_PLE1_GROUP,
+ DBG_PSE_PLE1_PG_INFO,
+ DBG_AGG_AALCR0,
+ DBG_AGG_AALCR1,
+ DBG_AGG_AALCR2,
+ DBG_AGG_AALCR3,
+ DBG_AGG_AALCR4,
+ DBG_AGG_B0BRR0,
+ DBG_AGG_B1BRR0,
+ DBG_AGG_B2BRR0,
+ DBG_AGG_B3BRR0,
+ DBG_AGG_AWSCR0,
+ DBG_AGG_PCR0,
+ DBG_AGG_TTCR0,
+ DBG_MIB_M0ARNG0,
+ DBG_MIB_M0DR2,
+ DBG_MIB_M0DR13,
+ __MT_DBG_REG_REV_MAX,
+};
+
+enum dbg_mask_rev {
+ DBG_MIB_M0SDR10_RX_MDRDY_COUNT,
+ DBG_MIB_M0SDR14_AMPDU,
+ DBG_MIB_M0SDR15_AMPDU_ACKED,
+ DBG_MIB_RX_FCS_ERROR_COUNT,
+ __MT_DBG_MASK_REV_MAX,
+};
+
+enum dbg_bit_rev {
+ __MT_DBG_BIT_REV_MAX,
+};
+
+static const u32 mt7915_dbg_base[] = {
+ [MT_DBG_WFDMA0_BASE] = 0xd4000,
+ [MT_DBG_WFDMA1_BASE] = 0xd5000,
+ [MT_DBG_WFDMA0_PCIE1_BASE] = 0xd8000,
+ [MT_DBG_WFDMA1_PCIE1_BASE] = 0xd9000,
+ [MT_DBG_WFDMA_EXT_CSR_BASE] = 0xd7000,
+ [MT_DBG_SWDEF_BASE] = 0x41f200,
+};
+
+static const u32 mt7916_dbg_base[] = {
+ [MT_DBG_WFDMA0_BASE] = 0xd4000,
+ [MT_DBG_WFDMA1_BASE] = 0xd5000,
+ [MT_DBG_WFDMA0_PCIE1_BASE] = 0xd8000,
+ [MT_DBG_WFDMA1_PCIE1_BASE] = 0xd9000,
+ [MT_DBG_WFDMA_EXT_CSR_BASE] = 0xd7000,
+ [MT_DBG_SWDEF_BASE] = 0x411400,
+};
+
+static const u32 mt7986_dbg_base[] = {
+ [MT_DBG_WFDMA0_BASE] = 0x24000,
+ [MT_DBG_WFDMA1_BASE] = 0x25000,
+ [MT_DBG_WFDMA0_PCIE1_BASE] = 0x28000,
+ [MT_DBG_WFDMA1_PCIE1_BASE] = 0x29000,
+ [MT_DBG_WFDMA_EXT_CSR_BASE] = 0x27000,
+ [MT_DBG_SWDEF_BASE] = 0x411400,
+};
+
+/* mt7915 regs with different base and offset */
+static const struct __dbg_reg mt7915_dbg_reg[] = {
+ [DBG_INT_SOURCE_CSR] = { MT_DBG_WFDMA_EXT_CSR_BASE, 0x10 },
+ [DBG_INT_MASK_CSR] = { MT_DBG_WFDMA_EXT_CSR_BASE, 0x14 },
+ [DBG_INT1_SOURCE_CSR] = { MT_DBG_WFDMA_EXT_CSR_BASE, 0x88 },
+ [DBG_INT1_MASK_CSR] = { MT_DBG_WFDMA_EXT_CSR_BASE, 0x8c },
+ [DBG_TX_RING_BASE] = { MT_DBG_WFDMA1_BASE, 0x400 },
+ [DBG_RX_EVENT_RING_BASE] = { MT_DBG_WFDMA1_BASE, 0x500 },
+ [DBG_RX_STS_RING_BASE] = { MT_DBG_WFDMA1_BASE, 0x510 },
+ [DBG_RX_DATA_RING_BASE] = { MT_DBG_WFDMA0_BASE, 0x500 },
+ [DBG_DMA_ICSC_FR0] = { DBG_INVALID_BASE, 0x0f0 },
+ [DBG_DMA_ICSC_FR1] = { DBG_INVALID_BASE, 0x0f4 },
+ [DBG_TMAC_ICSCR0] = { DBG_INVALID_BASE, 0x200 },
+ [DBG_RMAC_RXICSRPT] = { DBG_INVALID_BASE, 0x618},
+ [DBG_MIB_M0SDR0] = { DBG_INVALID_BASE, 0x010},
+ [DBG_MIB_M0SDR3] = { DBG_INVALID_BASE, 0x014},
+ [DBG_MIB_M0SDR4] = { DBG_INVALID_BASE, 0x018},
+ [DBG_MIB_M0SDR5] = { DBG_INVALID_BASE, 0x01c},
+ [DBG_MIB_M0SDR7] = { DBG_INVALID_BASE, 0x024},
+ [DBG_MIB_M0SDR8] = { DBG_INVALID_BASE, 0x028},
+ [DBG_MIB_M0SDR9] = { DBG_INVALID_BASE, 0x02C},
+ [DBG_MIB_M0SDR10] = { DBG_INVALID_BASE, 0x030},
+ [DBG_MIB_M0SDR11] = { DBG_INVALID_BASE, 0x034},
+ [DBG_MIB_M0SDR12] = { DBG_INVALID_BASE, 0x038},
+ [DBG_MIB_M0SDR14] = { DBG_INVALID_BASE, 0x040},
+ [DBG_MIB_M0SDR15] = { DBG_INVALID_BASE, 0x044},
+ [DBG_MIB_M0SDR16] = { DBG_INVALID_BASE, 0x048},
+ [DBG_MIB_M0SDR17] = { DBG_INVALID_BASE, 0x04c},
+ [DBG_MIB_M0SDR18] = { DBG_INVALID_BASE, 0x050},
+ [DBG_MIB_M0SDR19] = { DBG_INVALID_BASE, 0x054},
+ [DBG_MIB_M0SDR20] = { DBG_INVALID_BASE, 0x058},
+ [DBG_MIB_M0SDR21] = { DBG_INVALID_BASE, 0x05c},
+ [DBG_MIB_M0SDR22] = { DBG_INVALID_BASE, 0x060},
+ [DBG_MIB_M0SDR23] = { DBG_INVALID_BASE, 0x064},
+ [DBG_MIB_M0DR0] = { DBG_INVALID_BASE, 0x0a0},
+ [DBG_MIB_M0DR1] = { DBG_INVALID_BASE, 0x0a4},
+ [DBG_MIB_MUBF] = { DBG_INVALID_BASE, 0x090},
+ [DBG_MIB_M0DR6] = { DBG_INVALID_BASE, 0x0b8},
+ [DBG_MIB_M0DR7] = { DBG_INVALID_BASE, 0x0bc},
+ [DBG_MIB_M0DR8] = { DBG_INVALID_BASE, 0x0c0},
+ [DBG_MIB_M0DR9] = { DBG_INVALID_BASE, 0x0c4},
+ [DBG_MIB_M0DR10] = { DBG_INVALID_BASE, 0x0c8},
+ [DBG_MIB_M0DR11] = { DBG_INVALID_BASE, 0x0cc},
+ [DBG_MIB_M0DR12] = { DBG_INVALID_BASE, 0x160},
+ [DBG_WTBLON_WDUCR] = { DBG_INVALID_BASE, 0x0},
+ [DBG_UWTBL_WDUCR] = { DBG_INVALID_BASE, 0x0},
+ [DBG_PLE_DRR_TABLE_CTRL] = { DBG_INVALID_BASE, 0x388},
+ [DBG_PLE_DRR_TABLE_RDATA] = { DBG_INVALID_BASE, 0x350},
+ [DBG_PLE_PBUF_CTRL] = { DBG_INVALID_BASE, 0x014},
+ [DBG_PLE_QUEUE_EMPTY] = { DBG_INVALID_BASE, 0x0b0},
+ [DBG_PLE_FREEPG_CNT] = { DBG_INVALID_BASE, 0x100},
+ [DBG_PLE_FREEPG_HEAD_TAIL] = { DBG_INVALID_BASE, 0x104},
+ [DBG_PLE_PG_HIF_GROUP] = { DBG_INVALID_BASE, 0x110},
+ [DBG_PLE_HIF_PG_INFO] = { DBG_INVALID_BASE, 0x114},
+ [DBG_PLE_PG_HIF_TXCMD_GROUP] = { DBG_INVALID_BASE, 0x120},
+ [DBG_PLE_HIF_TXCMD_PG_INFO] = { DBG_INVALID_BASE, 0x124},
+ [DBG_PLE_PG_CPU_GROUP] = { DBG_INVALID_BASE, 0x150},
+ [DBG_PLE_CPU_PG_INFO] = { DBG_INVALID_BASE, 0x154},
+ [DBG_PLE_FL_QUE_CTRL] = { DBG_INVALID_BASE, 0x1b0},
+ [DBG_PLE_NATIVE_TXCMD_Q_EMPTY] = { DBG_INVALID_BASE, 0x22c},
+ [DBG_PLE_TXCMD_Q_EMPTY] = { DBG_INVALID_BASE, 0x230},
+ [DBG_PLE_AC_QEMPTY] = { DBG_INVALID_BASE, 0x500},
+ [DBG_PLE_AC_OFFSET] = { DBG_INVALID_BASE, 0x040},
+ [DBG_PLE_STATION_PAUSE] = { DBG_INVALID_BASE, 0x400},
+ [DBG_PLE_DIS_STA_MAP] = { DBG_INVALID_BASE, 0x440},
+ [DBG_PSE_PBUF_CTRL] = { DBG_INVALID_BASE, 0x014},
+ [DBG_PSE_FREEPG_CNT] = { DBG_INVALID_BASE, 0x100},
+ [DBG_PSE_FREEPG_HEAD_TAIL] = { DBG_INVALID_BASE, 0x104},
+ [DBG_PSE_HIF0_PG_INFO] = { DBG_INVALID_BASE, 0x114},
+ [DBG_PSE_PG_HIF1_GROUP] = { DBG_INVALID_BASE, 0x118},
+ [DBG_PSE_HIF1_PG_INFO] = { DBG_INVALID_BASE, 0x11c},
+ [DBG_PSE_PG_CPU_GROUP] = { DBG_INVALID_BASE, 0x150},
+ [DBG_PSE_CPU_PG_INFO] = { DBG_INVALID_BASE, 0x154},
+ [DBG_PSE_PG_PLE_GROUP] = { DBG_INVALID_BASE, 0x160},
+ [DBG_PSE_PLE_PG_INFO] = { DBG_INVALID_BASE, 0x164},
+ [DBG_PSE_PG_LMAC0_GROUP] = { DBG_INVALID_BASE, 0x170},
+ [DBG_PSE_LMAC0_PG_INFO] = { DBG_INVALID_BASE, 0x174},
+ [DBG_PSE_PG_LMAC1_GROUP] = { DBG_INVALID_BASE, 0x178},
+ [DBG_PSE_LMAC1_PG_INFO] = { DBG_INVALID_BASE, 0x17c},
+ [DBG_PSE_PG_LMAC2_GROUP] = { DBG_INVALID_BASE, 0x180},
+ [DBG_PSE_LMAC2_PG_INFO] = { DBG_INVALID_BASE, 0x184},
+ [DBG_PSE_PG_LMAC3_GROUP] = { DBG_INVALID_BASE, 0x188},
+ [DBG_PSE_LMAC3_PG_INFO] = { DBG_INVALID_BASE, 0x18c},
+ [DBG_PSE_PG_MDP_GROUP] = { DBG_INVALID_BASE, 0x198},
+ [DBG_PSE_MDP_PG_INFO] = { DBG_INVALID_BASE, 0x19c},
+ [DBG_PSE_PG_PLE1_GROUP] = { DBG_INVALID_BASE, 0x168},
+ [DBG_PSE_PLE1_PG_INFO] = { DBG_INVALID_BASE, 0x16c},
+ [DBG_AGG_AALCR0] = { DBG_INVALID_BASE, 0x048},
+ [DBG_AGG_AALCR1] = { DBG_INVALID_BASE, 0x04c},
+ [DBG_AGG_AALCR2] = { DBG_INVALID_BASE, 0x050},
+ [DBG_AGG_AALCR3] = { DBG_INVALID_BASE, 0x054},
+ [DBG_AGG_AALCR4] = { DBG_INVALID_BASE, 0x058},
+ [DBG_AGG_B0BRR0] = { DBG_INVALID_BASE, 0x100},
+ [DBG_AGG_B1BRR0] = { DBG_INVALID_BASE, 0x104},
+ [DBG_AGG_B2BRR0] = { DBG_INVALID_BASE, 0x108},
+ [DBG_AGG_B3BRR0] = { DBG_INVALID_BASE, 0x10c},
+ [DBG_AGG_AWSCR0] = { DBG_INVALID_BASE, 0x030},
+ [DBG_AGG_PCR0] = { DBG_INVALID_BASE, 0x040},
+ [DBG_AGG_TTCR0] = { DBG_INVALID_BASE, 0x04c},
+ [DBG_MIB_M0ARNG0] = { DBG_INVALID_BASE, 0x4b8},
+ [DBG_MIB_M0DR2] = { DBG_INVALID_BASE, 0x0a8},
+ [DBG_MIB_M0DR13] = { DBG_INVALID_BASE, 0x164},
+};
+
+/* mt7986/mt7916 regs with different base and offset */
+static const struct __dbg_reg mt7916_dbg_reg[] = {
+ [DBG_INT_SOURCE_CSR] = { MT_DBG_WFDMA0_BASE, 0x200 },
+ [DBG_INT_MASK_CSR] = { MT_DBG_WFDMA0_BASE, 0x204 },
+ [DBG_INT1_SOURCE_CSR] = { MT_DBG_WFDMA0_PCIE1_BASE, 0x200 },
+ [DBG_INT1_MASK_CSR] = { MT_DBG_WFDMA0_PCIE1_BASE, 0x204 },
+ [DBG_TX_RING_BASE] = { MT_DBG_WFDMA0_BASE, 0x400 },
+ [DBG_RX_EVENT_RING_BASE] = { MT_DBG_WFDMA0_BASE, 0x500 },
+ [DBG_RX_STS_RING_BASE] = { MT_DBG_WFDMA0_BASE, 0x520 },
+ [DBG_RX_DATA_RING_BASE] = { MT_DBG_WFDMA0_BASE, 0x540 },
+ [DBG_DMA_ICSC_FR0] = { DBG_INVALID_BASE, 0x05c },
+ [DBG_DMA_ICSC_FR1] = { DBG_INVALID_BASE, 0x060 },
+ [DBG_TMAC_ICSCR0] = { DBG_INVALID_BASE, 0x120 },
+ [DBG_RMAC_RXICSRPT] = { DBG_INVALID_BASE, 0xd0 },
+ [DBG_MIB_M0SDR0] = { DBG_INVALID_BASE, 0x7d8},
+ [DBG_MIB_M0SDR3] = { DBG_INVALID_BASE, 0x698},
+ [DBG_MIB_M0SDR4] = { DBG_INVALID_BASE, 0x788},
+ [DBG_MIB_M0SDR5] = { DBG_INVALID_BASE, 0x780},
+ [DBG_MIB_M0SDR7] = { DBG_INVALID_BASE, 0x5a8},
+ [DBG_MIB_M0SDR8] = { DBG_INVALID_BASE, 0x78c},
+ [DBG_MIB_M0SDR9] = { DBG_INVALID_BASE, 0x024},
+ [DBG_MIB_M0SDR10] = { DBG_INVALID_BASE, 0x76c},
+ [DBG_MIB_M0SDR11] = { DBG_INVALID_BASE, 0x790},
+ [DBG_MIB_M0SDR12] = { DBG_INVALID_BASE, 0x558},
+ [DBG_MIB_M0SDR14] = { DBG_INVALID_BASE, 0x564},
+ [DBG_MIB_M0SDR15] = { DBG_INVALID_BASE, 0x564},
+ [DBG_MIB_M0SDR16] = { DBG_INVALID_BASE, 0x7fc},
+ [DBG_MIB_M0SDR17] = { DBG_INVALID_BASE, 0x800},
+ [DBG_MIB_M0SDR18] = { DBG_INVALID_BASE, 0x030},
+ [DBG_MIB_M0SDR19] = { DBG_INVALID_BASE, 0x5ac},
+ [DBG_MIB_M0SDR20] = { DBG_INVALID_BASE, 0x5b0},
+ [DBG_MIB_M0SDR21] = { DBG_INVALID_BASE, 0x5b4},
+ [DBG_MIB_M0SDR22] = { DBG_INVALID_BASE, 0x770},
+ [DBG_MIB_M0SDR23] = { DBG_INVALID_BASE, 0x774},
+ [DBG_MIB_M0DR0] = { DBG_INVALID_BASE, 0x594},
+ [DBG_MIB_M0DR1] = { DBG_INVALID_BASE, 0x598},
+ [DBG_MIB_MUBF] = { DBG_INVALID_BASE, 0x7ac},
+ [DBG_MIB_M0DR6] = { DBG_INVALID_BASE, 0x658},
+ [DBG_MIB_M0DR7] = { DBG_INVALID_BASE, 0x65c},
+ [DBG_MIB_M0DR8] = { DBG_INVALID_BASE, 0x56c},
+ [DBG_MIB_M0DR9] = { DBG_INVALID_BASE, 0x570},
+ [DBG_MIB_M0DR10] = { DBG_INVALID_BASE, 0x578},
+ [DBG_MIB_M0DR11] = { DBG_INVALID_BASE, 0x574},
+ [DBG_MIB_M0DR12] = { DBG_INVALID_BASE, 0x654},
+ [DBG_WTBLON_WDUCR] = { DBG_INVALID_BASE, 0x200},
+ [DBG_UWTBL_WDUCR] = { DBG_INVALID_BASE, 0x094},
+ [DBG_PLE_DRR_TABLE_CTRL] = { DBG_INVALID_BASE, 0x490},
+ [DBG_PLE_DRR_TABLE_RDATA] = { DBG_INVALID_BASE, 0x470},
+ [DBG_PLE_PBUF_CTRL] = { DBG_INVALID_BASE, 0x004},
+ [DBG_PLE_QUEUE_EMPTY] = { DBG_INVALID_BASE, 0x360},
+ [DBG_PLE_FREEPG_CNT] = { DBG_INVALID_BASE, 0x380},
+ [DBG_PLE_FREEPG_HEAD_TAIL] = { DBG_INVALID_BASE, 0x384},
+ [DBG_PLE_PG_HIF_GROUP] = { DBG_INVALID_BASE, 0x00c},
+ [DBG_PLE_HIF_PG_INFO] = { DBG_INVALID_BASE, 0x388},
+ [DBG_PLE_PG_HIF_TXCMD_GROUP] = { DBG_INVALID_BASE, 0x014},
+ [DBG_PLE_HIF_TXCMD_PG_INFO] = { DBG_INVALID_BASE, 0x390},
+ [DBG_PLE_PG_CPU_GROUP] = { DBG_INVALID_BASE, 0x018},
+ [DBG_PLE_CPU_PG_INFO] = { DBG_INVALID_BASE, 0x394},
+ [DBG_PLE_FL_QUE_CTRL] = { DBG_INVALID_BASE, 0x3e0},
+ [DBG_PLE_NATIVE_TXCMD_Q_EMPTY] = { DBG_INVALID_BASE, 0x370},
+ [DBG_PLE_TXCMD_Q_EMPTY] = { DBG_INVALID_BASE, 0x36c},
+ [DBG_PLE_AC_QEMPTY] = { DBG_INVALID_BASE, 0x600},
+ [DBG_PLE_AC_OFFSET] = { DBG_INVALID_BASE, 0x080},
+ [DBG_PLE_STATION_PAUSE] = { DBG_INVALID_BASE, 0x100},
+ [DBG_PLE_DIS_STA_MAP] = { DBG_INVALID_BASE, 0x180},
+ [DBG_PSE_PBUF_CTRL] = { DBG_INVALID_BASE, 0x004},
+ [DBG_PSE_FREEPG_CNT] = { DBG_INVALID_BASE, 0x380},
+ [DBG_PSE_FREEPG_HEAD_TAIL] = { DBG_INVALID_BASE, 0x384},
+ [DBG_PSE_HIF0_PG_INFO] = { DBG_INVALID_BASE, 0x150},
+ [DBG_PSE_PG_HIF1_GROUP] = { DBG_INVALID_BASE, 0x154},
+ [DBG_PSE_HIF1_PG_INFO] = { DBG_INVALID_BASE, 0x160},
+ [DBG_PSE_PG_CPU_GROUP] = { DBG_INVALID_BASE, 0x118},
+ [DBG_PSE_CPU_PG_INFO] = { DBG_INVALID_BASE, 0x158},
+ [DBG_PSE_PG_PLE_GROUP] = { DBG_INVALID_BASE, 0x11c},
+ [DBG_PSE_PLE_PG_INFO] = { DBG_INVALID_BASE, 0x15c},
+ [DBG_PSE_PG_LMAC0_GROUP] = { DBG_INVALID_BASE, 0x124},
+ [DBG_PSE_LMAC0_PG_INFO] = { DBG_INVALID_BASE, 0x164},
+ [DBG_PSE_PG_LMAC1_GROUP] = { DBG_INVALID_BASE, 0x128},
+ [DBG_PSE_LMAC1_PG_INFO] = { DBG_INVALID_BASE, 0x168},
+ [DBG_PSE_PG_LMAC2_GROUP] = { DBG_INVALID_BASE, 0x12c},
+ [DBG_PSE_LMAC2_PG_INFO] = { DBG_INVALID_BASE, 0x16c},
+ [DBG_PSE_PG_LMAC3_GROUP] = { DBG_INVALID_BASE, 0x130},
+ [DBG_PSE_LMAC3_PG_INFO] = { DBG_INVALID_BASE, 0x17c},
+ [DBG_PSE_PG_MDP_GROUP] = { DBG_INVALID_BASE, 0x134},
+ [DBG_PSE_MDP_PG_INFO] = { DBG_INVALID_BASE, 0x174},
+ [DBG_PSE_PG_PLE1_GROUP] = { DBG_INVALID_BASE, 0x120},
+ [DBG_PSE_PLE1_PG_INFO] = { DBG_INVALID_BASE, 0x160},
+ [DBG_AGG_AALCR0] = { DBG_INVALID_BASE, 0x028},
+ [DBG_AGG_AALCR1] = { DBG_INVALID_BASE, 0x144},
+ [DBG_AGG_AALCR2] = { DBG_INVALID_BASE, 0x14c},
+ [DBG_AGG_AALCR3] = { DBG_INVALID_BASE, 0x154},
+ [DBG_AGG_AALCR4] = { DBG_INVALID_BASE, 0x02c},
+ [DBG_AGG_B0BRR0] = { DBG_INVALID_BASE, 0x08c},
+ [DBG_AGG_B1BRR0] = { DBG_INVALID_BASE, 0x148},
+ [DBG_AGG_B2BRR0] = { DBG_INVALID_BASE, 0x150},
+ [DBG_AGG_B3BRR0] = { DBG_INVALID_BASE, 0x158},
+ [DBG_AGG_AWSCR0] = { DBG_INVALID_BASE, 0x05c},
+ [DBG_AGG_PCR0] = { DBG_INVALID_BASE, 0x06c},
+ [DBG_AGG_TTCR0] = { DBG_INVALID_BASE, 0x07c},
+ [DBG_MIB_M0ARNG0] = { DBG_INVALID_BASE, 0x0b0},
+ [DBG_MIB_M0DR2] = { DBG_INVALID_BASE, 0x7dc},
+ [DBG_MIB_M0DR13] = { DBG_INVALID_BASE, 0x7ec},
+};
+
+static const struct __dbg_mask mt7915_dbg_mask[] = {
+ [DBG_MIB_M0SDR10_RX_MDRDY_COUNT]= {25, 0},
+ [DBG_MIB_M0SDR14_AMPDU] = {23, 0},
+ [DBG_MIB_M0SDR15_AMPDU_ACKED] = {23, 0},
+ [DBG_MIB_RX_FCS_ERROR_COUNT] = {15, 0},
+};
+
+static const struct __dbg_mask mt7916_dbg_mask[] = {
+ [DBG_MIB_M0SDR10_RX_MDRDY_COUNT]= {31, 0},
+ [DBG_MIB_M0SDR14_AMPDU] = {31, 0},
+ [DBG_MIB_M0SDR15_AMPDU_ACKED] = {31, 0},
+ [DBG_MIB_RX_FCS_ERROR_COUNT] = {31, 16},
+};
+
+/* used to differentiate between generations */
+struct mt7915_dbg_reg_desc {
+ const u32 id;
+ const u32 *base_rev;
+ const struct __dbg_reg *reg_rev;
+ const struct __dbg_mask *mask_rev;
+};
+
+static const struct mt7915_dbg_reg_desc dbg_reg_s[] = {
+ { 0x7915,
+ mt7915_dbg_base,
+ mt7915_dbg_reg,
+ mt7915_dbg_mask
+ },
+ { 0x7906,
+ mt7916_dbg_base,
+ mt7916_dbg_reg,
+ mt7916_dbg_mask
+ },
+ { 0x7986,
+ mt7986_dbg_base,
+ mt7916_dbg_reg,
+ mt7916_dbg_mask
+ },
+};
+
+struct bin_debug_hdr {
+ __le32 magic_num;
+ __le16 serial_id;
+ __le16 msg_type;
+ __le16 len;
+ __le16 des_len; /* descriptor len for rxd */
+} __packed;
+
+#define __DBG_REG_MAP(_dev, id, ofs) ((_dev)->dbg_reg->base_rev[(id)] + (ofs))
+#define __DBG_REG_BASE(_dev, id) ((_dev)->dbg_reg->reg_rev[(id)].base)
+#define __DBG_REG_OFFS(_dev, id) ((_dev)->dbg_reg->reg_rev[(id)].offs)
+
+#define __DBG_MASK(_dev, id) GENMASK((_dev)->dbg_reg->mask_rev[(id)].end, \
+ (_dev)->dbg_reg->mask_rev[(id)].start)
+#define __DBG_REG(_dev, id) __DBG_REG_MAP((_dev), __DBG_REG_BASE((_dev), (id)), \
+ __DBG_REG_OFFS((_dev), (id)))
+
+#define __DBG_FIELD_GET(id, _reg) (((_reg) & __DBG_MASK(dev, (id))) >> \
+ dev->dbg_reg->mask_rev[(id)].start)
+#define __DBG_FIELD_PREP(id, _reg) (((_reg) << dev->dbg_reg->mask_rev[(id)].start) & \
+ __DBG_MASK(dev, (id)))
+
+
+#define MT_DBG_TX_RING_BASE __DBG_REG(dev, DBG_TX_RING_BASE)
+#define MT_DBG_RX_EVENT_RING_BASE __DBG_REG(dev, DBG_RX_EVENT_RING_BASE)
+#define MT_DBG_RX_STS_RING_BASE __DBG_REG(dev, DBG_RX_STS_RING_BASE)
+#define MT_DBG_RX_DATA_RING_BASE __DBG_REG(dev, DBG_RX_DATA_RING_BASE)
+
+#define MT_DBG_TX_RING_CTRL(n) (MT_DBG_TX_RING_BASE + (0x10 * (n)))
+#define MT_DBG_RX_DATA_RING_CTRL(n) (MT_DBG_RX_DATA_RING_BASE + (0x10 * (n)))
+#define MT_DBG_RX_EVENT_RING_CTRL(n) (MT_DBG_RX_EVENT_RING_BASE + (0x10 * (n)))
+
+/* WFDMA COMMON */
+#define MT_DBG_INT_SOURCE_CSR __DBG_REG(dev, DBG_INT_SOURCE_CSR)
+#define MT_DBG_INT_MASK_CSR __DBG_REG(dev, DBG_INT_MASK_CSR)
+#define MT_DBG_INT1_SOURCE_CSR __DBG_REG(dev, DBG_INT1_SOURCE_CSR)
+#define MT_DBG_INT1_MASK_CSR __DBG_REG(dev, DBG_INT1_MASK_CSR)
+
+/* WFDMA0 */
+#define MT_DBG_WFDMA0(_ofs) __DBG_REG_MAP(dev, MT_DBG_WFDMA0_BASE, (_ofs))
+
+#define MT_DBG_WFDMA0_INT_SOURCE_CSR MT_DBG_WFDMA0(0x200)
+#define MT_DBG_WFDMA0_INT_MASK_CSR MT_DBG_WFDMA0(0x204)
+
+#define MT_DBG_WFDMA0_GLO_CFG MT_DBG_WFDMA0(0x208)
+#define MT_DBG_WFDMA0_GLO_CFG_TX_DMA_EN BIT(0)
+#define MT_DBG_WFDMA0_GLO_CFG_RX_DMA_EN BIT(2)
+#define MT_DBG_WFDMA0_GLO_CFG_TX_BUSY_MASK BIT(1)
+#define MT_DBG_WFDMA0_GLO_CFG_RX_BUSY_MASK BIT(3)
+
+
+/* WFDMA1 */
+#define MT_DBG_WFDMA1(_ofs) __DBG_REG_MAP(dev, MT_DBG_WFDMA1_BASE, (_ofs))
+#define MT_DBG_WFDMA1_INT_SOURCE_CSR MT_DBG_WFDMA1(0x200)
+#define MT_DBG_WFDMA1_INT_MASK_CSR MT_DBG_WFDMA1(0x204)
+
+#define MT_DBG_WFDMA1_GLO_CFG MT_DBG_WFDMA1(0x208)
+
+#define MT_DBG_WFDMA1_GLO_CFG_TX_DMA_EN BIT(0)
+#define MT_DBG_WFDMA1_GLO_CFG_RX_DMA_EN BIT(2)
+#define MT_DBG_WFDMA1_GLO_CFG_TX_BUSY_MASK BIT(1)
+#define MT_DBG_WFDMA1_GLO_CFG_RX_BUSY_MASK BIT(3)
+
+/* WFDMA0 PCIE1 */
+#define MT_DBG_WFDMA0_PCIE1(_ofs) __DBG_REG_MAP(dev, MT_DBG_WFDMA0_PCIE1_BASE, (_ofs))
+
+#define MT_DBG_WFDMA0_PCIE1_INT_SOURCE_CSR MT_DBG_WFDMA0_PCIE1(0x200)
+#define MT_DBG_WFDMA0_PCIE1_INT_MASK_CSR MT_DBG_WFDMA0_PCIE1(0x204)
+#define MT_DBG_WFDMA0_PCIE1_GLO_CFG MT_DBG_WFDMA0_PCIE1(0x208)
+#define MT_DBG_WFDMA0_PCIE1_RX1_CTRL0 MT_DBG_WFDMA1_PCIE1(0x510)
+
+#define MT_DBG_WFDMA0_PCIE1_GLO_CFG_TX_DMA_EN BIT(0)
+#define MT_DBG_WFDMA0_PCIE1_GLO_CFG_TX_BUSY_MASK BIT(1)
+#define MT_DBG_WFDMA0_PCIE1_GLO_CFG_RX_DMA_EN BIT(2)
+#define MT_DBG_WFDMA0_PCIE1_GLO_CFG_RX_BUSY_MASK BIT(3)
+
+/* WFDMA1 PCIE1 */
+#define MT_DBG_WFDMA1_PCIE1(_ofs) __DBG_REG_MAP(dev, MT_DBG_WFDMA1_PCIE1_BASE, (_ofs))
+#define MT_DBG_WFDMA1_PCIE1_INT_SOURCE_CSR MT_DBG_WFDMA1_PCIE1(0x200)
+#define MT_DBG_WFDMA1_PCIE1_INT_MASK_CSR MT_DBG_WFDMA1_PCIE1(0x204)
+#define MT_DBG_WFDMA1_PCIE1_GLO_CFG MT_DBG_WFDMA1_PCIE1(0x208)
+#define MT_DBG_WFDMA1_PCIE1_TX19_CTRL0 MT_DBG_WFDMA1_PCIE1(0x330)
+#define MT_DBG_WFDMA1_PCIE1_RX2_CTRL0 MT_DBG_WFDMA1_PCIE1(0x520)
+
+#define MT_DBG_WFDMA1_PCIE1_GLO_CFG_TX_DMA_EN BIT(0)
+#define MT_DBG_WFDMA1_PCIE1_GLO_CFG_TX_BUSY_MASK BIT(1)
+#define MT_DBG_WFDMA1_PCIE1_GLO_CFG_RX_DMA_EN BIT(2)
+#define MT_DBG_WFDMA1_PCIE1_GLO_CFG_RX_BUSY_MASK BIT(3)
+
+#define MT_DBG_WFDMA_HOST_DMA0_GLO_CFG_RX_DMA_EN_MASK BIT(2)
+#define MT_DBG_WFDMA_HOST_DMA0_GLO_CFG_TX_DMA_EN_MASK BIT(0)
+#define MT_DBG_WFDMA_HOST_DMA0_GLO_CFG_RX_DMA_BUSY_MASK BIT(3)
+#define MT_DBG_WFDMA_HOST_DMA0_GLO_CFG_TX_DMA_BUSY_MASK BIT(1)
+
+
+/* WF DMA TOP: band 0(0x820E7000),band 1(0x820F7000) */
+#define MT_DBG_WF_DMA_BASE(_band) ((_band) ? 0x820F7000 : 0x820E7000)
+#define MT_DBG_WF_DMA(_band, ofs) (MT_WF_DMA_BASE(_band) + (ofs))
+
+#define MT_DBG_DMA_DCR0(_band) MT_DBG_WF_DMA((_band), 0x000)
+#define MT_DBG_DMA_DCR0_MAX_RX_LEN GENMASK(15, 3)
+#define MT_DBG_DMA_DCR0_RXD_G5_EN BIT(23)
+
+#define MT_DBG_DMA_ICSC_FR0(_band) MT_DBG_WF_DMA((_band), __DBG_REG_OFFS(dev, DBG_DMA_ICSC_FR0))
+#define MT_DBG_DMA_ICSC_FR0_RXBF_EN BIT(25)
+#define MT_DBG_DMA_ICSC_FR0_EN BIT(24)
+#define MT_DBG_DMA_ICSC_FR0_TOUT_MASK GENMASK(23, 16)
+#define MT_DBG_DMA_ICSC_FR0_PID_MASK GENMASK(9, 8)
+#define MT_DBG_DMA_ICSC_FR0_QID_MASK GENMASK(6, 0)
+
+#define MT_DBG_DMA_ICSC_FR1(_band) MT_DBG_WF_DMA((_band), __DBG_REG_OFFS(dev, DBG_DMA_ICSC_FR1))
+#define MT_DBG_DMA_ICSC_FR1_AGG_SIZE_MASK GENMASK(26, 16)
+#define MT_DBG_DMA_ICSC_FR1_MAX_FRAME_SIZE_MASK GENMASK(10, 0)
+
+/* TMAC: band 0(0x820e4000), band 1(0x820f4000) */
+#define MT_DBG_WF_TMAC_BASE(_band) ((_band) ? 0x820f4000 : 0x820e4000)
+#define MT_DBG_WF_TMAC(_band, ofs) (MT_DBG_WF_TMAC_BASE(_band) + (ofs))
+
+#define MT_DBG_TMAC_ICSCR0(_band) MT_DBG_WF_TMAC((_band), __DBG_REG_OFFS(dev, DBG_TMAC_ICSCR0))
+#define MT_DBG_TMAC_ICSCR0_ICSRPT_EN BIT(0)
+
+/* RMAC: band 0(0x820E5000), band 1(0x820f5000) */
+#define MT_DBG_WF_RMAC_BASE(_band) ((_band) ? 0x820f5000 : 0x820E5000)
+#define MT_DBG_WF_RMAC(_band, ofs) (MT_DBG_WF_RMAC_BASE(_band) + (ofs))
+
+#define MT_DBG_RMAC_RXICSRPT(_band) MT_DBG_WF_RMAC((_band), __DBG_REG_OFFS(dev, DBG_RMAC_RXICSRPT))
+#define MT_DBG_RMAC_RXICSRPT_ICSRPT_EN BIT(0)
+
+/* MIB: band 0(0x820ed000), band 1(0x820fd000) */
+#define MT_DBG_MIB_BASE(_band) ((_band) ? 0x820fd000 : 0x820ed000)
+#define MT_DBG_MIB(_band, ofs) (MT_DBG_MIB_BASE(_band) + (ofs))
+
+
+#define MT_DBG_MIB_M0SCR0(_band) MT_DBG_MIB((_band), 0x00)
+#define MT_DBG_MIB_M0PBSCR(_band) MT_DBG_MIB((_band), 0x04)
+
+#define MT_DBG_MIB_M0SDR0(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR0))
+#define MT_DBG_MIB_M0SDR3(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR3))
+#define MT_DBG_MIB_RX_FCS_ERROR_COUNT_MASK __DBG_MASK(dev, DBG_MIB_RX_FCS_ERROR_COUNT)
+#define MT_DBG_MIB_M0SDR4(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR4))
+#define MT_DBG_MIB_M0SDR5(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR5))
+#define MT_DBG_MIB_M0SDR6(_band) MT_DBG_MIB((_band), 0x20)
+#define MT_DBG_MIB_M0SDR7(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR7))
+#define MT_DBG_MIB_M0SDR8(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR8))
+#define MT_DBG_MIB_M0SDR9(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR9))
+#define MT_DBG_MIB_M0SDR10(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR10))
+#define MT_DBG_MIB_M0SDR10_RX_MDRDY_COUNT_MASK __DBG_MASK(dev, DBG_MIB_M0SDR10_RX_MDRDY_COUNT)
+#define MT_DBG_MIB_M0SDR11(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR11))
+
+#define MT_DBG_MIB_M0SDR12(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR12))
+
+#define MT_DBG_MIB_M0SDR14(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR14))
+#define MT_DBG_MIB_M0SDR14_AMPDU_MASK __DBG_MASK(dev, DBG_MIB_M0SDR14_AMPDU)
+#define MT_DBG_MIB_M0SDR15(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR15))
+#define MT_DBG_MIB_M0SDR15_AMPDU_ACKED_MASK __DBG_MASK(dev, DBG_MIB_M0SDR15_AMPDU_ACKED)
+#define MT_DBG_MIB_M0SDR16(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR16))
+#define MT_DBG_MIB_M0SDR17(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR17))
+#define MT_DBG_MIB_M0SDR18(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR18))
+#define MT_DBG_MIB_M0SDR19(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR19))
+#define MT_DBG_MIB_M0SDR20(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR20))
+#define MT_DBG_MIB_M0SDR21(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR21))
+#define MT_DBG_MIB_M0SDR22(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR22))
+#define MT_DBG_MIB_M0SDR23(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0SDR23))
+#define MT_DBG_MIB_M0DR0(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0DR0))
+#define MT_DBG_MIB_M0DR1(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0DR1))
+
+#define MT_DBG_MIB_MUBF(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_MUBF))
+#define MT_DBG_MIB_M0DR6(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0DR6))
+#define MT_DBG_MIB_M0DR7(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0DR7))
+#define MT_DBG_MIB_M0DR8(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0DR8))
+#define MT_DBG_MIB_M0DR9(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0DR9))
+#define MT_DBG_MIB_M0DR10(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0DR10))
+#define MT_DBG_MIB_M0DR11(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0DR11))
+ #define MT_DBG_MIB_M0DR12(_band) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0DR12))
+
+/* WTBLON TOP: 0x820D4000/pcie(0x34000) rbus(0x434000) */
+#define MT_DBG_WTBLON_TOP_BASE 0x820D4000
+#define MT_DBG_WTBLON_TOP(ofs) (MT_WTBLON_TOP_BASE + (ofs))
+#define MT_DBG_WTBLON_TOP_WDUCR MT_DBG_WTBLON_TOP(__DBG_REG_OFFS(dev, DBG_WTBLON_WDUCR))
+#define MT_DBG_WTBLON_TOP_WDUCR_GROUP GENMASK(2, 0)
+
+#define WF_WTBLON_TOP_B0BTCRn_ADDR (MT_DBG_WTBLON_TOP_BASE + 0x1000) // 5000
+#define WF_WTBLON_TOP_B0BTBCRn_ADDR (MT_DBG_WTBLON_TOP_BASE + 0x1010) // 5010
+#define WF_WTBLON_TOP_B0BRCRn_ADDR (MT_DBG_WTBLON_TOP_BASE + 0x1020) // 5020
+#define WF_WTBLON_TOP_B0BRBCRn_ADDR (MT_DBG_WTBLON_TOP_BASE + 0x1030) // 5030
+#define WF_WTBLON_TOP_B0BTDCRn_ADDR (MT_DBG_WTBLON_TOP_BASE + 0x1040) // 5040
+#define WF_WTBLON_TOP_B0BRDCRn_ADDR (MT_DBG_WTBLON_TOP_BASE + 0x1050) // 5050
+#define WF_WTBLON_TOP_B0MBTCRn_ADDR (MT_DBG_WTBLON_TOP_BASE + 0x1100) // 5100
+#define WF_WTBLON_TOP_B0MBTBCRn_ADDR (MT_DBG_WTBLON_TOP_BASE + 0x1140) // 5140
+#define WF_WTBLON_TOP_B0MBRCRn_ADDR (MT_DBG_WTBLON_TOP_BASE + 0x1180) // 5180
+#define WF_WTBLON_TOP_B0MBRBCRn_ADDR (MT_DBG_WTBLON_TOP_BASE + 0x11C0) // 51C0
+
+#define WF_WTBLON_TOP_B1BTCRn_ADDR (MT_DBG_WTBLON_TOP_BASE + 0x1800) // 5800
+
+/* WTBLON TOP: 0x820C4000/pcie(0xa8000) rbus(0x4a8000) */
+#define MT_DBG_UWTBL_TOP_BASE 0x820C4000
+#define MT_DBG_UWTBL_TOP(ofs) (MT_DBG_UWTBL_TOP_BASE + (ofs))
+
+#define MT_DBG_UWTBL_TOP_WDUCR MT_DBG_WTBLON_TOP(__DBG_REG_OFFS(dev, DBG_UWTBL_WDUCR))
+
+#define MT_UWTBL_TOP_WDUCR_TARGET BIT(31)
+#define MT_UWTBL_TOP_WDUCR_GROUP GENMASK(3, 0)
+
+
+/* WTBL : 0x820D8000/pcie(0x38000) rbus(0x438000) */
+#define MT_DBG_WTBL_BASE 0x820D8000
+
+/* PLE related CRs. */
+#define MT_DBG_PLE_BASE 0x820C0000
+#define MT_DBG_PLE(ofs) (MT_DBG_PLE_BASE + (ofs))
+
+#define MT_DBG_PLE_DRR_TAB_CTRL MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_DRR_TABLE_CTRL))
+#define MT_DBG_PLE_DRR_TAB_RD_OFS __DBG_REG_OFFS(dev, DBG_PLE_DRR_TABLE_RDATA)
+
+#define MT_DBG_PLE_DRR_TABLE_RDATA0 MT_DBG_PLE(MT_DBG_PLE_DRR_TAB_RD_OFS + 0x0)
+#define MT_DBG_PLE_DRR_TABLE_RDATA1 MT_DBG_PLE(MT_DBG_PLE_DRR_TAB_RD_OFS + 0x4)
+#define MT_DBG_PLE_DRR_TABLE_RDATA2 MT_DBG_PLE(MT_DBG_PLE_DRR_TAB_RD_OFS + 0x8)
+#define MT_DBG_PLE_DRR_TABLE_RDATA3 MT_DBG_PLE(MT_DBG_PLE_DRR_TAB_RD_OFS + 0xc)
+#define MT_DBG_PLE_DRR_TABLE_RDATA4 MT_DBG_PLE(MT_DBG_PLE_DRR_TAB_RD_OFS + 0x10)
+#define MT_DBG_PLE_DRR_TABLE_RDATA5 MT_DBG_PLE(MT_DBG_PLE_DRR_TAB_RD_OFS + 0x14)
+#define MT_DBG_PLE_DRR_TABLE_RDATA6 MT_DBG_PLE(MT_DBG_PLE_DRR_TAB_RD_OFS + 0x18)
+#define MT_DBG_PLE_DRR_TABLE_RDATA7 MT_DBG_PLE(MT_DBG_PLE_DRR_TAB_RD_OFS+ 0x1c)
+
+#define MT_DBG_PLE_PBUF_CTRL_ADDR MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_PBUF_CTRL))
+#define MT_DBG_PLE_QUEUE_EMPTY MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_QUEUE_EMPTY))
+#define MT_DBG_PLE_FREEPG_CNT MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_FREEPG_CNT))
+#define MT_DBG_PLE_FREEPG_HEAD_TAIL MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_FREEPG_HEAD_TAIL))
+#define MT_DBG_PLE_PG_HIF_GROUP MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_PG_HIF_GROUP))
+#define MT_DBG_PLE_HIF_PG_INFO MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_HIF_PG_INFO))
+#define MT_DBG_PLE_PG_HIF_TXCMD_GROUP MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_PG_HIF_TXCMD_GROUP))
+#define MT_DBG_PLE_HIF_TXCMD_PG_INFO MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_HIF_TXCMD_PG_INFO))
+#define MT_DBG_PLE_PG_CPU_GROUP MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_PG_CPU_GROUP))
+#define MT_DBG_PLE_CPU_PG_INFO MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_CPU_PG_INFO))
+#define PLE_FL_QUE_CTRL_OFFSET __DBG_REG_OFFS(dev, DBG_PLE_FL_QUE_CTRL)
+#define MT_DBG_PLE_FL_QUE_CTRL0 MT_DBG_PLE(PLE_FL_QUE_CTRL_OFFSET + 0x0)
+#define MT_DBG_PLE_FL_QUE_CTRL1 MT_DBG_PLE(PLE_FL_QUE_CTRL_OFFSET + 0x4)
+#define MT_DBG_PLE_FL_QUE_CTRL2 MT_DBG_PLE(PLE_FL_QUE_CTRL_OFFSET + 0x8)
+#define MT_DBG_PLE_FL_QUE_CTRL3 MT_DBG_PLE(PLE_FL_QUE_CTRL_OFFSET + 0xc)
+#define MT_DBG_PLE_NATIVE_TXCMD_Q_EMPTY MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_NATIVE_TXCMD_Q_EMPTY))
+#define MT_DBG_PLE_TXCMD_Q_EMPTY MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_TXCMD_Q_EMPTY))
+
+#define MT_DBG_PLE_PBUF_CTRL_PAGE_SIZE_MASK BIT(31)
+#define MT_DBG_PLE_PBUF_CTRL_OFFSET_MASK GENMASK(25, 17)
+#define MT_DBG_PLE_PBUF_CTRL_TOTAL_PAGE_NUM_MASK GENMASK(11, 0)
+
+#define MT_DBG_PLE_FREEPG_CNT_FREEPG_CNT_MASK GENMASK(11, 0)
+#define MT_DBG_PLE_FREEPG_CNT_FFA_CNT_MASK GENMASK(27, 16)
+#define MT_DBG_PLE_FREEPG_HEAD_TAIL_FREEPG_TAIL_MASK GENMASK(27, 16)
+#define MT_DBG_PLE_FREEPG_HEAD_TAIL_FREEPG_HEAD_MASK GENMASK(11, 0)
+#define MT_DBG_PLE_PG_HIF_GROUP_HIF_MAX_QUOTA_MASK GENMASK(27, 16)
+#define MT_DBG_PLE_PG_HIF_GROUP_HIF_MIN_QUOTA_MASK GENMASK(11, 0)
+
+#define MT_DBG_PLE_HIF_PG_INFO_HIF_SRC_CNT_MASK GENMASK(27, 16)
+#define MT_DBG_PLE_HIF_PG_INFO_HIF_RSV_CNT_MASK GENMASK(11, 0)
+
+#define MT_DBG_PLE_PG_HIF_TXCMD_GROUP_HIF_TXCMD_MAX_QUOTA_MASK GENMASK(27, 16)
+#define MT_DBG_PLE_PG_HIF_TXCMD_GROUP_HIF_TXCMD_MIN_QUOTA_MASK GENMASK(11, 0)
+
+#define MT_DBG_PLE_HIF_TXCMD_PG_INFO_HIF_TXCMD_SRC_CNT_MASK GENMASK(27, 16)
+#define MT_DBG_PLE_HIF_TXCMD_PG_INFO_HIF_TXCMD_RSV_CNT_MASK GENMASK(11, 0)
+
+#define MT_DBG_PLE_TXCMD_PG_INFO_HIF_TXCMD_SRC_CNT_MASK GENMASK(27, 16)
+#define MT_DBG_PLE_TXCMD_PG_INFO_HIF_TXCMD_RSV_CNT_MASK GENMASK(11, 0)
+
+#define MT_DBG_PLE_PG_CPU_GROUP_CPU_MAX_QUOTA_MASK GENMASK(27, 16)
+#define MT_DBG_PLE_PG_CPU_GROUP_CPU_MIN_QUOTA_MASK GENMASK(11, 0)
+
+#define MT_DBG_PLE_CPU_PG_INFO_CPU_SRC_CNT_MASK GENMASK(27, 16)
+#define MT_DBG_PLE_CPU_PG_INFO_CPU_RSV_CNT_MASK GENMASK(11, 0)
+
+#define MT_DBG_PLE_Q_EMPTY_ALL_AC_EMPTY_MASK BIT(24)
+#define MT_DBG_PLE_FL_QUE_CTRL0_EXECUTE_MASK BIT(31)
+#define MT_DBG_PLE_FL_QUE_CTRL0_Q_BUF_QID_MASK GENMASK(30, 24)
+
+#define MT_PLE_FL_QUE_CTRL0_Q_BUF_QID_SHFT 24
+#define MT_PLE_FL_QUE_CTRL0_Q_BUF_PID_SHFT 10
+
+#define MT_DBG_PLE_FL_QUE_CTRL2_Q_TAIL_FID_MASK GENMASK(27, 16)
+#define MT_DBG_PLE_FL_QUE_CTRL2_Q_HEAD_FID_MASK GENMASK(11, 0)
+#define MT_DBG_PLE_FL_QUE_CTRL3_Q_PKT_NUM_MASK GENMASK(11, 0)
+
+#define MT_DBG_PLE_STATION_PAUSE(n) MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_STATION_PAUSE) + ((n) << 2))
+#define MT_DBG_PLE_DIS_STA_MAP(n) MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_DIS_STA_MAP) + ((n) << 2))
+#define MT_DBG_PLE_AC_QEMPTY(ac, n) MT_DBG_PLE(__DBG_REG_OFFS(dev, DBG_PLE_AC_QEMPTY) + \
+ __DBG_REG_OFFS(dev, DBG_PLE_AC_OFFSET) * (ac) + ((n) << 2))
+
+#define MT_DBG_PLE_AMSDU_PACK_MSDU_CNT(n) MT_DBG_PLE(0x10e0 + ((n) << 2))
+
+/* pseinfo related CRs. */
+#define MT_DBG_PSE_BASE 0x820C8000
+#define MT_DBG_PSE(ofs) (MT_DBG_PSE_BASE + (ofs))
+
+#define MT_DBG_PSE_PBUF_CTRL MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_PBUF_CTRL))
+#define MT_DBG_PSE_QUEUE_EMPTY MT_DBG_PSE(0x0b0)
+#define MT_DBG_PSE_FREEPG_CNT MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_FREEPG_CNT))
+#define MT_DBG_PSE_FREEPG_HEAD_TAIL MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_FREEPG_HEAD_TAIL))
+#define MT_DBG_PSE_PG_HIF0_GROUP MT_DBG_PSE(0x110)
+#define MT_DBG_PSE_HIF0_PG_INFO MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_HIF0_PG_INFO))
+#define MT_DBG_PSE_PG_HIF1_GROUP MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_PG_HIF1_GROUP))
+#define MT_DBG_PSE_HIF1_PG_INFO MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_HIF1_PG_INFO))
+#define MT_DBG_PSE_PG_CPU_GROUP MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_PG_CPU_GROUP))
+#define MT_DBG_PSE_CPU_PG_INFO MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_CPU_PG_INFO))
+#define MT_DBG_PSE_PG_LMAC0_GROUP MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_PG_LMAC0_GROUP))
+#define MT_DBG_PSE_LMAC0_PG_INFO MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_LMAC0_PG_INFO))
+#define MT_DBG_PSE_PG_LMAC1_GROUP MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_PG_LMAC1_GROUP))
+#define MT_DBG_PSE_LMAC1_PG_INFO MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_LMAC1_PG_INFO))
+#define MT_DBG_PSE_PG_LMAC2_GROUP MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_PG_LMAC2_GROUP))
+#define MT_DBG_PSE_LMAC2_PG_INFO MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_LMAC2_PG_INFO))
+#define MT_DBG_PSE_PG_PLE_GROUP MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_PG_PLE_GROUP))
+#define MT_DBG_PSE_PLE_PG_INFO MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_PLE_PG_INFO))
+#define MT_DBG_PSE_PG_LMAC3_GROUP MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_PG_LMAC3_GROUP))
+#define MT_DBG_PSE_LMAC3_PG_INFO MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_LMAC3_PG_INFO))
+#define MT_DBG_PSE_PG_MDP_GROUP MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_PG_MDP_GROUP))
+#define MT_DBG_PSE_MDP_PG_INFO MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_MDP_PG_INFO))
+#define MT_DBG_PSE_PG_PLE1_GROUP MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_PG_PLE1_GROUP))
+#define MT_DBG_PSE_PLE1_PG_INFO MT_DBG_PSE(__DBG_REG_OFFS(dev, DBG_PSE_PLE1_PG_INFO))
+
+#define MT_DBG_PSE_PBUF_CTRL_PAGE_SIZE_CFG_MASK BIT(31)
+#define MT_DBG_PSE_PBUF_CTRL_PBUF_OFFSET_MASK GENMASK(25, 17)
+#define MT_DBG_PSE_PBUF_CTRL_TOTAL_PAGE_NUM_MASK GENMASK(11, 0)
+#define MT_DBG_PSE_QUEUE_EMPTY_RLS_Q_EMTPY_MASK BIT(31)
+#define MT_DBG_PSE_QUEUE_EMPTY_MDP_RXIOC_QUEUE_EMPTY_MASK BIT(23)
+#define MT_DBG_PSE_QUEUE_EMPTY_MDP_TXIOC_QUEUE_EMPTY_MASK BIT(22)
+#define MT_DBG_PSE_QUEUE_EMPTY_SFD_PARK_QUEUE_EMPTY_MASK BIT(21)
+#define MT_DBG_PSE_QUEUE_EMPTY_SEC_RX_QUEUE_EMPTY_SHFT BIT(20)
+#define MT_DBG_PSE_QUEUE_EMPTY_SEC_TX_QUEUE_EMPTY_MASK BIT(19)
+#define MT_DBG_PSE_QUEUE_EMPTY_MDP_RX_QUEUE_EMPTY_MASK BIT(18)
+#define MT_DBG_PSE_QUEUE_EMPTY_MDP_TX_QUEUE_EMPTY_MASK BIT(17)
+#define MT_DBG_PSE_QUEUE_EMPTY_LMAC_TX_QUEUE_EMPTY_MASK BIT(16)
+#define MT_DBG_PSE_QUEUE_EMPTY_HIF_5_EMPTY_MASK BIT(13)
+#define MT_DBG_PSE_QUEUE_EMPTY_HIF_4_EMPTY_MASK BIT(12)
+#define MT_DBG_PSE_QUEUE_EMPTY_HIF_3_EMPTY_MASK BIT(11)
+#define MT_DBG_PSE_QUEUE_EMPTY_HIF_2_EMPTY_MASK BIT(10)
+#define MT_DBG_PSE_QUEUE_EMPTY_HIF_1_EMPTY_MASK BIT(9)
+#define MT_DBG_PSE_QUEUE_EMPTY_HIF_0_EMPTY_MASK BIT(8)
+#define MT_DBG_PSE_QUEUE_EMPTY_CPU_Q3_EMPTY_MASK BIT(3)
+#define MT_DBG_PSE_QUEUE_EMPTY_CPU_Q2_EMPTY_MASK BIT(2)
+#define MT_DBG_PSE_QUEUE_EMPTY_CPU_Q1_EMPTY_MASK BIT(1)
+#define MT_DBG_PSE_QUEUE_EMPTY_CPU_Q0_EMPTY_MASK BIT(0)
+#define MT_DBG_PSE_FREEPG_CNT_FFA_CNT_MASK GENMASK(27, 16)
+#define MT_DBG_PSE_FREEPG_CNT_FREEPG_CNT_MASK GENMASK(11, 0)
+#define MT_DBG_PSE_FREEPG_HEAD_TAIL_FREEPG_TAIL_MASK GENMASK(27, 16)
+#define MT_DBG_PSE_FREEPG_HEAD_TAIL_FREEPG_HEAD_MASK GENMASK(11, 0)
+#define MT_DBG_PSE_PG_HIF0_GROUP_HIF0_MAX_QUOTA_MASK GENMASK(27, 16)
+#define MT_DBG_PSE_PG_HIF0_GROUP_HIF0_MIN_QUOTA_MASK GENMASK(11, 0)
+#define MT_DBG_PSE_PG_HIF0_GROUP_HIF0_MAX_QUOTA_MASK GENMASK(27, 16)
+#define MT_DBG_PSE_PG_HIF0_GROUP_HIF0_MIN_QUOTA_MASK GENMASK(11, 0)
+#define MT_DBG_PSE_HIF0_PG_INFO_HIF0_SRC_CNT_MASK GENMASK(27, 16)
+#define MT_DBG_PSE_HIF0_PG_INFO_HIF0_RSV_CNT_MASK GENMASK(11, 0)
+#define MT_DBG_PSE_PG_HIF1_GROUP_HIF1_MAX_QUOTA_MASK GENMASK(27, 16)
+#define MT_DBG_PSE_PG_HIF1_GROUP_HIF1_MIN_QUOTA_MASK GENMASK(11, 0)
+#define MT_DBG_PSE_HIF1_PG_INFO_HIF1_SRC_CNT_MASK GENMASK(27, 16)
+#define MT_DBG_PSE_HIF1_PG_INFO_HIF1_RSV_CNT_MASK GENMASK(11, 0)
+#define MT_DBG_PSE_CPU_PG_INFO_CPU_SRC_CNT_MASK GENMASK(27, 16)
+#define MT_DBG_PSE_CPU_PG_INFO_CPU_RSV_CNT_MASK GENMASK(11, 0)
+#define MT_DBG_PSE_PG_PLE_GROUP_PLE_MAX_QUOTA_MASK GENMASK(27, 16)
+#define MT_DBG_PSE_PG_PLE_GROUP_PLE_MIN_QUOTA_MASK GENMASK(11, 0)
+#define MT_DBG_PSE_PG_CPU_GROUP_CPU_MAX_QUOTA_MASK GENMASK(27, 16)
+#define MT_DBG_PSE_PG_CPU_GROUP_CPU_MIN_QUOTA_MASK GENMASK(11, 0)
+#define MT_DBG_PSE_PLE_PG_INFO_PLE_SRC_CNT_MASK GENMASK(27, 16)
+#define MT_DBG_PSE_PLE_PG_INFO_PLE_RSV_CNT_MASK GENMASK(11, 0)
+#define MT_DBG_PSE_PG_LMAC0_GROUP_LMAC0_MAX_QUOTA_MASK GENMASK(27, 16)
+#define MT_DBG_PSE_PG_LMAC0_GROUP_LMAC0_MIN_QUOTA_MASK GENMASK(11, 0)
+#define MT_DBG_PSE_LMAC0_PG_INFO_LMAC0_SRC_CNT_MASK GENMASK(27, 16)
+#define MT_DBG_PSE_LMAC0_PG_INFO_LMAC0_RSV_CNT_MASK GENMASK(11, 0)
+#define MT_DBG_PSE_PG_LMAC1_GROUP_LMAC1_MAX_QUOTA_MASK GENMASK(27, 16)
+#define MT_DBG_TOP_PG_LMAC1_GROUP_LMAC1_MIN_QUOTA_MASK GENMASK(11, 0)
+#define MT_DBG_PSE_LMAC1_PG_INFO_LMAC1_SRC_CNT_MASK GENMASK(27, 16)
+#define MT_DBG_PSE_LMAC1_PG_INFO_LMAC1_RSV_CNT_MASK GENMASK(11, 0)
+#define MT_DBG_PSE_PG_LMAC2_GROUP_LMAC2_MAX_QUOTA_MASK GENMASK(27, 16)
+#define MT_DBG_PSE_PG_LMAC2_GROUP_LMAC2_MIN_QUOTA_MASK GENMASK(11, 0)
+#define MT_DBG_PSE_LMAC2_PG_INFO_LMAC2_SRC_CNT_MASK GENMASK(27, 16)
+#define MT_DBG_PSE_LMAC2_PG_INFO_LMAC2_RSV_CNT_MASK GENMASK(11, 0)
+#define MT_DBG_PSE_PG_LMAC3_GROUP_LMAC3_MAX_QUOTA_MASK GENMASK(27, 16)
+#define MT_DBG_TOP_PG_LMAC3_GROUP_LMAC3_MIN_QUOTA_MASK GENMASK(11, 0)
+#define MT_DBG_PSE_LMAC3_PG_INFO_LMAC3_SRC_CNT_MASK GENMASK(27, 16)
+#define MT_DBG_PSE_LMAC3_PG_INFO_LMAC3_RSV_CNT_MASK GENMASK(11, 0)
+#define MT_DBG_PSE_PG_LMAC3_GROUP_LMAC3_MAX_QUOTA_MASK GENMASK(27, 16)
+#define MT_DBG_TOP_PG_LMAC3_GROUP_LMAC3_MIN_QUOTA_MASK GENMASK(11, 0)
+#define MT_DBG_PSE_PG_MDP_GROUP_MDP_MAX_QUOTA_MASK GENMASK(27, 16)
+#define MT_DBG_PSE_PG_MDP_GROUP_MDP_MIN_QUOTA_MASK GENMASK(11, 0)
+#define MT_DBG_PSE_MDP_PG_INFO_MDP_SRC_CNT_MASK GENMASK(27, 16)
+#define MT_DBG_PSE_MDP_PG_INFO_MDP_RSV_CNT_MASK GENMASK(11, 0)
+
+#define MT_DBG_PSE_FL_QUE_CTRL_0_ADDR MT_DBG_PLE(0x1b0)
+#define MT_DBG_PSE_FL_QUE_CTRL_0_EXECUTE_MASK BIT(31)
+#define MT_DBG_PSE_FL_QUE_CTRL_0_Q_BUF_QID_SHFT 24
+#define MT_DBG_PSE_FL_QUE_CTRL_0_Q_BUF_PID_SHFT 10
+#define MT_DBG_PSE_FL_QUE_CTRL_0_Q_BUF_WLANID_MASK GENMASK(9, 0)
+
+#define MT_DBG_PSE_FL_QUE_CTRL_2_ADDR MT_DBG_PLE(0x1b8)
+#define MT_DBG_PSE_FL_QUE_CTRL_2_QUEUE_TAIL_FID_MASK GENMASK(27, 16)
+#define MT_DBG_PSE_FL_QUE_CTRL_2_QUEUE_HEAD_FID_MASK GENMASK(11, 0)
+
+#define MT_DBG_PSE_FL_QUE_CTRL_3_ADDR MT_DBG_PLE(0x1bc)
+#define MT_DBG_PSE_FL_QUE_CTRL_3_QUEUE_PKT_NUM_MASK GENMASK(11, 0)
+
+
+/* AGG */
+#define MT_DBG_AGG_BASE(_band) ((_band) ? 0x820f2000 : 0x820e2000)
+#define MT_DBG_AGG(_band, ofs) (MT_DBG_AGG_BASE(_band) + (ofs))
+
+#define MT_DBG_AGG_AALCR0(_band) MT_DBG_AGG((_band), __DBG_REG_OFFS(dev, DBG_AGG_AALCR0))
+#define MT_DBG_AGG_AALCR1(_band) MT_DBG_AGG((_band), __DBG_REG_OFFS(dev, DBG_AGG_AALCR1))
+#define MT_DBG_AGG_AALCR2(_band) MT_DBG_AGG((_band), __DBG_REG_OFFS(dev, DBG_AGG_AALCR2))
+#define MT_DBG_AGG_AALCR3(_band) MT_DBG_AGG((_band), __DBG_REG_OFFS(dev, DBG_AGG_AALCR3))
+#define MT_DBG_AGG_AALCR4(_band) MT_DBG_AGG((_band), __DBG_REG_OFFS(dev, DBG_AGG_AALCR4))
+#define MT_DBG_AGG_B0BRR0(_band) MT_DBG_AGG((_band), __DBG_REG_OFFS(dev, DBG_AGG_B0BRR0))
+#define MT_DBG_AGG_B1BRR0(_band) MT_DBG_AGG((_band), __DBG_REG_OFFS(dev, DBG_AGG_B1BRR0))
+#define MT_DBG_AGG_B2BRR0(_band) MT_DBG_AGG((_band), __DBG_REG_OFFS(dev, DBG_AGG_B2BRR0))
+#define MT_DBG_AGG_B3BRR0(_band) MT_DBG_AGG((_band), __DBG_REG_OFFS(dev, DBG_AGG_B3BRR0))
+#define MT_DBG_AGG_AWSCR(_band, n) MT_DBG_AGG((_band), __DBG_REG_OFFS(dev, DBG_AGG_AWSCR0) + ((n) << 2))
+#define MT_DBG_AGG_PCR(_band, n) MT_DBG_AGG((_band), __DBG_REG_OFFS(dev, DBG_AGG_PCR0) + ((n) << 2))
+#define MT_DBG_AGG_TTCR(_band, n) MT_DBG_AGG((_band), __DBG_REG_OFFS(dev, DBG_AGG_TTCR0) + ((n) << 2))
+#define MT_DBG_MIB_M0ARNG(_band, n) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0ARNG0) + ((n) << 2))
+#define MT_DBG_MIB_M0DR2(_band, n) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0DR2) + ((n) << 2))
+#define MT_DBG_MIB_M0DR13(_band, n) MT_DBG_MIB((_band), __DBG_REG_OFFS(dev, DBG_MIB_M0DR13) + ((n) << 2))
+
+#define MT_DBG_AGG_AALCR_ACx3_AGG_LIMIT_MASK GENMASK(31, 24)
+#define MT_DBG_AGG_AALCR_ACx2_AGG_LIMIT_MASK GENMASK(23, 16)
+#define MT_DBG_AGG_AALCR_ACx1_AGG_LIMIT_MASK GENMASK(15, 8)
+#define MT_DBG_AGG_AALCR_ACx0_AGG_LIMIT_MASK GENMASK(7, 0)
+#define MT_DBG_AGG_AALCR4_ALTX0_AGG_LIMIT_MASK GENMASK(7, 0)
+
+#define MT_DBG_AGG_AWSCR0_WINSIZE3_MASK GENMASK(31, 24)
+#define MT_DBG_AGG_AWSCR0_WINSIZE2_MASK GENMASK(23, 16)
+#define MT_DBG_AGG_AWSCR0_WINSIZE1_MASK GENMASK(15, 8)
+#define MT_DBG_AGG_AWSCR0_WINSIZE0_MASK GENMASK(7, 0)
+
+#define MT_DBG_AGG_AWSCR1_WINSIZE7_MASK GENMASK(31, 24)
+#define MT_DBG_AGG_AWSCR1_WINSIZE6_MASK GENMASK(23, 16)
+#define MT_DBG_AGG_AWSCR1_WINSIZE5_MASK GENMASK(15, 8)
+#define MT_DBG_AGG_AWSCR1_WINSIZE4_MASK GENMASK(7, 0)
+
+#define MT_DBG_AGG_AWSCR2_WINSIZEB_MASK GENMASK(31, 24)
+#define MT_DBG_AGG_AWSCR2_WINSIZEA_MASK GENMASK(23, 16)
+#define MT_DBG_AGG_AWSCR2_WINSIZE9_MASK GENMASK(15, 8)
+#define MT_DBG_AGG_AWSCR2_WINSIZE8_MASK GENMASK(7, 0)
+
+#define MT_DBG_AGG_AWSCR3_WINSIZEE_MASK GENMASK(23, 16)
+#define MT_DBG_AGG_AWSCR3_WINSIZED_MASK GENMASK(15, 8)
+#define MT_DBG_AGG_AWSCR3_WINSIZEC_MASK GENMASK(7, 0)
+
+#define MT_DBG_MIB_M0ARNG0_AGG_RANG_SEL3_MASK GENMASK(31, 24)
+#define MT_DBG_MIB_M0ARNG0_AGG_RANG_SEL2_MASK GENMASK(23, 16)
+#define MT_DBG_MIB_M0ARNG0_AGG_RANG_SEL1_MASK GENMASK(15, 8)
+#define MT_DBG_MIB_M0ARNG0_AGG_RANG_SEL0_MASK GENMASK(7, 0)
+
+#define MT_DBG_MIB_M0ARNG1_AGG_RANG_SEL7_MASK GENMASK(31, 24)
+#define MT_DBG_MIB_M0ARNG1_AGG_RANG_SEL6_MASK GENMASK(23, 16)
+#define MT_DBG_MIB_M0ARNG1_AGG_RANG_SEL5_MASK GENMASK(15, 8)
+#define MT_DBG_MIB_M0ARNG1_AGG_RANG_SEL4_MASK GENMASK(7, 0)
+
+#define MT_DBG_MIB_M0ARNG2_AGG_RANG_SEL11_MASK GENMASK(31, 24)
+#define MT_DBG_MIB_M0ARNG2_AGG_RANG_SEL10_MASK GENMASK(23, 16)
+#define MT_DBG_MIB_M0ARNG2_AGG_RANG_SEL9_MASK GENMASK(15, 8)
+#define MT_DBG_MIB_M0ARNG2_AGG_RANG_SEL8_MASK GENMASK(7, 0)
+
+#define MT_DBG_MIB_M0ARNG3_AGG_RANG_SEL14_MASK GENMASK(23, 16)
+#define MT_DBG_MIB_M0ARNG3_AGG_RANG_SEL13_MASK GENMASK(15, 8)
+#define MT_DBG_MIB_M0ARNG3_AGG_RANG_SEL12_MASK GENMASK(7, 0)
+
+#define MT_DBG_MIB_M0DR2_TRX_AGG_RANGE1_CNT_MASK GENMASK(31, 16)
+#define MT_DBG_MIB_M0DR2_TRX_AGG_RANGE0_CNT_MASK GENMASK(15, 0)
+#define MT_DBG_MIB_M0DR3_TRX_AGG_RANGE3_CNT_MASK GENMASK(31, 16)
+#define MT_DBG_MIB_M0DR3_TRX_AGG_RANGE2_CNT_MASK GENMASK(15, 0)
+#define MT_DBG_MIB_M0DR4_TRX_AGG_RANGE5_CNT_MASK GENMASK(31, 16)
+#define MT_DBG_MIB_M0DR4_TRX_AGG_RANGE4_CNT_MASK GENMASK(15, 0)
+#define MT_DBG_MIB_M0DR5_TRX_AGG_RANGE7_CNT_MASK GENMASK(31, 16)
+#define MT_DBG_MIB_M0DR5_TRX_AGG_RANGE6_CNT_MASK GENMASK(15, 0)
+#define MT_DBG_MIB_M0DR13_TRX_AGG_RANGE9_CNT_MASK GENMASK(31, 16)
+#define MT_DBG_MIB_M0DR13_TRX_AGG_RANGE8_CNT_MASK GENMASK(15, 0)
+#define MT_DBG_MIB_M0DR14_TRX_AGG_RANGE11_CNT_MASK GENMASK(31, 16)
+#define MT_DBG_MIB_M0DR14_TRX_AGG_RANGE10_CNT_MASK GENMASK(15, 0)
+#define MT_DBG_MIB_M0DR15_TRX_AGG_RANGE13_CNT_MASK GENMASK(31, 16)
+#define MT_DBG_MIB_M0DR15_TRX_AGG_RANGE12_CNT_MASK GENMASK(15, 0)
+#define MT_DBG_MIB_M0DR16_TRX_AGG_RANGE15_CNT_MASK GENMASK(31, 16)
+#define MT_DBG_MIB_M0DR16_TRX_AGG_RANGE14_CNT_MASK GENMASK(15, 0)
+
+/* mt7915 host DMA*/
+#define MT_DBG_INT_DMA1_R0_DONE BIT(0)
+#define MT_DBG_INT_DMA1_R1_DONE BIT(1)
+#define MT_DBG_INT_DMA1_R2_DONE BIT(2)
+
+#define MT_DBG_INT_DMA1_T16_DONE BIT(26)
+#define MT_DBG_INT_DMA1_T17_DONE BIT(27)
+#define MT_DBG_INT_DMA1_T18_DONE BIT(30)
+#define MT_DBG_INT_DMA1_T19_DONE BIT(31)
+#define MT_DBG_INT_DMA1_T20_DONE BIT(15)
+
+#define MT_DBG_EXT_WRAP_INT_DMA0_R0_DONE BIT(16)
+#define MT_DBG_EXT_WRAP_INT_DMA0_R1_DONE BIT(17)
+
+/* mt7986 host DMA */
+#define MT_DBG_INT_DMA0_R0_DONE BIT(0)
+#define MT_DBG_INT_DMA0_R1_DONE BIT(1)
+#define MT_DBG_INT_DMA0_R2_DONE BIT(2)
+#define MT_DBG_INT_DMA0_R3_DONE BIT(3)
+#define MT_DBG_INT_DMA0_R4_DONE BIT(22)
+#define MT_DBG_INT_DMA0_R5_DONE BIT(23)
+
+#define MT_DBG_INT_DMA0_T16_DONE BIT(26)
+#define MT_DBG_INT_DMA0_T17_DONE BIT(27)
+#define MT_DBG_INT_DMA0_T18_DONE BIT(30)
+#define MT_DBG_INT_DMA0_T19_DONE BIT(31)
+#define MT_DBG_INT_DMA0_T20_DONE BIT(25)
+
+/* MCU DMA */
+#define WF_WFDMA_MCU_DMA0_BASE 0x54000000
+#define WF_WFDMA_MCU_DMA0_HOST_INT_STA_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x200) // 0200
+#define WF_WFDMA_MCU_DMA0_HOST_INT_ENA_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0X204) // 0204
+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x208) // 0208
+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK 0x00000008 // RX_DMA_BUSY[3]
+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT 3
+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_EN_MASK 0x00000004 // RX_DMA_EN[2]
+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_RX_DMA_EN_SHFT 2
+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK 0x00000002 // TX_DMA_BUSY[1]
+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT 1
+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_EN_MASK 0x00000001 // TX_DMA_EN[0]
+#define WF_WFDMA_MCU_DMA0_WPDMA_GLO_CFG_TX_DMA_EN_SHFT 0
+
+#define WF_WFDMA_MCU_DMA1_BASE 0x55000000
+#define WF_WFDMA_MCU_DMA1_HOST_INT_STA_ADDR (WF_WFDMA_MCU_DMA1_BASE + 0x200) // 0200
+#define WF_WFDMA_MCU_DMA1_HOST_INT_ENA_ADDR (WF_WFDMA_MCU_DMA1_BASE + 0X204) // 0204
+#define WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_ADDR (WF_WFDMA_MCU_DMA1_BASE + 0x208) // 0208
+#define WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK 0x00000008 // RX_DMA_BUSY[3]
+#define WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT 3
+#define WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_RX_DMA_EN_MASK 0x00000004 // RX_DMA_EN[2]
+#define WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_RX_DMA_EN_SHFT 2
+#define WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK 0x00000002 // TX_DMA_BUSY[1]
+#define WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT 1
+#define WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_TX_DMA_EN_MASK 0x00000001 // TX_DMA_EN[0]
+#define WF_WFDMA_MCU_DMA1_WPDMA_GLO_CFG_TX_DMA_EN_SHFT 0
+#define WF_WFDMA_MCU_DMA1_WPDMA_TX_RING0_CTRL0_ADDR (WF_WFDMA_MCU_DMA1_BASE + 0x300) // 0300
+#define WF_WFDMA_MCU_DMA1_WPDMA_TX_RING1_CTRL0_ADDR (WF_WFDMA_MCU_DMA1_BASE + 0x310) // 0310
+#define WF_WFDMA_MCU_DMA1_WPDMA_TX_RING2_CTRL0_ADDR (WF_WFDMA_MCU_DMA1_BASE + 0x320) // 0320
+#define WF_WFDMA_MCU_DMA1_WPDMA_RX_RING0_CTRL0_ADDR (WF_WFDMA_MCU_DMA1_BASE + 0x500) // 0500
+#define WF_WFDMA_MCU_DMA1_WPDMA_RX_RING1_CTRL0_ADDR (WF_WFDMA_MCU_DMA1_BASE + 0x510) // 0510
+#define WF_WFDMA_MCU_DMA1_WPDMA_RX_RING2_CTRL0_ADDR (WF_WFDMA_MCU_DMA1_BASE + 0x520) // 0520
+#define WF_WFDMA_MCU_DMA1_WPDMA_RX_RING3_CTRL0_ADDR (WF_WFDMA_MCU_DMA1_BASE + 0x530) // 0530
+#define WF_WFDMA_MCU_DMA1_WPDMA_RX_RING4_CTRL0_ADDR (WF_WFDMA_MCU_DMA1_BASE + 0x540) // 0540
+
+#define WF_WFDMA_MCU_DMA1_PCIE1_BASE 0x59000000
+#define WF_WFDMA_MCU_DMA1_PCIE1_HOST_INT_STA_ADDR (WF_WFDMA_MCU_DMA1_PCIE1_BASE + 0x200) // 0200
+#define WF_WFDMA_MCU_DMA1_PCIE1_HOST_INT_ENA_ADDR (WF_WFDMA_MCU_DMA1_PCIE1_BASE + 0X204) // 0204
+#define WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_ADDR (WF_WFDMA_MCU_DMA1_PCIE1_BASE + 0x208) // 0208
+#define WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK 0x00000008 // RX_DMA_BUSY[3]
+#define WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT 3
+#define WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_RX_DMA_EN_MASK 0x00000004 // RX_DMA_EN[2]
+#define WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_RX_DMA_EN_SHFT 2
+#define WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK 0x00000002 // TX_DMA_BUSY[1]
+#define WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT 1
+#define WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_TX_DMA_EN_MASK 0x00000001 // TX_DMA_EN[0]
+#define WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_GLO_CFG_TX_DMA_EN_SHFT 0
+#define WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_TX_RING2_CTRL0_ADDR (WF_WFDMA_MCU_DMA1_PCIE1_BASE + 0x320) // 0320
+#define WF_WFDMA_MCU_DMA1_PCIE1_WPDMA_RX_RING3_CTRL0_ADDR (WF_WFDMA_MCU_DMA1_PCIE1_BASE + 0x530) // 0530
+
+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING0_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x300) // 0300
+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING1_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x310) // 0310
+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING2_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x320) // 0320
+/* mt7986 add */
+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING3_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x330) // 0330
+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING4_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x340) // 0340
+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING5_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x350) // 0350
+#define WF_WFDMA_MCU_DMA0_WPDMA_TX_RING6_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x360) // 0360
+
+
+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING0_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x500) // 0500
+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING1_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x510) // 0510
+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING2_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x520) // 0520
+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING3_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x530) // 0530
+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING4_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x540) // 0540
+
+/* mt7986 add */
+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING5_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x550) // 0550
+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING6_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x560) // 0560
+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING7_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x570) // 0570
+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING8_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x580) // 0580
+#define WF_WFDMA_MCU_DMA0_WPDMA_RX_RING9_CTRL0_ADDR (WF_WFDMA_MCU_DMA0_BASE + 0x590) // 0590
+
+/* MEM DMA */
+#define WF_WFDMA_MEM_DMA_BASE 0x58000000
+#define WF_WFDMA_MEM_DMA_HOST_INT_STA_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x200) // 0200
+#define WF_WFDMA_MEM_DMA_HOST_INT_ENA_ADDR (WF_WFDMA_MEM_DMA_BASE + 0X204) // 0204
+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x208) // 0208
+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_BUSY_MASK 0x00000008 // RX_DMA_BUSY[3]
+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_BUSY_SHFT 3
+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_EN_MASK 0x00000004 // RX_DMA_EN[2]
+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_RX_DMA_EN_SHFT 2
+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_BUSY_MASK 0x00000002 // TX_DMA_BUSY[1]
+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_BUSY_SHFT 1
+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_EN_MASK 0x00000001 // TX_DMA_EN[0]
+#define WF_WFDMA_MEM_DMA_WPDMA_GLO_CFG_TX_DMA_EN_SHFT 0
+#define WF_WFDMA_MEM_DMA_WPDMA_TX_RING0_CTRL0_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x300) // 0300
+#define WF_WFDMA_MEM_DMA_WPDMA_TX_RING1_CTRL0_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x310) // 0310
+#define WF_WFDMA_MEM_DMA_WPDMA_RX_RING0_CTRL0_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x500) // 0500
+#define WF_WFDMA_MEM_DMA_WPDMA_RX_RING1_CTRL0_ADDR (WF_WFDMA_MEM_DMA_BASE + 0x510) // 0510
+
+enum resource_attr {
+ HIF_TX_DATA,
+ HIF_TX_CMD,
+ HIF_TX_CMD_WM, /* direct path to WMCPU, only exist for WFDMA arch with 2 CPU */
+ HIF_TX_FWDL,
+ HIF_RX_DATA,
+ HIF_RX_EVENT,
+ RING_ATTR_NUM
+};
+
+struct hif_pci_tx_ring_desc {
+ u32 hw_int_mask;
+ u16 ring_size;
+ enum resource_attr ring_attr;
+ u8 band_idx;
+ char *const ring_info;
+};
+
+struct hif_pci_rx_ring_desc {
+ u32 hw_desc_base;
+ u32 hw_int_mask;
+ u16 ring_size;
+ enum resource_attr ring_attr;
+ u16 max_rx_process_cnt;
+ u16 max_sw_read_idx_inc;
+ char *const ring_info;
+};
+
+const struct hif_pci_tx_ring_desc mt7915_tx_ring_layout[] = {
+ {
+ .hw_int_mask = MT_DBG_INT_DMA1_T16_DONE,
+ .ring_size = 128,
+ .ring_attr = HIF_TX_FWDL,
+ .ring_info = "FWDL"
+ },
+ {
+ .hw_int_mask = MT_DBG_INT_DMA1_T17_DONE,
+ .ring_size = 256,
+ .ring_attr = HIF_TX_CMD_WM,
+ .ring_info = "cmd to WM"
+ },
+ {
+ .hw_int_mask = MT_DBG_INT_DMA1_T18_DONE,
+ .ring_size = 2048,
+ .ring_attr = HIF_TX_DATA,
+ .ring_info = "band0 TXD"
+ },
+ {
+ .hw_int_mask = MT_DBG_INT_DMA1_T19_DONE,
+ .ring_size = 2048,
+ .ring_attr = HIF_TX_DATA,
+ .ring_info = "band1 TXD"
+ },
+ {
+ .hw_int_mask = MT_DBG_INT_DMA1_T20_DONE,
+ .ring_size = 256,
+ .ring_attr = HIF_TX_CMD,
+ .ring_info = "cmd to WA"
+ }
+};
+
+const struct hif_pci_rx_ring_desc mt7915_rx_ring_layout[] = {
+ {
+ .hw_int_mask = MT_DBG_EXT_WRAP_INT_DMA0_R0_DONE,
+ .ring_size = 1536,
+ .ring_attr = HIF_RX_DATA,
+ .ring_info = "band0 RX data"
+ },
+ {
+ .hw_int_mask = MT_DBG_EXT_WRAP_INT_DMA0_R1_DONE,
+ .ring_size = 1536,
+ .ring_attr = HIF_RX_DATA,
+ .ring_info = "band1 RX data"
+ },
+ {
+ .hw_int_mask = MT_DBG_INT_DMA1_R0_DONE,
+ .ring_size = 512,
+ .ring_attr = HIF_RX_EVENT,
+ .ring_info = "event from WM"
+ },
+ {
+ .hw_int_mask = MT_DBG_INT_DMA1_R1_DONE,
+ .ring_size = 1024,
+ .ring_attr = HIF_RX_EVENT,
+ .ring_info = "event from WA band0"
+ },
+ {
+ .hw_int_mask = MT_DBG_INT_DMA1_R2_DONE,
+ .ring_size = 512,
+ .ring_attr = HIF_RX_EVENT,
+ .ring_info = "event from WA band1"
+ }
+};
+
+const struct hif_pci_tx_ring_desc mt7986_tx_ring_layout[] = {
+ {
+ .hw_int_mask = MT_DBG_INT_DMA0_T16_DONE,
+ .ring_size = 128,
+ .ring_attr = HIF_TX_FWDL,
+ .ring_info = "FWDL"
+ },
+ {
+ .hw_int_mask = MT_DBG_INT_DMA0_T17_DONE,
+ .ring_size = 256,
+ .ring_attr = HIF_TX_CMD_WM,
+ .ring_info = "cmd to WM"
+ },
+ {
+ .hw_int_mask = MT_DBG_INT_DMA0_T18_DONE,
+ .ring_size = 2048,
+ .ring_attr = HIF_TX_DATA,
+ .ring_info = "band0 TXD"
+ },
+ {
+ .hw_int_mask = MT_DBG_INT_DMA0_T19_DONE,
+ .ring_size = 2048,
+ .ring_attr = HIF_TX_DATA,
+ .ring_info = "band1 TXD"
+ },
+ {
+ .hw_int_mask = MT_DBG_INT_DMA0_T20_DONE,
+ .ring_size = 256,
+ .ring_attr = HIF_TX_CMD,
+ .ring_info = "cmd to WA"
+ }
+};
+
+const struct hif_pci_rx_ring_desc mt7986_rx_ring_layout[] = {
+ {
+ .hw_int_mask = MT_DBG_INT_DMA0_R4_DONE,
+ .ring_size = 1536,
+ .ring_attr = HIF_RX_DATA,
+ .ring_info = "band0 RX data"
+ },
+ {
+ .hw_int_mask = MT_DBG_INT_DMA0_R5_DONE,
+ .ring_size = 1536,
+ .ring_attr = HIF_RX_DATA,
+ .ring_info = "band1 RX data"
+ },
+ {
+ .hw_int_mask = MT_DBG_INT_DMA0_R0_DONE,
+ .ring_size = 512,
+ .ring_attr = HIF_RX_EVENT,
+ .ring_info = "event from WM"
+ },
+ {
+ .hw_int_mask = MT_DBG_INT_DMA0_R1_DONE,
+ .ring_size = 512,
+ .ring_attr = HIF_RX_EVENT,
+ .ring_info = "event from WA"
+ },
+ {
+ .hw_int_mask = MT_DBG_INT_DMA0_R2_DONE,
+ .ring_size = 1024,
+ .ring_attr = HIF_RX_EVENT,
+ .ring_info = "STS WA band0"
+ },
+ {
+ .hw_int_mask = MT_DBG_INT_DMA0_R3_DONE,
+ .ring_size = 512,
+ .ring_attr = HIF_RX_EVENT,
+ .ring_info = "STS WA band1"
+ },
+};
+
+/* mibinfo related CRs. */
+#define BN0_WF_MIB_TOP_BASE 0x820ed000
+#define BN1_WF_MIB_TOP_BASE 0x820fd000
+
+#define BN0_WF_MIB_TOP_BTOCR_ADDR (BN0_WF_MIB_TOP_BASE + 0x400) // D400
+#define BN0_WF_MIB_TOP_BTBCR_ADDR (BN0_WF_MIB_TOP_BASE + 0x428) // D428
+#define BN0_WF_MIB_TOP_BTDCR_ADDR (BN0_WF_MIB_TOP_BASE + 0x4F0) // D4F0
+
+#define BN0_WF_MIB_TOP_BSDR0_ADDR (BN0_WF_MIB_TOP_BASE + 0x688) // D688
+#define BN0_WF_MIB_TOP_BSDR1_ADDR (BN0_WF_MIB_TOP_BASE + 0x690) // D690
+
+#define BN0_WF_MIB_TOP_BSDR2_ADDR (BN0_WF_MIB_TOP_BASE + 0x518) // D518
+#define BN0_WF_MIB_TOP_BSDR3_ADDR (BN0_WF_MIB_TOP_BASE + 0x520) // D520
+#define BN0_WF_MIB_TOP_BSDR4_ADDR (BN0_WF_MIB_TOP_BASE + 0x528) // D528
+#define BN0_WF_MIB_TOP_BSDR5_ADDR (BN0_WF_MIB_TOP_BASE + 0x530) // D530
+#define BN0_WF_MIB_TOP_BSDR6_ADDR (BN0_WF_MIB_TOP_BASE + 0x538) // D538
+
+#define BN0_WF_MIB_TOP_BROCR_ADDR (BN0_WF_MIB_TOP_BASE + 0x5B8) // D5B8
+#define BN0_WF_MIB_TOP_BRBCR_ADDR (BN0_WF_MIB_TOP_BASE + 0x5E0) // D5E0
+#define BN0_WF_MIB_TOP_BRDCR_ADDR (BN0_WF_MIB_TOP_BASE + 0x630) // D630
+
+#define BN0_WF_MIB_TOP_M0SDR0_BEACONTXCOUNT_MASK 0x0000FFFF // BEACONTXCOUNT[15..0]
+
+#define BN0_WF_MIB_TOP_M0SDR4_RX_FIFO_FULL_COUNT_MASK 0x0000FFFF // RX_FIFO_FULL_COUNT[15..0]
+
+#define BN0_WF_MIB_TOP_M0SDR5_RX_MPDU_COUNT_MASK 0xFFFFFFFF // RX_MPDU_COUNT[31..0]
+
+#define BN0_WF_MIB_TOP_M0SDR6_CHANNEL_IDLE_COUNT_MASK 0x0000FFFF // CHANNEL_IDLE_COUNT[15..0]
+
+#define BN1_WF_MIB_TOP_BTOCR_ADDR (BN1_WF_MIB_TOP_BASE + 0x400) // D400
+
+#define BN0_WF_MIB_TOP_M0SDR7_VEC_MISS_COUNT_MASK 0x0000FFFF // VEC_MISS_COUNT[15..0]
+#define BN0_WF_MIB_TOP_M0SDR8_DELIMITER_FAIL_COUNT_MASK 0x0000FFFF // DELIMITER_FAIL_COUNT[15..0]
+#define BN0_WF_MIB_TOP_M0SDR9_CCA_NAV_TX_TIME_MASK 0x00FFFFFF // CCA_NAV_TX_TIME[23..0]
+
+#define BN0_WF_MIB_TOP_M0SDR11_RX_LEN_MISMATCH_MASK 0x0000FFFF // RX_LEN_MISMATCH[15..0]
+
+#define BN0_WF_MIB_TOP_M0SDR16_P_CCA_TIME_MASK 0x00FFFFFF // P_CCA_TIME[23..0]
+#define BN0_WF_MIB_TOP_M0SDR17_S_CCA_TIME_MASK 0x00FFFFFF // S_CCA_TIME[23..0]
+#define BN0_WF_MIB_TOP_M0SDR18_P_ED_TIME_MASK 0x00FFFFFF // P_ED_TIME[23..0]
+#define BN0_WF_MIB_TOP_M0SDR19_CCK_MDRDY_TIME_MASK 0x00FFFFFF // CCK_MDRDY_TIME[23..0]
+#define BN0_WF_MIB_TOP_M0SDR20_OFDM_LG_MIXED_VHT_MDRDY_TIME_MASK 0x00FFFFFF // OFDM_LG_MIXED_VHT_MDRDY_TIME[23..0]
+#define BN0_WF_MIB_TOP_M0SDR21_OFDM_GREEN_MDRDY_TIME_MASK 0x00FFFFFF // OFDM_GREEN_MDRDY_TIME[23..0]
+
+#define BN0_WF_MIB_TOP_M0SDR22_ADDR (BN0_WF_MIB_TOP_BASE + 0x60) // D060
+#define BN0_WF_MIB_TOP_M0SDR23_ADDR (BN0_WF_MIB_TOP_BASE + 0x64) // D064
+
+#define BN0_WF_MIB_TOP_M0SDR34_MUBF_TX_COUNT_MASK 0x0000FFFF // MUBF_TX_COUNT[15..0]
+
+#define BN0_WF_MIB_TOP_M0DR0_TX_40MHZ_CNT_MASK 0xFFFF0000 // TX_40MHZ_CNT[31..16]
+#define BN0_WF_MIB_TOP_M0DR0_TX_40MHZ_CNT_SHFT 16
+#define BN0_WF_MIB_TOP_M0DR0_TX_20MHZ_CNT_MASK 0x0000FFFF // TX_20MHZ_CNT[15..0]
+#define BN0_WF_MIB_TOP_M0DR0_TX_20MHZ_CNT_SHFT 0
+
+#define BN0_WF_MIB_TOP_M0DR1_TX_160MHZ_CNT_MASK 0xFFFF0000 // TX_160MHZ_CNT[31..16]
+#define BN0_WF_MIB_TOP_M0DR1_TX_160MHZ_CNT_SHFT 16
+#define BN0_WF_MIB_TOP_M0DR1_TX_80MHZ_CNT_MASK 0x0000FFFF // TX_80MHZ_CNT[15..0]
+#define BN0_WF_MIB_TOP_M0DR1_TX_80MHZ_CNT_SHFT 0
+
+#define BN0_WF_MIB_TOP_M0DR6_TX_DDLMT_RNG2_CNT_MASK 0xFFFF0000 // TX_DDLMT_RNG2_CNT[31..16]
+#define BN0_WF_MIB_TOP_M0DR6_TX_DDLMT_RNG2_CNT_SHFT 16
+#define BN0_WF_MIB_TOP_M0DR6_TX_DDLMT_RNG1_CNT_MASK 0x0000FFFF // TX_DDLMT_RNG1_CNT[15..0]
+#define BN0_WF_MIB_TOP_M0DR6_TX_DDLMT_RNG1_CNT_SHFT 0
+
+#define BN0_WF_MIB_TOP_M0DR7_TX_DDLMT_RNG4_CNT_MASK 0xFFFF0000 // TX_DDLMT_RNG4_CNT[31..16]
+#define BN0_WF_MIB_TOP_M0DR7_TX_DDLMT_RNG4_CNT_SHFT 16
+#define BN0_WF_MIB_TOP_M0DR7_TX_DDLMT_RNG3_CNT_MASK 0x0000FFFF // TX_DDLMT_RNG3_CNT[15..0]
+#define BN0_WF_MIB_TOP_M0DR7_TX_DDLMT_RNG3_CNT_SHFT 0
+
+#define BN0_WF_MIB_TOP_M0DR10_MU_FAIL_PPDU_CNT_MASK 0x0000FFFF // MU_FAIL_PPDU_CNT[15..0]
+
+#define BN0_WF_MIB_TOP_M0B0SDR0_ADDR (BN0_WF_MIB_TOP_BASE + 0x100) // D100
+#define BN0_WF_MIB_TOP_M0B0SDR0_RTSRETRYCOUNT_MASK 0xFFFF0000 // RTSRETRYCOUNT[31..16]
+#define BN0_WF_MIB_TOP_M0B0SDR0_RTSRETRYCOUNT_SHFT 16
+#define BN0_WF_MIB_TOP_M0B0SDR0_RTSTXCOUNT_MASK 0x0000FFFF // RTSTXCOUNT[15..0]
+#define BN0_WF_MIB_TOP_M0B0SDR0_RTSTXCOUNT_SHFT 0
+#define BN0_WF_MIB_TOP_M0B0SDR1_ADDR (BN0_WF_MIB_TOP_BASE + 0x104) // D104
+#define BN0_WF_MIB_TOP_M0B0SDR1_ACKFAILCOUNT_MASK 0xFFFF0000 // ACKFAILCOUNT[31..16]
+#define BN0_WF_MIB_TOP_M0B0SDR1_ACKFAILCOUNT_SHFT 16
+#define BN0_WF_MIB_TOP_M0B0SDR1_BAMISSCOUNT_MASK 0x0000FFFF // BAMISSCOUNT[15..0]
+#define BN0_WF_MIB_TOP_M0B0SDR1_BAMISSCOUNT_SHFT 0
+#define BN0_WF_MIB_TOP_M0B0SDR2_ADDR (BN0_WF_MIB_TOP_BASE + 0x108) // D108
+#define BN0_WF_MIB_TOP_M0B0SDR2_FRAMERETRY2COUNT_MASK 0xFFFF0000 // FRAMERETRY2COUNT[31..16]
+#define BN0_WF_MIB_TOP_M0B0SDR2_FRAMERETRY2COUNT_SHFT 16
+#define BN0_WF_MIB_TOP_M0B0SDR2_FRAMERETRYCOUNT_MASK 0x0000FFFF // FRAMERETRYCOUNT[15..0]
+#define BN0_WF_MIB_TOP_M0B0SDR2_FRAMERETRYCOUNT_SHFT 0
+#define BN0_WF_MIB_TOP_M0B0SDR3_ADDR (BN0_WF_MIB_TOP_BASE + 0x10C) // D10C
+#define BN0_WF_MIB_TOP_M0B0SDR3_FRAMERETRY3COUNT_MASK 0x0000FFFF // FRAMERETRY3COUNT[15..0]
+#define BN0_WF_MIB_TOP_M0B0SDR3_FRAMERETRY3COUNT_SHFT 0
+#define BN0_WF_MIB_TOP_M0DR12_TX_DDLMT_RNG0_CNT_MASK 0x0000FFFF // TX_DDLMT_RNG0_CNT[15..0]
+
+
+#define BN0_WF_MIB_TOP_BTOCR_TX_OK_COUNT2np1_MASK 0xFFFF0000 // TX_OK_COUNT2np1[31..16]
+#define BN0_WF_MIB_TOP_BTOCR_TX_OK_COUNT2np1_SHFT 16
+#define BN0_WF_MIB_TOP_BTOCR_TX_OK_COUNT2n_MASK 0x0000FFFF // TX_OK_COUNT2n[15..0]
+#define BN0_WF_MIB_TOP_BTOCR_TX_OK_COUNT2n_SHFT 0
+
+#define BN0_WF_MIB_TOP_BTDCR_TX_DATA_COUNT2np1_MASK 0xFFFF0000 // TX_DATA_COUNT2np1[31..16]
+#define BN0_WF_MIB_TOP_BTDCR_TX_DATA_COUNT2np1_SHFT 16
+#define BN0_WF_MIB_TOP_BTDCR_TX_DATA_COUNT2n_MASK 0x0000FFFF // TX_DATA_COUNT2n[15..0]
+#define BN0_WF_MIB_TOP_BTDCR_TX_DATA_COUNT2n_SHFT 0
+
+#define BN0_WF_MIB_TOP_BROCR_RX_OK_COUNT2np1_MASK 0xFFFF0000 // RX_OK_COUNT2np1[31..16]
+#define BN0_WF_MIB_TOP_BROCR_RX_OK_COUNT2np1_SHFT 16
+#define BN0_WF_MIB_TOP_BROCR_RX_OK_COUNT2n_MASK 0x0000FFFF // RX_OK_COUNT2n[15..0]
+#define BN0_WF_MIB_TOP_BROCR_RX_OK_COUNT2n_SHFT 0
+
+#define BN0_WF_MIB_TOP_BRDCR_RX_DATA_COUNT2np1_MASK 0xFFFF0000 // RX_DATA_COUNT2np1[31..16]
+#define BN0_WF_MIB_TOP_BRDCR_RX_DATA_COUNT2np1_SHFT 16
+#define BN0_WF_MIB_TOP_BRDCR_RX_DATA_COUNT2n_MASK 0x0000FFFF // RX_DATA_COUNT2n[15..0]
+#define BN0_WF_MIB_TOP_BRDCR_RX_DATA_COUNT2n_SHFT 0
+
+#define BN0_WF_MIB_TOP_BSDR0_RTSTXCOUNT2np1_MASK 0xFFFF0000 // RTSTXCOUNT2np1[31..16]
+#define BN0_WF_MIB_TOP_BSDR0_RTSTXCOUNT2np1_SHFT 16
+#define BN0_WF_MIB_TOP_BSDR0_RTSTXCOUNT2n_MASK 0x0000FFFF // RTSTXCOUNT2n[15..0]
+#define BN0_WF_MIB_TOP_BSDR0_RTSTXCOUNT2n_SHFT 0
+
+#define BN0_WF_MIB_TOP_BSDR1_RTSRETRYCOUNT2np1_MASK 0xFFFF0000 // RTSRETRYCOUNT2np1[31..16]
+#define BN0_WF_MIB_TOP_BSDR1_RTSRETRYCOUNT2np1_SHFT 16
+#define BN0_WF_MIB_TOP_BSDR1_RTSRETRYCOUNT2n_MASK 0x0000FFFF // RTSRETRYCOUNT2n[15..0]
+#define BN0_WF_MIB_TOP_BSDR1_RTSRETRYCOUNT2n_SHFT 0
+
+#define BN0_WF_MIB_TOP_BSDR2_BAMISSCOUNT2np1_MASK 0xFFFF0000 // BAMISSCOUNT2np1[31..16]
+#define BN0_WF_MIB_TOP_BSDR2_BAMISSCOUNT2np1_SHFT 16
+#define BN0_WF_MIB_TOP_BSDR2_BAMISSCOUNT2n_MASK 0x0000FFFF // BAMISSCOUNT2n[15..0]
+#define BN0_WF_MIB_TOP_BSDR2_BAMISSCOUNT2n_SHFT 0
+
+#define BN0_WF_MIB_TOP_BSDR3_ACKFAILCOUNT2np1_MASK 0xFFFF0000 // ACKFAILCOUNT2np1[31..16]
+#define BN0_WF_MIB_TOP_BSDR3_ACKFAILCOUNT2np1_SHFT 16
+#define BN0_WF_MIB_TOP_BSDR3_ACKFAILCOUNT2n_MASK 0x0000FFFF // ACKFAILCOUNT2n[15..0]
+#define BN0_WF_MIB_TOP_BSDR3_ACKFAILCOUNT2n_SHFT 0
+
+#define BN0_WF_MIB_TOP_BSDR4_FRAMERETRYCOUNT2np1_MASK 0xFFFF0000 // FRAMERETRYCOUNT2np1[31..16]
+#define BN0_WF_MIB_TOP_BSDR4_FRAMERETRYCOUNT2np1_SHFT 16
+#define BN0_WF_MIB_TOP_BSDR4_FRAMERETRYCOUNT2n_MASK 0x0000FFFF // FRAMERETRYCOUNT2n[15..0]
+#define BN0_WF_MIB_TOP_BSDR4_FRAMERETRYCOUNT2n_SHFT 0
+
+#define BN0_WF_MIB_TOP_BSDR5_FRAMERETRY2COUNT2np1_MASK 0xFFFF0000 // FRAMERETRY2COUNT2np1[31..16]
+#define BN0_WF_MIB_TOP_BSDR5_FRAMERETRY2COUNT2np1_SHFT 16
+#define BN0_WF_MIB_TOP_BSDR5_FRAMERETRY2COUNT2n_MASK 0x0000FFFF // FRAMERETRY2COUNT2n[15..0]
+#define BN0_WF_MIB_TOP_BSDR5_FRAMERETRY2COUNT2n_SHFT 0
+
+#define BN0_WF_MIB_TOP_BSDR6_FRAMERETRY3COUNT2np1_MASK 0xFFFF0000 // FRAMERETRY3COUNT2np1[31..16]
+#define BN0_WF_MIB_TOP_BSDR6_FRAMERETRY3COUNT2np1_SHFT 16
+#define BN0_WF_MIB_TOP_BSDR6_FRAMERETRY3COUNT2n_MASK 0x0000FFFF // FRAMERETRY3COUNT2n[15..0]
+#define BN0_WF_MIB_TOP_BSDR6_FRAMERETRY3COUNT2n_SHFT 0
+/* TXD */
+
+#define MT_TXD1_ETYP BIT(15)
+#define MT_TXD1_VLAN BIT(14)
+#define MT_TXD1_RMVL BIT(13)
+#define MT_TXD1_AMS BIT(13)
+#define MT_TXD1_EOSP BIT(12)
+#define MT_TXD1_MRD BIT(11)
+
+#define MT_TXD7_CTXD BIT(26)
+#define MT_TXD7_CTXD_CNT GENMASK(25, 23)
+#define MT_TXD7_TAT GENMASK(9, 0)
+
+#endif
+#endif
diff --git a/mt7915/mtk_debugfs.c b/mt7915/mtk_debugfs.c
new file mode 100644
index 00000000..ccaaea78
--- /dev/null
+++ b/mt7915/mtk_debugfs.c
@@ -0,0 +1,2921 @@
+#include<linux/inet.h>
+#include "mt7915.h"
+#include "mt7915_debug.h"
+#include "mac.h"
+#include "mcu.h"
+
+#ifdef MTK_DEBUG
+#define LWTBL_IDX2BASE_ID GENMASK(14, 8)
+#define LWTBL_IDX2BASE_DW GENMASK(7, 2)
+#define LWTBL_IDX2BASE(_id, _dw) (MT_DBG_WTBL_BASE | \
+ FIELD_PREP(LWTBL_IDX2BASE_ID, _id) | \
+ FIELD_PREP(LWTBL_IDX2BASE_DW, _dw))
+
+#define UWTBL_IDX2BASE_ID GENMASK(12, 6)
+#define UWTBL_IDX2BASE_DW GENMASK(5, 2)
+#define UWTBL_IDX2BASE(_id, _dw) (MT_DBG_UWTBL_TOP_BASE | 0x2000 | \
+ FIELD_PREP(UWTBL_IDX2BASE_ID, _id) | \
+ FIELD_PREP(UWTBL_IDX2BASE_DW, _dw))
+
+#define KEYTBL_IDX2BASE_KEY GENMASK(12, 6)
+#define KEYTBL_IDX2BASE_DW GENMASK(5, 2)
+#define KEYTBL_IDX2BASE(_key, _dw) (MT_DBG_UWTBL_TOP_BASE | 0x2000 | \
+ FIELD_PREP(KEYTBL_IDX2BASE_KEY, _key) | \
+ FIELD_PREP(KEYTBL_IDX2BASE_DW, _dw))
+
+enum mt7915_wtbl_type {
+ WTBL_TYPE_LMAC, /* WTBL in LMAC */
+ WTBL_TYPE_UMAC, /* WTBL in UMAC */
+ WTBL_TYPE_KEY, /* Key Table */
+ MAX_NUM_WTBL_TYPE
+};
+
+static int mt7915_wtbl_read_raw(struct mt7915_dev *dev, u16 idx,
+ enum mt7915_wtbl_type type, u16 start_dw,
+ u16 len, void *buf)
+{
+ u32 *dest_cpy = (u32 *)buf;
+ u32 size_dw = len;
+ u32 src = 0;
+
+ if (!buf)
+ return 0xFF;
+
+ if (type == WTBL_TYPE_LMAC) {
+ mt76_wr(dev, MT_DBG_WTBLON_TOP_WDUCR,
+ FIELD_PREP(MT_DBG_WTBLON_TOP_WDUCR_GROUP, (idx >> 7)));
+ src = LWTBL_IDX2BASE(idx, start_dw);
+ } else if (type == WTBL_TYPE_UMAC) {
+ mt76_wr(dev, MT_DBG_UWTBL_TOP_WDUCR,
+ FIELD_PREP(MT_UWTBL_TOP_WDUCR_GROUP, (idx >> 7)));
+ src = UWTBL_IDX2BASE(idx, start_dw);
+ } else if (type == WTBL_TYPE_KEY) {
+ mt76_wr(dev, MT_DBG_UWTBL_TOP_WDUCR,
+ MT_UWTBL_TOP_WDUCR_TARGET |
+ FIELD_PREP(MT_UWTBL_TOP_WDUCR_GROUP, (idx >> 7)));
+ src = KEYTBL_IDX2BASE(idx, start_dw);
+ }
+
+ while (size_dw--) {
+ *dest_cpy++ = mt76_rr(dev, src);
+ src += 4;
+ };
+
+ return 0;
+}
+
+static int mt7915_wtbl_write_raw(struct mt7915_dev *dev, u16 idx,
+ enum mt7915_wtbl_type type, u16 start_dw,
+ u32 val)
+{
+ u32 addr = 0;
+
+ if (type == WTBL_TYPE_LMAC) {
+ mt76_wr(dev, MT_DBG_WTBLON_TOP_WDUCR,
+ FIELD_PREP(MT_WTBLON_TOP_WDUCR_GROUP, (idx >> 7)));
+ addr = LWTBL_IDX2BASE(idx, start_dw);
+ } else if (type == WTBL_TYPE_UMAC) {
+ mt76_wr(dev, MT_DBG_UWTBL_TOP_WDUCR,
+ FIELD_PREP(MT_UWTBL_TOP_WDUCR_GROUP, (idx >> 7)));
+ addr = UWTBL_IDX2BASE(idx, start_dw);
+ } else if (type == WTBL_TYPE_KEY) {
+ mt76_wr(dev, MT_DBG_UWTBL_TOP_WDUCR,
+ MT_UWTBL_TOP_WDUCR_TARGET |
+ FIELD_PREP(MT_UWTBL_TOP_WDUCR_GROUP, (idx >> 7)));
+ addr = KEYTBL_IDX2BASE(idx, start_dw);
+ }
+
+ mt76_wr(dev, addr, val);
+
+ return 0;
+}
+
+void mt7915_packet_log_to_host(struct mt7915_dev *dev, const void *data, int len, int type, int des_len)
+{
+ struct bin_debug_hdr *hdr;
+ char *buf;
+
+ if (len > 1500 - sizeof(*hdr))
+ len = 1500 - sizeof(*hdr);
+
+ buf = kzalloc(sizeof(*hdr) + len, GFP_KERNEL);
+ if (!buf)
+ return;
+
+ hdr = (struct bin_debug_hdr *)buf;
+ hdr->magic_num = cpu_to_le32(PKT_BIN_DEBUG_MAGIC);
+ hdr->serial_id = cpu_to_le16(dev->dbg.fwlog_seq++);
+ hdr->msg_type = cpu_to_le16(type);
+ hdr->len = cpu_to_le16(len);
+ hdr->des_len = cpu_to_le16(des_len);
+
+ memcpy(buf + sizeof(*hdr), data, len);
+
+ mt7915_debugfs_rx_log(dev, buf, sizeof(*hdr) + len);
+}
+
+static int
+mt7915_fw_debug_module_set(void *data, u64 module)
+{
+ struct mt7915_dev *dev = data;
+
+ dev->dbg.fw_dbg_module = module;
+ return 0;
+}
+
+static int
+mt7915_fw_debug_module_get(void *data, u64 *module)
+{
+ struct mt7915_dev *dev = data;
+
+ *module = dev->dbg.fw_dbg_module;
+ return 0;
+}
+
+DEFINE_DEBUGFS_ATTRIBUTE(fops_fw_debug_module, mt7915_fw_debug_module_get,
+ mt7915_fw_debug_module_set, "%lld\n");
+
+static int
+mt7915_fw_debug_level_set(void *data, u64 level)
+{
+ struct mt7915_dev *dev = data;
+
+ dev->dbg.fw_dbg_lv = level;
+ mt7915_mcu_fw_dbg_ctrl(dev, dev->dbg.fw_dbg_module, dev->dbg.fw_dbg_lv);
+ return 0;
+}
+
+static int
+mt7915_fw_debug_level_get(void *data, u64 *level)
+{
+ struct mt7915_dev *dev = data;
+
+ *level = dev->dbg.fw_dbg_lv;
+ return 0;
+}
+
+DEFINE_DEBUGFS_ATTRIBUTE(fops_fw_debug_level, mt7915_fw_debug_level_get,
+ mt7915_fw_debug_level_set, "%lld\n");
+
+#define MAX_TX_MODE 12
+static char *HW_TX_MODE_STR[] = {"CCK", "OFDM", "HT-Mix", "HT-GF", "VHT",
+ "N/A", "N/A", "N/A", "HE_SU", "HE_EXT_SU",
+ "HE_TRIG", "HE_MU", "N/A"};
+static char *HW_TX_RATE_CCK_STR[] = {"1M", "2Mlong", "5.5Mlong", "11Mlong",
+ "N/A", "2Mshort", "5.5Mshort", "11Mshort",
+ "N/A"};
+static char *HW_TX_RATE_OFDM_STR[] = {"6M", "9M", "12M", "18M", "24M", "36M",
+ "48M", "54M", "N/A"};
+static char *fcap_str[] = {"20MHz", "20/40MHz", "20/40/80MHz",
+ "20/40/80/160/80+80MHz"};
+
+static char *hw_rate_ofdm_str(u16 ofdm_idx)
+{
+ switch (ofdm_idx) {
+ case 11: /* 6M */
+ return HW_TX_RATE_OFDM_STR[0];
+
+ case 15: /* 9M */
+ return HW_TX_RATE_OFDM_STR[1];
+
+ case 10: /* 12M */
+ return HW_TX_RATE_OFDM_STR[2];
+
+ case 14: /* 18M */
+ return HW_TX_RATE_OFDM_STR[3];
+
+ case 9: /* 24M */
+ return HW_TX_RATE_OFDM_STR[4];
+
+ case 13: /* 36M */
+ return HW_TX_RATE_OFDM_STR[5];
+
+ case 8: /* 48M */
+ return HW_TX_RATE_OFDM_STR[6];
+
+ case 12: /* 54M */
+ return HW_TX_RATE_OFDM_STR[7];
+
+ default:
+ return HW_TX_RATE_OFDM_STR[8];
+ }
+}
+
+static char *hw_rate_str(u8 mode, u16 rate_idx)
+{
+ if (mode == 0)
+ return rate_idx < 8 ? HW_TX_RATE_CCK_STR[rate_idx] : HW_TX_RATE_CCK_STR[8];
+ else if (mode == 1)
+ return hw_rate_ofdm_str(rate_idx);
+ else
+ return "MCS";
+}
+
+static void parse_rate(struct seq_file *s, u16 rate_idx, u16 txrate)
+{
+ u16 txmode, mcs, nss, stbc;
+
+ txmode = FIELD_GET(GENMASK(9, 6), txrate);
+ mcs = FIELD_GET(GENMASK(5, 0), txrate);
+ nss = FIELD_GET(GENMASK(12, 10), txrate);
+ stbc = FIELD_GET(BIT(13), txrate);
+
+ seq_printf(s, "\tRate%d(0x%x):TxMode=%d(%s), TxRate=%d(%s), Nsts=%d, STBC=%d\n",
+ rate_idx + 1, txrate,
+ txmode, (txmode < MAX_TX_MODE ? HW_TX_MODE_STR[txmode] : HW_TX_MODE_STR[MAX_TX_MODE]),
+ mcs, hw_rate_str(txmode, mcs), nss, stbc);
+}
+
+#define LWTBL_LEN_IN_DW 32
+#define UWTBL_LEN_IN_DW 8
+#define ONE_KEY_ENTRY_LEN_IN_DW 8
+static int mt7915_sta_info(struct seq_file *s, void *data)
+{
+ struct mt7915_dev *dev = dev_get_drvdata(s->private);
+ u8 lwtbl[LWTBL_LEN_IN_DW*4] = {0};
+ u16 i = 0;
+
+ for (i=0; i < mt7915_wtbl_size(dev); i++) {
+ mt7915_wtbl_read_raw(dev, i, WTBL_TYPE_LMAC, 0,
+ LWTBL_LEN_IN_DW, lwtbl);
+ if (lwtbl[4] || lwtbl[5] || lwtbl[6] || lwtbl[7] || lwtbl[0] || lwtbl[1])
+ seq_printf(s, "wcid:%d\tAddr: %02x:%02x:%02x:%02x:%02x:%02x\n",
+ i, lwtbl[4], lwtbl[5], lwtbl[6], lwtbl[7], lwtbl[0], lwtbl[1]);
+ }
+
+ return 0;
+}
+
+static int mt7915_wtbl_read(struct seq_file *s, void *data)
+{
+ struct mt7915_dev *dev = dev_get_drvdata(s->private);
+ u8 lwtbl[LWTBL_LEN_IN_DW*4] = {0};
+ int x;
+ u32 *addr = 0;
+ u32 dw_value = 0;
+
+ mt7915_wtbl_read_raw(dev, dev->wlan_idx, WTBL_TYPE_LMAC, 0,
+ LWTBL_LEN_IN_DW, lwtbl);
+ seq_printf(s, "Dump WTBL info of WLAN_IDX:%d\n", dev->wlan_idx);
+ seq_printf(s, "LMAC WTBL Addr: group:0x%x=0x%x addr: 0x%lx\n",
+ MT_DBG_WTBLON_TOP_WDUCR,
+ mt76_rr(dev, MT_DBG_WTBLON_TOP_WDUCR),
+ LWTBL_IDX2BASE(dev->wlan_idx, 0));
+ for (x = 0; x < LWTBL_LEN_IN_DW; x++) {
+ seq_printf(s, "DW%02d: %02x %02x %02x %02x\n",
+ x,
+ lwtbl[x * 4 + 3],
+ lwtbl[x * 4 + 2],
+ lwtbl[x * 4 + 1],
+ lwtbl[x * 4]);
+ }
+
+ seq_printf(s, "\n\tAddr: %02x:%02x:%02x:%02x:%02x:%02x(D0[B0~15], D1[B0~31])\n",
+ lwtbl[4], lwtbl[5], lwtbl[6], lwtbl[7], lwtbl[0], lwtbl[1]);
+
+ // DW0, DW1
+ seq_printf(s, "LWTBL DW 0/1\n\t");
+ addr = (u32 *)&(lwtbl[0]);
+ dw_value = *addr;
+ seq_printf(s, "MUAR_IDX:%lu/ ", FIELD_GET(GENMASK(21, 16), dw_value));
+ seq_printf(s, "RCA1:%ld/ ", FIELD_GET(BIT(22), dw_value));
+ seq_printf(s, "KID:%lu/ ", FIELD_GET(GENMASK(24, 23), dw_value));
+ seq_printf(s, "RCID:%ld/ ", FIELD_GET(BIT(25), dw_value));
+ seq_printf(s, "FROM_DS:%ld\n\t", FIELD_GET(BIT(26), dw_value));
+ seq_printf(s, "TO_DS:%ld/ ", FIELD_GET(BIT(27), dw_value));
+ seq_printf(s, "RV:%ld/ ", FIELD_GET(BIT(28), dw_value));
+ seq_printf(s, "RCA2:%ld/ ", FIELD_GET(BIT(29), dw_value));
+ seq_printf(s, "WPI_FLAG:%ld\n", FIELD_GET(BIT(30), dw_value));
+
+ // DW2
+ seq_printf(s, "LWTBL DW 2\n\t");
+ addr = (u32 *)&(lwtbl[2*4]);
+ dw_value = *addr;
+ seq_printf(s, "AID12:%lu/ ", FIELD_GET(GENMASK(11, 0), dw_value));
+ seq_printf(s, "SU:%ld/ ", FIELD_GET(BIT(12), dw_value));
+ seq_printf(s, "SPP_EN:%ld/ ", FIELD_GET(BIT(13), dw_value));
+ seq_printf(s, "WPI_EVEN:%ld\n\t",FIELD_GET(BIT(14), dw_value));
+ seq_printf(s, "CIPHER:%lu/ ", FIELD_GET(GENMASK(20, 16), dw_value));
+ seq_printf(s, "CIPHER_IGTK:%lu/ ",FIELD_GET(GENMASK(22, 21), dw_value));
+ seq_printf(s, "AAD_OM:%ld\n\t", FIELD_GET(BIT(15), dw_value));
+ seq_printf(s, "SW:%ld/ ", FIELD_GET(BIT(24), dw_value));
+ seq_printf(s, "UL:%ld/ ", FIELD_GET(BIT(25), dw_value));
+ seq_printf(s, "TX_POWER_SAVE:%ld\n\t", FIELD_GET(BIT(26), dw_value));
+ seq_printf(s, "QOS:%ld/ ", FIELD_GET(BIT(27), dw_value));
+ seq_printf(s, "HT:%ld/ ", FIELD_GET(BIT(28), dw_value));
+ seq_printf(s, "VHT:%ld/ ", FIELD_GET(BIT(29), dw_value));
+ seq_printf(s, "HE:%ld/ ", FIELD_GET(BIT(30), dw_value));
+ seq_printf(s, "MESH:%ld\n", FIELD_GET(BIT(31), dw_value));
+
+ // DW3
+ seq_printf(s, "LWTBL DW 3\n\t");
+ addr = (u32 *)&(lwtbl[3*4]);
+ dw_value = *addr;
+ seq_printf(s, "WMM_Q:%lu/ ", FIELD_GET(GENMASK(1, 0), dw_value));
+ seq_printf(s, "RXD_DUP_MODE:%lu\n\t", FIELD_GET(GENMASK(3, 2), dw_value));
+ seq_printf(s, "VLAN2ETH:%ld/ ", FIELD_GET(BIT(4), dw_value));
+ seq_printf(s, "BEAM_CHG:%ld/ ", FIELD_GET(BIT(5), dw_value));
+ seq_printf(s, "DIS_BA256:%ld\n\t", FIELD_GET(BIT(6), dw_value));
+ seq_printf(s, "PFMU_IDX:%lu/ ", FIELD_GET(GENMASK(15, 8), dw_value));
+ seq_printf(s, "ULPF_IDX:%lu\n\t", FIELD_GET(GENMASK(23, 16), dw_value));
+ seq_printf(s, "RIBF:%ld/ ", FIELD_GET(BIT(24), dw_value));
+ seq_printf(s, "ULPF:%ld\n\t", FIELD_GET(BIT(25), dw_value));
+ seq_printf(s, "IGN_FBK:%ld/ ", FIELD_GET(BIT(26), dw_value));
+ seq_printf(s, "TBF:%ld/ ", FIELD_GET(BIT(29), dw_value));
+ seq_printf(s, "TBF_VHT:%ld/ ", FIELD_GET(BIT(30), dw_value));
+ seq_printf(s, "TBF_HE:%ld\n", FIELD_GET(BIT(31), dw_value));
+
+ // DW4
+ seq_printf(s, "LWTBL DW 4\n\t");
+ addr = (u32 *)&(lwtbl[4*4]);
+ dw_value = *addr;
+ seq_printf(s, "ANT_ID_STS0:%lu/ ", FIELD_GET(GENMASK(2, 0), dw_value));
+ seq_printf(s, "STS1:%lu/ ", FIELD_GET(GENMASK(5, 3), dw_value));
+ seq_printf(s, "STS2:%lu/ ", FIELD_GET(GENMASK(8, 6), dw_value));
+ seq_printf(s, "STS3:%lu\n\t", FIELD_GET(GENMASK(11, 9), dw_value));
+ seq_printf(s, "ANT_ID_STS4:%lu/ ", FIELD_GET(GENMASK(14, 12), dw_value));
+ seq_printf(s, "STS5:%lu/ ", FIELD_GET(GENMASK(17, 15), dw_value));
+ seq_printf(s, "STS6:%ld/ ", FIELD_GET(GENMASK(20, 18), dw_value));
+ seq_printf(s, "STS7:%lu\n\t", FIELD_GET(GENMASK(23, 21), dw_value));
+ seq_printf(s, "CASCAD:%ld/ ", FIELD_GET(BIT(24), dw_value));
+ seq_printf(s, "LDPC_HT:%ld/ ", FIELD_GET(BIT(25), dw_value));
+ seq_printf(s, "LDPC_VHT:%ld/ ", FIELD_GET(BIT(26), dw_value));
+ seq_printf(s, "LDPC_HE:%ld\n\t", FIELD_GET(BIT(27), dw_value));
+ seq_printf(s, "DIS_RHTR:%ld/ ", FIELD_GET(BIT(28), dw_value));
+ seq_printf(s, "ALL_ACK:%ld/ ", FIELD_GET(BIT(29), dw_value));
+ seq_printf(s, "DROP:%ld/ ", FIELD_GET(BIT(30), dw_value));
+ seq_printf(s, "ACK_EN:%ld\n", FIELD_GET(BIT(31), dw_value));
+
+ // DW5
+ seq_printf(s, "LWTBL DW 5\n\t");
+ addr = (u32 *)&(lwtbl[5*4]);
+ dw_value = *addr;
+ seq_printf(s, "AF:%lu/ ", FIELD_GET(GENMASK(2, 0), dw_value));
+ seq_printf(s, "AF_HE:%lu/ ", FIELD_GET(GENMASK(4, 3), dw_value));
+ seq_printf(s, "RTS:%ld/ ", FIELD_GET(BIT(5), dw_value));
+ seq_printf(s, "SMPS:%ld/ ", FIELD_GET(BIT(6), dw_value));
+ seq_printf(s, "DYN_BW:%ld\n\t", FIELD_GET(BIT(7), dw_value));
+ seq_printf(s, "MMSS:%lu/ ", FIELD_GET(GENMASK(10, 8), dw_value));
+ seq_printf(s, "USR:%ld/ ", FIELD_GET(BIT(11), dw_value));
+ seq_printf(s, "SR_RATE:%lu/ ", FIELD_GET(GENMASK(14, 12), dw_value));
+ seq_printf(s, "SR_ABORT:%ld\n\t", FIELD_GET(BIT(15), dw_value));
+ seq_printf(s, "TX_POWER_OFFSET:%lu/ ", FIELD_GET(GENMASK(21, 16), dw_value));
+ seq_printf(s, "WTBL_MPDU_SIZE:%lu\n\t", FIELD_GET(GENMASK(23, 22), dw_value));
+ seq_printf(s, "PE:%lu/ ", FIELD_GET(GENMASK(25, 24), dw_value));
+ seq_printf(s, "DOPPL:%ld/ ", FIELD_GET(BIT(26), dw_value));
+ seq_printf(s, "TXOP_PS_CAP:%ld/ ", FIELD_GET(BIT(27), dw_value));
+ seq_printf(s, "DONOT_UPDATE_I_PSM:%ld\n\t", FIELD_GET(BIT(28), dw_value));
+ seq_printf(s, "I_PSM:%ld/ ", FIELD_GET(BIT(29), dw_value));
+ seq_printf(s, "PSM:%ld/ ", FIELD_GET(BIT(30), dw_value));
+ seq_printf(s, "SKIP_TX:%ld\n", FIELD_GET(BIT(31), dw_value));
+
+ // DW6
+ seq_printf(s, "LWTBL DW 6\n\t");
+ seq_printf(s, "TID 0/1/2/3/4/5/6/7 BA_WIN_SIZE:");
+ addr = (u32 *)&(lwtbl[6*4]);
+ dw_value = *addr;
+ seq_printf(s, "%lu/ ", FIELD_GET(GENMASK(3, 0), dw_value));
+ seq_printf(s, "%lu/ ", FIELD_GET(GENMASK(7, 4), dw_value));
+ seq_printf(s, "%lu/ ", FIELD_GET(GENMASK(11, 8), dw_value));
+ seq_printf(s, "%lu/ ", FIELD_GET(GENMASK(15, 12), dw_value));
+ seq_printf(s, "%lu/ ", FIELD_GET(GENMASK(19, 16), dw_value));
+ seq_printf(s, "%lu/ ", FIELD_GET(GENMASK(23, 20), dw_value));
+ seq_printf(s, "%lu/ ", FIELD_GET(GENMASK(27, 24), dw_value));
+ seq_printf(s, "%lu\n", FIELD_GET(GENMASK(31, 28), dw_value));
+
+ // DW7
+ seq_printf(s, "LWTBL DW 7\n\t");
+ addr = (u32 *)&(lwtbl[7*4]);
+ dw_value = *addr;
+ seq_printf(s, "CBRN:%lu/ ", FIELD_GET(GENMASK(2, 0), dw_value));
+ seq_printf(s, "DBNSS_EN:%ld/ ", FIELD_GET(BIT(3), dw_value));
+ seq_printf(s, "BAF_EN:%ld/ ", FIELD_GET(BIT(4), dw_value));
+ seq_printf(s, "RDGBA:%ld\n\t", FIELD_GET(BIT(5), dw_value));
+ seq_printf(s, "RDG:%ld/ ", FIELD_GET(BIT(6), dw_value));
+ seq_printf(s, "SPE_IDX:%lu/ ", FIELD_GET(GENMASK(11, 7), dw_value));
+ seq_printf(s, "G2:%ld/ ", FIELD_GET(BIT(12), dw_value));
+ seq_printf(s, "G4:%ld/ ", FIELD_GET(BIT(13), dw_value));
+ seq_printf(s, "G8:%ld/ ", FIELD_GET(BIT(14), dw_value));
+ seq_printf(s, "G16:%ld\n\t", FIELD_GET(BIT(15), dw_value));
+ seq_printf(s, "G2_LTF:%lu/ ", FIELD_GET(GENMASK(17, 16), dw_value));
+ seq_printf(s, "G4_LTF:%lu/ ", FIELD_GET(GENMASK(19, 18), dw_value));
+ seq_printf(s, "G8_LTF:%lu/ ", FIELD_GET(GENMASK(21, 20), dw_value));
+ seq_printf(s, "G16_LTF:%lu\n\t", FIELD_GET(GENMASK(23, 22), dw_value));
+ seq_printf(s, "G2_HE:%lu/ ", FIELD_GET(GENMASK(25, 24), dw_value));
+ seq_printf(s, "G4_HE:%lu/ ", FIELD_GET(GENMASK(27, 27), dw_value));
+ seq_printf(s, "G8_HE:%lu/ ", FIELD_GET(GENMASK(29, 28), dw_value));
+ seq_printf(s, "G16_HE:%lu\n", FIELD_GET(GENMASK(31, 30), dw_value));
+
+ // DW8
+ seq_printf(s, "LWTBL DW 8\n\t");
+ addr = (u32 *)&(lwtbl[8*4]);
+ dw_value = *addr;
+ seq_printf(s, "FAIL_CNT_AC0:%lu/ ", FIELD_GET(GENMASK(4, 0), dw_value));
+ seq_printf(s, "AC1:%lu/ ", FIELD_GET(GENMASK(9, 5), dw_value));
+ seq_printf(s, "AC2:%lu/ ", FIELD_GET(GENMASK(14, 10), dw_value));
+ seq_printf(s, "AC3:%lu\n\t", FIELD_GET(GENMASK(19, 15), dw_value));
+ seq_printf(s, "PARTIAL_AID:%lu/ ", FIELD_GET(GENMASK(28, 20), dw_value));
+ seq_printf(s, "CHK_PER:%lu\n", FIELD_GET(BIT(31), dw_value));
+
+ // DW9
+ seq_printf(s, "LWTBL DW 9\n\t");
+ addr = (u32 *)&(lwtbl[9*4]);
+ dw_value = *addr;
+ seq_printf(s, "RX_AVG_MPDU:%lu/ ", FIELD_GET(GENMASK(13, 0), dw_value));
+ seq_printf(s, "PRITX_SW_MODE:%ld/ ", FIELD_GET(BIT(16), dw_value));
+ seq_printf(s, "PRITX_PLR:%ld\n\t", FIELD_GET(BIT(17), dw_value));
+ seq_printf(s, "PRITX_DCM:%ld/ ", FIELD_GET(BIT(18), dw_value));
+ seq_printf(s, "PRITX_ER160:%ld/ ", FIELD_GET(BIT(19), dw_value));
+ seq_printf(s, "PRITX_ERSU:%lu\n\t", FIELD_GET(BIT(20), dw_value));
+ seq_printf(s, "MPDU_FAIL_CNT:%lu/ ", FIELD_GET(GENMASK(25, 23), dw_value));
+ seq_printf(s, "MPDU_OK_CNT:%lu/ ", FIELD_GET(GENMASK(28, 26), dw_value));
+ seq_printf(s, "RATE_IDX:%lu\n\t", FIELD_GET(GENMASK(31, 29), dw_value));
+ seq_printf(s, "FCAP:%s\n", fcap_str[FIELD_GET(GENMASK(22, 21), dw_value)]);
+
+ // DW10
+ seq_printf(s, "LWTBL DW 10\n");
+ addr = (u32 *)&(lwtbl[10*4]);
+ dw_value = *addr;
+ parse_rate(s, 0, FIELD_GET(GENMASK(13, 0), dw_value));
+ parse_rate(s, 1, FIELD_GET(GENMASK(29, 16), dw_value));
+ // DW11
+ seq_printf(s, "LWTBL DW 11\n");
+ addr = (u32 *)&(lwtbl[11*4]);
+ dw_value = *addr;
+ parse_rate(s, 2, FIELD_GET(GENMASK(13, 0), dw_value));
+ parse_rate(s, 3, FIELD_GET(GENMASK(29, 16), dw_value));
+ // DW12
+ seq_printf(s, "LWTBL DW 12\n");
+ addr = (u32 *)&(lwtbl[12*4]);
+ dw_value = *addr;
+ parse_rate(s, 4, FIELD_GET(GENMASK(13, 0), dw_value));
+ parse_rate(s, 5, FIELD_GET(GENMASK(29, 16), dw_value));
+ // DW13
+ seq_printf(s, "LWTBL DW 13\n");
+ addr = (u32 *)&(lwtbl[13*4]);
+ dw_value = *addr;
+ parse_rate(s, 6, FIELD_GET(GENMASK(13, 0), dw_value));
+ parse_rate(s, 7, FIELD_GET(GENMASK(29, 16), dw_value));
+
+ //DW28
+ seq_printf(s, "LWTBL DW 28\n\t");
+ addr = (u32 *)&(lwtbl[28*4]);
+ dw_value = *addr;
+ seq_printf(s, "OM_INFO:%lu/ ", FIELD_GET(GENMASK(11, 0), dw_value));
+ seq_printf(s, "OM_RXD_DUP_MODE:%u\n\t", !!(dw_value & BIT(12)) );
+
+ //DW29
+ seq_printf(s, "LWTBL DW 29\n");
+ addr = (u32 *)&(lwtbl[29*4]);
+ dw_value = *addr;
+ seq_printf(s, "USER_RSSI:%lu/ ", FIELD_GET(GENMASK(8, 0), dw_value));
+ seq_printf(s, "USER_SNR:%lu/ ", FIELD_GET(GENMASK(14, 9), dw_value));
+ seq_printf(s, "RAPID_REACTION_RATE:%lu/ ", FIELD_GET(GENMASK(26, 16), dw_value));
+ seq_printf(s, "HT_AMSDU(Read Only):%u/ ", !!(dw_value & BIT(30)) );
+ seq_printf(s, "AMSDU_CROSS_LG(Read Only):%u\n\t ", !!(dw_value & BIT(31)));
+
+ //DW30
+ seq_printf(s, "LWTBL DW 30\n\t");
+ addr = (u32 *)&(lwtbl[30*4]);
+ dw_value = *addr;
+ seq_printf(s, "RCPI 0:%lu/ ", FIELD_GET(GENMASK(7, 0), dw_value));
+ seq_printf(s, "RCPI 1:%lu/ ", FIELD_GET(GENMASK(15, 8), dw_value));
+ seq_printf(s, "RCPI 2:%lu/ ", FIELD_GET(GENMASK(23, 16), dw_value));
+ seq_printf(s, "RCPI 3:%lu\n\t", FIELD_GET(GENMASK(31, 24), dw_value));
+
+ //DW31
+ seq_printf(s, "LWTBL DW 31\n\t");
+ addr = (u32 *)&(lwtbl[31*4]);
+ dw_value = *addr;
+ seq_printf(s, "RCPI 4:%lu/ ", FIELD_GET(GENMASK(7, 0), dw_value));
+ seq_printf(s, "RCPI 5:%lu/ ", FIELD_GET(GENMASK(15, 8), dw_value));
+ seq_printf(s, "RCPI 6:%lu/ ", FIELD_GET(GENMASK(23, 16), dw_value));
+ seq_printf(s, "RCPI 7:%lu\n\t", FIELD_GET(GENMASK(31, 24), dw_value));
+
+ return 0;
+}
+
+static int mt7915_uwtbl_read(struct seq_file *s, void *data)
+{
+ struct mt7915_dev *dev = dev_get_drvdata(s->private);
+ u8 uwtbl[UWTBL_LEN_IN_DW * 4] = {0};
+ u8 keytbl[ONE_KEY_ENTRY_LEN_IN_DW*4] = {0};
+ int x;
+ u32 *addr = 0;
+ u32 dw_value = 0;
+ u32 amsdu_len = 0;
+ u32 u2SN = 0;
+ u16 keyloc0, keyloc1;
+
+ mt7915_wtbl_read_raw(dev, dev->wlan_idx, WTBL_TYPE_UMAC, 0,
+ UWTBL_LEN_IN_DW, uwtbl);
+ seq_printf(s, "Dump WTBL info of WLAN_IDX:%d\n", dev->wlan_idx);
+ seq_printf(s, "UMAC WTBL Addr: group:0x%x=0x%x addr: 0x%lx\n",
+ MT_DBG_WTBLON_TOP_WDUCR,
+ mt76_rr(dev, MT_DBG_WTBLON_TOP_WDUCR),
+ UWTBL_IDX2BASE(dev->wlan_idx, 0));
+ for (x = 0; x < UWTBL_LEN_IN_DW; x++) {
+ seq_printf(s, "DW%02d: %02x %02x %02x %02x\n",
+ x,
+ uwtbl[x * 4 + 3],
+ uwtbl[x * 4 + 2],
+ uwtbl[x * 4 + 1],
+ uwtbl[x * 4]);
+ }
+
+ /* UMAC WTBL DW 0 */
+ seq_printf(s, "\nUWTBL PN\n\t");
+ addr = (u32 *)&(uwtbl[0]);
+ dw_value = *addr;
+ seq_printf(s, "PN0:%lu/ ", FIELD_GET(GENMASK(7, 0), dw_value));
+ seq_printf(s, "PN1:%lu/ ", FIELD_GET(GENMASK(15, 8), dw_value));
+ seq_printf(s, "PN2:%lu\n\t", FIELD_GET(GENMASK(23, 16), dw_value));
+ seq_printf(s, "PN3:%lu/ ", FIELD_GET(GENMASK(31, 24), dw_value));
+
+ addr = (u32 *)&(uwtbl[1 * 4]);
+ dw_value = *addr;
+ seq_printf(s, "PN4:%lu/ ", FIELD_GET(GENMASK(7, 0), dw_value));
+ seq_printf(s, "PN5:%lu\n", FIELD_GET(GENMASK(15, 8), dw_value));
+
+ /* UMAC WTBL DW SN part */
+ seq_printf(s, "\nUWTBL SN\n");
+ addr = (u32 *)&(uwtbl[2 * 4]);
+ dw_value = *addr;
+ seq_printf(s, "TID0_AC0_SN:%lu\n", FIELD_GET(GENMASK(11, 0), dw_value));
+ seq_printf(s, "TID1_AC1_SN:%lu\n", FIELD_GET(GENMASK(23, 12), dw_value));
+
+ u2SN = FIELD_GET(GENMASK(31, 24), dw_value);
+ addr = (u32 *)&(uwtbl[3 * 4]);
+ dw_value = *addr;
+ u2SN |= FIELD_GET(GENMASK(3, 0), dw_value);
+ seq_printf(s, "TID2_AC2_SN:%u\n", u2SN);
+ seq_printf(s, "TID3_AC3_SN:%lu\n", FIELD_GET(GENMASK(15, 4), dw_value));
+ seq_printf(s, "TID4_SN:%lu\n", FIELD_GET(GENMASK(27, 16), dw_value));
+
+ u2SN = FIELD_GET(GENMASK(31, 28), dw_value);
+ addr = (u32 *)&(uwtbl[4 * 4]);
+ dw_value = *addr;
+ u2SN |= FIELD_GET(GENMASK(7, 0), dw_value);
+ seq_printf(s, "TID5_SN:%u\n", u2SN);
+ seq_printf(s, "TID6_SN:%lu\n", FIELD_GET(GENMASK(19, 8), dw_value));
+ seq_printf(s, "TID7_SN:%lu\n", FIELD_GET(GENMASK(31, 20), dw_value));
+
+ addr = (u32 *)&(uwtbl[1 * 4]);
+ dw_value = *addr;
+ seq_printf(s, "COM_SN:%lu\n", FIELD_GET(GENMASK(27, 16), dw_value));
+
+ /* UMAC WTBL DW 0 */
+ seq_printf(s, "\nUWTBL others\n");
+
+ addr = (u32 *)&(uwtbl[5 * 4]);
+ dw_value = *addr;
+ keyloc0 = FIELD_GET(GENMASK(10, 0), dw_value);
+ keyloc1 = FIELD_GET(GENMASK(26, 16), dw_value);
+ seq_printf(s, "\tKey Loc 1/2:%lu/%lu\n",
+ FIELD_GET(GENMASK(10, 0), dw_value),
+ FIELD_GET(GENMASK(26, 16), dw_value));
+ seq_printf(s, "\tUWTBL_QOS:%lu\n", FIELD_GET(BIT(27), dw_value));
+ seq_printf(s, "\tUWTBL_HT_VHT_HE:%lu\n", FIELD_GET(BIT(28), dw_value));
+
+ addr = (u32 *)&(uwtbl[6*4]);
+ dw_value = *addr;
+ seq_printf(s, "\tHW AMSDU Enable:%lu\n", FIELD_GET(BIT(9), dw_value));
+
+ amsdu_len = FIELD_GET(GENMASK(5, 0), dw_value);
+ if (amsdu_len == 0)
+ seq_printf(s, "\tHW AMSDU Len:invalid (WTBL value=0x%x)\n", amsdu_len);
+ else if (amsdu_len == 1)
+ seq_printf(s, "\tHW AMSDU Len:%d~%d (WTBL value=0x%x)\n",
+ 1,
+ 255,
+ amsdu_len);
+ else
+ seq_printf(s, "\tHW AMSDU Len:%d~%d (WTBL value=0x%x)\n",
+ 256 * (amsdu_len - 1),
+ 256 * (amsdu_len - 1) + 255,
+ amsdu_len
+ );
+ seq_printf(s, "\tHW AMSDU Num:%lu (WTBL value=0x%lx)\n",
+ FIELD_GET(GENMASK(8, 6), dw_value) + 1,
+ FIELD_GET(GENMASK(8, 6), dw_value));
+
+ /* Parse KEY link */
+ seq_printf(s, "\n\tkeyloc0:%d\n", keyloc0);
+ if(keyloc0 != GENMASK(10, 0)) {
+ mt7915_wtbl_read_raw(dev, keyloc0, WTBL_TYPE_KEY,
+ 0, ONE_KEY_ENTRY_LEN_IN_DW, keytbl);
+ seq_printf(s, "KEY WTBL Addr: group:0x%x=0x%x addr: 0x%lx\n",
+ MT_DBG_WTBLON_TOP_WDUCR,
+ mt76_rr(dev, MT_DBG_WTBLON_TOP_WDUCR),
+ KEYTBL_IDX2BASE(keyloc0, 0));
+
+ for (x = 0; x < ONE_KEY_ENTRY_LEN_IN_DW; x++) {
+ seq_printf(s, "DW%02d: %02x %02x %02x %02x\n",
+ x,
+ keytbl[x * 4 + 3],
+ keytbl[x * 4 + 2],
+ keytbl[x * 4 + 1],
+ keytbl[x * 4]);
+ }
+ }
+
+ seq_printf(s, "\n\tkeyloc1:%d\n", keyloc1);
+ if(keyloc1 != GENMASK(26, 16)) {
+ mt7915_wtbl_read_raw(dev, keyloc1, WTBL_TYPE_KEY,
+ 0, ONE_KEY_ENTRY_LEN_IN_DW, keytbl);
+ seq_printf(s, "KEY WTBL Addr: group:0x%x=0x%x addr: 0x%lx\n",
+ MT_DBG_WTBLON_TOP_WDUCR,
+ mt76_rr(dev, MT_DBG_WTBLON_TOP_WDUCR),
+ KEYTBL_IDX2BASE(keyloc1, 0));
+
+ for (x = 0; x < ONE_KEY_ENTRY_LEN_IN_DW; x++) {
+ seq_printf(s, "DW%02d: %02x %02x %02x %02x\n",
+ x,
+ keytbl[x * 4 + 3],
+ keytbl[x * 4 + 2],
+ keytbl[x * 4 + 1],
+ keytbl[x * 4]);
+ }
+ }
+ return 0;
+}
+
+static void
+dump_dma_tx_ring_info(struct seq_file *s, struct mt7915_dev *dev, char *str, u32 ring_base)
+{
+ u32 base, cnt, cidx, didx, queue_cnt;
+
+ base= mt76_rr(dev, ring_base);
+ cnt = mt76_rr(dev, ring_base + 4);
+ cidx = mt76_rr(dev, ring_base + 8);
+ didx = mt76_rr(dev, ring_base + 12);
+ queue_cnt = (cidx >= didx) ? (cidx - didx) : (cidx - didx + cnt);
+
+ seq_printf(s, "%20s %10x %10x %10x %10x %10x\n", str, base, cnt, cidx, didx, queue_cnt);
+}
+
+static void
+dump_dma_rx_ring_info(struct seq_file *s, struct mt7915_dev *dev, char *str, u32 ring_base)
+{
+ u32 base, cnt, cidx, didx, queue_cnt;
+
+ base= mt76_rr(dev, ring_base);
+ cnt = mt76_rr(dev, ring_base + 4);
+ cidx = mt76_rr(dev, ring_base + 8);
+ didx = mt76_rr(dev, ring_base + 12);
+ queue_cnt = (didx > cidx) ? (didx - cidx - 1) : (didx - cidx + cnt - 1);
+
+ seq_printf(s, "%20s %10x %10x %10x %10x %10x\n", str, base, cnt, cidx, didx, queue_cnt);
+}
+
+static void
+mt7915_show_host_dma_info(struct seq_file *s, struct mt7915_dev *dev)
+{
+ u32 sys_ctrl[10] = {};
+
+ /* HOST DMA */
+ sys_ctrl[0] = mt76_rr(dev, MT_DBG_INT_SOURCE_CSR);
+ sys_ctrl[1] = mt76_rr(dev, MT_DBG_INT_MASK_CSR);
+ sys_ctrl[2] = mt76_rr(dev, MT_DBG_WFDMA0_INT_SOURCE_CSR);
+ sys_ctrl[3] = mt76_rr(dev, MT_DBG_WFDMA0_INT_MASK_CSR);
+ sys_ctrl[4] = mt76_rr(dev, MT_DBG_WFDMA1_INT_SOURCE_CSR);
+ sys_ctrl[5] = mt76_rr(dev, MT_DBG_WFDMA1_INT_MASK_CSR);
+ sys_ctrl[6] = mt76_rr(dev, MT_DBG_WFDMA0_GLO_CFG);
+ sys_ctrl[7] = mt76_rr(dev, MT_DBG_WFDMA1_GLO_CFG);
+ seq_printf(s, "HOST_DMA Configuration\n");
+ seq_printf(s, "%10s %10s %10s %10s %10s %10s\n",
+ "DMA", "IntCSR", "IntMask", "Glocfg", "Tx/RxEn", "Tx/RxBusy");
+ seq_printf(s, "%10s %10x %10x\n",
+ "Merge", sys_ctrl[0], sys_ctrl[1]);
+ seq_printf(s, "%10s %10x %10x %10x %4lx/%5lx %4lx/%5lx\n",
+ "DMA0", sys_ctrl[2], sys_ctrl[3], sys_ctrl[6],
+ FIELD_GET(MT_DBG_WFDMA0_GLO_CFG_TX_DMA_EN, sys_ctrl[6]),
+ FIELD_GET(MT_DBG_WFDMA0_GLO_CFG_RX_DMA_EN, sys_ctrl[6]),
+ FIELD_GET(MT_DBG_WFDMA0_GLO_CFG_TX_BUSY_MASK, sys_ctrl[6]),
+ FIELD_GET(MT_DBG_WFDMA0_GLO_CFG_RX_BUSY_MASK, sys_ctrl[6]));
+
+ seq_printf(s, "%10s %10x %10x %10x %4lx/%5lx %4lx/%5lx\n",
+ "DMA1", sys_ctrl[4], sys_ctrl[5], sys_ctrl[7],
+ FIELD_GET(MT_DBG_WFDMA1_GLO_CFG_TX_DMA_EN, sys_ctrl[7]),
+ FIELD_GET(MT_DBG_WFDMA1_GLO_CFG_RX_DMA_EN, sys_ctrl[7]),
+</