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git01.mediatek.com / filogic / uboot / f6aa39e58128a81a46b0d3a909ace31f9e767632 / arch / arm / mach-socfpga / include / mach / sdram.h
  1. 3ea5951 ddr: altera: Configuring SDRAM extra cycles timing parameters by Chin Liang See · Wed Sep 21 10:25:56 2016 +0800
  2. f00a6ea ddr: altera: sequencer: Wrap misc remaining macros by Marek Vasut · Sun Aug 02 19:18:47 2015 +0200
  3. 3bf9204 ddr: altera: sequencer: Wrap IO_* macros by Marek Vasut · Sun Aug 02 19:00:23 2015 +0200
  4. 39b620e ddr: altera: sequencer: Wrap RW_MGR_* macros by Marek Vasut · Sun Aug 02 18:12:08 2015 +0200
  5. 3384e74 ddr: altera: sequencer: Wrap ac_rom_init and inst_rom_init by Marek Vasut · Sun Aug 02 17:15:19 2015 +0200
  6. 14c5d9a ddr: altera: sequencer: Clean up mach/sdram.h by Marek Vasut · Sun Aug 02 17:02:11 2015 +0200
  7. 32ada57 ddr: altera: sdram: Introduce socfpga_sdram_get_config() by Marek Vasut · Sat Aug 01 21:35:18 2015 +0200
  8. 1b1cc10 ddr: altera: sdram: Clean up sdram_mmr_init_full() part 8 by Marek Vasut · Sat Aug 01 22:25:29 2015 +0200
  9. 33acf0f ddr: altera: Wrap SOCFPGA_SDR_ADDRESS into SDR_PHYGRP.*ADDRESS by Marek Vasut · Sun Jul 12 20:05:54 2015 +0200
  10. e08c559 ddr: altera: Move struct sdram_prot_rule prototype by Marek Vasut · Sun Jul 26 10:37:54 2015 +0200
  11. 429642c driver/ddr/altera: Add DDR driver for Altera's SDRAM controller by Dinh Nguyen · Tue Jun 02 22:52:48 2015 -0500
  12. cfcf5d6 ARM: socfpga: move SoC headers to mach-socfpga/include/mach by Masahiro Yamada · Tue Apr 21 20:38:22 2015 +0900[Renamed from arch/arm/include/asm/arch-socfpga/sdram.h]
  13. ae91756 arm: socfpga: spl: Add stub sdram.h by Marek Vasut · Tue Apr 21 12:30:09 2015 +0200